diff --git a/chipflow/platform/silicon_step.py b/chipflow/platform/silicon_step.py
index 02eee447..6e1b81f4 100644
--- a/chipflow/platform/silicon_step.py
+++ b/chipflow/platform/silicon_step.py
@@ -89,6 +89,11 @@ def build_cli_parser(self, parser):
             "--wait",
             help="Maintain connection to cloud and trace build messages. Filtering is based on the log level (see `verbose` option).",
             default=False, action="store_true")
+        submit_subparser.add_argument(
+            "--build-mode",
+            help="Build mode: 'full' (default) runs complete build with P&R, GDS, LVS; 'synth_only' runs synthesis only.",
+            choices=["full", "synth_only"],
+            default=None)
 
     def run_cli(self, args):
         # Import here to avoid circular dependency
@@ -148,6 +153,12 @@ def submit(self, rtlil_path, args):
             if chipflow_backend_version:
                 data["chipflow_backend_version"] = chipflow_backend_version
 
+            # Build mode: "full" (default) or "synth_only"
+            # Can be set via CLI argument or CHIPFLOW_BUILD_MODE environment variable
+            build_mode = getattr(args, 'build_mode', None) or os.environ.get("CHIPFLOW_BUILD_MODE")
+            if build_mode:
+                data["build_mode"] = build_mode
+
             pads = {}
             for iface, port in self.platform._ports.items():
                 width = len(port.pins)