From 0f4130a01f2d970cad14acd29bd853eb03db820a Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Fri, 14 Nov 2025 11:16:14 +0000 Subject: [PATCH 01/65] Added imem.sv --- repo/rtl/imem.sv | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 repo/rtl/imem.sv diff --git a/repo/rtl/imem.sv b/repo/rtl/imem.sv new file mode 100644 index 0000000..0cd2f48 --- /dev/null +++ b/repo/rtl/imem.sv @@ -0,0 +1,13 @@ +module imem ( + input logic [31:0] addr, + output logic [31:0] instr +); + + logic [31:0] mem [0:255]; + + initial begin + $readmemh("program.hex", mem); + end + + assign instr = mem[addr[9:2]]; +endmodule From ce442c5b808bfc4bf3a5fef24e0845864eed47ea Mon Sep 17 00:00:00 2001 From: minimish1 Date: Fri, 14 Nov 2025 11:17:20 +0000 Subject: [PATCH 02/65] Added PC.sv --- repo/rtl/PC.sv | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 repo/rtl/PC.sv diff --git a/repo/rtl/PC.sv b/repo/rtl/PC.sv new file mode 100644 index 0000000..90e1232 --- /dev/null +++ b/repo/rtl/PC.sv @@ -0,0 +1,21 @@ +module PC #( + parameter WIDTH = 32 +)( + input logic clk, + input logic rst, + input logic PCsrc, + input logic immOp, + output logic [WIDTH-1:0] pc +); + +logic [WIDTH-1:0] branch_PC; +logic [WIDTH-1:0] inc_PC; + +always_ff @(posedge clk) + if (rst) pc <= {WIDTH{1'b0}}; + else + assign inc_PC = pc + {{WIDTH-3{1'b0}}, 2'b100}; // pc + 4 + assign branch_PC = pc + immOp; + if (PCsrc) pc <= branch_PC; + else pc <= inc_PC; +endmodule From 46f87e44da8510e2df52661e034f393d53b6ef09 Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Fri, 14 Nov 2025 11:36:25 +0000 Subject: [PATCH 03/65] Added control.sv --- repo/rtl/control.sv | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 repo/rtl/control.sv diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv new file mode 100644 index 0000000..3c1c384 --- /dev/null +++ b/repo/rtl/control.sv @@ -0,0 +1,41 @@ +module control ( + input logic [6:0] opcode, + input logic EQ, + output logic RegWrite, + output logic ALUsrc, + output logic ALUctrl, // 0 = add, 1 = sub + output logic ImmSrc, // 0 = I-type, 1 = B-type + output logic PCSrc +); + logic branch; + + always_comb begin + RegWrite = 0; + ALUsrc = 0; + ALUctrl = 0; + ImmSrc = 0; + branch = 0; + + case (opcode) + 7'b0010011: begin // ADDI + RegWrite = 1; + ALUsrc = 1; // immediate + ALUctrl = 0; // add + ImmSrc = 0; // I-type + branch = 0; + end + + 7'b1100011: begin // BNE + RegWrite = 0; + ALUsrc = 0; + ALUctrl = 1; // subtract + ImmSrc = 1; // B-type immediate + branch = 1; + end + endcase + end + + assign PCSrc = branch & (~EQ); + +endmodule + From cd24c26d408ec55a22bd65475cac98df3d4c6ce4 Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Fri, 14 Nov 2025 11:40:08 +0000 Subject: [PATCH 04/65] Added signext.sv --- repo/rtl/signext.sv | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 repo/rtl/signext.sv diff --git a/repo/rtl/signext.sv b/repo/rtl/signext.sv new file mode 100644 index 0000000..7625c96 --- /dev/null +++ b/repo/rtl/signext.sv @@ -0,0 +1,22 @@ +module signext ( + input logic [31:0] instr, + input logic ImmSrc, + output logic [31:0] ImmOp +); + + logic [31:0] immI; + logic [31:0] immB; + + assign immI = {{20{instr[31]}}, instr[31:20]}; + + assign immB = {{19{instr[31]}}, + instr[31], // imm[12] + instr[7], // imm[11] + instr[30:25], // imm[10:5] + instr[11:8], // imm[4:1] + 1'b0 // imm[0] + }; + + assign ImmOp = (ImmSrc == 0) ? immI : immB; +endmodule + From c4c799ffaefebedc3465f927b2b0215dbfeacb11 Mon Sep 17 00:00:00 2001 From: minimish1 Date: Fri, 14 Nov 2025 11:41:19 +0000 Subject: [PATCH 05/65] Added PC.sv --- repo/rtl/PC.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/repo/rtl/PC.sv b/repo/rtl/PC.sv index 90e1232..6b6a2ee 100644 --- a/repo/rtl/PC.sv +++ b/repo/rtl/PC.sv @@ -14,7 +14,7 @@ logic [WIDTH-1:0] inc_PC; always_ff @(posedge clk) if (rst) pc <= {WIDTH{1'b0}}; else - assign inc_PC = pc + {{WIDTH-3{1'b0}}, 2'b100}; // pc + 4 + assign inc_PC = pc + {{WIDTH-3{1'b0}}, 3'b100}; // pc + 4 assign branch_PC = pc + immOp; if (PCsrc) pc <= branch_PC; else pc <= inc_PC; From 1f45afcfce16525b54d72ce8b2e2e7cb87ade6ed Mon Sep 17 00:00:00 2001 From: minimish1 Date: Fri, 14 Nov 2025 11:51:39 +0000 Subject: [PATCH 06/65] Added PC.sv --- repo/rtl/PC.sv | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/repo/rtl/PC.sv b/repo/rtl/PC.sv index 6b6a2ee..e4dc31d 100644 --- a/repo/rtl/PC.sv +++ b/repo/rtl/PC.sv @@ -4,18 +4,22 @@ module PC #( input logic clk, input logic rst, input logic PCsrc, - input logic immOp, + input logic [WIDTH-1:0] immOp, output logic [WIDTH-1:0] pc ); logic [WIDTH-1:0] branch_PC; logic [WIDTH-1:0] inc_PC; +logic [WIDTH-1:0] next_PC; -always_ff @(posedge clk) - if (rst) pc <= {WIDTH{1'b0}}; +assign inc_PC = pc + WIDTH'd4; +assign branch_PC = pc + immOp; +assign next_PC = PCsrc ? branch_PC : inc_PC; + +always_ff @(posedge clk or posedge rst) begin + if (rst) + pc <= {WIDTH{1'b0}}; else - assign inc_PC = pc + {{WIDTH-3{1'b0}}, 3'b100}; // pc + 4 - assign branch_PC = pc + immOp; - if (PCsrc) pc <= branch_PC; - else pc <= inc_PC; + pc <= next_PC; + end endmodule From a2ee2cb120c892bfe062087e45422a67b335fdaa Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Wed, 19 Nov 2025 15:05:33 +0000 Subject: [PATCH 07/65] Ignore macOS .DS_Store files --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 .gitignore diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..69d1af0 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +.DS_Store +repo/.DS_Store From 369768a61e69c0e115d4b7165d87ebeb22df4d4b Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Wed, 19 Nov 2025 15:12:58 +0000 Subject: [PATCH 08/65] alu/regfileetc --- repo/rtl/alu.sv | 32 +++++++++++++++++++++++++ repo/rtl/data_unit.sv | 56 +++++++++++++++++++++++++++++++++++++++++++ repo/rtl/reg_file.sv | 32 +++++++++++++++++++++++++ repo/rtl/register.sv | 11 +++++++++ 4 files changed, 131 insertions(+) create mode 100644 repo/rtl/alu.sv create mode 100644 repo/rtl/data_unit.sv create mode 100644 repo/rtl/reg_file.sv create mode 100644 repo/rtl/register.sv diff --git a/repo/rtl/alu.sv b/repo/rtl/alu.sv new file mode 100644 index 0000000..d84c653 --- /dev/null +++ b/repo/rtl/alu.sv @@ -0,0 +1,32 @@ +module alu( + + input logic [31:0] alu_op1, + input logic [31:0] alu_op2, + input logic alu_ctrl, + + output logic [31:0] alu_out, + output logic eq + +); + +logic [31:0] equality; +logic [31:0] sum; + +always_comb begin + + equality = alu_op1 - alu_op2; + sum = alu_op1 + alu_op2; + + if(alu_ctrl == 1'b0) + alu_out = sum; + else + alu_out = equality; + + if(equality == 32'b0) + eq = 1; + else + eq = 0; + +end + +endmodule diff --git a/repo/rtl/data_unit.sv b/repo/rtl/data_unit.sv new file mode 100644 index 0000000..10fed85 --- /dev/null +++ b/repo/rtl/data_unit.sv @@ -0,0 +1,56 @@ +module data_unit( + + input logic [5:0] rs1, + input logic [5:0] rs2, + input logic [5:0] rd, + input logic reg_write, + input logic [31:0] din, + input logic [31:0] imm_op, + input logic alu_src, + input logic alu_ctrl, + + + output logic [31:0] a0, + output logic eq_out + +); + +logic [31:0] mux_out; +logic [31:0] rd1; +logic [31:0] rd2; + + +reg_file1 reg_file( + + .read_addr1(rs1), + .read_addr2(rs2), + .write_addr(rd), + .wd3(din), + .rd1(rd1), + .rd2(rd2), + .a0(a0) + +); + +opsel mux( + + .in0(rd2), + .in1(imm_op), + .sel(alu_src), + .out(mux_out) +); + + +alu1 alu( + + .alu_op1(rd1), + .alu_op2(mux_out), + .alu_ctrl(alu_ctrl), + .alu_out(din), + .eq(eq_out) + + +); + + +endmodule diff --git a/repo/rtl/reg_file.sv b/repo/rtl/reg_file.sv new file mode 100644 index 0000000..52346a0 --- /dev/null +++ b/repo/rtl/reg_file.sv @@ -0,0 +1,32 @@ +module reg_file #( + parameter ADDRESS_WIDTH = 5, + DATA_WIDTH = 32 +)( + input logic clk, + input logic [ADDRESS_WIDTH-1:0] write_addr, + input logic [ADDRESS_WIDTH-1:0] read_addr1, + input logic [ADDRESS_WIDTH-1:0] read_addr2, + input logic [DATA_WIDTH-1:0] wd3, + input logic we3, + output logic [DATA_WIDTH-1:0] dout1, + output logic [DATA_WIDTH-1:0] dout2, + output logic [DATA_WIDTH-1:0] a0 +); + +logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; + + +always_ff @(posedge clk)begin + + if (we3 == 1'b1) + ram_array[write_addr] <= wd3; + + dout1 <= ram_array[read_addr1]; + dout2 <= ram_array[read_addr2]; + a0 <= ram_array[0]; + +end + + + +endmodule diff --git a/repo/rtl/register.sv b/repo/rtl/register.sv new file mode 100644 index 0000000..9daa813 --- /dev/null +++ b/repo/rtl/register.sv @@ -0,0 +1,11 @@ +module register( + + input logic clk, + input logic [31:0] d, + output logic [31:0] q +); + + always_ff @(posedge clk) + q <= d; + +endmodule From fb7bc7837cb82a888995e826be3702d694c4d6f3 Mon Sep 17 00:00:00 2001 From: Sicovo Date: Thu, 20 Nov 2025 10:49:54 +0000 Subject: [PATCH 09/65] Verify Fixed --- repo/tb/compile.sh | 2 +- repo/tb/doit.sh | 18 ++++++++++++------ 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/repo/tb/compile.sh b/repo/tb/compile.sh index af69829..1d3a146 100755 --- a/repo/tb/compile.sh +++ b/repo/tb/compile.sh @@ -52,7 +52,7 @@ riscv64-unknown-elf-objdump -f -d --source -m riscv \ a.out.reloc > ${SCRIPT_DIR}/${basename}.dis # Formats into a hex file -od -v -An -t x1 "a.bin" | tr -s '\n' | awk '{$1=$1};1' > "${output_file}" +od -v -An -t x4 "a.bin" | sed 's/^[ \t]*//' > "${output_file}" rm "a.out.reloc" rm "a.out" diff --git a/repo/tb/doit.sh b/repo/tb/doit.sh index 921062b..f439f51 100755 --- a/repo/tb/doit.sh +++ b/repo/tb/doit.sh @@ -38,12 +38,18 @@ for file in "${files[@]}"; do name="top" fi - # Automatically detect latest GoogleTest installation under Homebrew - GTEST_BASE=$(brew --prefix googletest 2>/dev/null) - if [ -z "$GTEST_BASE" ]; then - echo "${RED}Error: GoogleTest not found via Homebrew.${RESET}" - exit 1 - fi + + # # Automatically detect latest GoogleTest installation under Homebrew（macOS) + # GTEST_BASE=$(brew --prefix googletest 2>/dev/null) + # if [ -z "$GTEST_BASE" ]; then + # echo "${RED}Error: GoogleTest not found via Homebrew.${RESET}" + # exit 1 + # fi + + # --- GoogleTest for Ubuntu --- + # gtest headers and static libs installed via apt (libgtest-dev) + GTEST_INCLUDE="/usr/include" + GTEST_LIB="/usr/lib" # Construct include and lib paths dynamically GTEST_INCLUDE="$GTEST_BASE/include" From afc4b80af3c65eed2216ce9f6352d7af21b52399 Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Thu, 20 Nov 2025 10:52:52 +0000 Subject: [PATCH 10/65] data_unit fixed --- repo/rtl/data_unit.sv | 9 +++++---- repo/rtl/top.sv | 24 +++++++++++++++++++++++- 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/repo/rtl/data_unit.sv b/repo/rtl/data_unit.sv index 10fed85..19562d5 100644 --- a/repo/rtl/data_unit.sv +++ b/repo/rtl/data_unit.sv @@ -26,9 +26,11 @@ reg_file1 reg_file( .read_addr2(rs2), .write_addr(rd), .wd3(din), - .rd1(rd1), - .rd2(rd2), - .a0(a0) + .dout1(rd1), + .dout2(rd2), + .a0(a0), + .clk(clk), + .we3(reg_write) ); @@ -49,7 +51,6 @@ alu1 alu( .alu_out(din), .eq(eq_out) - ); diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index b25a766..4a2c556 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -5,5 +5,27 @@ module top #( input logic rst, output logic [DATA_WIDTH-1:0] a0 ); - assign a0 = 32'd5; + +assign a0 = 32'd5; + + + +data_unit1 data_unit( + + + + +); + + + + + + + + + + + + endmodule From f66e53443bf24b89871f7744a5df4ed6213b7ffa Mon Sep 17 00:00:00 2001 From: minimish1 Date: Thu, 20 Nov 2025 18:30:57 +0000 Subject: [PATCH 11/65] Added top.sv --- repo/rtl/top.sv | 74 +++++++++++++++++++++++++++++++++++++------------ 1 file changed, 57 insertions(+), 17 deletions(-) diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index 4a2c556..529bc61 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -1,31 +1,71 @@ module top #( - DATA_WIDTH = 32 + parameter DATA_WIDTH = 32, + parameter ADDRESS_WIDTH = 5 ) ( input logic clk, input logic rst, output logic [DATA_WIDTH-1:0] a0 ); - -assign a0 = 32'd5; - - - -data_unit1 data_unit( - - - +logic RegWrite; +logic ALUsrc; +logic ALUctrl; +logic ImmSrc; +logic PCsrc; +logic EQ; + +logic [DATA_WIDTH-1:0] pc; +logic [DATA_WIDTH-1:0] ImmOp; +logic [DATA_WIDTH-1:0] instr; + +logic [ADDRESS_WIDTH-1:0] rs1; +logic [ADDRESS_WIDTH-1:0] rs2; +logic [ADDRESS_WIDTH-1:0] rd; + +assign rs1 = instr[19:15]; +assign rs2 = instr[24:20]; +assign rd = instr[11:7]; + +PC pc_module ( + .clk(clk), + .rst(rst), + .ImmOp(ImmOp), + .PCsrc(PCsrc), + .pc(pc) ); +imem imem ( + .addr(pc), + .instr(instr) +); +control control ( + .instr(instr), + .EQ(EQ), + .RegWrite(RegWrite), + .ALUsrc(ALUsrc), + .ALUctrl(ALUctrl), + .ImmSrc(ImmSrc), + .PCsrc(PCsrc) +); +signext signext ( + .instr(instr), + .ImmSrc(ImmSrc), + .ImmOp(ImmOp) +); - - - - - - - +reg_alu_top reg_alu_top ( + .clk(clk), + .AD1(rs1), + .AD2(rs2), + .AD3(rd), + .RegWrite(RegWrite), + .ImmOp(ImmOp), + .ALUsrc(ALUsrc), + .ALUctrl(ALUctrl), + .EQ(EQ), + .a0(a0) +); endmodule From ce76eb73522b5597715af36a36d4e77eaccb5a90 Mon Sep 17 00:00:00 2001 From: minimish1 Date: Thu, 20 Nov 2025 18:32:05 +0000 Subject: [PATCH 12/65] reg_alu_top.sv --- repo/rtl/reg_alu_top.sv | 49 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 repo/rtl/reg_alu_top.sv diff --git a/repo/rtl/reg_alu_top.sv b/repo/rtl/reg_alu_top.sv new file mode 100644 index 0000000..91fdd59 --- /dev/null +++ b/repo/rtl/reg_alu_top.sv @@ -0,0 +1,49 @@ +module reg_alu_top #( + parameter DATA_WIDTH = 32, + ADDRESS_WIDTH = 5 +) ( + input logic clk, + input logic [ADDRESS_WIDTH-1:0] AD1, + input logic [ADDRESS_WIDTH-1:0] AD2, + input logic [ADDRESS_WIDTH-1:0] AD3, + input logic [DATA_WIDTH-1:0] ImmOp, + input logic RegWrite, + input logic ALUctrl, + input logic ALUsrc, + output logic EQ, + output logic [DATA_WIDTH-1:0] a0 +); + +logic [DATA_WIDTH-1:0] ALUout; +logic [DATA_WIDTH-1:0] ALUop1; +logic [DATA_WIDTH-1:0] ALUop2; +logic [DATA_WIDTH-1:0] regOp2; + +reg_file reg_file ( + .clk(clk), + .read_addr1(AD1), + .read_addr2(AD2), + .write_addr(AD3), + .wd3(ALUout), + .we3(RegWrite), + .dout1(ALUop1), + .dout2(regOp2), + .a0(a0) +); + +mux mux ( + .in0(regOp2), + .in1(ImmOp), + .sel(ALUsrc), + .out(ALUop2) +); + +alu alu ( + .alu_op1(ALUop1), + .alu_op2(ALUop2), + .alu_ctrl(ALUctrl), + .alu_out(ALUout), + .eq(EQ) +); + +endmodule From fe422cd10ab51bf0c036a19c0c77f4d6f74f43f0 Mon Sep 17 00:00:00 2001 From: minimish1 Date: Thu, 20 Nov 2025 18:33:48 +0000 Subject: [PATCH 13/65] Fixed all modules --- repo/rtl/PC.sv | 6 +++--- repo/rtl/control.sv | 16 +++++++++++++--- repo/rtl/data_unit.sv | 2 +- repo/rtl/mux.sv | 2 +- repo/rtl/reg_file.sv | 1 - 5 files changed, 18 insertions(+), 9 deletions(-) diff --git a/repo/rtl/PC.sv b/repo/rtl/PC.sv index e4dc31d..1e8f739 100644 --- a/repo/rtl/PC.sv +++ b/repo/rtl/PC.sv @@ -4,7 +4,7 @@ module PC #( input logic clk, input logic rst, input logic PCsrc, - input logic [WIDTH-1:0] immOp, + input logic [WIDTH-1:0] ImmOp, output logic [WIDTH-1:0] pc ); @@ -12,8 +12,8 @@ logic [WIDTH-1:0] branch_PC; logic [WIDTH-1:0] inc_PC; logic [WIDTH-1:0] next_PC; -assign inc_PC = pc + WIDTH'd4; -assign branch_PC = pc + immOp; +assign inc_PC = pc + {{WIDTH-3{1'b0}}, 3'b100}; +assign branch_PC = pc + ImmOp; assign next_PC = PCsrc ? branch_PC : inc_PC; always_ff @(posedge clk or posedge rst) begin diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index 3c1c384..1cba515 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -1,13 +1,15 @@ module control ( - input logic [6:0] opcode, + input logic [31:0] instr, input logic EQ, output logic RegWrite, output logic ALUsrc, output logic ALUctrl, // 0 = add, 1 = sub output logic ImmSrc, // 0 = I-type, 1 = B-type - output logic PCSrc + output logic PCsrc ); logic branch; + logic [6:0] opcode; + assign opcode = instr[6:0]; always_comb begin RegWrite = 0; @@ -32,10 +34,18 @@ module control ( ImmSrc = 1; // B-type immediate branch = 1; end + + default: begin + RegWrite = 0; + ALUsrc = 0; + ALUctrl = 0; + ImmSrc = 0; + branch = 0; + end endcase end - assign PCSrc = branch & (~EQ); + assign PCsrc = branch & (~EQ); endmodule diff --git a/repo/rtl/data_unit.sv b/repo/rtl/data_unit.sv index 19562d5..2564eb0 100644 --- a/repo/rtl/data_unit.sv +++ b/repo/rtl/data_unit.sv @@ -3,7 +3,7 @@ module data_unit( input logic [5:0] rs1, input logic [5:0] rs2, input logic [5:0] rd, - input logic reg_write, + input logic reg_write, input logic [31:0] din, input logic [31:0] imm_op, input logic alu_src, diff --git a/repo/rtl/mux.sv b/repo/rtl/mux.sv index 11ef1e1..5c4b400 100644 --- a/repo/rtl/mux.sv +++ b/repo/rtl/mux.sv @@ -1,5 +1,5 @@ module mux #( - DATA_WIDTH = 32 + parameter DATA_WIDTH = 32 ) ( input logic [DATA_WIDTH-1:0] in0, input logic [DATA_WIDTH-1:0] in1, diff --git a/repo/rtl/reg_file.sv b/repo/rtl/reg_file.sv index 52346a0..284feda 100644 --- a/repo/rtl/reg_file.sv +++ b/repo/rtl/reg_file.sv @@ -15,7 +15,6 @@ module reg_file #( logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; - always_ff @(posedge clk)begin if (we3 == 1'b1) From 130cba12f543a3e51138c6b4f0a9ad4fbc9f2415 Mon Sep 17 00:00:00 2001 From: minimish1 Date: Fri, 21 Nov 2025 10:33:48 +0000 Subject: [PATCH 14/65] Warnings fixed --- repo/rtl/control.sv | 2 ++ repo/rtl/data_unit.sv | 6 +++--- repo/rtl/imem.sv | 2 ++ repo/rtl/signext.sv | 2 ++ 4 files changed, 9 insertions(+), 3 deletions(-) diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index 1cba515..cd4b5db 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -1,5 +1,7 @@ module control ( + /* verilator lint_off UNUSED */ input logic [31:0] instr, + /* verilator lint_on UNUSED */ input logic EQ, output logic RegWrite, output logic ALUsrc, diff --git a/repo/rtl/data_unit.sv b/repo/rtl/data_unit.sv index 2564eb0..63b2e89 100644 --- a/repo/rtl/data_unit.sv +++ b/repo/rtl/data_unit.sv @@ -20,7 +20,7 @@ logic [31:0] rd1; logic [31:0] rd2; -reg_file1 reg_file( +reg_file reg_file( .read_addr1(rs1), .read_addr2(rs2), @@ -34,7 +34,7 @@ reg_file1 reg_file( ); -opsel mux( +mux mux( .in0(rd2), .in1(imm_op), @@ -43,7 +43,7 @@ opsel mux( ); -alu1 alu( +alu alu( .alu_op1(rd1), .alu_op2(mux_out), diff --git a/repo/rtl/imem.sv b/repo/rtl/imem.sv index 0cd2f48..1076e55 100644 --- a/repo/rtl/imem.sv +++ b/repo/rtl/imem.sv @@ -1,6 +1,8 @@ module imem ( + /* verilator lint_off UNUSED */ input logic [31:0] addr, output logic [31:0] instr + /* verilator lint_on UNUSED */ ); logic [31:0] mem [0:255]; diff --git a/repo/rtl/signext.sv b/repo/rtl/signext.sv index 7625c96..c1ac25f 100644 --- a/repo/rtl/signext.sv +++ b/repo/rtl/signext.sv @@ -1,5 +1,7 @@ module signext ( + /* verilator lint_off UNUSED */ input logic [31:0] instr, + /* verilator lint_on UNUSED */ input logic ImmSrc, output logic [31:0] ImmOp ); From 65c432ee9028b016780472ec2507fffa8fc2c987 Mon Sep 17 00:00:00 2001 From: minimish1 Date: Fri, 21 Nov 2025 12:07:48 +0000 Subject: [PATCH 15/65] Added mian decoder --- repo/rtl/main_decoder.sv | 67 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 repo/rtl/main_decoder.sv diff --git a/repo/rtl/main_decoder.sv b/repo/rtl/main_decoder.sv new file mode 100644 index 0000000..6f38772 --- /dev/null +++ b/repo/rtl/main_decoder.sv @@ -0,0 +1,67 @@ +module main_decoder ( + input logic [6:0] opcode, + output logic ResultsSrc, + output logic MemWrite, + output logic ALUsrc, + output logic RegWrite, + output logic Branch, + output logic [1:0] ImmSrc, + output logic [1:0] ALUop +); + +always_comb begin + case(opcode) + + 7'b0000011: begin + ResultsSrc = 1; + MemWrite = 0; + ALUsrc = 1; + RegWrite = 1; + Branch = 0; + ImmSrc = 2'b00; + ALUop = 2'b00; + end + + 7'b0100011: begin + ResultsSrc = X; + MemWrite = 1; + ALUsrc = 1; + RegWrite = 0; + Branch = 0; + ImmSrc = 2'b01; + ALUop = 2'b00; + end + + 7'b0110011: begin + ResultsSrc = 0; + MemWrite = 0; + ALUsrc = 0; + RegWrite = 1; + Branch = 0; + ImmSrc = 2'bXX; + ALUop = 2'b10; + end + + 7'b1100011: begin + ResultsSrc = X; + MemWrite = 0; + ALUsrc = 0; + RegWrite = 0; + Branch = 1; + ImmSrc = 2'b10; + ALUop = 2'b01; + end + + default: begin + ResultsSrc = 0; + MemWrite = 0; + ALUsrc = 0; + RegWrite = 0; + Branch = 0; + ImmSrc = 2'b00; + ALUop = 2'b00; + end + endcase +end + +endmodule \ No newline at end of file From 6c4948cd12734b642a959bc0cebb2953816cd381 Mon Sep 17 00:00:00 2001 From: minimish1 Date: Fri, 21 Nov 2025 12:18:00 +0000 Subject: [PATCH 16/65] Fixed reg_file.sv --- repo/rtl/reg_file.sv | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/repo/rtl/reg_file.sv b/repo/rtl/reg_file.sv index 284feda..b688fc6 100644 --- a/repo/rtl/reg_file.sv +++ b/repo/rtl/reg_file.sv @@ -17,15 +17,12 @@ logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; always_ff @(posedge clk)begin - if (we3 == 1'b1) + if (we3 == 1'b1 && write_addr != 0) ram_array[write_addr] <= wd3; - - dout1 <= ram_array[read_addr1]; - dout2 <= ram_array[read_addr2]; - a0 <= ram_array[0]; - end - +assign dout1 = ram_array[read_addr1]; +assign dout2 = ram_array[read_addr2]; +assign a0 = ram_array[10]; endmodule From feb764cb4ffb25d74d1d5eae9f0d305db4ad23f5 Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Fri, 21 Nov 2025 12:33:23 +0000 Subject: [PATCH 17/65] F1 light implementation task 4 added to repo --- repo/task4/clktick.sv | 46 +++++++++++++++++++ repo/task4/delay.sh | 17 +++++++ repo/task4/delay.sv | 50 +++++++++++++++++++++ repo/task4/delay_tb.cpp | 65 +++++++++++++++++++++++++++ repo/task4/f1_fsm.sv | 83 ++++++++++++++++++++++++++++++++++ repo/task4/lfsr_7.sv | 21 +++++++++ repo/task4/lfsr_9.sv | 21 +++++++++ repo/task4/run_top.sh | 15 +++++++ repo/task4/top.sv | 53 ++++++++++++++++++++++ repo/task4/top_tb.cpp | 99 +++++++++++++++++++++++++++++++++++++++++ repo/task4/vbuddy.cfg | 1 + 11 files changed, 471 insertions(+) create mode 100644 repo/task4/clktick.sv create mode 100644 repo/task4/delay.sh create mode 100644 repo/task4/delay.sv create mode 100644 repo/task4/delay_tb.cpp create mode 100644 repo/task4/f1_fsm.sv create mode 100644 repo/task4/lfsr_7.sv create mode 100644 repo/task4/lfsr_9.sv create mode 100644 repo/task4/run_top.sh create mode 100644 repo/task4/top.sv create mode 100644 repo/task4/top_tb.cpp create mode 100644 repo/task4/vbuddy.cfg diff --git a/repo/task4/clktick.sv b/repo/task4/clktick.sv new file mode 100644 index 0000000..813f606 --- /dev/null +++ b/repo/task4/clktick.sv @@ -0,0 +1,46 @@ +module clktick #( + parameter WIDTH = 8 +)( + // interface signals + input logic clk, // clock + input logic rst, // reset + input logic en, // enable signal + input logic [WIDTH-1:0] N, // clock divided by N+1 + output logic tick // tick output +); + +logic [WIDTH-1:0] count; + +/* +How this works: basically we want a component that takes in a clock, +and produces a pulse lasting for one cycle every N + 1 cycles +Internally, this uses a counter. If reset is high, we set the counter to N +Then, on every rising edge of the clock, we check the value of count. +If count is non-zero, then we keep tick (the output) low, and decrement count by 1 every cycle. +Once count has reached 0, then on the rising edge of the clock, we set the output to 1, and reset count to N +So for example: we set N = 3 +So we have a table for the values of N and tick at the start of each cycle +i | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 +N | 3 | 2 | 1 | 0 | 3 | 2 | 1 | 0 | 3 +tick | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 +So we see that tick becomes 1 every (N + 1) i.e. 4 cycles +Note that there is a delay. i.e. at the begining of cycle 3, N = 0 but tick is still 0. +It is only at the begining of cycle 4 that tick is 1. +*/ + +always_ff @ (posedge clk, posedge rst) + if (rst) begin + tick <= 1'b0; + count <= N; + end + else if (en) begin + if (count == 0) begin + tick <= 1'b1; + count <= N; + end + else begin + tick <= 1'b0; + count <= count - 1'b1; + end + end +endmodule diff --git a/repo/task4/delay.sh b/repo/task4/delay.sh new file mode 100644 index 0000000..a488675 --- /dev/null +++ b/repo/task4/delay.sh @@ -0,0 +1,17 @@ +#!/bin/sh + +# cleanup +rm -rf obj_dir +rm -f *.vcd + +# run Verilator to translate Verilog into C++, including C++ testbench +verilator -Wall --cc --trace delay.sv --exe delay_tb.cpp + +# build C++ project via make automatically generated by Verilator +make -j -C obj_dir/ -f Vdelay.mk Vdelay + +# run executable simulation file +echo "\nRunning simulation" +obj_dir/Vdelay +echo "\nSimulation completed" + diff --git a/repo/task4/delay.sv b/repo/task4/delay.sv new file mode 100644 index 0000000..6978297 --- /dev/null +++ b/repo/task4/delay.sv @@ -0,0 +1,50 @@ +module delay #( + parameter WIDTH = 7 // no of bits in delay counter +)( + input logic clk, // clock signal + input logic rst, // reset signal + input logic trigger, // trigger input signal + input logic [WIDTH-1:0] n, // no of clock cycle delay + output logic time_out // output pulse signal +); + // Declare counter + logic [WIDTH-1:0] count = {WIDTH{1'b0}}; // internal counter + + // Define our states + typedef enum {IDLE, COUNTING, TIME_OUT, WAIT_LOW} my_state; + my_state current_state, next_state; + + // counter + always_ff @(posedge clk, posedge rst) + if (rst | trigger | count=={WIDTH{1'b0}}) count <= n - 1'b1; + else count <= count - 1'b1; + + // state transition + always_ff @(posedge clk, posedge rst) + if (rst) current_state <= IDLE; + else current_state <= next_state; + + // next state logic + always_comb + case (current_state) + IDLE: if (trigger==1'b1) next_state = COUNTING; + else next_state = current_state; + COUNTING: if (count=={WIDTH{1'b0}}) next_state = TIME_OUT; + else next_state = current_state; + TIME_OUT: if (trigger==1'b1) next_state = WAIT_LOW; + else next_state = IDLE; + WAIT_LOW: if (trigger==1'b0) next_state = IDLE; + else next_state = current_state; + default: next_state = IDLE; + endcase + + // output logic + always_comb + case (current_state) + IDLE: time_out = 1'b0; + COUNTING: time_out = 1'b0; + TIME_OUT: time_out = 1'b1; + WAIT_LOW: time_out = 1'b0; + default: time_out = 1'b0; + endcase +endmodule diff --git a/repo/task4/delay_tb.cpp b/repo/task4/delay_tb.cpp new file mode 100644 index 0000000..f4d207f --- /dev/null +++ b/repo/task4/delay_tb.cpp @@ -0,0 +1,65 @@ +#include "verilated.h" +#include "verilated_vcd_c.h" +#include "Vdelay.h" + +#include "../vbuddy.cpp" // include vbuddy code +#define MAX_SIM_CYC 100000 + +int main(int argc, char **argv, char **env) +{ + int simcyc; // simulation clock count + int tick; // each clk cycle has two ticks for two edges + int lights = 0; // state to toggle LED lights + + Verilated::commandArgs(argc, argv); + // init top verilog instance + Vdelay *top = new Vdelay; + // init trace dump + Verilated::traceEverOn(true); + VerilatedVcdC *tfp = new VerilatedVcdC; + top->trace(tfp, 99); + tfp->open("delay.vcd"); + + // init Vbuddy + if (vbdOpen() != 1) + return (-1); + vbdHeader("L3T2:Delay"); + vbdSetMode(1); // Flag mode set to one-shot + + // initialize simulation inputs + top->clk = 1; + top->rst = 0; + top->trigger = 0; + top->n = vbdValue(); + + // run simulation for MAX_SIM_CYC clock cycles + for (simcyc = 0; simcyc < MAX_SIM_CYC; simcyc++) + { + // dump variables into VCD file and toggle clock + for (tick = 0; tick < 2; tick++) + { + tfp->dump(2 * simcyc + tick); + top->clk = !top->clk; + top->eval(); + } + + // Display toggle neopixel + if (top->time_out) + { + vbdBar(lights); + lights = lights ^ 0xFF; + } + // set up input signals of testbench + top->rst = (simcyc < 2); // assert reset for 1st cycle + top->trigger = vbdFlag(); + top->n = vbdValue(); + vbdCycle(simcyc); + + if (Verilated::gotFinish() || vbdGetkey() == 'q') + exit(0); + } + + vbdClose(); // ++++ + tfp->close(); + exit(0); +} diff --git a/repo/task4/f1_fsm.sv b/repo/task4/f1_fsm.sv new file mode 100644 index 0000000..a56af2e --- /dev/null +++ b/repo/task4/f1_fsm.sv @@ -0,0 +1,83 @@ +module f1_fsm ( + input logic rst, + input logic en, + input logic clk, + input logic trigger, + output logic [7:0] data_out, + output logic cmd_delay, + output logic cmd_seq +); + +typedef enum {S0, S1, S2, S3, S4, S5, S6, S7, S8} light_state; +light_state curr_state, next_state; + +// initialise cmd_seq and cmd_delay to 0 +assign cmd_seq = 0; +assign cmd_delay = 0; + +// update the states on each clock cycle or async reset or async trigger +always_ff @ (posedge clk, posedge rst) + if (rst) curr_state <= S0; // if reset, set back to 00000000 + else if (en) curr_state <= next_state; // if en, set curr state to next state, else leave curr state alone + +// logic to decide what is the next state +// so this combinational logic will update the next_state, +// but the next state will only be assigned to the curr state on a posedge clk when en is high +always_comb begin + case (curr_state) + S0: next_state = S1; + S1: next_state = S2; + S2: next_state = S3; + S3: next_state = S4; + S4: next_state = S5; + S5: next_state = S6; + S6: next_state = S7; + S7: next_state = S8; + S8: next_state = S0; + default: next_state = S0; + endcase +end + +/* +We make the modification such that initially cmd_seq and cmd_delay are set to 0, and we are in state 0 +When we push the switch and set trigger = 1, we asynchronously update cmd_seq = 1 +This will allow the 1s ticks from clktick.sv to enable the FSM such that the FSM will start changing states every second +Note that when we are in S0, we update cmd_seq = 1 if trigger = 1, else we leave cmd_seq alone. +This means that once we set cmd_seq = 1 due to the trigger, we do not reset it back to 0 and block the en signal from clktick +Instead even after the trigger goes low, cmd_seq remains high so that the en signal from clktick can come in and update the FSM +Note also that trigger only has an effect when we are in S0. If we are in other states, the trigger doesn't do anything +Then once we are in the other states, we also do not update cmd_seq so it remains high +It is only once we are in S8, we set cmd_seq = 0 so that we transmit the time_out signal as the enable +Whereas for cmd_delay, once we are in S8, we set cmd_delay = 1, to wait for the en signal time_out +Then once the signal comes and we go back to S0, we set cmd_delay back to 0 +In between on other states, we also do not update cmd_delay +*/ + +// output logic +always_comb + case (curr_state) + S0: begin + data_out = 8'b00000000; + if (trigger) cmd_seq = 1'b1; + cmd_delay = 1'b0; + end + S1: data_out = 8'b00000001; + S2: data_out = 8'b00000011; + S3: data_out = 8'b00000111; + S4: data_out = 8'b00001111; + S5: data_out = 8'b00011111; + S6: data_out = 8'b00111111; + S7: data_out = 8'b01111111; + S8: begin + data_out = 8'b11111111; + cmd_seq = 1'b0; + cmd_delay = 1'b1; + end + default: begin + data_out = 8'b00000000; + cmd_seq = 1'b0; + cmd_delay = 1'b0; + end + endcase + +endmodule diff --git a/repo/task4/lfsr_7.sv b/repo/task4/lfsr_7.sv new file mode 100644 index 0000000..3fcd839 --- /dev/null +++ b/repo/task4/lfsr_7.sv @@ -0,0 +1,21 @@ +module lfsr_7 ( + input logic clk, + input logic rst, + input logic en, + output logic [6:0] data_out +); + +// initialise 7-bit shift register to 1 +logic[6:0] sreg = 7'b1; + +always_ff @ (posedge clk, posedge rst) + // async reset to 1 + if (rst) + sreg <= 7'b1; + // else if en, perform shift and pass bit 3 and bit 7 XORed to LSB + else if (en) + sreg <= {sreg[5:0], sreg[2] ^ sreg[6]}; + +assign data_out = sreg; + +endmodule diff --git a/repo/task4/lfsr_9.sv b/repo/task4/lfsr_9.sv new file mode 100644 index 0000000..6ea5697 --- /dev/null +++ b/repo/task4/lfsr_9.sv @@ -0,0 +1,21 @@ +module lfsr_9 ( + input logic clk, + input logic rst, + input logic en, + output logic [8:0] data_out +); + +// initialise 9-bit shift register to 1 +logic[8:0] sreg = 9'b1; + +always_ff @ (posedge clk, posedge rst) + // async reset to 1 + if (rst) + sreg <= 9'b1; + // else if en, perform shift and pass bit 3 and bit 7 XORed to LSB + else if (en) + sreg <= {sreg[7:0], sreg[3] ^ sreg[8]}; + +assign data_out = sreg; + +endmodule diff --git a/repo/task4/run_top.sh b/repo/task4/run_top.sh new file mode 100644 index 0000000..ba97659 --- /dev/null +++ b/repo/task4/run_top.sh @@ -0,0 +1,15 @@ +#!/bin/sh + +# cleanup +rm -rf obj_dir +rm -f top.vcd + +# run Verilator to translate Verilog into C++, including C++ testbench +# dumps the output files into a new folder obj_dir. Also generates the .mk file +verilator -Wall --cc --trace top.sv clktick.sv delay.sv f1_fsm.sv lfsr_7.sv --exe top_tb.cpp + +# build C++ project via make, automatically generated by Verilator +make -j -C obj_dir/ -f Vtop.mk Vtop + +# run executable simulation file +obj_dir/Vtop \ No newline at end of file diff --git a/repo/task4/top.sv b/repo/task4/top.sv new file mode 100644 index 0000000..7dffd2f --- /dev/null +++ b/repo/task4/top.sv @@ -0,0 +1,53 @@ +module top ( + input logic[7:0] N, // for clktick + input logic rst, // reset + input logic clk, + input logic trigger, // trigger for f1_fsm + output logic[7:0] data_out +); + +// intermediate signals +// the output of f1_fsm fed back into clktick and delay +// both default to 0 +logic cmd_seq; +logic cmd_delay; + +// intermediate signal +logic tick; // output of clktick +logic[6:0] prbs; // output of pseudo random binary module +logic time_out; + +clktick ticker1s ( + .rst (rst), + .clk (clk), + .en (cmd_seq), + .N (N), + .tick (tick) +); + +lfsr_7 prb_generator( + .clk (clk), + .rst (rst), + .en (1'b1), // always enable random generator + .data_out (prbs) +); + +delay delay_random( + .clk (clk), + .rst (rst), + .trigger (cmd_delay), + .n (prbs), + .time_out (time_out) +); + +f1_fsm light_fsm( + .rst (rst), + .en (cmd_seq ? tick : time_out), + .clk (clk), + .trigger (trigger), + .data_out (data_out), + .cmd_delay (cmd_delay), + .cmd_seq (cmd_seq) +); + +endmodule diff --git a/repo/task4/top_tb.cpp b/repo/task4/top_tb.cpp new file mode 100644 index 0000000..47e82db --- /dev/null +++ b/repo/task4/top_tb.cpp @@ -0,0 +1,99 @@ +#include "Vtop.h" +#include "verilated.h" +#include "verilated_vcd_c.h" +#include "../vbuddy.cpp" // include vbuddy code +#define MAX_SIM_CYC 100000 + + +int main(int argc, char **argv, char **env) +{ + int simcyc; // simulation clock count + int tick; // each clk cycle has two ticks for two edges + + Verilated::commandArgs(argc, argv); + // init top verilog instance + Vtop *top = new Vtop; + // init trace dump + Verilated::traceEverOn(true); + VerilatedVcdC *tfp = new VerilatedVcdC; + top->trace(tfp, 99); + tfp->open("top.vcd"); + + // init Vbuddy + if (vbdOpen() != 1) + return (-1); + vbdHeader("L3T3:FullF1"); + + vbdSetMode(1); + + // initialize simulation inputs + top->clk = 1; + top->rst = 1; // force reset on first 2 cycles + top->N = vbdValue(); // vbdValue() = 42 gives approx 1s tick + top->trigger = vbdFlag(); + + // boolean to keep track of whether the stopwatch has been started + bool is_timing = false; + // boolean to keep track of whether we are in the midst of a sequence + bool in_sequence = false; + + // run simulation for MAX_SIM_CYC clock cycles + for (simcyc = 0; simcyc < MAX_SIM_CYC; simcyc++) + { + // dump variables into VCD file and toggle clock + for (tick = 0; tick < 2; tick++) + { + tfp->dump(2 * simcyc + tick); + top->clk = !top->clk; + top->eval(); + } + + vbdBar(top -> data_out & 0xFF); + + // set up input signals of testbench + top->rst = (simcyc < 2); // assert reset for 1st cycle + top->N = vbdValue(); + vbdCycle(simcyc); + + // suppose initially data_out is 0. Thus in_sequence is False + // once the fsm starts counting up, then we set in_sequence to True, and it stays true while it counts up + if (top -> data_out) { + in_sequence = true; + } + int flag_val = vbdFlag(); + // if we are not currently timing, we can just set top -> trigger = flag_val which has the same behaviour as before + // if we are at S0, this will kick off the sequence, else if we are not in S0, pressing the button doesn't do anything + if (!is_timing) { + top -> trigger = flag_val; + } + // else if we are timing, then we want the button press to just stop the stopwatch + // we do not set top -> trigger = flag_val because we do not want this button press to trigger another sequence + else if (flag_val) { + is_timing = false; + in_sequence = false; + int rxntime = vbdElapsed(); + vbdHex(4, (rxntime >> 12) & 0xF); + vbdHex(3, (rxntime >> 8) & 0xF); + vbdHex(2, (rxntime >> 4) & 0xF); + vbdHex(1, (rxntime) & 0xF); + } + // if the data_out is 0 (i.e. we are in S0), we first check if we are in_sequence + // i.e. did the lights just go off. If so, we start timing + if (top -> data_out == 0) { + if (in_sequence) { + is_timing = true; + // very important to set this to false + // because otherwise we will keep on entering here and resetting the start time + in_sequence = false; + vbdInitWatch(); + } + } + + if (Verilated::gotFinish() || vbdGetkey() == 'q') + exit(0); + } + + vbdClose(); // ++++ + tfp->close(); + exit(0); +} diff --git a/repo/task4/vbuddy.cfg b/repo/task4/vbuddy.cfg new file mode 100644 index 0000000..f448d2b --- /dev/null +++ b/repo/task4/vbuddy.cfg @@ -0,0 +1 @@ +/dev/ttyUSB0 From 5bbebbf50de481d265a1524234c7e18a93138df8 Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Fri, 21 Nov 2025 18:03:07 +0000 Subject: [PATCH 18/65] Comments added & reg alu top removed --- repo/rtl/PC.sv | 30 +++++++++----- repo/rtl/alu.sv | 30 ++++++++------ repo/rtl/control.sv | 10 +++-- repo/rtl/data_unit.sv | 87 +++++++++++++++++++--------------------- repo/rtl/imem.sv | 7 +++- repo/rtl/main_decoder.sv | 25 +++++++----- repo/rtl/mux.sv | 13 +++--- repo/rtl/reg_alu_top.sv | 49 ---------------------- repo/rtl/reg_file.sv | 30 ++++++++------ repo/rtl/register.sv | 9 +++-- repo/rtl/signext.sv | 13 +++--- repo/rtl/top.sv | 16 +++++--- 12 files changed, 156 insertions(+), 163 deletions(-) delete mode 100644 repo/rtl/reg_alu_top.sv diff --git a/repo/rtl/PC.sv b/repo/rtl/PC.sv index 1e8f739..130bdd5 100644 --- a/repo/rtl/PC.sv +++ b/repo/rtl/PC.sv @@ -1,25 +1,37 @@ module PC #( parameter WIDTH = 32 )( - input logic clk, - input logic rst, - input logic PCsrc, - input logic [WIDTH-1:0] ImmOp, - output logic [WIDTH-1:0] pc + input logic clk, // system clock + input logic rst, // asynchronous reset + input logic PCsrc, // selects between sequential PC and branch target + input logic [WIDTH-1:0] ImmOp, // immediate offset for branch target + output logic [WIDTH-1:0] pc // current program counter ); -logic [WIDTH-1:0] branch_PC; +// compute PC+4 (normal sequential execution) logic [WIDTH-1:0] inc_PC; + +// compute PC+immediate (branch target address) +logic [WIDTH-1:0] branch_PC; + +// next PC after the mux logic [WIDTH-1:0] next_PC; +// add 4 to PC for next instruction assign inc_PC = pc + {{WIDTH-3{1'b0}}, 3'b100}; + +// add immediate offset to PC for branch target assign branch_PC = pc + ImmOp; + +// select between sequential PC and branch PC assign next_PC = PCsrc ? branch_PC : inc_PC; +// program counter register with asynchronous reset always_ff @(posedge clk or posedge rst) begin if (rst) - pc <= {WIDTH{1'b0}}; + pc <= {WIDTH{1'b0}}; // Reset PC to 0 else - pc <= next_PC; - end + pc <= next_PC; // Update PC normally +end + endmodule diff --git a/repo/rtl/alu.sv b/repo/rtl/alu.sv index d84c653..7cb1654 100644 --- a/repo/rtl/alu.sv +++ b/repo/rtl/alu.sv @@ -1,32 +1,38 @@ module alu( - input logic [31:0] alu_op1, - input logic [31:0] alu_op2, - input logic alu_ctrl, - - output logic [31:0] alu_out, - output logic eq - + input logic [31:0] alu_op1, // first operand for the ALU + input logic [31:0] alu_op2, // second operand for the ALU + input logic alu_ctrl, // ALU control signal: selects operation + // 0 -> addition (for addi) + // 1 -> subtraction (for bne) + + output logic [31:0] alu_out, // ALU output result + output logic eq // equality flag: 1 if alu_op1 == alu_op2 ); -logic [31:0] equality; -logic [31:0] sum; +// internal signals to hold intermediate results +logic [31:0] equality; // difference between operands, used for comparison +logic [31:0] sum; // sum of operands, used for addition +// combinational logic block (no clock) always_comb begin + // compute subtraction for branch comparison equality = alu_op1 - alu_op2; + // compute addition for arithmetic instructions sum = alu_op1 + alu_op2; + // select ALU output based on control signal if(alu_ctrl == 1'b0) - alu_out = sum; + alu_out = sum; // alu_ctrl=0 -> addition (addi) else - alu_out = equality; + alu_out = equality; // alu_ctrl=1 → subtraction (bne) + // set equality flag: 1 if operands are equal, 0 otherwise if(equality == 32'b0) eq = 1; else eq = 0; end - endmodule diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index cd4b5db..3963b35 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -2,17 +2,20 @@ module control ( /* verilator lint_off UNUSED */ input logic [31:0] instr, /* verilator lint_on UNUSED */ - input logic EQ, + input logic EQ, // equality flag from ALU (1 if operands are equal) output logic RegWrite, output logic ALUsrc, output logic ALUctrl, // 0 = add, 1 = sub output logic ImmSrc, // 0 = I-type, 1 = B-type - output logic PCsrc + output logic PCsrc // select next PC: 0 = PC+4, 1 = branch target ); + + // internal signals logic branch; logic [6:0] opcode; - assign opcode = instr[6:0]; + assign opcode = instr[6:0]; // extract opcode (bits [6:0]) + // combinational logic: decode opcode to generate control signals always_comb begin RegWrite = 0; ALUsrc = 0; @@ -47,6 +50,7 @@ module control ( endcase end + // determine next PC: branch taken if branch instruction AND operands not equal assign PCsrc = branch & (~EQ); endmodule diff --git a/repo/rtl/data_unit.sv b/repo/rtl/data_unit.sv index 63b2e89..689e82d 100644 --- a/repo/rtl/data_unit.sv +++ b/repo/rtl/data_unit.sv @@ -1,57 +1,52 @@ -module data_unit( - - input logic [5:0] rs1, - input logic [5:0] rs2, - input logic [5:0] rd, - input logic reg_write, - input logic [31:0] din, - input logic [31:0] imm_op, - input logic alu_src, - input logic alu_ctrl, - - - output logic [31:0] a0, - output logic eq_out - +module data_unit #( + parameter DATA_WIDTH = 32, + ADDRESS_WIDTH = 5 +) ( + input logic clk, + input logic [ADDRESS_WIDTH-1:0] AD1, // rs1 address + input logic [ADDRESS_WIDTH-1:0] AD2, // rs2 address + input logic [ADDRESS_WIDTH-1:0] AD3, // rd address + input logic [DATA_WIDTH-1:0] ImmOp, // immediate value + input logic RegWrite, // write enable + input logic ALUctrl, // ALU control + input logic ALUsrc, // select imm or reg + output logic EQ, // ALU equality flag + output logic [DATA_WIDTH-1:0] a0 // x10 output ); -logic [31:0] mux_out; -logic [31:0] rd1; -logic [31:0] rd2; - - -reg_file reg_file( +logic [DATA_WIDTH-1:0] ALUout; // ALU result +logic [DATA_WIDTH-1:0] ALUop1; // ALU operand 1 +logic [DATA_WIDTH-1:0] ALUop2; // ALU operand 2 +logic [DATA_WIDTH-1:0] regOp2; // register file operand 2 - .read_addr1(rs1), - .read_addr2(rs2), - .write_addr(rd), - .wd3(din), - .dout1(rd1), - .dout2(rd2), - .a0(a0), +// register file: read rs1/rs2, write rd +reg_file reg_file ( .clk(clk), - .we3(reg_write) - + .read_addr1(AD1), + .read_addr2(AD2), + .write_addr(AD3), + .wd3(ALUout), + .we3(RegWrite), + .dout1(ALUop1), + .dout2(regOp2), + .a0(a0) ); -mux mux( - - .in0(rd2), - .in1(imm_op), - .sel(alu_src), - .out(mux_out) +// select ALU operand 2: register or immediate +mux mux ( + .in0(regOp2), + .in1(ImmOp), + .sel(ALUsrc), + .out(ALUop2) ); - -alu alu( - - .alu_op1(rd1), - .alu_op2(mux_out), - .alu_ctrl(alu_ctrl), - .alu_out(din), - .eq(eq_out) - +// ALU executes operation and sets EQ +alu alu ( + .alu_op1(ALUop1), + .alu_op2(ALUop2), + .alu_ctrl(ALUctrl), + .alu_out(ALUout), + .eq(EQ) ); - endmodule diff --git a/repo/rtl/imem.sv b/repo/rtl/imem.sv index 1076e55..9ff81f6 100644 --- a/repo/rtl/imem.sv +++ b/repo/rtl/imem.sv @@ -1,15 +1,18 @@ module imem ( /* verilator lint_off UNUSED */ - input logic [31:0] addr, - output logic [31:0] instr + input logic [31:0] addr, // byte address from the program counter (PC) + output logic [31:0] instr // 32-bit instruction read from memory /* verilator lint_on UNUSED */ ); + // instruction memory array: 256 instructions, each 32 bits wide logic [31:0] mem [0:255]; + // preload instructions from an external hex file at simulation start initial begin $readmemh("program.hex", mem); end + // output the instruction corresponding to the PC address assign instr = mem[addr[9:2]]; endmodule diff --git a/repo/rtl/main_decoder.sv b/repo/rtl/main_decoder.sv index 6f38772..b23e37d 100644 --- a/repo/rtl/main_decoder.sv +++ b/repo/rtl/main_decoder.sv @@ -1,19 +1,21 @@ module main_decoder ( - input logic [6:0] opcode, - output logic ResultsSrc, - output logic MemWrite, - output logic ALUsrc, - output logic RegWrite, - output logic Branch, - output logic [1:0] ImmSrc, - output logic [1:0] ALUop + input logic [6:0] opcode, // 7-bit opcode field from the instruction + output logic ResultsSrc, // selects data written to register file (ALU result or memory data) + output logic MemWrite, // enable writing to data memory + output logic ALUsrc, // selects ALU second operand (0 = register, 1 = immediate) + output logic RegWrite, // enable writing to register file + output logic Branch, // indicates branch instruction + output logic [1:0] ImmSrc, // selects type of immediate + output logic [1:0] ALUop // encodes ALU operation type (passed to ALU control) ); +// combinational logic to decode opcode and generate control signals always_comb begin case(opcode) + // load instructions (e.g., LW) 7'b0000011: begin - ResultsSrc = 1; + ResultsSrc = 1; MemWrite = 0; ALUsrc = 1; RegWrite = 1; @@ -22,6 +24,7 @@ always_comb begin ALUop = 2'b00; end + // store instructions (e.g., SW) 7'b0100011: begin ResultsSrc = X; MemWrite = 1; @@ -32,6 +35,7 @@ always_comb begin ALUop = 2'b00; end + // R-type instructions (e.g., ADD, SUB) 7'b0110011: begin ResultsSrc = 0; MemWrite = 0; @@ -42,6 +46,7 @@ always_comb begin ALUop = 2'b10; end + // branch instructions (e.g., BNE, BEQ) 7'b1100011: begin ResultsSrc = X; MemWrite = 0; @@ -49,7 +54,7 @@ always_comb begin RegWrite = 0; Branch = 1; ImmSrc = 2'b10; - ALUop = 2'b01; + ALUop = 2'b01; // ALU performs subtraction for comparison end default: begin diff --git a/repo/rtl/mux.sv b/repo/rtl/mux.sv index 5c4b400..648a387 100644 --- a/repo/rtl/mux.sv +++ b/repo/rtl/mux.sv @@ -1,11 +1,14 @@ module mux #( parameter DATA_WIDTH = 32 ) ( - input logic [DATA_WIDTH-1:0] in0, - input logic [DATA_WIDTH-1:0] in1, - input logic sel, - output logic [DATA_WIDTH-1:0] out + input logic [DATA_WIDTH-1:0] in0, // first input (selected when sel = 0) + input logic [DATA_WIDTH-1:0] in1, // second input (selected when sel = 1) + input logic sel, // control signal to choose input + output logic [DATA_WIDTH-1:0] out // output of the multiplexer ); + + // combinational assignment: + // if sel == 1, output in1; otherwise, output in0 assign out = sel ? in1 : in0; -endmodule +endmodule \ No newline at end of file diff --git a/repo/rtl/reg_alu_top.sv b/repo/rtl/reg_alu_top.sv deleted file mode 100644 index 91fdd59..0000000 --- a/repo/rtl/reg_alu_top.sv +++ /dev/null @@ -1,49 +0,0 @@ -module reg_alu_top #( - parameter DATA_WIDTH = 32, - ADDRESS_WIDTH = 5 -) ( - input logic clk, - input logic [ADDRESS_WIDTH-1:0] AD1, - input logic [ADDRESS_WIDTH-1:0] AD2, - input logic [ADDRESS_WIDTH-1:0] AD3, - input logic [DATA_WIDTH-1:0] ImmOp, - input logic RegWrite, - input logic ALUctrl, - input logic ALUsrc, - output logic EQ, - output logic [DATA_WIDTH-1:0] a0 -); - -logic [DATA_WIDTH-1:0] ALUout; -logic [DATA_WIDTH-1:0] ALUop1; -logic [DATA_WIDTH-1:0] ALUop2; -logic [DATA_WIDTH-1:0] regOp2; - -reg_file reg_file ( - .clk(clk), - .read_addr1(AD1), - .read_addr2(AD2), - .write_addr(AD3), - .wd3(ALUout), - .we3(RegWrite), - .dout1(ALUop1), - .dout2(regOp2), - .a0(a0) -); - -mux mux ( - .in0(regOp2), - .in1(ImmOp), - .sel(ALUsrc), - .out(ALUop2) -); - -alu alu ( - .alu_op1(ALUop1), - .alu_op2(ALUop2), - .alu_ctrl(ALUctrl), - .alu_out(ALUout), - .eq(EQ) -); - -endmodule diff --git a/repo/rtl/reg_file.sv b/repo/rtl/reg_file.sv index b688fc6..324eb4e 100644 --- a/repo/rtl/reg_file.sv +++ b/repo/rtl/reg_file.sv @@ -1,28 +1,32 @@ module reg_file #( - parameter ADDRESS_WIDTH = 5, - DATA_WIDTH = 32 + parameter ADDRESS_WIDTH = 5, // 32 registers + DATA_WIDTH = 32 // 32-bits )( - input logic clk, - input logic [ADDRESS_WIDTH-1:0] write_addr, - input logic [ADDRESS_WIDTH-1:0] read_addr1, - input logic [ADDRESS_WIDTH-1:0] read_addr2, - input logic [DATA_WIDTH-1:0] wd3, - input logic we3, - output logic [DATA_WIDTH-1:0] dout1, - output logic [DATA_WIDTH-1:0] dout2, - output logic [DATA_WIDTH-1:0] a0 + input logic clk, // clock + input logic [ADDRESS_WIDTH-1:0] write_addr, // destination register + input logic [ADDRESS_WIDTH-1:0] read_addr1, // source register 1 address (rs1) + input logic [ADDRESS_WIDTH-1:0] read_addr2, // source register 2 address (rs2) + input logic [DATA_WIDTH-1:0] wd3, // write data + input logic we3, // write enable + output logic [DATA_WIDTH-1:0] dout1, // register file output for rs1 + output logic [DATA_WIDTH-1:0] dout2, // register file output for rs2 + output logic [DATA_WIDTH-1:0] a0 // special output for register x10 (a0) ); +// 32 32-bit registers logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; -always_ff @(posedge clk)begin - +// write operation (synchronous) -> writes occur only if we3 is asserted +always_ff @(posedge clk) begin if (we3 == 1'b1 && write_addr != 0) ram_array[write_addr] <= wd3; end +// read operations (combinational) -> outputs change immediately when read_addr changes assign dout1 = ram_array[read_addr1]; assign dout2 = ram_array[read_addr2]; + +// special readout of x10 (a0) assign a0 = ram_array[10]; endmodule diff --git a/repo/rtl/register.sv b/repo/rtl/register.sv index 9daa813..386bf62 100644 --- a/repo/rtl/register.sv +++ b/repo/rtl/register.sv @@ -1,11 +1,12 @@ module register( - input logic clk, - input logic [31:0] d, - output logic [31:0] q + input logic clk, // clock signal + input logic [31:0] d, // input data + output logic [31:0] q // stored output data ); - always_ff @(posedge clk) + // simple D-flip-flop register -> on every rising edge of clk, q updates to the value of d + always_ff @(posedge clk) q <= d; endmodule diff --git a/repo/rtl/signext.sv b/repo/rtl/signext.sv index c1ac25f..5f08a2a 100644 --- a/repo/rtl/signext.sv +++ b/repo/rtl/signext.sv @@ -1,13 +1,13 @@ module signext ( /* verilator lint_off UNUSED */ - input logic [31:0] instr, + input logic [31:0] instr, // full 32-bit instruction word /* verilator lint_on UNUSED */ - input logic ImmSrc, - output logic [31:0] ImmOp + input logic ImmSrc, // 0 = I-type immediate, 1 = B-type immediate + output logic [31:0] ImmOp // sign-extended immediate output ); - logic [31:0] immI; - logic [31:0] immB; + logic [31:0] immI; // I-type immediate + logic [31:0] immB; // B-type immediate assign immI = {{20{instr[31]}}, instr[31:20]}; @@ -19,6 +19,9 @@ module signext ( 1'b0 // imm[0] }; + // select appropriate immediate based on instruction type assign ImmOp = (ImmSrc == 0) ? immI : immB; + endmodule + diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index 529bc61..e4e0c76 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -4,7 +4,7 @@ module top #( ) ( input logic clk, input logic rst, - output logic [DATA_WIDTH-1:0] a0 + output logic [DATA_WIDTH-1:0] a0 // x10 output ); logic RegWrite; @@ -22,10 +22,12 @@ logic [ADDRESS_WIDTH-1:0] rs1; logic [ADDRESS_WIDTH-1:0] rs2; logic [ADDRESS_WIDTH-1:0] rd; -assign rs1 = instr[19:15]; -assign rs2 = instr[24:20]; -assign rd = instr[11:7]; +// decode instruction fields +assign rs1 = instr[19:15]; // source register 1 +assign rs2 = instr[24:20]; // source register 2 +assign rd = instr[11:7]; // destination register +// program Counter: holds current instruction address PC pc_module ( .clk(clk), .rst(rst), @@ -34,11 +36,13 @@ PC pc_module ( .pc(pc) ); +// instruction memory: fetch instruction at PC imem imem ( .addr(pc), .instr(instr) ); +// control unit: generate control signals based on opcode control control ( .instr(instr), .EQ(EQ), @@ -49,13 +53,15 @@ control control ( .PCsrc(PCsrc) ); +// sign-extension unit: generate immediate values signext signext ( .instr(instr), .ImmSrc(ImmSrc), .ImmOp(ImmOp) ); -reg_alu_top reg_alu_top ( +// datapath unit: ALU + register file + muxes +data_unit data_unit ( .clk(clk), .AD1(rs1), .AD2(rs2), From cae624bf304cd3ded9dc6b9115bf04304a5ecf5c Mon Sep 17 00:00:00 2001 From: Sicovo Date: Fri, 21 Nov 2025 21:31:27 +0000 Subject: [PATCH 19/65] F1 starting light --- repo/tb/asm/f1.s | 50 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 repo/tb/asm/f1.s diff --git a/repo/tb/asm/f1.s b/repo/tb/asm/f1.s new file mode 100644 index 0000000..44632de --- /dev/null +++ b/repo/tb/asm/f1.s @@ -0,0 +1,50 @@ +.text +.globl main +main: + li t1, 0 + li t2, 0x12345678 + li a0, 0 + +light_loop: + slli t1, t1, 1 + ori t1, t1, 1 + + addi a0, t1, 0 + + jal ra, fixed_delay + + li t3, 0xFF + bne t1, t3, light_loop + + addi t1, t2, 0 + jal ra, random_delay + addi t2, t1, 0 + + li a0, 0 + +fixed_delay: + li t0, 50000 +fixed_loop: + addi t0, t0, -1 + bne t0, zero, fixed_loop + jalr x0, ra, 0 + +random_delay: + slli t4, t1, 7 + xor t1, t1, t4 + + srli t4, t1, 9 + xor t1, t1, t4 + + slli t4, t1, 8 + xor t1, t1, t4 + + andi t0, t1, 0x3FF + +random_loop: + addi t0, t0, -1 + bne t0, zero, random_loop + + jalr x0, ra, 0 + + \ No newline at end of file From 3f50982903589a5bc97b908a93a60ee94c567857 Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Fri, 21 Nov 2025 22:26:50 +0000 Subject: [PATCH 20/65] Added new testbench folder to repo with f1.s file --- repo/tb/asm/{program.S => 1_addi_bne.s} | 7 +- repo/tb/asm/2_li_add.s | 12 + repo/tb/asm/3_lbu_sb.s | 17 + repo/tb/asm/4_jal_ret.s | 16 + repo/tb/asm/5_pdf.s | 53 + repo/tb/asm/f1.s | 48 + repo/tb/assemble.sh | 47 + repo/tb/c/return_5.c | 23 - repo/tb/compile.sh | 59 - repo/tb/doit.sh | 45 +- repo/tb/reference/Makefile | 17 + repo/tb/reference/README.md | 1 + repo/tb/reference/Reference_Prog.md | 95 + repo/tb/reference/Reference_Prog.pdf | Bin 0 -> 314872 bytes repo/tb/reference/format_hex.sh | 5 + repo/tb/reference/gaussian.mem | 4096 ++++++++++++++++++++++ repo/tb/reference/images/memory_map.jpg | Bin 0 -> 11833 bytes repo/tb/reference/images/pdf_listing.jpg | Bin 0 -> 137825 bytes repo/tb/reference/noisy.mem | 4096 ++++++++++++++++++++++ repo/tb/reference/pdf.asm | 76 + repo/tb/reference/pdf.s | 43 + repo/tb/reference/triangle.mem | 4096 ++++++++++++++++++++++ repo/tb/tests/base_testbench.h | 44 - repo/tb/tests/cpu_testbench.h | 99 + repo/tb/tests/mux_tb.cpp | 64 - repo/tb/tests/testbench.h | 39 - repo/tb/tests/verify.cpp | 75 +- repo/tb/verification.md | 48 + 28 files changed, 12919 insertions(+), 302 deletions(-) rename repo/tb/asm/{program.S => 1_addi_bne.s} (56%) create mode 100644 repo/tb/asm/2_li_add.s create mode 100644 repo/tb/asm/3_lbu_sb.s create mode 100644 repo/tb/asm/4_jal_ret.s create mode 100644 repo/tb/asm/5_pdf.s create mode 100644 repo/tb/asm/f1.s create mode 100644 repo/tb/assemble.sh delete mode 100644 repo/tb/c/return_5.c delete mode 100755 repo/tb/compile.sh mode change 100755 => 100644 repo/tb/doit.sh create mode 100644 repo/tb/reference/Makefile create mode 100644 repo/tb/reference/README.md create mode 100644 repo/tb/reference/Reference_Prog.md create mode 100644 repo/tb/reference/Reference_Prog.pdf create mode 100644 repo/tb/reference/format_hex.sh create mode 100644 repo/tb/reference/gaussian.mem create mode 100644 repo/tb/reference/images/memory_map.jpg create mode 100644 repo/tb/reference/images/pdf_listing.jpg create mode 100644 repo/tb/reference/noisy.mem create mode 100644 repo/tb/reference/pdf.asm create mode 100644 repo/tb/reference/pdf.s create mode 100644 repo/tb/reference/triangle.mem delete mode 100644 repo/tb/tests/base_testbench.h create mode 100644 repo/tb/tests/cpu_testbench.h delete mode 100644 repo/tb/tests/mux_tb.cpp delete mode 100644 repo/tb/tests/testbench.h create mode 100644 repo/tb/verification.md diff --git a/repo/tb/asm/program.S b/repo/tb/asm/1_addi_bne.s similarity index 56% rename from repo/tb/asm/program.S rename to repo/tb/asm/1_addi_bne.s index 988d9c3..1c94cca 100644 --- a/repo/tb/asm/program.S +++ b/repo/tb/asm/1_addi_bne.s @@ -1,5 +1,7 @@ .text .globl main +# this is a modified version of the Lab4 test program +# which doesn't run in an infinite loop main: addi t1, zero, 0xff # t1 = 255 addi a0, zero, 0x0 # output = 0 @@ -9,4 +11,7 @@ iloop: addi a0, a1, 0 # output = i addi a1, a1, 1 # i++ bne a1, t1, iloop # if i != 255, goto iloop - bne t1, zero, mloop # if t1 != 0 (hint: ALWAYS) goto mloop + bne a0, zero, finish # enter finish state + +finish: # expected result is 254 + bne a0, zero, finish # loop forever diff --git a/repo/tb/asm/2_li_add.s b/repo/tb/asm/2_li_add.s new file mode 100644 index 0000000..c3002dc --- /dev/null +++ b/repo/tb/asm/2_li_add.s @@ -0,0 +1,12 @@ +.text +.globl main +main: + # li is broken into lui and addi for >12-bit values + # don't forget that addi sign-extends + li t1, -9000 # t1 = -9000 + li t2, 10000 # t2 = 10000 + add a0, t1, t2 # a0 = t1 + t2 (=1000) + bne a0, zero, finish # enter finish state + +finish: # expected result is 1000 + bne a0, zero, finish # loop forever diff --git a/repo/tb/asm/3_lbu_sb.s b/repo/tb/asm/3_lbu_sb.s new file mode 100644 index 0000000..a3d7930 --- /dev/null +++ b/repo/tb/asm/3_lbu_sb.s @@ -0,0 +1,17 @@ +.text +.globl main +main: + li s0, 0x00010000 # create pointer to base of data array + + li t1, 100 + sb t1, 0(s0) # store 100 at address 0x00010000 + li t2, 200 + sb t2, 1(s0) # store 200 at address 0x00010001 + + lbu t3, 0(s0) # t3 = *(0x00010000) (=100) + lbu t4, 1(s0) # t4 = *(0x00010001) (=200) + add a0, t3, t4 # a0 = t3 + t4 (=300) + bne a0, zero, finish # enter finish state + +finish: # expected result is 300 + bne a0, zero, finish # loop forever diff --git a/repo/tb/asm/4_jal_ret.s b/repo/tb/asm/4_jal_ret.s new file mode 100644 index 0000000..25f0002 --- /dev/null +++ b/repo/tb/asm/4_jal_ret.s @@ -0,0 +1,16 @@ +.text +.globl main +main: + li t1, 50 # t1 = 50 + jal ra, add_one # call add_one (t1 = 51) + jal ra, add_one # call add_one (t1 = 52) + jal ra, add_one # call add_one (t1 = 53) + j finish +add_one: + addi t1, t1, 1 # t += 1 + ret # return to main + +finish: # function to set the return value then wait + addi a0, t1, 0 # a0 = t1 (expected = 53) +_wait: + bne a0, zero, _wait # loop forever diff --git a/repo/tb/asm/5_pdf.s b/repo/tb/asm/5_pdf.s new file mode 100644 index 0000000..383745a --- /dev/null +++ b/repo/tb/asm/5_pdf.s @@ -0,0 +1,53 @@ +.text +.globl main +.equ base_pdf, 0x100 +.equ base_data, 0x10000 +.equ max_count, 200 +# this is a modified version of the pdf program that returns the sum +# of the value of all the bins +# default distribution is gaussian +main: + JAL ra, init # jump to init, ra and save position to ra + JAL ra, build + JAL ra, display + J finish + +init: # function to initialise PDF buffer memory + LI a1, 0x100 # loop_count a1 = 256 +_loop1: # repeat + ADDI a1, a1, -1 # decrement a1 + SB zero, base_pdf(a1) # mem[base_pdf+a1) = 0 + BNE a1, zero, _loop1 # until a1 = 0 + RET + +build: # function to build prob dist func (pdf) + LI a1, base_data # a1 = base address of data array + LI a2, 0 # a2 = offset into of data array + LI a3, base_pdf # a3 = base address of pdf array + LI a4, max_count # a4 = maximum count to terminate +_loop2: # repeat + ADD a5, a1, a2 # a5 = data base address + offset + LBU t0, 0(a5) # t0 = data value + ADD a6, t0, a3 # a6 = index into pdf array + LBU t1, 0(a6) # t1 = current bin count + ADDI t1, t1, 1 # increment bin count + SB t1, 0(a6) # update bin count + ADDI a2, a2, 1 # point to next data in array + BNE t1, a4, _loop2 # until bin count reaches max + RET + +display: # function send PDF array value to a0 for display + LI s1, 0 # s1 = counter to sum pdf values (not in original) + LI a1, 0 # a1 = offset into pdf array + LI a2, 255 # a2 = max index of pdf array +_loop3: # repeat + LBU a0, base_pdf(a1) # a0 = mem[base_pdf+a1) + ADD s1, s1, a0 # s1 += mem[base_pdf+a1) + ADDI a1, a1, 1 # incr + BNE a1, a2, _loop3 # until end of pdf array + RET + +finish: # function to set the return value then wait + ADDI a0, s1, 0 # a0 = sum of pdf values (expected = 15363) +_wait: + BNE a0, zero, _wait # loop forever diff --git a/repo/tb/asm/f1.s b/repo/tb/asm/f1.s new file mode 100644 index 0000000..b7e4ac5 --- /dev/null +++ b/repo/tb/asm/f1.s @@ -0,0 +1,48 @@ +.text +.globl main +main: + li t1, 0 + li t2, 0x12345678 + li a0, 0 + +light_loop: + slli t1, t1, 1 + ori t1, t1, 1 + + addi a0, t1, 0 + + jal ra, fixed_delay + + li t3, 0xFF + bne t1, t3, light_loop + + addi t1, t2, 0 + jal ra, random_delay + addi t2, t1, 0 + + li a0, 0 + +fixed_delay: + li t0, 50000 +fixed_loop: + addi t0, t0, -1 + bne t0, zero, fixed_loop + jalr x0, ra, 0 + +random_delay: + slli t4, t1, 7 + xor t1, t1, t4 + + srli t4, t1, 9 + xor t1, t1, t4 + + slli t4, t1, 8 + xor t1, t1, t4 + + andi t0, t1, 0x3FF + +random_loop: + addi t0, t0, -1 + bne t0, zero, random_loop + + jalr x0, ra, 0 \ No newline at end of file diff --git a/repo/tb/assemble.sh b/repo/tb/assemble.sh new file mode 100644 index 0000000..f837ef3 --- /dev/null +++ b/repo/tb/assemble.sh @@ -0,0 +1,47 @@ +#!/bin/bash + +# Usage: ./assemble.sh + +# Default vars +SCRIPT_DIR=$(dirname "$(realpath "$0")") +output_file="$SCRIPT_DIR/program.hex" + +# Handle terminal arguments +if [[ $# -eq 0 ]]; then + echo "Usage: ./assemble.sh " + exit 1 +fi + +input_file=$1 +basename=$(basename "$input_file" | sed 's/\.[^.]*$//') +parent=$(dirname "$input_file") +file_extension="${input_file##*.}" +LOG_DIR="$SCRIPT_DIR/test_out/$basename" + +# Create output directory for disassembly, hex and waveforms +mkdir -p $LOG_DIR + +riscv64-unknown-elf-as -R -march=rv32im -mabi=ilp32 \ + -o "a.out" "$input_file" + +riscv64-unknown-elf-ld -melf32lriscv \ + -e 0xBFC00000 \ + -Ttext 0xBFC00000 \ + -o "a.out.reloc" "a.out" + +riscv64-unknown-elf-objcopy -O binary \ + -j .text "a.out.reloc" "a.bin" + +rm *dis 2>/dev/null + +# This generates a disassembly file +# Memory in wrong place, but makes it easier to read (should be main = 0xbfc00000) +riscv64-unknown-elf-objdump -f -d --source -m riscv \ + a.out.reloc > ${LOG_DIR}/program.dis + +# Formats into a hex file +od -v -An -t x1 "a.bin" | tr -s '\n' | awk '{$1=$1};1' > "${output_file}" + +rm "a.out.reloc" +rm "a.out" +rm "a.bin" diff --git a/repo/tb/c/return_5.c b/repo/tb/c/return_5.c deleted file mode 100644 index 3c10f0c..0000000 --- a/repo/tb/c/return_5.c +++ /dev/null @@ -1,23 +0,0 @@ -#if !defined(__riscv) -#include -#else - -// entry point (0x0): compiler places earlier functions lower in memory. -int main(); - -void _start() -{ - main(); - - // Infinite loop to prevent undefined access to memory - while (1) - { - } -} - -#endif - -int main() -{ - return 5; -} \ No newline at end of file diff --git a/repo/tb/compile.sh b/repo/tb/compile.sh deleted file mode 100755 index 1d3a146..0000000 --- a/repo/tb/compile.sh +++ /dev/null @@ -1,59 +0,0 @@ -#!/bin/bash - -# Usage: ./compile.sh - -# Default vars -SCRIPT_DIR=$(dirname "$(realpath "$0")") -output_file="../rtl/program.hex" - -# Handle terminal arguments -if [[ $# -eq 0 ]]; then - echo "Usage: ./compile.sh " - exit 1 -fi - -input_file=$1 -basename=$(basename "$input_file" | sed 's/\.[^.]*$//') -parent=$(dirname "$input_file") -file_extension="${input_file##*.}" - -# Compile the C code if necessary. -if [ $file_extension == "c" ]; then - # IMPORTANT: MUST NOT OPTIMIZE COMPILER! Or instructions could be lost! - riscv64-unknown-elf-gcc -S -g -O0 -fno-builtin -static \ - -march=rv32im -mabi=ilp32 \ - -o "${basename}.s" $input_file \ - -Wno-unused-result - # To get test case 24 passing, you need to modify ^^^^ - input_file="${basename}.s" -fi - -riscv64-unknown-elf-as -R -march=rv32im -mabi=ilp32 \ - -o "a.out" "${input_file}" - -# Remove the .s file if necessary -if [ $file_extension == "c" ]; then - rm ${input_file} -fi - -riscv64-unknown-elf-ld -melf32lriscv \ - -e 0xBFC00000 \ - -Ttext 0xBFC00000 \ - -o "a.out.reloc" "a.out" - -riscv64-unknown-elf-objcopy -O binary \ - -j .text "a.out.reloc" "a.bin" - -rm *dis 2>/dev/null - -# This generates a disassembly file -# Memory in wrong place, but makes it easier to read (should be main = 0xbfc00000) -riscv64-unknown-elf-objdump -f -d --source -m riscv \ - a.out.reloc > ${SCRIPT_DIR}/${basename}.dis - -# Formats into a hex file -od -v -An -t x4 "a.bin" | sed 's/^[ \t]*//' > "${output_file}" - -rm "a.out.reloc" -rm "a.out" -rm "a.bin" \ No newline at end of file diff --git a/repo/tb/doit.sh b/repo/tb/doit.sh old mode 100755 new mode 100644 index f439f51..56c58a2 --- a/repo/tb/doit.sh +++ b/repo/tb/doit.sh @@ -24,37 +24,20 @@ else files=("$@") fi -# Cleanup -rm -rf obj_dir - cd $SCRIPT_DIR +# Wipe previous test output +rm -rf test_out/* + # Iterate through files for file in "${files[@]}"; do name=$(basename "$file" _tb.cpp | cut -f1 -d\-) - + # If verify.cpp -> we are testing the top module if [ $name == "verify.cpp" ]; then name="top" fi - - # # Automatically detect latest GoogleTest installation under Homebrew（macOS) - # GTEST_BASE=$(brew --prefix googletest 2>/dev/null) - # if [ -z "$GTEST_BASE" ]; then - # echo "${RED}Error: GoogleTest not found via Homebrew.${RESET}" - # exit 1 - # fi - - # --- GoogleTest for Ubuntu --- - # gtest headers and static libs installed via apt (libgtest-dev) - GTEST_INCLUDE="/usr/include" - GTEST_LIB="/usr/lib" - - # Construct include and lib paths dynamically - GTEST_INCLUDE="$GTEST_BASE/include" - GTEST_LIB="$GTEST_BASE/lib" - # Translate Verilog -> C++ including testbench verilator -Wall --trace \ -cc ${RTL_FOLDER}/${name}.sv \ @@ -62,30 +45,22 @@ for file in "${files[@]}"; do -y ${RTL_FOLDER} \ --prefix "Vdut" \ -o Vdut \ - -CFLAGS "-std=c++17 -isystem ${GTEST_INCLUDE}" \ - -LDFLAGS "-L${GTEST_LIB} -lgtest -lgtest_main -lpthread" + -LDFLAGS "-lgtest -lgtest_main -lpthread" # Build C++ project with automatically generated Makefile make -j -C obj_dir/ -f Vdut.mk - + # Run executable simulation file ./obj_dir/Vdut - + # Check if the test succeeded or not if [ $? -eq 0 ]; then ((passes++)) else ((fails++)) fi - + done -# Exit as a pass or fail (for CI purposes) -if [ $fails -eq 0 ]; then - echo "${GREEN}Success! All ${passes} test(s) passed!" - exit 0 -else - total=$((passes + fails)) - echo "${RED}Failure! Only ${passes} test(s) passed out of ${total}." - exit 1 -fi +# Save obj_dir in test_out +mv obj_dir test_out/ diff --git a/repo/tb/reference/Makefile b/repo/tb/reference/Makefile new file mode 100644 index 0000000..05de74b --- /dev/null +++ b/repo/tb/reference/Makefile @@ -0,0 +1,17 @@ +# Make file to assembly RISC-V assembly language program(s) in myprog folder +# ... relocate instruction to start at 0xBFC00000 +# ... output hex file ready to be read into instruction memory + +clean: + @rm -f *.hex *.asm *.out *.bin + +reference: pdf.s + @riscv64-unknown-elf-as -R -march=rv32im -mabi=ilp32 -o pdf.out pdf.s + @riscv64-unknown-elf-ld -melf32lriscv -e 0xBFC00000 -Ttext 0xBFC00000 -o pdf.out.reloc pdf.out + @riscv64-unknown-elf-objcopy -O binary -j .text pdf.out.reloc pdf.bin + @riscv64-unknown-elf-objdump -D -S -l -F -Mno-aliases pdf.out.reloc > pdf.asm + @set -euo pipefail + @od -v -An -t x1 pdf.bin | tr -s '\n' | awk '{pdf=pdf};1' > pdf.hex + @rm pdf.out + @rm pdf.out.reloc + @rm pdf.bin diff --git a/repo/tb/reference/README.md b/repo/tb/reference/README.md new file mode 100644 index 0000000..591cf27 --- /dev/null +++ b/repo/tb/reference/README.md @@ -0,0 +1 @@ +Reference_Prog.md \ No newline at end of file diff --git a/repo/tb/reference/Reference_Prog.md b/repo/tb/reference/Reference_Prog.md new file mode 100644 index 0000000..5d2112c --- /dev/null +++ b/repo/tb/reference/Reference_Prog.md @@ -0,0 +1,95 @@ +
+ +## EIE2 Instruction Set Architecture & Compiler (IAC) + +--- +## Reference Program for Team Project + +**_Peter Cheung, V1.0 - 9 Dec 2022_** + +--- + +
+ +This assembly language program, **_pdf.s_** is a common test for team's CPU design. The program reads 8-bit data +from a data memory array starting at 0x10000 and produces a probability distribution function (PDF) in a pdf array at 0x100. + +## New Memory Map + +


+To run this program, you need to increase your data memory space according to the memory map shown here. The data memory space from 0x00000000 to 0x0001FFF is used in the following ways: + +* 0x00000000 to 0x000000FF is 256 bytes reserved for other purpose (not used here) +* 0x00000100 to 0x000001FF is 256 bytes to store the probability distribution function (pdf array) +* 0x00010000 to 0x0001FFFF is a 65,536-bytes array that stores the data the PDF of which is to be calculated + +The rest of the data memory space is not used by this program. +
+ +___ + +## How is probability distribution function calculated? +___ + +To find the PDF of an array of data (e.g. signals), we need to reserve a block of memory to store the distribution. Each entry is a "bin", storing how many times a data value occurred. Since the data is 8-bit wide, the range of data value is from 0 to 255. We therefore only need an array of size 256. + +To start, the count in each bin of the data array must be initialised to zero. We then read the data one byte at a time. If a data value is v, we increment by one the "frequency count" in bin base_address + v. We stop building the PDF array if any bin reaches a count of 255. + +--- + +## The Reference Program **_pdf.s_** +--- + +Here is the reference program with line number. + + +


+ +It consists of 4 segments: +1. The main program loop, +2. The init function, +3. The build function, +4. The display function. + +There are a number of important issues to note: + +* Lines 1-4 are assembler directives. **.text** means what follows is a program section. **.equ** defines symbolic constants. + +* Lines 5-10 are the main program which initialize the pdf array bin counts to zero, then build the pdf function, and finally go into an infinite loop that keep outputing the pdf array to a0, which can be displayed on Vbuddy in the testbench. + +* I have used pseudoinstructions throughout to make the program more readable. For example, line 21 +```brainfuck + LI a1, base_data +``` +is translated to the real instruction: +```brainfuck + LUI a1, 0x10 +``` + +The 32-bit constant **_base_data_** is 0x10000, which is larger than 12 bits allowed by I-type instructions. Therefore, we need to use the LUI instruciton. This requires the programmer to understand how the LUI instruction works. The LI pseudoinstruction hides such details from the programmable. Of course, as a hardware architect, you NEED to know that this instruction is translated to a LUI instruction! + +* To help you mapping all pseudoinstruction to real instructions, I have provided you with a Makefile in the reference folder, which not only assembles the pdf.s source code to a hex file ready to be loading into instruction memory, but also produces the assembly listing in a .asm file. + +* To **make** everything, simply type the command: + +```bash + make reference +``` + +* Provided in the repo are four data files each contains 65,536 bytes of signal data. They are: + 1. sine.mem - a sinewave signal. + 2. triangle.mem - a triangular wave signal. + 3. gaussian.mem - a noise signal with a gaussian distribution. + 4. noisy.mem - a noisy sinewave signal. + +* You can read any of these data into the data memory data_array at the base address 0x10000 with the SystemVerilog directive: + +```Verilog + $readmemh('xxxx.mem', data_array, 0x10000); +``` +* This program has data or control hazards if run on a pipelined version of the RISC-V processor. You must add NOP yourself to get round the hazards. + +* You are free to modify the pdf.s code but you should tell me what you have done and why. + +* Evidence of this program working would be the plot of the PDF on Vbuddy. This can be done by plotting the value of top->a0 AFTER the function which builds the distribution is finished. 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zfCeF?=eh#t{(8Rcn{k=QWwAMOM$Wh|)cLp*x(ajPGr=8qS8Ogvi85*q|A2B-&Hn~@ z{qaOrsVJUUwIwBzz(p{HnRa^TKSwMP_4{$UZBL%jup*msdhRVPGKpSS|M>m2F!e_d z$-xPArot)j!9$~C^en4D5<8#MOt$Z_M6aD~gQ79&|A}6sQuZ9|jb*QTk%KrF`gWDS zq2bG{PM((iPop6k*8TYN>6}+u3NHpJu!@OM`v!S&i5q(EZYN?r{T27@L_X3Asd&7P z4ds;AN2ZP;k+JgITdzPThm@9i*}tulMJ38B6!T&@KqH_<_1)Czse(j>e5WGAogT{9 zb_|EYr$&vHPng?Uuhw+2~v6V{QJo#rLRl2|1 z$BzD3Ca}49b!?XRqn2!vhCr&xo0(I)d&|EyvC+TyBI1Nz)W`Y!?7ta!{wp1i)7a=^ zyASskB0nzqQQE@!`<2v!h5kMtjQ`^?zKY|KyGK#q6DVTPrpxqTbiR7N&f`RvIwJwPBK5G4pC0b-5--X?5zTC^${SdYK_|C1n)|1PhB*~pH)clOsrykPKhWLz zn<8t%{eh|uSZQ5DVgJOybk;b{)#w2ZZrh~nRpUveHq|W)-Egy4`4Q>2b(o}5%E@mG zX)92~_T`1BFm{1i+Qmq6b@fy290a5_7E}Le($b=*z-2BI_Cim_Mlksn%4xX#$gDlru>MJl2ms?EaKbk`qc;qn z$p1-%^~ZvYbZ-IivV5tFIePz#o8 (File Offset: 0x1000): +main(): +bfc00000: 010000ef jal ra,bfc00010 (File Offset: 0x1010) +bfc00004: 020000ef jal ra,bfc00024 (File Offset: 0x1024) + +bfc00008 (File Offset: 0x1008): +forever(): +bfc00008: 050000ef jal ra,bfc00058 (File Offset: 0x1058) +bfc0000c: ffdff06f jal zero,bfc00008 (File Offset: 0x1008) + +bfc00010 (File Offset: 0x1010): +init(): +bfc00010: 10000593 addi a1,zero,256 + +bfc00014 <_loop1> (File Offset: 0x1014): +_loop1(): +bfc00014: fff58593 addi a1,a1,-1 +bfc00018: 10058023 sb zero,256(a1) +bfc0001c: fe059ce3 bne a1,zero,bfc00014 <_loop1> (File Offset: 0x1014) +bfc00020: 00008067 jalr zero,0(ra) + +bfc00024 (File Offset: 0x1024): +build(): +bfc00024: 000105b7 lui a1,0x10 +bfc00028: 00000613 addi a2,zero,0 +bfc0002c: 10000693 addi a3,zero,256 +bfc00030: 0c800713 addi a4,zero,200 + +bfc00034 <_loop2> (File Offset: 0x1034): +_loop2(): +bfc00034: 00c587b3 add a5,a1,a2 +bfc00038: 0007c283 lbu t0,0(a5) +bfc0003c: 00d28833 add a6,t0,a3 +bfc00040: 00084303 lbu t1,0(a6) +bfc00044: 00130313 addi t1,t1,1 +bfc00048: 00680023 sb t1,0(a6) +bfc0004c: 00160613 addi a2,a2,1 +bfc00050: fee312e3 bne t1,a4,bfc00034 <_loop2> (File Offset: 0x1034) +bfc00054: 00008067 jalr zero,0(ra) + +bfc00058 (File Offset: 0x1058): +display(): +bfc00058: 00000593 addi a1,zero,0 +bfc0005c: 0ff00613 addi a2,zero,255 + +bfc00060 <_loop3> (File Offset: 0x1060): +_loop3(): +bfc00060: 1005c503 lbu a0,256(a1) # 10100 (File Offset: 0xffffffff40411100) +bfc00064: 00158593 addi a1,a1,1 +bfc00068: fec59ce3 bne a1,a2,bfc00060 <_loop3> (File Offset: 0x1060) +bfc0006c: 00008067 jalr zero,0(ra) + +Disassembly of section .riscv.attributes: + +00000000 <.riscv.attributes> (File Offset: 0x1070): + 0: 1e41 .2byte 0x1e41 + 2: 0000 .2byte 0x0 + 4: 7200 .2byte 0x7200 + 6: 7369 .2byte 0x7369 + 8: 01007663 bgeu zero,a6,14 (File Offset: 0x1084) + c: 0014 .2byte 0x14 + e: 0000 .2byte 0x0 + 10: 7205 .2byte 0x7205 + 12: 3376 .2byte 0x3376 + 14: 6932 .2byte 0x6932 + 16: 7032 .2byte 0x7032 + 18: 5f30 .2byte 0x5f30 + 1a: 326d .2byte 0x326d + 1c: 3070 .2byte 0x3070 + ... diff --git a/repo/tb/reference/pdf.s b/repo/tb/reference/pdf.s new file mode 100644 index 0000000..0dbb664 --- /dev/null +++ b/repo/tb/reference/pdf.s @@ -0,0 +1,43 @@ +.text +.equ base_pdf, 0x100 +.equ base_data, 0x10000 +.equ max_count, 200 +main: + JAL ra, init # jump to init, ra and save position to ra + JAL ra, build +forever: + JAL ra, display + J forever + +init: # function to initialise PDF buffer memory + LI a1, 0x100 # loop_count a1 = 256 +_loop1: # repeat + ADDI a1, a1, -1 # decrement a1 + SB zero, base_pdf(a1) # mem[base_pdf+a1) = 0 + BNE a1, zero, _loop1 # until a1 = 0 + RET + +build: # function to build prob dist func (pdf) + LI a1, base_data # a1 = base address of data array + LI a2, 0 # a2 = offset into of data array + LI a3, base_pdf # a3 = base address of pdf array + LI a4, max_count # a4 = maximum count to terminate +_loop2: # repeat + ADD a5, a1, a2 # a5 = data base address + offset + LBU t0, 0(a5) # t0 = data value + ADD a6, t0, a3 # a6 = index into pdf array + LBU t1, 0(a6) # t1 = current bin count + ADDI t1, t1, 1 # increment bin count + SB t1, 0(a6) # update bin count + ADDI a2, a2, 1 # point to next data in array + BNE t1, a4, _loop2 # until bin count reaches max + RET + +display: # function send PDF array value to a0 for display + LI a1, 0 # a1 = offset into pdf array + LI a2, 255 # a2 = max index of pdf array +_loop3: # repeat + LBU a0, base_pdf(a1) # a0 = mem[base_pdf+a1) + addi a1, a1, 1 # incr + BNE a1, a2, _loop3 # until end of pdf array + RET diff --git a/repo/tb/reference/triangle.mem b/repo/tb/reference/triangle.mem new file mode 100644 index 0000000..bdc2852 --- /dev/null +++ b/repo/tb/reference/triangle.mem @@ -0,0 +1,4096 @@ + 1 2 3 4 5 7 8 9 A B C E F 10 11 12 +14 15 16 17 18 19 1B 1C 1D 1E 1F 20 22 23 24 25 +26 28 29 2A 2B 2C 2D 2F 30 31 32 33 35 36 37 38 +39 3A 3C 3D 3E 3F 40 41 43 44 45 46 47 49 4A 4B +4C 4D 4E 50 51 52 53 54 56 57 58 59 5A 5B 5D 5E +5F 60 61 62 64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 +72 73 74 75 77 78 79 7A 7B 7C 7E 7F 80 81 82 83 +85 86 87 88 89 8B 8C 8D 8E 8F 90 92 93 94 95 96 +97 99 9A 9B 9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 +AA AC AD AE AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC +BD BE C0 C1 C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF +D0 D1 D2 D4 D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 +E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF +DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD +CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA +B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 +A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 +93 92 90 8F 8E 8D 8C 8B 89 88 87 86 85 83 82 81 +80 7F 7E 7C 7B 7A 79 78 77 75 74 73 72 71 6F 6E +6D 6C 6B 6A 68 67 66 65 64 62 61 60 5F 5E 5D 5B +5A 59 58 57 56 54 53 52 51 50 4E 4D 4C 4B 4A 49 +47 46 45 44 43 41 40 3F 3E 3D 3C 3A 39 38 37 36 +35 33 32 31 30 2F 2D 2C 2B 2A 29 28 26 25 24 23 +22 20 1F 1E 1D 1C 1B 19 18 17 16 15 14 12 11 10 + F E C B A 9 8 7 5 4 3 2 1 2 3 4 + 5 7 8 9 A B C E F 10 11 12 14 15 16 17 +18 19 1B 1C 1D 1E 1F 20 22 23 24 25 26 28 29 2A +2B 2C 2D 2F 30 31 32 33 35 36 37 38 39 3A 3C 3D +3E 3F 40 41 43 44 45 46 47 49 4A 4B 4C 4D 4E 50 +51 52 53 54 56 57 58 59 5A 5B 5D 5E 5F 60 61 62 +64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 +77 78 79 7A 7B 7C 7E 7F 80 81 82 83 85 86 87 88 +89 8B 8C 8D 8E 8F 90 92 93 94 95 96 97 99 9A 9B +9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE +AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 +C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 +D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 +E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF DE DD DC DB +D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD CB CA C9 C8 +C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA B8 B7 B6 B5 +B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 A6 A4 A3 A2 +A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 93 92 90 8F +8E 8D 8C 8B 89 88 87 86 85 83 82 81 80 7F 7E 7C +7B 7A 79 78 77 75 74 73 72 71 6F 6E 6D 6C 6B 6A +68 67 66 65 64 62 61 60 5F 5E 5D 5B 5A 59 58 57 +56 54 53 52 51 50 4E 4D 4C 4B 4A 49 47 46 45 44 +43 41 40 3F 3E 3D 3C 3A 39 38 37 36 35 33 32 31 +30 2F 2D 2C 2B 2A 29 28 26 25 24 23 22 20 1F 1E +1D 1C 1B 19 18 17 16 15 14 12 11 10 F E C B + A 9 8 7 5 4 3 2 1 2 3 4 5 7 8 9 + A B C E F 10 11 12 14 15 16 17 18 19 1B 1C +1D 1E 1F 20 22 23 24 25 26 28 29 2A 2B 2C 2D 2F +30 31 32 33 35 36 37 38 39 3A 3C 3D 3E 3F 40 41 +43 44 45 46 47 49 4A 4B 4C 4D 4E 50 51 52 53 54 +56 57 58 59 5A 5B 5D 5E 5F 60 61 62 64 65 66 67 +68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 77 78 79 7A +7B 7C 7E 7F 80 81 82 83 85 86 87 88 89 8B 8C 8D +8E 8F 90 92 93 94 95 96 97 99 9A 9B 9C 9D 9F A0 +A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE AF B0 B1 B3 +B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 C2 C3 C4 C5 +C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 D5 D6 D7 D8 +D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 E8 E9 EA E9 +E8 E6 E5 E4 E3 E2 E1 DF DE DD DC DB D9 D8 D7 D6 +D5 D4 D2 D1 D0 CF CE CD CB CA C9 C8 C7 C5 C4 C3 +C2 C1 C0 BE BD BC BB BA B8 B7 B6 B5 B4 B3 B1 B0 +AF AE AD AC AA A9 A8 A7 A6 A4 A3 A2 A1 A0 9F 9D +9C 9B 9A 99 97 96 95 94 93 92 90 8F 8E 8D 8C 8B +89 88 87 86 85 83 82 81 80 7F 7E 7C 7B 7A 79 78 +77 75 74 73 72 71 6F 6E 6D 6C 6B 6A 68 67 66 65 +64 62 61 60 5F 5E 5D 5B 5A 59 58 57 56 54 53 52 +51 50 4E 4D 4C 4B 4A 49 47 46 45 44 43 41 40 3F +3E 3D 3C 3A 39 38 37 36 35 33 32 31 30 2F 2D 2C +2B 2A 29 28 26 25 24 23 22 20 1F 1E 1D 1C 1B 19 +18 17 16 15 14 12 11 10 F E C B A 9 8 7 + 5 4 3 2 1 2 3 4 5 7 8 9 A B C E + F 10 11 12 14 15 16 17 18 19 1B 1C 1D 1E 1F 20 +22 23 24 25 26 28 29 2A 2B 2C 2D 2F 30 31 32 33 +35 36 37 38 39 3A 3C 3D 3E 3F 40 41 43 44 45 46 +47 49 4A 4B 4C 4D 4E 50 51 52 53 54 56 57 58 59 +5A 5B 5D 5E 5F 60 61 62 64 65 66 67 68 6A 6B 6C +6D 6E 6F 71 72 73 74 75 77 78 79 7A 7B 7C 7E 7F +80 81 82 83 85 86 87 88 89 8B 8C 8D 8E 8F 90 92 +93 94 95 96 97 99 9A 9B 9C 9D 9F A0 A1 A2 A3 A4 +A6 A7 A8 A9 AA AC AD AE AF B0 B1 B3 B4 B5 B6 B7 +B8 BA BB BC BD BE C0 C1 C2 C3 C4 C5 C7 C8 C9 CA +CB CD CE CF D0 D1 D2 D4 D5 D6 D7 D8 D9 DB DC DD +DE DF E1 E2 E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 +E3 E2 E1 DF DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 +D0 CF CE CD CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE +BD BC BB BA B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC +AA A9 A8 A7 A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 +97 96 95 94 93 92 90 8F 8E 8D 8C 8B 89 88 87 86 +85 83 82 81 80 7F 7E 7C 7B 7A 79 78 77 75 74 73 +72 71 6F 6E 6D 6C 6B 6A 68 67 66 65 64 62 61 60 +5F 5E 5D 5B 5A 59 58 57 56 54 53 52 51 50 4E 4D +4C 4B 4A 49 47 46 45 44 43 41 40 3F 3E 3D 3C 3A +39 38 37 36 35 33 32 31 30 2F 2D 2C 2B 2A 29 28 +26 25 24 23 22 20 1F 1E 1D 1C 1B 19 18 17 16 15 +14 12 11 10 F E C B A 9 8 7 5 4 3 2 + 1 2 3 4 5 7 8 9 A B C E F 10 11 12 +14 15 16 17 18 19 1B 1C 1D 1E 1F 20 22 23 24 25 +26 28 29 2A 2B 2C 2D 2F 30 31 32 33 35 36 37 38 +39 3A 3C 3D 3E 3F 40 41 43 44 45 46 47 49 4A 4B +4C 4D 4E 50 51 52 53 54 56 57 58 59 5A 5B 5D 5E +5F 60 61 62 64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 +72 73 74 75 77 78 79 7A 7B 7C 7E 7F 80 81 82 83 +85 86 87 88 89 8B 8C 8D 8E 8F 90 92 93 94 95 96 +97 99 9A 9B 9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 +AA AC AD AE AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC +BD BE C0 C1 C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF +D0 D1 D2 D4 D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 +E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF +DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD +CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA +B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 +A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 +93 92 90 8F 8E 8D 8C 8B 89 88 87 86 85 83 82 81 +80 7F 7E 7C 7B 7A 79 78 77 75 74 73 72 71 6F 6E +6D 6C 6B 6A 68 67 66 65 64 62 61 60 5F 5E 5D 5B +5A 59 58 57 56 54 53 52 51 50 4E 4D 4C 4B 4A 49 +47 46 45 44 43 41 40 3F 3E 3D 3C 3A 39 38 37 36 +35 33 32 31 30 2F 2D 2C 2B 2A 29 28 26 25 24 23 +22 20 1F 1E 1D 1C 1B 19 18 17 16 15 14 12 11 10 + F E C B A 9 8 7 5 4 3 2 1 2 3 4 + 5 7 8 9 A B C E F 10 11 12 14 15 16 17 +18 19 1B 1C 1D 1E 1F 20 22 23 24 25 26 28 29 2A +2B 2C 2D 2F 30 31 32 33 35 36 37 38 39 3A 3C 3D +3E 3F 40 41 43 44 45 46 47 49 4A 4B 4C 4D 4E 50 +51 52 53 54 56 57 58 59 5A 5B 5D 5E 5F 60 61 62 +64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 +77 78 79 7A 7B 7C 7E 7F 80 81 82 83 85 86 87 88 +89 8B 8C 8D 8E 8F 90 92 93 94 95 96 97 99 9A 9B +9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE +AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 +C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 +D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 +E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF DE DD DC DB +D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD CB CA C9 C8 +C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA B8 B7 B6 B5 +B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 A6 A4 A3 A2 +A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 93 92 90 8F +8E 8D 8C 8B 89 88 87 86 85 83 82 81 80 7F 7E 7C +7B 7A 79 78 77 75 74 73 72 71 6F 6E 6D 6C 6B 6A +68 67 66 65 64 62 61 60 5F 5E 5D 5B 5A 59 58 57 +56 54 53 52 51 50 4E 4D 4C 4B 4A 49 47 46 45 44 +43 41 40 3F 3E 3D 3C 3A 39 38 37 36 35 33 32 31 +30 2F 2D 2C 2B 2A 29 28 26 25 24 23 22 20 1F 1E +1D 1C 1B 19 18 17 16 15 14 12 11 10 F E C B + A 9 8 7 5 4 3 2 1 2 3 4 5 7 8 9 + A B C E F 10 11 12 14 15 16 17 18 19 1B 1C +1D 1E 1F 20 22 23 24 25 26 28 29 2A 2B 2C 2D 2F +30 31 32 33 35 36 37 38 39 3A 3C 3D 3E 3F 40 41 +43 44 45 46 47 49 4A 4B 4C 4D 4E 50 51 52 53 54 +56 57 58 59 5A 5B 5D 5E 5F 60 61 62 64 65 66 67 +68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 77 78 79 7A +7B 7C 7E 7F 80 81 82 83 85 86 87 88 89 8B 8C 8D +8E 8F 90 92 93 94 95 96 97 99 9A 9B 9C 9D 9F A0 +A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE AF B0 B1 B3 +B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 C2 C3 C4 C5 +C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 D5 D6 D7 D8 +D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 E8 E9 EA E9 +E8 E6 E5 E4 E3 E2 E1 DF DE DD DC DB D9 D8 D7 D6 +D5 D4 D2 D1 D0 CF CE CD CB CA C9 C8 C7 C5 C4 C3 +C2 C1 C0 BE BD BC BB BA B8 B7 B6 B5 B4 B3 B1 B0 +AF AE AD AC AA A9 A8 A7 A6 A4 A3 A2 A1 A0 9F 9D +9C 9B 9A 99 97 96 95 94 93 92 90 8F 8E 8D 8C 8B +89 88 87 86 85 83 82 81 80 7F 7E 7C 7B 7A 79 78 +77 75 74 73 72 71 6F 6E 6D 6C 6B 6A 68 67 66 65 +64 62 61 60 5F 5E 5D 5B 5A 59 58 57 56 54 53 52 +51 50 4E 4D 4C 4B 4A 49 47 46 45 44 43 41 40 3F +3E 3D 3C 3A 39 38 37 36 35 33 32 31 30 2F 2D 2C +2B 2A 29 28 26 25 24 23 22 20 1F 1E 1D 1C 1B 19 +18 17 16 15 14 12 11 10 F E C B A 9 8 7 + 5 4 3 2 1 2 3 4 5 7 8 9 A B C E + F 10 11 12 14 15 16 17 18 19 1B 1C 1D 1E 1F 20 +22 23 24 25 26 28 29 2A 2B 2C 2D 2F 30 31 32 33 +35 36 37 38 39 3A 3C 3D 3E 3F 40 41 43 44 45 46 +47 49 4A 4B 4C 4D 4E 50 51 52 53 54 56 57 58 59 +5A 5B 5D 5E 5F 60 61 62 64 65 66 67 68 6A 6B 6C +6D 6E 6F 71 72 73 74 75 77 78 79 7A 7B 7C 7E 7F +80 81 82 83 85 86 87 88 89 8B 8C 8D 8E 8F 90 92 +93 94 95 96 97 99 9A 9B 9C 9D 9F A0 A1 A2 A3 A4 +A6 A7 A8 A9 AA AC AD AE AF B0 B1 B3 B4 B5 B6 B7 +B8 BA BB BC BD BE C0 C1 C2 C3 C4 C5 C7 C8 C9 CA +CB CD CE CF D0 D1 D2 D4 D5 D6 D7 D8 D9 DB DC DD +DE DF E1 E2 E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 +E3 E2 E1 DF DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 +D0 CF CE CD CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE +BD BC BB BA B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC +AA A9 A8 A7 A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 +97 96 95 94 93 92 90 8F 8E 8D 8C 8B 89 88 87 86 +85 83 82 81 80 7F 7E 7C 7B 7A 79 78 77 75 74 73 +72 71 6F 6E 6D 6C 6B 6A 68 67 66 65 64 62 61 60 +5F 5E 5D 5B 5A 59 58 57 56 54 53 52 51 50 4E 4D +4C 4B 4A 49 47 46 45 44 43 41 40 3F 3E 3D 3C 3A +39 38 37 36 35 33 32 31 30 2F 2D 2C 2B 2A 29 28 +26 25 24 23 22 20 1F 1E 1D 1C 1B 19 18 17 16 15 +14 12 11 10 F E C B A 9 8 7 5 4 3 2 + 1 2 3 4 5 7 8 9 A B C E F 10 11 12 +14 15 16 17 18 19 1B 1C 1D 1E 1F 20 22 23 24 25 +26 28 29 2A 2B 2C 2D 2F 30 31 32 33 35 36 37 38 +39 3A 3C 3D 3E 3F 40 41 43 44 45 46 47 49 4A 4B +4C 4D 4E 50 51 52 53 54 56 57 58 59 5A 5B 5D 5E +5F 60 61 62 64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 +72 73 74 75 77 78 79 7A 7B 7C 7E 7F 80 81 82 83 +85 86 87 88 89 8B 8C 8D 8E 8F 90 92 93 94 95 96 +97 99 9A 9B 9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 +AA AC AD AE AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC +BD BE C0 C1 C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF +D0 D1 D2 D4 D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 +E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF +DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD +CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA +B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 +A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 +93 92 90 8F 8E 8D 8C 8B 89 88 87 86 85 83 82 81 +80 7F 7E 7C 7B 7A 79 78 77 75 74 73 72 71 6F 6E +6D 6C 6B 6A 68 67 66 65 64 62 61 60 5F 5E 5D 5B +5A 59 58 57 56 54 53 52 51 50 4E 4D 4C 4B 4A 49 +47 46 45 44 43 41 40 3F 3E 3D 3C 3A 39 38 37 36 +35 33 32 31 30 2F 2D 2C 2B 2A 29 28 26 25 24 23 +22 20 1F 1E 1D 1C 1B 19 18 17 16 15 14 12 11 10 + F E C B A 9 8 7 5 4 3 2 1 2 3 4 + 5 7 8 9 A B C E F 10 11 12 14 15 16 17 +18 19 1B 1C 1D 1E 1F 20 22 23 24 25 26 28 29 2A +2B 2C 2D 2F 30 31 32 33 35 36 37 38 39 3A 3C 3D +3E 3F 40 41 43 44 45 46 47 49 4A 4B 4C 4D 4E 50 +51 52 53 54 56 57 58 59 5A 5B 5D 5E 5F 60 61 62 +64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 +77 78 79 7A 7B 7C 7E 7F 80 81 82 83 85 86 87 88 +89 8B 8C 8D 8E 8F 90 92 93 94 95 96 97 99 9A 9B +9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE +AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 +C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 +D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 +E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF DE DD DC DB +D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD CB CA C9 C8 +C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA B8 B7 B6 B5 +B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 A6 A4 A3 A2 +A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 93 92 90 8F +8E 8D 8C 8B 89 88 87 86 85 83 82 81 80 7F 7E 7C +7B 7A 79 78 77 75 74 73 72 71 6F 6E 6D 6C 6B 6A +68 67 66 65 64 62 61 60 5F 5E 5D 5B 5A 59 58 57 +56 54 53 52 51 50 4E 4D 4C 4B 4A 49 47 46 45 44 +43 41 40 3F 3E 3D 3C 3A 39 38 37 36 35 33 32 31 +30 2F 2D 2C 2B 2A 29 28 26 25 24 23 22 20 1F 1E +1D 1C 1B 19 18 17 16 15 14 12 11 10 F E C B + A 9 8 7 5 4 3 2 1 2 3 4 5 7 8 9 + A B C E F 10 11 12 14 15 16 17 18 19 1B 1C +1D 1E 1F 20 22 23 24 25 26 28 29 2A 2B 2C 2D 2F +30 31 32 33 35 36 37 38 39 3A 3C 3D 3E 3F 40 41 +43 44 45 46 47 49 4A 4B 4C 4D 4E 50 51 52 53 54 +56 57 58 59 5A 5B 5D 5E 5F 60 61 62 64 65 66 67 +68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 77 78 79 7A +7B 7C 7E 7F 80 81 82 83 85 86 87 88 89 8B 8C 8D +8E 8F 90 92 93 94 95 96 97 99 9A 9B 9C 9D 9F A0 +A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE AF B0 B1 B3 +B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 C2 C3 C4 C5 +C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 D5 D6 D7 D8 +D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 E8 E9 EA E9 +E8 E6 E5 E4 E3 E2 E1 DF DE DD DC DB D9 D8 D7 D6 +D5 D4 D2 D1 D0 CF CE CD CB CA C9 C8 C7 C5 C4 C3 +C2 C1 C0 BE BD BC BB BA B8 B7 B6 B5 B4 B3 B1 B0 +AF AE AD AC AA A9 A8 A7 A6 A4 A3 A2 A1 A0 9F 9D +9C 9B 9A 99 97 96 95 94 93 92 90 8F 8E 8D 8C 8B +89 88 87 86 85 83 82 81 80 7F 7E 7C 7B 7A 79 78 +77 75 74 73 72 71 6F 6E 6D 6C 6B 6A 68 67 66 65 +64 62 61 60 5F 5E 5D 5B 5A 59 58 57 56 54 53 52 +51 50 4E 4D 4C 4B 4A 49 47 46 45 44 43 41 40 3F +3E 3D 3C 3A 39 38 37 36 35 33 32 31 30 2F 2D 2C +2B 2A 29 28 26 25 24 23 22 20 1F 1E 1D 1C 1B 19 +18 17 16 15 14 12 11 10 F E C B A 9 8 7 + 5 4 3 2 1 2 3 4 5 7 8 9 A B C E + F 10 11 12 14 15 16 17 18 19 1B 1C 1D 1E 1F 20 +22 23 24 25 26 28 29 2A 2B 2C 2D 2F 30 31 32 33 +35 36 37 38 39 3A 3C 3D 3E 3F 40 41 43 44 45 46 +47 49 4A 4B 4C 4D 4E 50 51 52 53 54 56 57 58 59 +5A 5B 5D 5E 5F 60 61 62 64 65 66 67 68 6A 6B 6C +6D 6E 6F 71 72 73 74 75 77 78 79 7A 7B 7C 7E 7F +80 81 82 83 85 86 87 88 89 8B 8C 8D 8E 8F 90 92 +93 94 95 96 97 99 9A 9B 9C 9D 9F A0 A1 A2 A3 A4 +A6 A7 A8 A9 AA AC AD AE AF B0 B1 B3 B4 B5 B6 B7 +B8 BA BB BC BD BE C0 C1 C2 C3 C4 C5 C7 C8 C9 CA +CB CD CE CF D0 D1 D2 D4 D5 D6 D7 D8 D9 DB DC DD +DE DF E1 E2 E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 +E3 E2 E1 DF DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 +D0 CF CE CD CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE +BD BC BB BA B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC +AA A9 A8 A7 A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 +97 96 95 94 93 92 90 8F 8E 8D 8C 8B 89 88 87 86 +85 83 82 81 80 7F 7E 7C 7B 7A 79 78 77 75 74 73 +72 71 6F 6E 6D 6C 6B 6A 68 67 66 65 64 62 61 60 +5F 5E 5D 5B 5A 59 58 57 56 54 53 52 51 50 4E 4D +4C 4B 4A 49 47 46 45 44 43 41 40 3F 3E 3D 3C 3A +39 38 37 36 35 33 32 31 30 2F 2D 2C 2B 2A 29 28 +26 25 24 23 22 20 1F 1E 1D 1C 1B 19 18 17 16 15 +14 12 11 10 F E C B A 9 8 7 5 4 3 2 + 1 2 3 4 5 7 8 9 A B C E F 10 11 12 +14 15 16 17 18 19 1B 1C 1D 1E 1F 20 22 23 24 25 +26 28 29 2A 2B 2C 2D 2F 30 31 32 33 35 36 37 38 +39 3A 3C 3D 3E 3F 40 41 43 44 45 46 47 49 4A 4B +4C 4D 4E 50 51 52 53 54 56 57 58 59 5A 5B 5D 5E +5F 60 61 62 64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 +72 73 74 75 77 78 79 7A 7B 7C 7E 7F 80 81 82 83 +85 86 87 88 89 8B 8C 8D 8E 8F 90 92 93 94 95 96 +97 99 9A 9B 9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 +AA AC AD AE AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC +BD BE C0 C1 C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF +D0 D1 D2 D4 D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 +E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF +DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD +CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA +B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 +A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 +93 92 90 8F 8E 8D 8C 8B 89 88 87 86 85 83 82 81 +80 7F 7E 7C 7B 7A 79 78 77 75 74 73 72 71 6F 6E +6D 6C 6B 6A 68 67 66 65 64 62 61 60 5F 5E 5D 5B +5A 59 58 57 56 54 53 52 51 50 4E 4D 4C 4B 4A 49 +47 46 45 44 43 41 40 3F 3E 3D 3C 3A 39 38 37 36 +35 33 32 31 30 2F 2D 2C 2B 2A 29 28 26 25 24 23 +22 20 1F 1E 1D 1C 1B 19 18 17 16 15 14 12 11 10 + F E C B A 9 8 7 5 4 3 2 1 2 3 4 + 5 7 8 9 A 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+E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF +DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD +CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA +B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 +A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 +93 92 90 8F 8E 8D 8C 8B 89 88 87 86 85 83 82 81 +80 7F 7E 7C 7B 7A 79 78 77 75 74 73 72 71 6F 6E +6D 6C 6B 6A 68 67 66 65 64 62 61 60 5F 5E 5D 5B +5A 59 58 57 56 54 53 52 51 50 4E 4D 4C 4B 4A 49 +47 46 45 44 43 41 40 3F 3E 3D 3C 3A 39 38 37 36 +35 33 32 31 30 2F 2D 2C 2B 2A 29 28 26 25 24 23 +22 20 1F 1E 1D 1C 1B 19 18 17 16 15 14 12 11 10 + F E C B A 9 8 7 5 4 3 2 1 2 3 4 + 5 7 8 9 A B C E F 10 11 12 14 15 16 17 +18 19 1B 1C 1D 1E 1F 20 22 23 24 25 26 28 29 2A +2B 2C 2D 2F 30 31 32 33 35 36 37 38 39 3A 3C 3D +3E 3F 40 41 43 44 45 46 47 49 4A 4B 4C 4D 4E 50 +51 52 53 54 56 57 58 59 5A 5B 5D 5E 5F 60 61 62 +64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 +77 78 79 7A 7B 7C 7E 7F 80 81 82 83 85 86 87 88 +89 8B 8C 8D 8E 8F 90 92 93 94 95 96 97 99 9A 9B +9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE +AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 +C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 +D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 +E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF DE DD DC DB +D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD CB CA C9 C8 +C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA B8 B7 B6 B5 +B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 A6 A4 A3 A2 +A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 93 92 90 8F +8E 8D 8C 8B 89 88 87 86 85 83 82 81 80 7F 7E 7C +7B 7A 79 78 77 75 74 73 72 71 6F 6E 6D 6C 6B 6A +68 67 66 65 64 62 61 60 5F 5E 5D 5B 5A 59 58 57 +56 54 53 52 51 50 4E 4D 4C 4B 4A 49 47 46 45 44 +43 41 40 3F 3E 3D 3C 3A 39 38 37 36 35 33 32 31 +30 2F 2D 2C 2B 2A 29 28 26 25 24 23 22 20 1F 1E +1D 1C 1B 19 18 17 16 15 14 12 11 10 F E C B + A 9 8 7 5 4 3 2 1 2 3 4 5 7 8 9 + A B C E F 10 11 12 14 15 16 17 18 19 1B 1C +1D 1E 1F 20 22 23 24 25 26 28 29 2A 2B 2C 2D 2F +30 31 32 33 35 36 37 38 39 3A 3C 3D 3E 3F 40 41 +43 44 45 46 47 49 4A 4B 4C 4D 4E 50 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D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD +CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA +B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 +A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 +93 92 90 8F 8E 8D 8C 8B 89 88 87 86 85 83 82 81 +80 7F 7E 7C 7B 7A 79 78 77 75 74 73 72 71 6F 6E +6D 6C 6B 6A 68 67 66 65 64 62 61 60 5F 5E 5D 5B +5A 59 58 57 56 54 53 52 51 50 4E 4D 4C 4B 4A 49 +47 46 45 44 43 41 40 3F 3E 3D 3C 3A 39 38 37 36 +35 33 32 31 30 2F 2D 2C 2B 2A 29 28 26 25 24 23 +22 20 1F 1E 1D 1C 1B 19 18 17 16 15 14 12 11 10 + F E C B A 9 8 7 5 4 3 2 1 2 3 4 + 5 7 8 9 A B C E F 10 11 12 14 15 16 17 +18 19 1B 1C 1D 1E 1F 20 22 23 24 25 26 28 29 2A +2B 2C 2D 2F 30 31 32 33 35 36 37 38 39 3A 3C 3D +3E 3F 40 41 43 44 45 46 47 49 4A 4B 4C 4D 4E 50 +51 52 53 54 56 57 58 59 5A 5B 5D 5E 5F 60 61 62 +64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 +77 78 79 7A 7B 7C 7E 7F 80 81 82 83 85 86 87 88 +89 8B 8C 8D 8E 8F 90 92 93 94 95 96 97 99 9A 9B +9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE +AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 +C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 +D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 +E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF DE DD DC DB +D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD CB CA C9 C8 +C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA B8 B7 B6 B5 +B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 A6 A4 A3 A2 +A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 93 92 90 8F +8E 8D 8C 8B 89 88 87 86 85 83 82 81 80 7F 7E 7C +7B 7A 79 78 77 75 74 73 72 71 6F 6E 6D 6C 6B 6A +68 67 66 65 64 62 61 60 5F 5E 5D 5B 5A 59 58 57 +56 54 53 52 51 50 4E 4D 4C 4B 4A 49 47 46 45 44 +43 41 40 3F 3E 3D 3C 3A 39 38 37 36 35 33 32 31 +30 2F 2D 2C 2B 2A 29 28 26 25 24 23 22 20 1F 1E +1D 1C 1B 19 18 17 16 15 14 12 11 10 F E C B + A 9 8 7 5 4 3 2 1 2 3 4 5 7 8 9 + A B C E F 10 11 12 14 15 16 17 18 19 1B 1C +1D 1E 1F 20 22 23 24 25 26 28 29 2A 2B 2C 2D 2F +30 31 32 33 35 36 37 38 39 3A 3C 3D 3E 3F 40 41 +43 44 45 46 47 49 4A 4B 4C 4D 4E 50 51 52 53 54 +56 57 58 59 5A 5B 5D 5E 5F 60 61 62 64 65 66 67 +68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 77 78 79 7A +7B 7C 7E 7F 80 81 82 83 85 86 87 88 89 8B 8C 8D +8E 8F 90 92 93 94 95 96 97 99 9A 9B 9C 9D 9F A0 +A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE AF B0 B1 B3 +B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 C2 C3 C4 C5 +C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 D5 D6 D7 D8 +D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 E8 E9 EA E9 +E8 E6 E5 E4 E3 E2 E1 DF DE DD DC DB D9 D8 D7 D6 +D5 D4 D2 D1 D0 CF CE CD CB CA C9 C8 C7 C5 C4 C3 +C2 C1 C0 BE BD BC BB BA B8 B7 B6 B5 B4 B3 B1 B0 +AF AE AD AC AA A9 A8 A7 A6 A4 A3 A2 A1 A0 9F 9D +9C 9B 9A 99 97 96 95 94 93 92 90 8F 8E 8D 8C 8B +89 88 87 86 85 83 82 81 80 7F 7E 7C 7B 7A 79 78 +77 75 74 73 72 71 6F 6E 6D 6C 6B 6A 68 67 66 65 +64 62 61 60 5F 5E 5D 5B 5A 59 58 57 56 54 53 52 +51 50 4E 4D 4C 4B 4A 49 47 46 45 44 43 41 40 3F +3E 3D 3C 3A 39 38 37 36 35 33 32 31 30 2F 2D 2C +2B 2A 29 28 26 25 24 23 22 20 1F 1E 1D 1C 1B 19 +18 17 16 15 14 12 11 10 F E C B A 9 8 7 + 5 4 3 2 1 2 3 4 5 7 8 9 A B C E + F 10 11 12 14 15 16 17 18 19 1B 1C 1D 1E 1F 20 +22 23 24 25 26 28 29 2A 2B 2C 2D 2F 30 31 32 33 +35 36 37 38 39 3A 3C 3D 3E 3F 40 41 43 44 45 46 +47 49 4A 4B 4C 4D 4E 50 51 52 53 54 56 57 58 59 +5A 5B 5D 5E 5F 60 61 62 64 65 66 67 68 6A 6B 6C +6D 6E 6F 71 72 73 74 75 77 78 79 7A 7B 7C 7E 7F +80 81 82 83 85 86 87 88 89 8B 8C 8D 8E 8F 90 92 +93 94 95 96 97 99 9A 9B 9C 9D 9F A0 A1 A2 A3 A4 +A6 A7 A8 A9 AA AC AD AE AF B0 B1 B3 B4 B5 B6 B7 +B8 BA BB BC BD BE C0 C1 C2 C3 C4 C5 C7 C8 C9 CA +CB CD CE CF D0 D1 D2 D4 D5 D6 D7 D8 D9 DB DC DD +DE DF E1 E2 E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 +E3 E2 E1 DF DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 +D0 CF CE CD CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE +BD BC BB BA B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC +AA A9 A8 A7 A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 +97 96 95 94 93 92 90 8F 8E 8D 8C 8B 89 88 87 86 +85 83 82 81 80 7F 7E 7C 7B 7A 79 78 77 75 74 73 +72 71 6F 6E 6D 6C 6B 6A 68 67 66 65 64 62 61 60 +5F 5E 5D 5B 5A 59 58 57 56 54 53 52 51 50 4E 4D +4C 4B 4A 49 47 46 45 44 43 41 40 3F 3E 3D 3C 3A +39 38 37 36 35 33 32 31 30 2F 2D 2C 2B 2A 29 28 +26 25 24 23 22 20 1F 1E 1D 1C 1B 19 18 17 16 15 +14 12 11 10 F E C B A 9 8 7 5 4 3 2 + 1 2 3 4 5 7 8 9 A B C E F 10 11 12 +14 15 16 17 18 19 1B 1C 1D 1E 1F 20 22 23 24 25 +26 28 29 2A 2B 2C 2D 2F 30 31 32 33 35 36 37 38 +39 3A 3C 3D 3E 3F 40 41 43 44 45 46 47 49 4A 4B +4C 4D 4E 50 51 52 53 54 56 57 58 59 5A 5B 5D 5E +5F 60 61 62 64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 +72 73 74 75 77 78 79 7A 7B 7C 7E 7F 80 81 82 83 +85 86 87 88 89 8B 8C 8D 8E 8F 90 92 93 94 95 96 +97 99 9A 9B 9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 +AA AC AD AE AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC +BD BE C0 C1 C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF +D0 D1 D2 D4 D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 +E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF +DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD +CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA +B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 +A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 +93 92 90 8F 8E 8D 8C 8B 89 88 87 86 85 83 82 81 +80 7F 7E 7C 7B 7A 79 78 77 75 74 73 72 71 6F 6E +6D 6C 6B 6A 68 67 66 65 64 62 61 60 5F 5E 5D 5B +5A 59 58 57 56 54 53 52 51 50 4E 4D 4C 4B 4A 49 +47 46 45 44 43 41 40 3F 3E 3D 3C 3A 39 38 37 36 +35 33 32 31 30 2F 2D 2C 2B 2A 29 28 26 25 24 23 +22 20 1F 1E 1D 1C 1B 19 18 17 16 15 14 12 11 10 + F E C B A 9 8 7 5 4 3 2 1 2 3 4 + 5 7 8 9 A B C E F 10 11 12 14 15 16 17 +18 19 1B 1C 1D 1E 1F 20 22 23 24 25 26 28 29 2A +2B 2C 2D 2F 30 31 32 33 35 36 37 38 39 3A 3C 3D +3E 3F 40 41 43 44 45 46 47 49 4A 4B 4C 4D 4E 50 +51 52 53 54 56 57 58 59 5A 5B 5D 5E 5F 60 61 62 +64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 +77 78 79 7A 7B 7C 7E 7F 80 81 82 83 85 86 87 88 +89 8B 8C 8D 8E 8F 90 92 93 94 95 96 97 99 9A 9B +9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE +AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 +C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 +D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 +E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF DE DD DC DB +D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD CB CA C9 C8 +C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA B8 B7 B6 B5 +B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 A6 A4 A3 A2 +A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 93 92 90 8F +8E 8D 8C 8B 89 88 87 86 85 83 82 81 80 7F 7E 7C +7B 7A 79 78 77 75 74 73 72 71 6F 6E 6D 6C 6B 6A +68 67 66 65 64 62 61 60 5F 5E 5D 5B 5A 59 58 57 +56 54 53 52 51 50 4E 4D 4C 4B 4A 49 47 46 45 44 +43 41 40 3F 3E 3D 3C 3A 39 38 37 36 35 33 32 31 +30 2F 2D 2C 2B 2A 29 28 26 25 24 23 22 20 1F 1E +1D 1C 1B 19 18 17 16 15 14 12 11 10 F E C B + A 9 8 7 5 4 3 2 1 2 3 4 5 7 8 9 + A B C E F 10 11 12 14 15 16 17 18 19 1B 1C +1D 1E 1F 20 22 23 24 25 26 28 29 2A 2B 2C 2D 2F +30 31 32 33 35 36 37 38 39 3A 3C 3D 3E 3F 40 41 +43 44 45 46 47 49 4A 4B 4C 4D 4E 50 51 52 53 54 +56 57 58 59 5A 5B 5D 5E 5F 60 61 62 64 65 66 67 +68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 77 78 79 7A +7B 7C 7E 7F 80 81 82 83 85 86 87 88 89 8B 8C 8D +8E 8F 90 92 93 94 95 96 97 99 9A 9B 9C 9D 9F A0 +A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE AF B0 B1 B3 +B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 C2 C3 C4 C5 +C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 D5 D6 D7 D8 +D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 E8 E9 EA E9 +E8 E6 E5 E4 E3 E2 E1 DF DE DD DC DB D9 D8 D7 D6 +D5 D4 D2 D1 D0 CF CE CD CB CA C9 C8 C7 C5 C4 C3 +C2 C1 C0 BE BD BC BB BA B8 B7 B6 B5 B4 B3 B1 B0 +AF AE AD AC AA A9 A8 A7 A6 A4 A3 A2 A1 A0 9F 9D +9C 9B 9A 99 97 96 95 94 93 92 90 8F 8E 8D 8C 8B +89 88 87 86 85 83 82 81 80 7F 7E 7C 7B 7A 79 78 +77 75 74 73 72 71 6F 6E 6D 6C 6B 6A 68 67 66 65 +64 62 61 60 5F 5E 5D 5B 5A 59 58 57 56 54 53 52 +51 50 4E 4D 4C 4B 4A 49 47 46 45 44 43 41 40 3F +3E 3D 3C 3A 39 38 37 36 35 33 32 31 30 2F 2D 2C +2B 2A 29 28 26 25 24 23 22 20 1F 1E 1D 1C 1B 19 +18 17 16 15 14 12 11 10 F E C B A 9 8 7 + 5 4 3 2 1 2 3 4 5 7 8 9 A B C E + F 10 11 12 14 15 16 17 18 19 1B 1C 1D 1E 1F 20 +22 23 24 25 26 28 29 2A 2B 2C 2D 2F 30 31 32 33 +35 36 37 38 39 3A 3C 3D 3E 3F 40 41 43 44 45 46 +47 49 4A 4B 4C 4D 4E 50 51 52 53 54 56 57 58 59 +5A 5B 5D 5E 5F 60 61 62 64 65 66 67 68 6A 6B 6C +6D 6E 6F 71 72 73 74 75 77 78 79 7A 7B 7C 7E 7F +80 81 82 83 85 86 87 88 89 8B 8C 8D 8E 8F 90 92 +93 94 95 96 97 99 9A 9B 9C 9D 9F A0 A1 A2 A3 A4 +A6 A7 A8 A9 AA AC AD AE AF B0 B1 B3 B4 B5 B6 B7 +B8 BA BB BC BD BE C0 C1 C2 C3 C4 C5 C7 C8 C9 CA +CB CD CE CF D0 D1 D2 D4 D5 D6 D7 D8 D9 DB DC DD +DE DF E1 E2 E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 +E3 E2 E1 DF DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 +D0 CF CE CD CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE +BD BC BB BA B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC +AA A9 A8 A7 A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 +97 96 95 94 93 92 90 8F 8E 8D 8C 8B 89 88 87 86 +85 83 82 81 80 7F 7E 7C 7B 7A 79 78 77 75 74 73 +72 71 6F 6E 6D 6C 6B 6A 68 67 66 65 64 62 61 60 +5F 5E 5D 5B 5A 59 58 57 56 54 53 52 51 50 4E 4D +4C 4B 4A 49 47 46 45 44 43 41 40 3F 3E 3D 3C 3A +39 38 37 36 35 33 32 31 30 2F 2D 2C 2B 2A 29 28 +26 25 24 23 22 20 1F 1E 1D 1C 1B 19 18 17 16 15 +14 12 11 10 F E C B A 9 8 7 5 4 3 2 + 1 2 3 4 5 7 8 9 A B C E F 10 11 12 +14 15 16 17 18 19 1B 1C 1D 1E 1F 20 22 23 24 25 +26 28 29 2A 2B 2C 2D 2F 30 31 32 33 35 36 37 38 +39 3A 3C 3D 3E 3F 40 41 43 44 45 46 47 49 4A 4B +4C 4D 4E 50 51 52 53 54 56 57 58 59 5A 5B 5D 5E +5F 60 61 62 64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 +72 73 74 75 77 78 79 7A 7B 7C 7E 7F 80 81 82 83 +85 86 87 88 89 8B 8C 8D 8E 8F 90 92 93 94 95 96 +97 99 9A 9B 9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 +AA AC AD AE AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC +BD BE C0 C1 C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF +D0 D1 D2 D4 D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 +E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF +DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD +CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA +B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 +A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 +93 92 90 8F 8E 8D 8C 8B 89 88 87 86 85 83 82 81 +80 7F 7E 7C 7B 7A 79 78 77 75 74 73 72 71 6F 6E +6D 6C 6B 6A 68 67 66 65 64 62 61 60 5F 5E 5D 5B +5A 59 58 57 56 54 53 52 51 50 4E 4D 4C 4B 4A 49 +47 46 45 44 43 41 40 3F 3E 3D 3C 3A 39 38 37 36 +35 33 32 31 30 2F 2D 2C 2B 2A 29 28 26 25 24 23 +22 20 1F 1E 1D 1C 1B 19 18 17 16 15 14 12 11 10 + F E C B A 9 8 7 5 4 3 2 1 2 3 4 + 5 7 8 9 A B C E F 10 11 12 14 15 16 17 +18 19 1B 1C 1D 1E 1F 20 22 23 24 25 26 28 29 2A +2B 2C 2D 2F 30 31 32 33 35 36 37 38 39 3A 3C 3D +3E 3F 40 41 43 44 45 46 47 49 4A 4B 4C 4D 4E 50 +51 52 53 54 56 57 58 59 5A 5B 5D 5E 5F 60 61 62 +64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 +77 78 79 7A 7B 7C 7E 7F 80 81 82 83 85 86 87 88 +89 8B 8C 8D 8E 8F 90 92 93 94 95 96 97 99 9A 9B +9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE +AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 +C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 +D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 +E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF DE DD DC DB +D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD CB CA C9 C8 +C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA B8 B7 B6 B5 +B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 A6 A4 A3 A2 +A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 93 92 90 8F +8E 8D 8C 8B 89 88 87 86 85 83 82 81 80 7F 7E 7C +7B 7A 79 78 77 75 74 73 72 71 6F 6E 6D 6C 6B 6A +68 67 66 65 64 62 61 60 5F 5E 5D 5B 5A 59 58 57 +56 54 53 52 51 50 4E 4D 4C 4B 4A 49 47 46 45 44 +43 41 40 3F 3E 3D 3C 3A 39 38 37 36 35 33 32 31 +30 2F 2D 2C 2B 2A 29 28 26 25 24 23 22 20 1F 1E +1D 1C 1B 19 18 17 16 15 14 12 11 10 F E C B + A 9 8 7 5 4 3 2 1 2 3 4 5 7 8 9 + A B C E F 10 11 12 14 15 16 17 18 19 1B 1C +1D 1E 1F 20 22 23 24 25 26 28 29 2A 2B 2C 2D 2F +30 31 32 33 35 36 37 38 39 3A 3C 3D 3E 3F 40 41 +43 44 45 46 47 49 4A 4B 4C 4D 4E 50 51 52 53 54 +56 57 58 59 5A 5B 5D 5E 5F 60 61 62 64 65 66 67 +68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 77 78 79 7A +7B 7C 7E 7F 80 81 82 83 85 86 87 88 89 8B 8C 8D +8E 8F 90 92 93 94 95 96 97 99 9A 9B 9C 9D 9F A0 +A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE AF B0 B1 B3 +B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 C2 C3 C4 C5 +C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 D5 D6 D7 D8 +D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 E8 E9 EA E9 +E8 E6 E5 E4 E3 E2 E1 DF DE DD DC DB D9 D8 D7 D6 +D5 D4 D2 D1 D0 CF CE CD CB CA C9 C8 C7 C5 C4 C3 +C2 C1 C0 BE BD BC BB BA B8 B7 B6 B5 B4 B3 B1 B0 +AF AE AD AC AA A9 A8 A7 A6 A4 A3 A2 A1 A0 9F 9D +9C 9B 9A 99 97 96 95 94 93 92 90 8F 8E 8D 8C 8B +89 88 87 86 85 83 82 81 80 7F 7E 7C 7B 7A 79 78 +77 75 74 73 72 71 6F 6E 6D 6C 6B 6A 68 67 66 65 +64 62 61 60 5F 5E 5D 5B 5A 59 58 57 56 54 53 52 +51 50 4E 4D 4C 4B 4A 49 47 46 45 44 43 41 40 3F +3E 3D 3C 3A 39 38 37 36 35 33 32 31 30 2F 2D 2C +2B 2A 29 28 26 25 24 23 22 20 1F 1E 1D 1C 1B 19 +18 17 16 15 14 12 11 10 F E C B A 9 8 7 + 5 4 3 2 1 2 3 4 5 7 8 9 A B C E + F 10 11 12 14 15 16 17 18 19 1B 1C 1D 1E 1F 20 +22 23 24 25 26 28 29 2A 2B 2C 2D 2F 30 31 32 33 +35 36 37 38 39 3A 3C 3D 3E 3F 40 41 43 44 45 46 +47 49 4A 4B 4C 4D 4E 50 51 52 53 54 56 57 58 59 +5A 5B 5D 5E 5F 60 61 62 64 65 66 67 68 6A 6B 6C +6D 6E 6F 71 72 73 74 75 77 78 79 7A 7B 7C 7E 7F +80 81 82 83 85 86 87 88 89 8B 8C 8D 8E 8F 90 92 +93 94 95 96 97 99 9A 9B 9C 9D 9F A0 A1 A2 A3 A4 +A6 A7 A8 A9 AA AC AD AE AF B0 B1 B3 B4 B5 B6 B7 +B8 BA BB BC BD BE C0 C1 C2 C3 C4 C5 C7 C8 C9 CA +CB CD CE CF D0 D1 D2 D4 D5 D6 D7 D8 D9 DB DC DD +DE DF E1 E2 E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 +E3 E2 E1 DF DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 +D0 CF CE CD CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE +BD BC BB BA B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC +AA A9 A8 A7 A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 +97 96 95 94 93 92 90 8F 8E 8D 8C 8B 89 88 87 86 +85 83 82 81 80 7F 7E 7C 7B 7A 79 78 77 75 74 73 +72 71 6F 6E 6D 6C 6B 6A 68 67 66 65 64 62 61 60 +5F 5E 5D 5B 5A 59 58 57 56 54 53 52 51 50 4E 4D +4C 4B 4A 49 47 46 45 44 43 41 40 3F 3E 3D 3C 3A +39 38 37 36 35 33 32 31 30 2F 2D 2C 2B 2A 29 28 +26 25 24 23 22 20 1F 1E 1D 1C 1B 19 18 17 16 15 +14 12 11 10 F E C B A 9 8 7 5 4 3 2 + 1 2 3 4 5 7 8 9 A B C E F 10 11 12 +14 15 16 17 18 19 1B 1C 1D 1E 1F 20 22 23 24 25 +26 28 29 2A 2B 2C 2D 2F 30 31 32 33 35 36 37 38 +39 3A 3C 3D 3E 3F 40 41 43 44 45 46 47 49 4A 4B +4C 4D 4E 50 51 52 53 54 56 57 58 59 5A 5B 5D 5E +5F 60 61 62 64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 +72 73 74 75 77 78 79 7A 7B 7C 7E 7F 80 81 82 83 +85 86 87 88 89 8B 8C 8D 8E 8F 90 92 93 94 95 96 +97 99 9A 9B 9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 +AA AC AD AE AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC +BD BE C0 C1 C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF +D0 D1 D2 D4 D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 +E3 E4 E5 E6 E8 E9 EA E9 E8 E6 E5 E4 E3 E2 E1 DF +DE DD DC DB D9 D8 D7 D6 D5 D4 D2 D1 D0 CF CE CD +CB CA C9 C8 C7 C5 C4 C3 C2 C1 C0 BE BD BC BB BA +B8 B7 B6 B5 B4 B3 B1 B0 AF AE AD AC AA A9 A8 A7 +A6 A4 A3 A2 A1 A0 9F 9D 9C 9B 9A 99 97 96 95 94 +93 92 90 8F 8E 8D 8C 8B 89 88 87 86 85 83 82 81 +80 7F 7E 7C 7B 7A 79 78 77 75 74 73 72 71 6F 6E +6D 6C 6B 6A 68 67 66 65 64 62 61 60 5F 5E 5D 5B +5A 59 58 57 56 54 53 52 51 50 4E 4D 4C 4B 4A 49 +47 46 45 44 43 41 40 3F 3E 3D 3C 3A 39 38 37 36 +35 33 32 31 30 2F 2D 2C 2B 2A 29 28 26 25 24 23 +22 20 1F 1E 1D 1C 1B 19 18 17 16 15 14 12 11 10 + F E C B A 9 8 7 5 4 3 2 1 2 3 4 + 5 7 8 9 A B C E F 10 11 12 14 15 16 17 +18 19 1B 1C 1D 1E 1F 20 22 23 24 25 26 28 29 2A +2B 2C 2D 2F 30 31 32 33 35 36 37 38 39 3A 3C 3D +3E 3F 40 41 43 44 45 46 47 49 4A 4B 4C 4D 4E 50 +51 52 53 54 56 57 58 59 5A 5B 5D 5E 5F 60 61 62 +64 65 66 67 68 6A 6B 6C 6D 6E 6F 71 72 73 74 75 +77 78 79 7A 7B 7C 7E 7F 80 81 82 83 85 86 87 88 +89 8B 8C 8D 8E 8F 90 92 93 94 95 96 97 99 9A 9B +9C 9D 9F A0 A1 A2 A3 A4 A6 A7 A8 A9 AA AC AD AE +AF B0 B1 B3 B4 B5 B6 B7 B8 BA BB BC BD BE C0 C1 +C2 C3 C4 C5 C7 C8 C9 CA CB CD CE CF D0 D1 D2 D4 +D5 D6 D7 D8 D9 DB DC DD DE DF E1 E2 E3 E4 E5 E6 diff --git a/repo/tb/tests/base_testbench.h b/repo/tb/tests/base_testbench.h deleted file mode 100644 index ef94861..0000000 --- a/repo/tb/tests/base_testbench.h +++ /dev/null @@ -1,44 +0,0 @@ -#pragma once - -#include - -#include "Vdut.h" -#include "verilated.h" -#include "verilated_vcd_c.h" -#include "gtest/gtest.h" - -#define MAX_SIM_CYCLES 10000 - -extern unsigned int ticks; - -class BaseTestbench : public ::testing::Test -{ -public: - void SetUp() override - { - top = std::make_unique(); -#ifndef __APPLE__ - tfp = std::make_unique(); - Verilated::traceEverOn(true); - top->trace(tfp.get(), 99); - tfp->open("waveform.vcd"); -#endif - initializeInputs(); - } - - void TearDown() override - { - top->final(); -#ifndef __APPLE__ - tfp->close(); -#endif - } - - virtual void initializeInputs() = 0; - -protected: - std::unique_ptr top; -#ifndef __APPLE__ - std::unique_ptr tfp; -#endif -}; \ No newline at end of file diff --git a/repo/tb/tests/cpu_testbench.h b/repo/tb/tests/cpu_testbench.h new file mode 100644 index 0000000..b60333a --- /dev/null +++ b/repo/tb/tests/cpu_testbench.h @@ -0,0 +1,99 @@ +#pragma once + +#include + +#include "Vdut.h" +#include "verilated.h" +#include "verilated_vcd_c.h" +#include "gtest/gtest.h" + +#define MAX_SIM_CYCLES 10000 + +class CpuTestbench : public ::testing::Test +{ +public: + void SetUp() override + { + // Create new context for simulation + context_ = new VerilatedContext; + ticks_ = 0; + } + + void setupTest(const std::string &name) + { + name_ = name; + // Assemble the program + std::ignore = system(("./assemble.sh asm/" + name_ + ".s").c_str()); + // Create default empty file for data memory + std::ignore = system("touch data.hex"); + } + + // CPU instantiated outside of SetUp to allow for correct + // program to be assembled and loaded into instruction memory + void initSimulation() + { + top_ = new Vdut(context_); + tfp_ = new VerilatedVcdC; + + // Initialise trace and simulation + Verilated::traceEverOn(true); + top_->trace(tfp_, 99); + tfp_->open(("test_out/" + name_ + "/waveform.vcd").c_str()); + + // Initialise inputs + top_->clk = 1; + top_->rst = 1; + top_->trigger = 0; + runSimulation(10); // Process reset + top_->rst = 0; + } + + // Runs the simulation for a clock cycle, evaluates the DUT, dumps waveform. + void runSimulation(int cycles = 1) + { + for (int i = 0; i < cycles; i++) + { + for (int clk = 0; clk < 2; clk++) + { + top_->eval(); + tfp_->dump(2 * ticks_ + clk); + top_->clk = !top_->clk; + } + ticks_++; + + if (Verilated::gotFinish()) + { + exit(0); + } + } + } + + void TearDown() override + { + // End trace and simulation + top_->final(); + tfp_->close(); + + // Free memory + if (top_) delete top_; + if (tfp_) delete tfp_; + delete context_; + + // Save data and program memory files to test_out directory + std::ignore = system(("mv data.hex test_out/" + name_ + "/data.hex").c_str()); + std::ignore = system(("mv program.hex test_out/" + name_ + "/program.hex").c_str()); + } + + void setData(const std::string &data_file) + { + // Fill data.hex with program data + std::ignore = system(("cp " + data_file + " data.hex").c_str()); + } + +protected: + VerilatedContext* context_; + Vdut* top_; + VerilatedVcdC* tfp_; + std::string name_; + unsigned int ticks_; +}; diff --git a/repo/tb/tests/mux_tb.cpp b/repo/tb/tests/mux_tb.cpp deleted file mode 100644 index 74c07a7..0000000 --- a/repo/tb/tests/mux_tb.cpp +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Verifies the results of the mux, exits with a 0 on success. - */ - -#include "base_testbench.h" - -Vdut *top; -VerilatedVcdC *tfp; -unsigned int ticks = 0; - -class MuxTestbench : public BaseTestbench -{ -protected: - void initializeInputs() override - { - top->sel = 0; - top->in0 = 0; - top->in1 = 0; - // output: out - } -}; - -TEST_F(MuxTestbench, Mux0WorksTest) -{ - top->sel = 0; - top->in0 = 1; - top->in1 = 0; - - top->eval(); - - EXPECT_EQ(top->out, 1); -} - -TEST_F(MuxTestbench, Mux1WorksTest) -{ - top->sel = 1; - top->in0 = 0; - top->in1 = 1; - - top->eval(); - - EXPECT_EQ(top->out, 1); -} - -int main(int argc, char **argv) -{ - top = new Vdut; - tfp = new VerilatedVcdC; - - Verilated::traceEverOn(true); - top->trace(tfp, 99); - tfp->open("waveform.vcd"); - - testing::InitGoogleTest(&argc, argv); - auto res = RUN_ALL_TESTS(); - - top->final(); - tfp->close(); - - delete top; - delete tfp; - - return res; -} diff --git a/repo/tb/tests/testbench.h b/repo/tb/tests/testbench.h deleted file mode 100644 index c37558c..0000000 --- a/repo/tb/tests/testbench.h +++ /dev/null @@ -1,39 +0,0 @@ -#pragma once - -#include "base_testbench.h" - -/** - * Class only exists because top->clk is not always accessible in the testbench, - * and will otherwise not compile. - */ -class Testbench : public BaseTestbench -{ -public: - // Runs the simulation for a clock cycle, evaluates the DUT, dumps waveform. - void runSimulation(int cycles = 1) - { - for (int i = 0; i < cycles; i++) - { - for (int clk = 0; clk < 2; clk++) - { - top->eval(); -#ifndef __APPLE__ - tfp->dump(2 * ticks + clk); -#endif - top->clk = !top->clk; - } - ticks++; - - if (Verilated::gotFinish()) - { - exit(0); - } - } - } - - void compile(const std::string &program) - { - // Compile - system(("./compile.sh " + program).c_str()); - } -}; \ No newline at end of file diff --git a/repo/tb/tests/verify.cpp b/repo/tb/tests/verify.cpp index b2168ed..ba210ae 100644 --- a/repo/tb/tests/verify.cpp +++ b/repo/tb/tests/verify.cpp @@ -1,49 +1,50 @@ -#include "testbench.h" #include +#include + +#include "cpu_testbench.h" #define CYCLES 10000 -unsigned int ticks = 0; +TEST_F(CpuTestbench, TestAddiBne) +{ + setupTest("1_addi_bne"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 254); +} + +TEST_F(CpuTestbench, TestLiAdd) +{ + setupTest("2_li_add"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 1000); +} -class CpuTestbench : public Testbench +TEST_F(CpuTestbench, TestLbuSb) { -protected: - void initializeInputs() override - { - top->clk = 1; - top->rst = 0; - } -}; - -TEST_F(CpuTestbench, BaseProgramTest) + setupTest("3_lbu_sb"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 300); +} + +TEST_F(CpuTestbench, TestJalRet) { - bool success = false; - system("./compile.sh asm/program.S"); - - for (int i = 0; i < CYCLES; i++) - { - runSimulation(1); - if (top->a0 == 254) - { - SUCCEED(); - success = true; - break; - } - } - if (!success) - { - FAIL() << "Counter did not reach 254"; - } + setupTest("4_jal_ret"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 53); } -// Note this is how we are going to test your CPU. Do not worry about this for -// now, as it requires a lot more instructions to function -// TEST_F(CpuTestbench, Return5Test) -// { -// system("./compile.sh c/return_5.c"); -// runSimulation(100); -// EXPECT_EQ(top->a0, 5); -// } +TEST_F(CpuTestbench, TestPdf) +{ + setupTest("5_pdf"); + setData("reference/gaussian.mem"); + initSimulation(); + runSimulation(CYCLES * 100); + EXPECT_EQ(top_->a0, 15363); +} int main(int argc, char **argv) { diff --git a/repo/tb/verification.md b/repo/tb/verification.md new file mode 100644 index 0000000..81464f3 --- /dev/null +++ b/repo/tb/verification.md @@ -0,0 +1,48 @@ +

+ +## EIE2 Instruction Set Architecture & Compiler (IAC) + +--- +## Verification of the CPU + +**Ryan Voecks, V2.0 - 25 Nov 2024** + +--- + +
+ +## Quick Start + +The verification testing in this repository is significantly different from Lab 4. You will need to copy the new `tb` folder to your coursework repository. + +To run the tests, run the `doit.sh` script in this folder. + +**IMPORTANT - Your code must meet the following requirements for the script to work properly:** +1. Your RTL must be in a top-level folder called `rtl`. +2. The top-level module of your RTL must have the following interface: +```sv +module top ( + input logic clk, + input logic rst, + input logic trigger, + output logic [31:0] a0 +); + +endmodule +``` +3. Your instruction memory must load the file `"program.hex"`. +4. Your data memory must load the file `"data.hex"`. + +To keep the RTL consistent, it is recommended to use a shell script that moves the correct hex instructions and data into `"program.hex"` and `"data.hex"` when testing the PDF and F1 starting lights for Vbuddy. + +## Explanation of the tests + +The `doit.sh` script compiles a verilator model of your RTL, using the `src/verify.cpp` testbench. The following steps are then taken for each test program: +1. Assemble the program. +2. Load the program (and data if needed) into the CPU memory. +3. Run the verilator model for many cycles. +4. Check if the return value (a0) matches the expected value. + +The verilator-generated `obj_dir` is stored in `tb/test_out`, along with the waveform, hex and disassembly for each test. + +You are free to add more tests if it helps with your testing, but you are only required to pass the tests given in this repository (alongside PDF and F1 programs on Vbuddy). From 2ac9bc4e1975e72665493730ead30ecbf62ebf9c Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Fri, 21 Nov 2025 22:36:30 +0000 Subject: [PATCH 21/65] Added f1.s --- repo/tb/asm/f1.s | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 repo/tb/asm/f1.s diff --git a/repo/tb/asm/f1.s b/repo/tb/asm/f1.s new file mode 100644 index 0000000..b7e4ac5 --- /dev/null +++ b/repo/tb/asm/f1.s @@ -0,0 +1,48 @@ +.text +.globl main +main: + li t1, 0 + li t2, 0x12345678 + li a0, 0 + +light_loop: + slli t1, t1, 1 + ori t1, t1, 1 + + addi a0, t1, 0 + + jal ra, fixed_delay + + li t3, 0xFF + bne t1, t3, light_loop + + addi t1, t2, 0 + jal ra, random_delay + addi t2, t1, 0 + + li a0, 0 + +fixed_delay: + li t0, 50000 +fixed_loop: + addi t0, t0, -1 + bne t0, zero, fixed_loop + jalr x0, ra, 0 + +random_delay: + slli t4, t1, 7 + xor t1, t1, t4 + + srli t4, t1, 9 + xor t1, t1, t4 + + slli t4, t1, 8 + xor t1, t1, t4 + + andi t0, t1, 0x3FF + +random_loop: + addi t0, t0, -1 + bne t0, zero, random_loop + + jalr x0, ra, 0 \ No newline at end of file From 61362c8c3a0bee57479026e4b18b466a4bd8c749 Mon Sep 17 00:00:00 2001 From: minimish1 Date: Sun, 23 Nov 2025 19:45:40 +0000 Subject: [PATCH 22/65] Fixed imem.sv --- repo/rtl/imem.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/repo/rtl/imem.sv b/repo/rtl/imem.sv index 1076e55..2002c35 100644 --- a/repo/rtl/imem.sv +++ b/repo/rtl/imem.sv @@ -8,7 +8,7 @@ module imem ( logic [31:0] mem [0:255]; initial begin - $readmemh("program.hex", mem); + $readmemh("../rtl/program.hex", mem); end assign instr = mem[addr[9:2]]; From b5735ece4489725c1ddf8ac2432ad2c82a8c3e59 Mon Sep 17 00:00:00 2001 From: minimish1 Date: Sun, 23 Nov 2025 22:42:58 +0000 Subject: [PATCH 23/65] Added opcode instructions and updated data_unit with data_mem --- repo/rtl/data_mem.sv | 23 +++++++++++++ repo/rtl/data_unit.sv | 30 ++++++++++++++--- repo/rtl/main_decoder.sv | 73 ++++++++++++++++++++++++++++++++++------ repo/rtl/top.sv | 4 ++- 4 files changed, 113 insertions(+), 17 deletions(-) create mode 100644 repo/rtl/data_mem.sv diff --git a/repo/rtl/data_mem.sv b/repo/rtl/data_mem.sv new file mode 100644 index 0000000..43330e5 --- /dev/null +++ b/repo/rtl/data_mem.sv @@ -0,0 +1,23 @@ +module data_mem #( + parameter DATA_WIDTH = 32, + ADDRESS_WIDTH = 32 +) ( + input logic clk, + input logic en, // write enable + input logic [ADDRESS_WIDTH-1:0] wr_addr, // memory address + input logic [DATA_WIDTH-1:0] din, // data to write + output logic [DATA_WIDTH-1:0] dout // data read +); + + // 2^32 32-bit memory locations + logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; + + assign dout = ram_array[wr_addr]; // read data from memory assynchronously + + always_ff @(posedge clk) begin + if (en == 1'b1) begin + ram_array[wr_addr] <= din; // write data to memory synchronously + end + end + +endmodule \ No newline at end of file diff --git a/repo/rtl/data_unit.sv b/repo/rtl/data_unit.sv index 689e82d..dd44727 100644 --- a/repo/rtl/data_unit.sv +++ b/repo/rtl/data_unit.sv @@ -7,9 +7,11 @@ module data_unit #( input logic [ADDRESS_WIDTH-1:0] AD2, // rs2 address input logic [ADDRESS_WIDTH-1:0] AD3, // rd address input logic [DATA_WIDTH-1:0] ImmOp, // immediate value - input logic RegWrite, // write enable + input logic RegWrite, // write enable to register file + input logic MemWrite, // write enable to memory input logic ALUctrl, // ALU control input logic ALUsrc, // select imm or reg + input logic ResultSrc, // select ALU or mem data output logic EQ, // ALU equality flag output logic [DATA_WIDTH-1:0] a0 // x10 output ); @@ -17,7 +19,9 @@ module data_unit #( logic [DATA_WIDTH-1:0] ALUout; // ALU result logic [DATA_WIDTH-1:0] ALUop1; // ALU operand 1 logic [DATA_WIDTH-1:0] ALUop2; // ALU operand 2 -logic [DATA_WIDTH-1:0] regOp2; // register file operand 2 +logic [DATA_WIDTH-1:0] WriteData; // register file output 2 +logic [DATA_WIDTH-1:0] ReadData; // data memory output +logic [DATA_WIDTH-1:0] result; // data to write back to register file // register file: read rs1/rs2, write rd reg_file reg_file ( @@ -28,13 +32,13 @@ reg_file reg_file ( .wd3(ALUout), .we3(RegWrite), .dout1(ALUop1), - .dout2(regOp2), + .dout2(WriteData), .a0(a0) ); // select ALU operand 2: register or immediate -mux mux ( - .in0(regOp2), +mux mux1 ( + .in0(WriteData), .in1(ImmOp), .sel(ALUsrc), .out(ALUop2) @@ -49,4 +53,20 @@ alu alu ( .eq(EQ) ); +// memory +data_mem data_mem ( + .clk(clk), + .en(MemWrite), + .wr_addr(ALUout), + .din(WriteData), + .dout(ReadData) +); + +mux mux2 ( + .in0(ALUout), + .in1(ReadData), + .sel(ResultSrc), + .out(result) +); + endmodule diff --git a/repo/rtl/main_decoder.sv b/repo/rtl/main_decoder.sv index b23e37d..29c84d6 100644 --- a/repo/rtl/main_decoder.sv +++ b/repo/rtl/main_decoder.sv @@ -1,6 +1,6 @@ module main_decoder ( input logic [6:0] opcode, // 7-bit opcode field from the instruction - output logic ResultsSrc, // selects data written to register file (ALU result or memory data) + output logic ResultSrc, // selects data written to register file (ALU result or memory data) output logic MemWrite, // enable writing to data memory output logic ALUsrc, // selects ALU second operand (0 = register, 1 = immediate) output logic RegWrite, // enable writing to register file @@ -13,9 +13,9 @@ module main_decoder ( always_comb begin case(opcode) - // load instructions (e.g., LW) + // load instructions: LB, LH, LW, LBU, LHU 7'b0000011: begin - ResultsSrc = 1; + ResultSrc = 1; MemWrite = 0; ALUsrc = 1; RegWrite = 1; @@ -24,9 +24,9 @@ always_comb begin ALUop = 2'b00; end - // store instructions (e.g., SW) + // store instructions: SB, SH, SW 7'b0100011: begin - ResultsSrc = X; + ResultSrc = 0; // don't care MemWrite = 1; ALUsrc = 1; RegWrite = 0; @@ -35,20 +35,20 @@ always_comb begin ALUop = 2'b00; end - // R-type instructions (e.g., ADD, SUB) + // R-type instructions: ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND 7'b0110011: begin - ResultsSrc = 0; + ResultSrc = 0; MemWrite = 0; ALUsrc = 0; RegWrite = 1; Branch = 0; - ImmSrc = 2'bXX; + ImmSrc = 2'b00; // don't care ALUop = 2'b10; end - // branch instructions (e.g., BNE, BEQ) + // B-type instructions: BEQ, BNE, BLT, BGE, BLTU, BGEU 7'b1100011: begin - ResultsSrc = X; + ResultSrc = 0; // don't care MemWrite = 0; ALUsrc = 0; RegWrite = 0; @@ -57,8 +57,59 @@ always_comb begin ALUop = 2'b01; // ALU performs subtraction for comparison end + // I-type arithmetic: ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI + 7'b0010011: begin + ResultSrc = 0; + MemWrite = 0; + ALUsrc = 1; + RegWrite = 1; + Branch = 0; + ImmSrc = 2'b00; + ALUop = 2'b10; + end + + 7'b0010111: begin // AUIPC U-type + ResultSrc = 0; + MemWrite = 0; + ALUsrc = 1; + RegWrite = 1; + Branch = 0; + ImmSrc = 2'b11; + ALUop = 2'b00; + end + + 7'b0110111: begin // LUI U-type + ResultSrc = 0; + MemWrite = 0; + ALUsrc = 1; + RegWrite = 1; + Branch = 0; + ImmSrc = 2'b11; + ALUop = 2'b00; + end + + 7'b1101111: begin // JAL J-type + ResultSrc = 0; // don't care + MemWrite = 0; + ALUsrc = 1; + RegWrite = 1; + Branch = 0; + ImmSrc = 2'b00; // don't care + ALUop = 2'b00; + end + + 7'b1100111: begin // JALR I-type + ResultSrc = 0; + MemWrite = 0; + ALUsrc = 1; + RegWrite = 1; + Branch = 0; + ImmSrc = 2'b00; + ALUop = 2'b00; + end + default: begin - ResultsSrc = 0; + ResultSrc = 0; MemWrite = 0; ALUsrc = 0; RegWrite = 0; diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index e4e0c76..7e6fcbe 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -16,12 +16,14 @@ logic EQ; logic [DATA_WIDTH-1:0] pc; logic [DATA_WIDTH-1:0] ImmOp; +logic [DATA_WIDTH-1:0] PCtarget; logic [DATA_WIDTH-1:0] instr; logic [ADDRESS_WIDTH-1:0] rs1; logic [ADDRESS_WIDTH-1:0] rs2; logic [ADDRESS_WIDTH-1:0] rd; +assign pc_next = pc + ImmOp; // decode instruction fields assign rs1 = instr[19:15]; // source register 1 assign rs2 = instr[24:20]; // source register 2 @@ -31,7 +33,7 @@ assign rd = instr[11:7]; // destination register PC pc_module ( .clk(clk), .rst(rst), - .ImmOp(ImmOp), + .ImmOp(PCtarget), .PCsrc(PCsrc), .pc(pc) ); From 5c671e0e7b90a9fc580a5885949c33a287879116 Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Sun, 23 Nov 2025 22:55:44 +0000 Subject: [PATCH 24/65] Fully explained f1.s with comments --- repo/tb/asm/f1.s | 84 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 56 insertions(+), 28 deletions(-) diff --git a/repo/tb/asm/f1.s b/repo/tb/asm/f1.s index b7e4ac5..3e06402 100644 --- a/repo/tb/asm/f1.s +++ b/repo/tb/asm/f1.s @@ -1,48 +1,76 @@ .text .globl main + +# REGISTERS +# t1 -> light pattern counter +# t2 -> saved RNG seed +# t3 -> max light pattern value +# t0 -> loop counters for delays +# t4 -> temporary for RNG calculations +# a0 -> output to lights + +# SUBROUTINES +# fixed_delay -> consistent delay for each light step +# random_delay -> pseudo-random delay using a simple LFSR + +# Lights turn on from right to left until all 8 are on after random delay + +# f1 starting light sequence + main: - li t1, 0 - li t2, 0x12345678 - li a0, 0 + li t1, 0 # initialise light pattern counter to 0 + li t2, 0x12345678 # seed for random delay generator + li a0, 0 # output register initialised to 0 + +# main light loop light_loop: - slli t1, t1, 1 - ori t1, t1, 1 + slli t1, t1, 1 # shift light pattern left by 1 + ori t1, t1, 1 # set LSB to 1 (lights accumulate) + + addi a0, t1, 0 # update output register with current light pattern - addi a0, t1, 0 + jal ra, fixed_delay # call fixed delay subroutine - jal ra, fixed_delay + li t3, 0xFF # maximum light pattern (all 8 lights on) + bne t1, t3, light_loop # repeat loop until all lights are on - li t3, 0xFF - bne t1, t3, light_loop +# random delay sequence +# runs a pseudo-random delay, updates the seed and turns off LEDs - addi t1, t2, 0 - jal ra, random_delay - addi t2, t1, 0 + addi t1, t2, 0 # copy RNG seed into t1 + jal ra, random_delay # call random delay subroutine + addi t2, t1, 0 # update RNG seed - li a0, 0 + li a0, 0 # turn off lights before next sequence + +# fixed delay subroutine +# runs a simple countdown, spaces out LED activations fixed_delay: - li t0, 50000 + li t0, 50000 # set fixed countdown fixed_loop: - addi t0, t0, -1 - bne t0, zero, fixed_loop - jalr x0, ra, 0 + addi t0, t0, -1 # decrement counter + bne t0, zero, fixed_loop # loop until t0 = 0 + jalr x0, ra, 0 # return to caller +# random delay subroutine -> implements LFSR +# uses the lowest 10 bits for delay, xorshift random generator random_delay: - slli t4, t1, 7 - xor t1, t1, t4 - - srli t4, t1, 9 - xor t1, t1, t4 + slli t4, t1, 7 # shift t1 left 7 bits + xor t1, t1, t4 # XOR to mix bits + srli t4, t1, 9 # shift t1 right 9 bits + xor t1, t1, t4 # XOR to mix bits + slli t4, t1, 8 # shift t1 left 8 bits + xor t1, t1, t4 # XOR to mix bits - slli t4, t1, 8 - xor t1, t1, t4 + andi t0, t1, 0x3FF # limit random delay to 10 bits (0-1023) - andi t0, t1, 0x3FF +# random countdown loop +# wait a random number of cycles (0-1023) random_loop: - addi t0, t0, -1 - bne t0, zero, random_loop + addi t0, t0, -1 # countdown random delay + bne t0, zero, random_loop # loop until t0 = 0 - jalr x0, ra, 0 \ No newline at end of file + jalr x0, ra, 0 # return to caller \ No newline at end of file From 14ce198ee28ac2d0423abeacc46bf13ef69142d2 Mon Sep 17 00:00:00 2001 From: Sicovo Date: Mon, 24 Nov 2025 13:54:34 +0000 Subject: [PATCH 25/65] ALU Decoder --- repo/rtl/alu_decoder.sv | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 repo/rtl/alu_decoder.sv diff --git a/repo/rtl/alu_decoder.sv b/repo/rtl/alu_decoder.sv new file mode 100644 index 0000000..61824cf --- /dev/null +++ b/repo/rtl/alu_decoder.sv @@ -0,0 +1,40 @@ +module alu_decoder ( + input logic [1:0] ALUOp, + input logic [2:0] funct3, + input logic funct75, + input logic [6:0] op, + output logic [2:0] ALUControl +); + + logic op5; + assign op5 = op[5]; + + always_comb begin + case (ALUOp) + + 2'b00: ALUControl = 3'b000; + + 2'b01: ALUControl = 3'b001; + + 2'b10: begin + unique case (funct3) + 3'b000: begin + if ({op5, funct75} == 2'b11) + ALUControl = 3'b001; + else + ALUControl = 3'b000; + end + + 3'b010: ALUControl = 3'b101; // slt + 3'b110: ALUControl = 3'b011; // or + 3'b111: ALUControl = 3'b010; //and + + default: ALUControl = 3'b000; + endcase + end + + default: ALUControl = 3'b000; + endcase + end + +endmodule \ No newline at end of file From a0c766b5b8182bde1adf8312c87e2c7ab70f7017 Mon Sep 17 00:00:00 2001 From: Sicovo Date: Mon, 24 Nov 2025 13:55:37 +0000 Subject: [PATCH 26/65] Unify ALUOp naming --- repo/rtl/main_decoder.sv | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/repo/rtl/main_decoder.sv b/repo/rtl/main_decoder.sv index 29c84d6..6e1456d 100644 --- a/repo/rtl/main_decoder.sv +++ b/repo/rtl/main_decoder.sv @@ -6,7 +6,7 @@ module main_decoder ( output logic RegWrite, // enable writing to register file output logic Branch, // indicates branch instruction output logic [1:0] ImmSrc, // selects type of immediate - output logic [1:0] ALUop // encodes ALU operation type (passed to ALU control) + output logic [1:0] ALUOp // encodes ALU operation type (passed to ALU control) ); // combinational logic to decode opcode and generate control signals @@ -21,7 +21,7 @@ always_comb begin RegWrite = 1; Branch = 0; ImmSrc = 2'b00; - ALUop = 2'b00; + ALUOp = 2'b00; end // store instructions: SB, SH, SW @@ -32,7 +32,7 @@ always_comb begin RegWrite = 0; Branch = 0; ImmSrc = 2'b01; - ALUop = 2'b00; + ALUOp = 2'b00; end // R-type instructions: ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND @@ -43,7 +43,7 @@ always_comb begin RegWrite = 1; Branch = 0; ImmSrc = 2'b00; // don't care - ALUop = 2'b10; + ALUOp = 2'b10; end // B-type instructions: BEQ, BNE, BLT, BGE, BLTU, BGEU @@ -54,7 +54,7 @@ always_comb begin RegWrite = 0; Branch = 1; ImmSrc = 2'b10; - ALUop = 2'b01; // ALU performs subtraction for comparison + ALUOp = 2'b01; // ALU performs subtraction for comparison end // I-type arithmetic: ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI @@ -65,7 +65,7 @@ always_comb begin RegWrite = 1; Branch = 0; ImmSrc = 2'b00; - ALUop = 2'b10; + ALUOp = 2'b10; end 7'b0010111: begin // AUIPC U-type @@ -75,7 +75,7 @@ always_comb begin RegWrite = 1; Branch = 0; ImmSrc = 2'b11; - ALUop = 2'b00; + ALUOp = 2'b00; end 7'b0110111: begin // LUI U-type @@ -85,7 +85,7 @@ always_comb begin RegWrite = 1; Branch = 0; ImmSrc = 2'b11; - ALUop = 2'b00; + ALUOp = 2'b00; end 7'b1101111: begin // JAL J-type @@ -95,7 +95,7 @@ always_comb begin RegWrite = 1; Branch = 0; ImmSrc = 2'b00; // don't care - ALUop = 2'b00; + ALUOp = 2'b00; end 7'b1100111: begin // JALR I-type @@ -105,7 +105,7 @@ always_comb begin RegWrite = 1; Branch = 0; ImmSrc = 2'b00; - ALUop = 2'b00; + ALUOp = 2'b00; end default: begin @@ -115,7 +115,7 @@ always_comb begin RegWrite = 0; Branch = 0; ImmSrc = 2'b00; - ALUop = 2'b00; + ALUOp = 2'b00; end endcase end From 039bd08084c1435457964ca3d10efedeb6285180 Mon Sep 17 00:00:00 2001 From: Sicovo Date: Mon, 24 Nov 2025 14:50:08 +0000 Subject: [PATCH 27/65] ALU Updated (3bits ALUControl) --- repo/rtl/alu.sv | 57 ++++++++++++++++++------------------------------- 1 file changed, 21 insertions(+), 36 deletions(-) diff --git a/repo/rtl/alu.sv b/repo/rtl/alu.sv index 7cb1654..7c847bb 100644 --- a/repo/rtl/alu.sv +++ b/repo/rtl/alu.sv @@ -1,38 +1,23 @@ -module alu( - - input logic [31:0] alu_op1, // first operand for the ALU - input logic [31:0] alu_op2, // second operand for the ALU - input logic alu_ctrl, // ALU control signal: selects operation - // 0 -> addition (for addi) - // 1 -> subtraction (for bne) - - output logic [31:0] alu_out, // ALU output result - output logic eq // equality flag: 1 if alu_op1 == alu_op2 +module alu ( + input logic [31:0] SrcA, + input logic [31:0] SrcB, + input logic [2:0] ALUControl, + output logic [31:0] ALUResult, + output logic Zero ); -// internal signals to hold intermediate results -logic [31:0] equality; // difference between operands, used for comparison -logic [31:0] sum; // sum of operands, used for addition - -// combinational logic block (no clock) -always_comb begin - - // compute subtraction for branch comparison - equality = alu_op1 - alu_op2; - // compute addition for arithmetic instructions - sum = alu_op1 + alu_op2; - - // select ALU output based on control signal - if(alu_ctrl == 1'b0) - alu_out = sum; // alu_ctrl=0 -> addition (addi) - else - alu_out = equality; // alu_ctrl=1 → subtraction (bne) - - // set equality flag: 1 if operands are equal, 0 otherwise - if(equality == 32'b0) - eq = 1; - else - eq = 0; - -end -endmodule + always_comb begin + case (ALUControl) + 3'b000: ALUResult = SrcA + SrcB; // add + 3'b001: ALUResult = SrcA - SrcB; // sub + 3'b010: ALUResult = SrcA & SrcB; // and + 3'b011: ALUResult = SrcA | SrcB; // or + 3'b101: ALUResult = ($signed(SrcA) < $signed(SrcB)) ? 32'b1:32'b0; + default: ALUResult = 32'b0; + + endcase + end + + assign Zero = (ALUResult == 32'b0); + +endmodule \ No newline at end of file From 1f2e8b2f359a44e71a3b7245e7bbc5dbaa71b09a Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Mon, 24 Nov 2025 19:59:25 +0000 Subject: [PATCH 28/65] Added top.sv --- repo/rtl/top.sv | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index 7e6fcbe..3ea1289 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -7,23 +7,26 @@ module top #( output logic [DATA_WIDTH-1:0] a0 // x10 output ); +// control signals logic RegWrite; -logic ALUsrc; -logic ALUctrl; -logic ImmSrc; +logic ALUSrc; +logic [2:0] ALUctrl; // 3-bit ALU control +logic [1:0] ImmSrc; // 2-bit immediate +logic [1:0] ResultSrc logic PCsrc; +logic MemWrite; logic EQ; +// data wires logic [DATA_WIDTH-1:0] pc; -logic [DATA_WIDTH-1:0] ImmOp; -logic [DATA_WIDTH-1:0] PCtarget; logic [DATA_WIDTH-1:0] instr; +logic [DATA_WIDTH-1:0] ImmOp; +// register file address fields logic [ADDRESS_WIDTH-1:0] rs1; logic [ADDRESS_WIDTH-1:0] rs2; logic [ADDRESS_WIDTH-1:0] rd; -assign pc_next = pc + ImmOp; // decode instruction fields assign rs1 = instr[19:15]; // source register 1 assign rs2 = instr[24:20]; // source register 2 @@ -33,8 +36,8 @@ assign rd = instr[11:7]; // destination register PC pc_module ( .clk(clk), .rst(rst), - .ImmOp(PCtarget), .PCsrc(PCsrc), + .ImmOp(ImmOp), .pc(pc) ); @@ -49,9 +52,11 @@ control control ( .instr(instr), .EQ(EQ), .RegWrite(RegWrite), - .ALUsrc(ALUsrc), + .ALUSrc(ALUSrc), .ALUctrl(ALUctrl), .ImmSrc(ImmSrc), + .ResultSrc(ResultSrc), + .MemWrite(MemWrite), .PCsrc(PCsrc) ); @@ -70,8 +75,10 @@ data_unit data_unit ( .AD3(rd), .RegWrite(RegWrite), .ImmOp(ImmOp), - .ALUsrc(ALUsrc), + .ALUSrc(ALUSrc), .ALUctrl(ALUctrl), + .ResultSrc(ResultSrc), + .MemWrite(MemWrite), .EQ(EQ), .a0(a0) ); From d3b8e18543d9c0c6b9913a2c2f15de6ebf9ef80f Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Mon, 24 Nov 2025 20:10:39 +0000 Subject: [PATCH 29/65] Fixed control.sv --- repo/rtl/control.sv | 90 ++++++++++++++++++++------------------------- 1 file changed, 40 insertions(+), 50 deletions(-) diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index 3963b35..70c5b01 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -1,57 +1,47 @@ module control ( - /* verilator lint_off UNUSED */ input logic [31:0] instr, - /* verilator lint_on UNUSED */ - input logic EQ, // equality flag from ALU (1 if operands are equal) - output logic RegWrite, - output logic ALUsrc, - output logic ALUctrl, // 0 = add, 1 = sub - output logic ImmSrc, // 0 = I-type, 1 = B-type - output logic PCsrc // select next PC: 0 = PC+4, 1 = branch target + input logic EQ, // ALU zero/equality flag + + output logic RegWrite, + output logic ALUSrc, + output logic [2:0] ALUctrl, + output logic [1:0] ImmSrc, + output logic [1:0] ResultSrc, + output logic MemWrite, + output logic PCsrc ); - // internal signals - logic branch; - logic [6:0] opcode; - assign opcode = instr[6:0]; // extract opcode (bits [6:0]) - - // combinational logic: decode opcode to generate control signals - always_comb begin - RegWrite = 0; - ALUsrc = 0; - ALUctrl = 0; - ImmSrc = 0; - branch = 0; - - case (opcode) - 7'b0010011: begin // ADDI - RegWrite = 1; - ALUsrc = 1; // immediate - ALUctrl = 0; // add - ImmSrc = 0; // I-type - branch = 0; - end - - 7'b1100011: begin // BNE - RegWrite = 0; - ALUsrc = 0; - ALUctrl = 1; // subtract - ImmSrc = 1; // B-type immediate - branch = 1; - end - - default: begin - RegWrite = 0; - ALUsrc = 0; - ALUctrl = 0; - ImmSrc = 0; - branch = 0; - end - endcase - end - - // determine next PC: branch taken if branch instruction AND operands not equal - assign PCsrc = branch & (~EQ); + // fields + logic [6:0] opcode = instr[6:0]; + logic [2:0] funct3 = instr[14:12]; + logic [6:0] funct7 = instr[31:25]; + + // wires between decoders + logic Branch; + logic [1:0] ALUOp; + + // instantiate main decoder + main_decoder main_dec ( + .opcode(opcode), + .RegWrite(RegWrite), + .ALUSrc(ALUSrc), + .ResultSrc(ResultSrc), + .MemWrite(MemWrite), + .ImmSrc(ImmSrc), + .Branch(Branch), + .ALUOp(ALUOp) + ); + + // instantiate ALU decoder + alu_decoder alu_dec ( + .ALUOp(ALUOp), + .funct3(funct3), + .funct7(funct7), + .ALUctrl(ALUctrl) + ); + + // PCsrc: branch AND zero + assign PCsrc = Branch & EQ; endmodule From 7af5d4db9d382ab60d5b85d530de374eb7f47d49 Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Mon, 24 Nov 2025 21:20:44 +0000 Subject: [PATCH 30/65] Fixed signext, top, control, decoders --- repo/rtl/alu_decoder.sv | 42 +++++----- repo/rtl/control.sv | 2 +- repo/rtl/main_decoder.sv | 167 ++++++++++++++++++++++----------------- repo/rtl/signext.sv | 49 ++++++++---- repo/rtl/top.sv | 2 +- 5 files changed, 154 insertions(+), 108 deletions(-) diff --git a/repo/rtl/alu_decoder.sv b/repo/rtl/alu_decoder.sv index 61824cf..2c4e202 100644 --- a/repo/rtl/alu_decoder.sv +++ b/repo/rtl/alu_decoder.sv @@ -1,34 +1,40 @@ module alu_decoder ( - input logic [1:0] ALUOp, - input logic [2:0] funct3, - input logic funct75, - input logic [6:0] op, + input logic [1:0] ALUOp, + input logic [2:0] funct3, + input logic funct75, // funct7[5] output logic [2:0] ALUControl ); - logic op5; - assign op5 = op[5]; +// for the full RV32I ALU, add R-type, I-type shift instructions, and STLU and SLTIU always_comb begin - case (ALUOp) + unique case (ALUOp) + // 00: Load/Store -> ADD 2'b00: ALUControl = 3'b000; + // 01: Branch -> SUB 2'b01: ALUControl = 3'b001; + // 10: R-type -> Use funct3 + funct7b5 2'b10: begin unique case (funct3) - 3'b000: begin - if ({op5, funct75} == 2'b11) - ALUControl = 3'b001; - else - ALUControl = 3'b000; - end - - 3'b010: ALUControl = 3'b101; // slt - 3'b110: ALUControl = 3'b011; // or - 3'b111: ALUControl = 3'b010; //and + 3'b000: ALUControl = funct75 ? 3'b001 // SUB + : 3'b000; // ADD + 3'b010: ALUControl = 3'b101; // SLT + 3'b110: ALUControl = 3'b011; // OR + 3'b111: ALUControl = 3'b010; // AND + default: ALUControl = 3'b000; + endcase + end + // 11: I-type ALU (ADDI/ANDI/ORI/SLTI) + 2'b11: begin + unique case (funct3) + 3'b000: ALUControl = 3'b000; // ADDI + 3'b010: ALUControl = 3'b101; // SLTI + 3'b110: ALUControl = 3'b011; // ORI + 3'b111: ALUControl = 3'b010; // ANDI default: ALUControl = 3'b000; endcase end @@ -37,4 +43,4 @@ module alu_decoder ( endcase end -endmodule \ No newline at end of file +endmodule diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index 70c5b01..193abc7 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -36,7 +36,7 @@ module control ( alu_decoder alu_dec ( .ALUOp(ALUOp), .funct3(funct3), - .funct7(funct7), + .funct75(funct7[5]), .ALUctrl(ALUctrl) ); diff --git a/repo/rtl/main_decoder.sv b/repo/rtl/main_decoder.sv index 6e1456d..c286b7d 100644 --- a/repo/rtl/main_decoder.sv +++ b/repo/rtl/main_decoder.sv @@ -1,5 +1,6 @@ module main_decoder ( input logic [6:0] opcode, // 7-bit opcode field from the instruction + output logic ResultSrc, // selects data written to register file (ALU result or memory data) output logic MemWrite, // enable writing to data memory output logic ALUsrc, // selects ALU second operand (0 = register, 1 = immediate) @@ -11,101 +12,123 @@ module main_decoder ( // combinational logic to decode opcode and generate control signals always_comb begin - case(opcode) + // default values (safe defaults) + ResultSrc = 0; + MemWrite = 0; + ALUsrc = 0; + RegWrite = 0; + Branch = 0; + ImmSrc = 2'b00; + ALUOp = 2'b00; + case(opcode) + // load instructions: LB, LH, LW, LBU, LHU - 7'b0000011: begin - ResultSrc = 1; - MemWrite = 0; - ALUsrc = 1; - RegWrite = 1; - Branch = 0; - ImmSrc = 2'b00; - ALUOp = 2'b00; + // opcode = 0000011 + 7'b0000011: begin + ResultSrc = 1; // load data from memory + MemWrite = 0; + ALUsrc = 1; // use immediate for address + RegWrite = 1; + Branch = 0; + ImmSrc = 2'b00; // I-type immediate + ALUOp = 2'b00; // ALU does ADD for address end // store instructions: SB, SH, SW - 7'b0100011: begin - ResultSrc = 0; // don't care - MemWrite = 1; - ALUsrc = 1; - RegWrite = 0; - Branch = 0; - ImmSrc = 2'b01; - ALUOp = 2'b00; + // opcode = 0100011 + 7'b0100011: begin + ResultSrc = 0; // don't care + MemWrite = 1; // write to data memory + ALUsrc = 1; // use immediate for address + RegWrite = 0; + Branch = 0; + ImmSrc = 2'b01; // S-type immediate + ALUOp = 2'b00; // ALU does ADD for address end // R-type instructions: ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND - 7'b0110011: begin - ResultSrc = 0; - MemWrite = 0; - ALUsrc = 0; - RegWrite = 1; - Branch = 0; - ImmSrc = 2'b00; // don't care - ALUOp = 2'b10; + // opcode = 0110011 + 7'b0110011: begin + ResultSrc = 0; + MemWrite = 0; + ALUsrc = 0; // second operand from register + RegWrite = 1; + Branch = 0; + ImmSrc = 2'b00; // don't care + ALUOp = 2'b10; // R-type ALU decoding end // B-type instructions: BEQ, BNE, BLT, BGE, BLTU, BGEU - 7'b1100011: begin - ResultSrc = 0; // don't care - MemWrite = 0; - ALUsrc = 0; - RegWrite = 0; - Branch = 1; - ImmSrc = 2'b10; - ALUOp = 2'b01; // ALU performs subtraction for comparison + // opcode = 1100011 + 7'b1100011: begin + ResultSrc = 0; // don't care + MemWrite = 0; + ALUsrc = 0; // use registers + RegWrite = 0; + Branch = 1; // enable branch logic + ImmSrc = 2'b10; // B-type immediate + ALUOp = 2'b01; // ALU subtracts for comparison end // I-type arithmetic: ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI + // opcode = 0010011 7'b0010011: begin - ResultSrc = 0; - MemWrite = 0; - ALUsrc = 1; - RegWrite = 1; - Branch = 0; - ImmSrc = 2'b00; - ALUOp = 2'b10; + ResultSrc = 0; + MemWrite = 0; + ALUsrc = 1; // use immediate + RegWrite = 1; + Branch = 0; + ImmSrc = 2'b00; // I-type immediate + ALUOp = 2'b11; // I-type ALU (distinct from R-type) end - 7'b0010111: begin // AUIPC U-type - ResultSrc = 0; - MemWrite = 0; - ALUsrc = 1; - RegWrite = 1; - Branch = 0; - ImmSrc = 2'b11; - ALUOp = 2'b00; + // AUIPC (U-type) + // opcode = 0010111 + 7'b0010111: begin + ResultSrc = 0; + MemWrite = 0; + ALUsrc = 1; + RegWrite = 1; + Branch = 0; + ImmSrc = 2'b11; // U-type immediate + ALUOp = 2'b00; end - 7'b0110111: begin // LUI U-type - ResultSrc = 0; - MemWrite = 0; - ALUsrc = 1; - RegWrite = 1; - Branch = 0; - ImmSrc = 2'b11; - ALUOp = 2'b00; + // LUI (U-type) + // opcode = 0110111 + 7'b0110111: begin + ResultSrc = 0; + MemWrite = 0; + ALUsrc = 1; + RegWrite = 1; + Branch = 0; + ImmSrc = 2'b11; // U-type immediate + ALUOp = 2'b00; end - 7'b1101111: begin // JAL J-type - ResultSrc = 0; // don't care - MemWrite = 0; - ALUsrc = 1; - RegWrite = 1; - Branch = 0; - ImmSrc = 2'b00; // don't care - ALUOp = 2'b00; + // JAL (J-type) + // opcode = 1101111 + 7'b1101111: begin + ResultSrc = 0; // return address is PC+4 (handled in datapath) + MemWrite = 0; + ALUsrc = 1; + RegWrite = 1; // write x[rd] = PC+4 + Branch = 0; + ImmSrc = 2'11; + ALUOp = 2'b00; end - 7'b1100111: begin // JALR I-type - ResultSrc = 0; - MemWrite = 0; - ALUsrc = 1; - RegWrite = 1; - Branch = 0; - ImmSrc = 2'b00; - ALUOp = 2'b00; + // JALR (I-type) + // opcode = 1100111 + 7'b1100111: begin + ResultSrc = 0; + MemWrite = 0; + ALUsrc = 1; + RegWrite = 1; + Branch = 0; + ImmSrc = 2'b00; + ALUOp = 2'b00; end default: begin diff --git a/repo/rtl/signext.sv b/repo/rtl/signext.sv index 5f08a2a..e7a3307 100644 --- a/repo/rtl/signext.sv +++ b/repo/rtl/signext.sv @@ -1,27 +1,44 @@ module signext ( - /* verilator lint_off UNUSED */ - input logic [31:0] instr, // full 32-bit instruction word - /* verilator lint_on UNUSED */ - input logic ImmSrc, // 0 = I-type immediate, 1 = B-type immediate - output logic [31:0] ImmOp // sign-extended immediate output + input logic [31:0] instr, + input logic [1:0] ImmSrc, // 2 bits + output logic [31:0] ImmOp ); - logic [31:0] immI; // I-type immediate - logic [31:0] immB; // B-type immediate + logic [31:0] immI, immS, immB, immU, immJ; + // I-type assign immI = {{20{instr[31]}}, instr[31:20]}; + // S-type + assign immS = {{20{instr[31]}}, instr[31:25], instr[11:7]}; + + // B-type assign immB = {{19{instr[31]}}, - instr[31], // imm[12] - instr[7], // imm[11] - instr[30:25], // imm[10:5] - instr[11:8], // imm[4:1] - 1'b0 // imm[0] - }; + instr[31], + instr[7], + instr[30:25], + instr[11:8], + 1'b0}; - // select appropriate immediate based on instruction type - assign ImmOp = (ImmSrc == 0) ? immI : immB; + // U-type (LUI, AUIPC) + assign immU = {instr[31:12], 12'b0}; -endmodule + // J-type (JAL) + assign immJ = {{11{instr[31]}}, + instr[31], + instr[19:12], + instr[20], + instr[30:21], + 1'b0}; + always_comb begin + unique case (ImmSrc) + 2'b00: ImmOp = immI; // I-type + 2'b01: ImmOp = immS; // S-type + 2'b10: ImmOp = immB; // B-type + 2'b11: ImmOp = immU; // U-type (could also be J-type depending on decoder) + default: ImmOp = immI; + endcase + end +endmodule diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index 3ea1289..d7436fc 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -12,7 +12,7 @@ logic RegWrite; logic ALUSrc; logic [2:0] ALUctrl; // 3-bit ALU control logic [1:0] ImmSrc; // 2-bit immediate -logic [1:0] ResultSrc +logic [1:0] ResultSrc; logic PCsrc; logic MemWrite; logic EQ; From 3af4ed22db6683a39adc7f2550c3629b7013e7a8 Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Tue, 25 Nov 2025 13:37:26 +0000 Subject: [PATCH 31/65] Changed ALUControl to 4 bits --- repo/rtl/alu_decoder.sv | 60 ++++++++++++++++++++++++++--------------- 1 file changed, 39 insertions(+), 21 deletions(-) diff --git a/repo/rtl/alu_decoder.sv b/repo/rtl/alu_decoder.sv index 2c4e202..f774d3d 100644 --- a/repo/rtl/alu_decoder.sv +++ b/repo/rtl/alu_decoder.sv @@ -2,45 +2,63 @@ module alu_decoder ( input logic [1:0] ALUOp, input logic [2:0] funct3, input logic funct75, // funct7[5] - output logic [2:0] ALUControl + output logic [3:0] ALUControl // extended to 4 bits ); -// for the full RV32I ALU, add R-type, I-type shift instructions, and STLU and SLTIU + // ALUControl encoding (4 bits) + // 0000 = ADD + // 0001 = SUB + // 0010 = AND + // 0011 = OR + // 0100 = XOR + // 0101 = SLL + // 0110 = SRL + // 0111 = SRA + // 1000 = SLT (signed) + // 1001 = SLTU (unsigned) + // (leave others for future) always_comb begin unique case (ALUOp) + // Load/Store/AUIPC: always ADD (address calculation) + 2'b00: ALUControl = 4'b0000; // ADD - // 00: Load/Store -> ADD - 2'b00: ALUControl = 3'b000; + // Branch comparison: set to SUB (we also use Zero and SLT flags) + 2'b01: ALUControl = 4'b0001; // SUB - // 01: Branch -> SUB - 2'b01: ALUControl = 3'b001; - - // 10: R-type -> Use funct3 + funct7b5 + // R-type: decode by funct3 + funct7 2'b10: begin unique case (funct3) - 3'b000: ALUControl = funct75 ? 3'b001 // SUB - : 3'b000; // ADD - 3'b010: ALUControl = 3'b101; // SLT - 3'b110: ALUControl = 3'b011; // OR - 3'b111: ALUControl = 3'b010; // AND - default: ALUControl = 3'b000; + 3'b000: ALUControl = funct75 ? 4'b0001 : 4'b0000; // SUB : ADD + 3'b001: ALUControl = 4'b0101; // SLL + 3'b010: ALUControl = 4'b1000; // SLT (signed) + 3'b011: ALUControl = 4'b1001; // SLTU (unsigned) + 3'b100: ALUControl = 4'b0100; // XOR + 3'b101: ALUControl = funct75 ? 4'b0111 : 4'b0110; // SRA : SRL + 3'b110: ALUControl = 4'b0011; // OR + 3'b111: ALUControl = 4'b0010; // AND + default: ALUControl = 4'b0000; endcase end - // 11: I-type ALU (ADDI/ANDI/ORI/SLTI) + // I-type: similar to R-type but shifts use funct7[5] as well 2'b11: begin unique case (funct3) - 3'b000: ALUControl = 3'b000; // ADDI - 3'b010: ALUControl = 3'b101; // SLTI - 3'b110: ALUControl = 3'b011; // ORI - 3'b111: ALUControl = 3'b010; // ANDI - default: ALUControl = 3'b000; + 3'b000: ALUControl = 4'b0000; // ADDI + 3'b001: ALUControl = 4'b0101; // SLLI (shamt) + 3'b010: ALUControl = 4'b1000; // SLTI + 3'b011: ALUControl = 4'b1001; // SLTIU + 3'b100: ALUControl = 4'b0100; // XORI + 3'b101: ALUControl = funct75 ? 4'b0111 : 4'b0110; // SRAI : SRLI + 3'b110: ALUControl = 4'b0011; // ORI + 3'b111: ALUControl = 4'b0010; // ANDI + default: ALUControl = 4'b0000; endcase end - default: ALUControl = 3'b000; + default: ALUControl = 4'b0000; endcase end endmodule +*/ \ No newline at end of file From f306c207d05d12cccabb6c83640eb5d920531250 Mon Sep 17 00:00:00 2001 From: minimish1 Date: Tue, 25 Nov 2025 13:53:47 +0000 Subject: [PATCH 32/65] Added alu instructions --- repo/rtl/alu.sv | 29 +++++++++++++++++++++++------ repo/rtl/signext.sv | 7 +++++-- 2 files changed, 28 insertions(+), 8 deletions(-) diff --git a/repo/rtl/alu.sv b/repo/rtl/alu.sv index 7c847bb..96fc01e 100644 --- a/repo/rtl/alu.sv +++ b/repo/rtl/alu.sv @@ -1,18 +1,35 @@ + // 0000 = ADD + // 0001 = SUB + // 0010 = AND + // 0011 = OR + // 0100 = XOR + // 0101 = SLL + // 0110 = SRL + // 0111 = SRA + // 1000 = SLT (signed) + // 1001 = SLTU (unsigned) + module alu ( input logic [31:0] SrcA, input logic [31:0] SrcB, - input logic [2:0] ALUControl, + input logic [3:0] ALUControl, output logic [31:0] ALUResult, output logic Zero ); always_comb begin case (ALUControl) - 3'b000: ALUResult = SrcA + SrcB; // add - 3'b001: ALUResult = SrcA - SrcB; // sub - 3'b010: ALUResult = SrcA & SrcB; // and - 3'b011: ALUResult = SrcA | SrcB; // or - 3'b101: ALUResult = ($signed(SrcA) < $signed(SrcB)) ? 32'b1:32'b0; + 4'b0000: ALUResult = SrcA + SrcB; // add + 4'b0001: ALUResult = SrcA - SrcB; // sub + 4'b0010: ALUResult = SrcA & SrcB; // and + 4'b0011: ALUResult = SrcA | SrcB; // or + 4'b0100: ALUResult = SrcA ^ SrcB; // xor + + 4'b0101 : ALUResult = SrcA << SrcB[4:0]; // sll + 4'b0110: ALUResult = SrcA >> SrcB[4:0]; // srl + 4'b0111: ALUResult = $signed(SrcA) >>> SrcB[4:0]; // sra + 4'b1000: ALUResult = ($signed(SrcA) < $signed(SrcB)) ? 32'b1 : 32'b0; //slt + 4'b1001: ALUResult = (SrcA < SrcB) ? 32'b1 : 32'b0; //sltu default: ALUResult = 32'b0; endcase diff --git a/repo/rtl/signext.sv b/repo/rtl/signext.sv index e7a3307..30b2f88 100644 --- a/repo/rtl/signext.sv +++ b/repo/rtl/signext.sv @@ -7,10 +7,13 @@ module signext ( logic [31:0] immI, immS, immB, immU, immJ; // I-type - assign immI = {{20{instr[31]}}, instr[31:20]}; + assign immI = {{20{instr[31]}}, + instr[31:20]}; // S-type - assign immS = {{20{instr[31]}}, instr[31:25], instr[11:7]}; + assign immS = {{20{instr[31]}}, + instr[31:25], + instr[11:7]}; // B-type assign immB = {{19{instr[31]}}, From 4b2c2ab80a40a34c8f4078bb01c98a96dbd74559 Mon Sep 17 00:00:00 2001 From: minimish1 Date: Tue, 25 Nov 2025 14:30:09 +0000 Subject: [PATCH 33/65] Changed ImmSrc to 3 bits --- repo/rtl/alu_decoder.sv | 1 - repo/rtl/control.sv | 6 +++--- repo/rtl/data_mem.sv | 2 +- repo/rtl/data_unit.sv | 4 +++- repo/rtl/main_decoder.sv | 26 +++++++++++------------ repo/rtl/signext.sv | 46 ++++++++++++++++++++-------------------- 6 files changed, 43 insertions(+), 42 deletions(-) diff --git a/repo/rtl/alu_decoder.sv b/repo/rtl/alu_decoder.sv index f774d3d..a8beed5 100644 --- a/repo/rtl/alu_decoder.sv +++ b/repo/rtl/alu_decoder.sv @@ -61,4 +61,3 @@ module alu_decoder ( end endmodule -*/ \ No newline at end of file diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index 193abc7..d2961d0 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -8,14 +8,14 @@ module control ( output logic [1:0] ImmSrc, output logic [1:0] ResultSrc, output logic MemWrite, - output logic PCsrc + output logic PCsrc, + output logic [2:0] funct3 ); // fields logic [6:0] opcode = instr[6:0]; - logic [2:0] funct3 = instr[14:12]; logic [6:0] funct7 = instr[31:25]; - + assign funct3 = instr[14:12]; // wires between decoders logic Branch; logic [1:0] ALUOp; diff --git a/repo/rtl/data_mem.sv b/repo/rtl/data_mem.sv index 43330e5..7a80919 100644 --- a/repo/rtl/data_mem.sv +++ b/repo/rtl/data_mem.sv @@ -11,7 +11,7 @@ module data_mem #( // 2^32 32-bit memory locations logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; - + assign dout = ram_array[wr_addr]; // read data from memory assynchronously always_ff @(posedge clk) begin diff --git a/repo/rtl/data_unit.sv b/repo/rtl/data_unit.sv index dd44727..40facb0 100644 --- a/repo/rtl/data_unit.sv +++ b/repo/rtl/data_unit.sv @@ -12,6 +12,7 @@ module data_unit #( input logic ALUctrl, // ALU control input logic ALUsrc, // select imm or reg input logic ResultSrc, // select ALU or mem data + input logic [2:0] funct3, // for memory access size output logic EQ, // ALU equality flag output logic [DATA_WIDTH-1:0] a0 // x10 output ); @@ -59,7 +60,8 @@ data_mem data_mem ( .en(MemWrite), .wr_addr(ALUout), .din(WriteData), - .dout(ReadData) + .dout(ReadData), + .funct3(funct3) ); mux mux2 ( diff --git a/repo/rtl/main_decoder.sv b/repo/rtl/main_decoder.sv index c286b7d..1bd306b 100644 --- a/repo/rtl/main_decoder.sv +++ b/repo/rtl/main_decoder.sv @@ -6,7 +6,7 @@ module main_decoder ( output logic ALUsrc, // selects ALU second operand (0 = register, 1 = immediate) output logic RegWrite, // enable writing to register file output logic Branch, // indicates branch instruction - output logic [1:0] ImmSrc, // selects type of immediate + output logic [2:0] ImmSrc, // selects type of immediate output logic [1:0] ALUOp // encodes ALU operation type (passed to ALU control) ); @@ -18,7 +18,7 @@ always_comb begin ALUsrc = 0; RegWrite = 0; Branch = 0; - ImmSrc = 2'b00; + ImmSrc = 3'b000; ALUOp = 2'b00; case(opcode) @@ -31,11 +31,11 @@ always_comb begin ALUsrc = 1; // use immediate for address RegWrite = 1; Branch = 0; - ImmSrc = 2'b00; // I-type immediate + ImmSrc = 2'b000; // I-type immediate ALUOp = 2'b00; // ALU does ADD for address end - // store instructions: SB, SH, SW + // store instructions: SB, SH, SW S-type // opcode = 0100011 7'b0100011: begin ResultSrc = 0; // don't care @@ -43,7 +43,7 @@ always_comb begin ALUsrc = 1; // use immediate for address RegWrite = 0; Branch = 0; - ImmSrc = 2'b01; // S-type immediate + ImmSrc = 2'b001; // S-type immediate ALUOp = 2'b00; // ALU does ADD for address end @@ -55,7 +55,7 @@ always_comb begin ALUsrc = 0; // second operand from register RegWrite = 1; Branch = 0; - ImmSrc = 2'b00; // don't care + ImmSrc = 2'b000; // don't care ALUOp = 2'b10; // R-type ALU decoding end @@ -67,7 +67,7 @@ always_comb begin ALUsrc = 0; // use registers RegWrite = 0; Branch = 1; // enable branch logic - ImmSrc = 2'b10; // B-type immediate + ImmSrc = 2'b010; // B-type immediate ALUOp = 2'b01; // ALU subtracts for comparison end @@ -79,7 +79,7 @@ always_comb begin ALUsrc = 1; // use immediate RegWrite = 1; Branch = 0; - ImmSrc = 2'b00; // I-type immediate + ImmSrc = 2'b000; // I-type immediate ALUOp = 2'b11; // I-type ALU (distinct from R-type) end @@ -91,7 +91,7 @@ always_comb begin ALUsrc = 1; RegWrite = 1; Branch = 0; - ImmSrc = 2'b11; // U-type immediate + ImmSrc = 2'b011; // U-type immediate ALUOp = 2'b00; end @@ -103,7 +103,7 @@ always_comb begin ALUsrc = 1; RegWrite = 1; Branch = 0; - ImmSrc = 2'b11; // U-type immediate + ImmSrc = 2'b011; // U-type immediate ALUOp = 2'b00; end @@ -115,7 +115,7 @@ always_comb begin ALUsrc = 1; RegWrite = 1; // write x[rd] = PC+4 Branch = 0; - ImmSrc = 2'11; + ImmSrc = 2'100; ALUOp = 2'b00; end @@ -127,7 +127,7 @@ always_comb begin ALUsrc = 1; RegWrite = 1; Branch = 0; - ImmSrc = 2'b00; + ImmSrc = 2'b000; ALUOp = 2'b00; end @@ -137,7 +137,7 @@ always_comb begin ALUsrc = 0; RegWrite = 0; Branch = 0; - ImmSrc = 2'b00; + ImmSrc = 2'b000; ALUOp = 2'b00; end endcase diff --git a/repo/rtl/signext.sv b/repo/rtl/signext.sv index 30b2f88..a9b1626 100644 --- a/repo/rtl/signext.sv +++ b/repo/rtl/signext.sv @@ -1,47 +1,47 @@ module signext ( input logic [31:0] instr, - input logic [1:0] ImmSrc, // 2 bits + input logic [2:0] ImmSrc, output logic [31:0] ImmOp ); logic [31:0] immI, immS, immB, immU, immJ; // I-type - assign immI = {{20{instr[31]}}, - instr[31:20]}; + assign immI = {{20{instr[31]}}, instr[31:20]}; // S-type - assign immS = {{20{instr[31]}}, - instr[31:25], + assign immS = {{20{instr[31]}}, + instr[31:25], instr[11:7]}; // B-type assign immB = {{19{instr[31]}}, - instr[31], - instr[7], - instr[30:25], - instr[11:8], - 1'b0}; + instr[31], // imm[12] + instr[7], // imm[11] + instr[30:25], // imm[10:5] + instr[11:8], // imm[4:1] + 1'b0}; // imm[0] = 0 // U-type (LUI, AUIPC) assign immU = {instr[31:12], 12'b0}; // J-type (JAL) assign immJ = {{11{instr[31]}}, - instr[31], - instr[19:12], - instr[20], - instr[30:21], - 1'b0}; + instr[31], // imm[20] + instr[19:12], // imm[19:12] + instr[20], // imm[11] + instr[30:21], // imm[10:1] + 1'b0}; // imm[0] = 0 + // MUX between immediate types always_comb begin unique case (ImmSrc) - 2'b00: ImmOp = immI; // I-type - 2'b01: ImmOp = immS; // S-type - 2'b10: ImmOp = immB; // B-type - 2'b11: ImmOp = immU; // U-type (could also be J-type depending on decoder) - default: ImmOp = immI; + 3'b000: ImmOp = immI; // I-type + 3'b001: ImmOp = immS; // S-type + 3'b010: ImmOp = immB; // B-type + 3'b011: ImmOp = immU; // U-type + 3'b100: ImmOp = immJ; // J-type + default: ImmOp = 32'b0; endcase - end - -endmodule +    end +endmodule \ No newline at end of file From e56ef3443c137a7e3b1cf6ab2f080b09d4b7ea0a Mon Sep 17 00:00:00 2001 From: minimish1 Date: Tue, 25 Nov 2025 16:33:39 +0000 Subject: [PATCH 34/65] Added most instructions --- repo/rtl/alu.sv | 23 +++++++++++++++++--- repo/rtl/control.sv | 45 ++++++++++++++++++++++++++++++++++------ repo/rtl/data_mem.sv | 40 ++++++++++++++++++++++++++++++++--- repo/rtl/data_unit.sv | 2 +- repo/rtl/main_decoder.sv | 22 ++++++++++---------- repo/rtl/signext.sv | 2 +- repo/rtl/top.sv | 15 +++++++++----- 7 files changed, 119 insertions(+), 30 deletions(-) diff --git a/repo/rtl/alu.sv b/repo/rtl/alu.sv index 96fc01e..2324c8f 100644 --- a/repo/rtl/alu.sv +++ b/repo/rtl/alu.sv @@ -14,7 +14,7 @@ module alu ( input logic [31:0] SrcB, input logic [3:0] ALUControl, output logic [31:0] ALUResult, - output logic Zero + output logic [2:0] Zero ); always_comb begin @@ -35,6 +35,23 @@ module alu ( endcase end - assign Zero = (ALUResult == 32'b0); - + if ($signed(SrcA) == $signed(SrcB)) begin + assign Zero = 3'b000; // zero flag + end + if ($signed(SrcA) != $signed(SrcB)) begin + assign Zero = 3'b001; // not equal + end + if ($signed(SrcA) < $signed(SrcB)) begin + assign Zero = 3'b010; // less than flag + end + if ($signed(SrcA) >= $signed(SrcB)) begin + assign Zero = 3'b011; // greater/equal than flag + end + if ($unsigned(SrcA) < $unsigned(SrcB)) begin + assign Zero = 3'b100; // less than flag unsigned + end + if ($unsigned(SrcA) >= $unsigned(SrcB)) begin + assign Zero = 3'b101; // greater/equal than flag unsinged + end + endmodule \ No newline at end of file diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index d2961d0..5016f0e 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -1,11 +1,10 @@ module control ( input logic [31:0] instr, - input logic EQ, // ALU zero/equality flag - + input logic [2:0] EQ, output logic RegWrite, output logic ALUSrc, output logic [2:0] ALUctrl, - output logic [1:0] ImmSrc, + output logic [2:0] ImmSrc, output logic [1:0] ResultSrc, output logic MemWrite, output logic PCsrc, @@ -40,8 +39,42 @@ module control ( .ALUctrl(ALUctrl) ); - // PCsrc: branch AND zero - assign PCsrc = Branch & EQ; - + if (Branch) begin + case(funct3) + 3'b000: begin // BEQ + if (EQ == 3'b000) begin + PCsrc = 1'b1; + end + end + 3'b001: begin // BNE + if (EQ == 3'b001) begin + PCsrc = 1'b1; + end + end + 3'b100: begin // BLT + if (EQ == 3'b010) begin + PCsrc = 1'b1; + end + end + 3'b101: begin // BGE + if (EQ == 3'b011) begin + PCsrc = 1'b1; + end + end + 3'b110: begin // BLTU + if (EQ == 3'b100) begin + PCsrc = 1'b1; + end + end + 3'b111: begin // BGEU + if (EQ == 3'b101) begin + PCsrc = 1'b1; + end + end + default: begin + PCsrc = 1'b0; + end + endcase + end endmodule diff --git a/repo/rtl/data_mem.sv b/repo/rtl/data_mem.sv index 7a80919..b21fe1d 100644 --- a/repo/rtl/data_mem.sv +++ b/repo/rtl/data_mem.sv @@ -6,17 +6,51 @@ module data_mem #( input logic en, // write enable input logic [ADDRESS_WIDTH-1:0] wr_addr, // memory address input logic [DATA_WIDTH-1:0] din, // data to write + input logic [2:0] funct3, // for byte/halfword/word selection output logic [DATA_WIDTH-1:0] dout // data read ); // 2^32 32-bit memory locations logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; - - assign dout = ram_array[wr_addr]; // read data from memory assynchronously + case(funct3) + 3'b000: begin // LB + assign dout = {{24{ram_array[wr_addr][7]}}, ram_array[wr_addr][7:0]}; + end + 3'b001: begin // LH + assign dout = {{16{ram_array[wr_addr][15]}}, ram_array[wr_addr][15:0]}; + end + 3'b010: begin // LW + assign dout = ram_array[wr_addr]; + end + 3'b100: begin // LBU + assign dout = {24'b0, ram_array[wr_addr][7:0]}; + end + 3'b101: begin // LHU + assign dout = {16'b0, ram_array[wr_addr][15:0]}; + end + default: begin + assign dout = ram_array[wr_addr]; // read data from memory assynchronously + + end + endcase + always_ff @(posedge clk) begin if (en == 1'b1) begin - ram_array[wr_addr] <= din; // write data to memory synchronously + case(funct3) + 3'b000: begin // SB + ram_array[wr_addr][7:0] <= din[7:0]; + end + 3'b001: begin // SH + ram_array[wr_addr][15:0] <= din[15:0]; + end + 3'b010: begin // SW + ram_array[wr_addr] <= din; + end + default: begin + ram_array[wr_addr] <= din; // write data to memory synchronously + end + endcase end end diff --git a/repo/rtl/data_unit.sv b/repo/rtl/data_unit.sv index 40facb0..f908d79 100644 --- a/repo/rtl/data_unit.sv +++ b/repo/rtl/data_unit.sv @@ -13,7 +13,7 @@ module data_unit #( input logic ALUsrc, // select imm or reg input logic ResultSrc, // select ALU or mem data input logic [2:0] funct3, // for memory access size - output logic EQ, // ALU equality flag + output logic [2:0] EQ, // ALU equality flag output logic [DATA_WIDTH-1:0] a0 // x10 output ); diff --git a/repo/rtl/main_decoder.sv b/repo/rtl/main_decoder.sv index 1bd306b..f0b968b 100644 --- a/repo/rtl/main_decoder.sv +++ b/repo/rtl/main_decoder.sv @@ -7,7 +7,7 @@ module main_decoder ( output logic RegWrite, // enable writing to register file output logic Branch, // indicates branch instruction output logic [2:0] ImmSrc, // selects type of immediate - output logic [1:0] ALUOp // encodes ALU operation type (passed to ALU control) + output logic [1:0] ALUOp, // encodes ALU operation type (passed to ALU control) ); // combinational logic to decode opcode and generate control signals @@ -31,7 +31,7 @@ always_comb begin ALUsrc = 1; // use immediate for address RegWrite = 1; Branch = 0; - ImmSrc = 2'b000; // I-type immediate + ImmSrc = 3'b000; // I-type immediate ALUOp = 2'b00; // ALU does ADD for address end @@ -43,7 +43,7 @@ always_comb begin ALUsrc = 1; // use immediate for address RegWrite = 0; Branch = 0; - ImmSrc = 2'b001; // S-type immediate + ImmSrc = 3'b001; // S-type immediate ALUOp = 2'b00; // ALU does ADD for address end @@ -55,7 +55,7 @@ always_comb begin ALUsrc = 0; // second operand from register RegWrite = 1; Branch = 0; - ImmSrc = 2'b000; // don't care + ImmSrc = 3'b000; // don't care ALUOp = 2'b10; // R-type ALU decoding end @@ -67,7 +67,7 @@ always_comb begin ALUsrc = 0; // use registers RegWrite = 0; Branch = 1; // enable branch logic - ImmSrc = 2'b010; // B-type immediate + ImmSrc = 3'b010; // B-type immediate ALUOp = 2'b01; // ALU subtracts for comparison end @@ -79,7 +79,7 @@ always_comb begin ALUsrc = 1; // use immediate RegWrite = 1; Branch = 0; - ImmSrc = 2'b000; // I-type immediate + ImmSrc = 3'b000; // I-type immediate ALUOp = 2'b11; // I-type ALU (distinct from R-type) end @@ -91,7 +91,7 @@ always_comb begin ALUsrc = 1; RegWrite = 1; Branch = 0; - ImmSrc = 2'b011; // U-type immediate + ImmSrc = 3'b011; // U-type immediate ALUOp = 2'b00; end @@ -103,7 +103,7 @@ always_comb begin ALUsrc = 1; RegWrite = 1; Branch = 0; - ImmSrc = 2'b011; // U-type immediate + ImmSrc = 3'b011; // U-type immediate ALUOp = 2'b00; end @@ -115,7 +115,7 @@ always_comb begin ALUsrc = 1; RegWrite = 1; // write x[rd] = PC+4 Branch = 0; - ImmSrc = 2'100; + ImmSrc = 3'b100; ALUOp = 2'b00; end @@ -127,7 +127,7 @@ always_comb begin ALUsrc = 1; RegWrite = 1; Branch = 0; - ImmSrc = 2'b000; + ImmSrc = 3'b000; ALUOp = 2'b00; end @@ -137,7 +137,7 @@ always_comb begin ALUsrc = 0; RegWrite = 0; Branch = 0; - ImmSrc = 2'b000; + ImmSrc = 3'b000; ALUOp = 2'b00; end endcase diff --git a/repo/rtl/signext.sv b/repo/rtl/signext.sv index a9b1626..e968c5c 100644 --- a/repo/rtl/signext.sv +++ b/repo/rtl/signext.sv @@ -43,5 +43,5 @@ module signext ( 3'b100: ImmOp = immJ; // J-type default: ImmOp = 32'b0; endcase -    end + end endmodule \ No newline at end of file diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index d7436fc..8b5ae92 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -11,22 +11,25 @@ module top #( logic RegWrite; logic ALUSrc; logic [2:0] ALUctrl; // 3-bit ALU control -logic [1:0] ImmSrc; // 2-bit immediate +logic [2:0] ImmSrc; // 2-bit immediate logic [1:0] ResultSrc; logic PCsrc; logic MemWrite; -logic EQ; +logic [2:0] EQ; +logic [2:0] funct3; // data wires logic [DATA_WIDTH-1:0] pc; logic [DATA_WIDTH-1:0] instr; logic [DATA_WIDTH-1:0] ImmOp; +logic [DATA_WIDTH-1:0] PCtarget; // register file address fields logic [ADDRESS_WIDTH-1:0] rs1; logic [ADDRESS_WIDTH-1:0] rs2; logic [ADDRESS_WIDTH-1:0] rd; +assign pc_next = pc + ImmOp; // PC + immediate for branch target // decode instruction fields assign rs1 = instr[19:15]; // source register 1 assign rs2 = instr[24:20]; // source register 2 @@ -37,7 +40,7 @@ PC pc_module ( .clk(clk), .rst(rst), .PCsrc(PCsrc), - .ImmOp(ImmOp), + .ImmOp(PCtarget), .pc(pc) ); @@ -57,7 +60,8 @@ control control ( .ImmSrc(ImmSrc), .ResultSrc(ResultSrc), .MemWrite(MemWrite), - .PCsrc(PCsrc) + .PCsrc(PCsrc), + .funct3(funct3) ); // sign-extension unit: generate immediate values @@ -80,7 +84,8 @@ data_unit data_unit ( .ResultSrc(ResultSrc), .MemWrite(MemWrite), .EQ(EQ), - .a0(a0) + .a0(a0), + .funct3(funct3) ); endmodule From ccad76928c3cd57bf93939de40d4bdd6e3a2d8e8 Mon Sep 17 00:00:00 2001 From: minimish1 Date: Tue, 25 Nov 2025 18:04:06 +0000 Subject: [PATCH 35/65] Added final instructions --- repo/rtl/PC.sv | 12 ++++-- repo/rtl/alu.sv | 79 ++++++++++++++++++++++++---------------- repo/rtl/control.sv | 70 +++++++++++++++++++++-------------- repo/rtl/data_unit.sv | 22 ++++++----- repo/rtl/main_decoder.sv | 24 ++++++------ repo/rtl/top.sv | 14 +++++-- 6 files changed, 134 insertions(+), 87 deletions(-) diff --git a/repo/rtl/PC.sv b/repo/rtl/PC.sv index 130bdd5..090778e 100644 --- a/repo/rtl/PC.sv +++ b/repo/rtl/PC.sv @@ -3,8 +3,9 @@ module PC #( )( input logic clk, // system clock input logic rst, // asynchronous reset - input logic PCsrc, // selects between sequential PC and branch target + input logic [1:0] PCsrc, // selects between sequential PC and branch target input logic [WIDTH-1:0] ImmOp, // immediate offset for branch target + input logic [WIDTH-1:0] JALRjump, // current program counter input output logic [WIDTH-1:0] pc // current program counter ); @@ -23,8 +24,13 @@ assign inc_PC = pc + {{WIDTH-3{1'b0}}, 3'b100}; // add immediate offset to PC for branch target assign branch_PC = pc + ImmOp; -// select between sequential PC and branch PC -assign next_PC = PCsrc ? branch_PC : inc_PC; +// select between sequential PC and branch PC and JALR target +case(PCsrc) + 2'b00: assign next_PC = inc_PC; // Next sequential instruction + 2'b01: assign next_PC = branch_PC; // Branch target + 2'b10: assign next_PC = JALRjump; // JALR target + default: assign next_PC = inc_PC; // Default to sequential +endcase // program counter register with asynchronous reset always_ff @(posedge clk or posedge rst) begin diff --git a/repo/rtl/alu.sv b/repo/rtl/alu.sv index 2324c8f..24ad38d 100644 --- a/repo/rtl/alu.sv +++ b/repo/rtl/alu.sv @@ -13,45 +13,60 @@ module alu ( input logic [31:0] SrcA, input logic [31:0] SrcB, input logic [3:0] ALUControl, + input logic [31:0] PC, + input logic [6:0] opcode, output logic [31:0] ALUResult, output logic [2:0] Zero ); always_comb begin - case (ALUControl) - 4'b0000: ALUResult = SrcA + SrcB; // add - 4'b0001: ALUResult = SrcA - SrcB; // sub - 4'b0010: ALUResult = SrcA & SrcB; // and - 4'b0011: ALUResult = SrcA | SrcB; // or - 4'b0100: ALUResult = SrcA ^ SrcB; // xor - 4'b0101 : ALUResult = SrcA << SrcB[4:0]; // sll - 4'b0110: ALUResult = SrcA >> SrcB[4:0]; // srl - 4'b0111: ALUResult = $signed(SrcA) >>> SrcB[4:0]; // sra - 4'b1000: ALUResult = ($signed(SrcA) < $signed(SrcB)) ? 32'b1 : 32'b0; //slt - 4'b1001: ALUResult = (SrcA < SrcB) ? 32'b1 : 32'b0; //sltu - default: ALUResult = 32'b0; + case(opcode) + 7'b0110111: begin // LUI + ALUResult = SrcB; // Load Upper Immediate + end + 7'b0010111: begin // AUIPC + ALUResult = PC + SrcB; // Add Upper Immediate to PC + end + default: begin + // perform ALU operation based on ALUControl signal + case (ALUControl) + 4'b0000: ALUResult = SrcA + SrcB; // add + 4'b0001: ALUResult = SrcA - SrcB; // sub + 4'b0010: ALUResult = SrcA & SrcB; // and + 4'b0011: ALUResult = SrcA | SrcB; // or + 4'b0100: ALUResult = SrcA ^ SrcB; // xor + + 4'b0101 : ALUResult = SrcA << SrcB[4:0]; // sll + 4'b0110: ALUResult = SrcA >> SrcB[4:0]; // srl + 4'b0111: ALUResult = $signed(SrcA) >>> SrcB[4:0]; // sra + 4'b1000: ALUResult = ($signed(SrcA) < $signed(SrcB)) ? 32'b1 : 32'b0; //slt + 4'b1001: ALUResult = (SrcA < SrcB) ? 32'b1 : 32'b0; //sltu + default: ALUResult = 32'b0; + + endcase + + if ($signed(SrcA) == $signed(SrcB)) begin + assign Zero = 3'b000; // zero flag + end + if ($signed(SrcA) != $signed(SrcB)) begin + assign Zero = 3'b001; // not equal + end + if ($signed(SrcA) < $signed(SrcB)) begin + assign Zero = 3'b010; // less than flag + end + if ($signed(SrcA) >= $signed(SrcB)) begin + assign Zero = 3'b011; // greater/equal than flag + end + if ($unsigned(SrcA) < $unsigned(SrcB)) begin + assign Zero = 3'b100; // less than flag unsigned + end + if ($unsigned(SrcA) >= $unsigned(SrcB)) begin + assign Zero = 3'b101; // greater/equal than flag unsinged + end + + end endcase end - - if ($signed(SrcA) == $signed(SrcB)) begin - assign Zero = 3'b000; // zero flag - end - if ($signed(SrcA) != $signed(SrcB)) begin - assign Zero = 3'b001; // not equal - end - if ($signed(SrcA) < $signed(SrcB)) begin - assign Zero = 3'b010; // less than flag - end - if ($signed(SrcA) >= $signed(SrcB)) begin - assign Zero = 3'b011; // greater/equal than flag - end - if ($unsigned(SrcA) < $unsigned(SrcB)) begin - assign Zero = 3'b100; // less than flag unsigned - end - if ($unsigned(SrcA) >= $unsigned(SrcB)) begin - assign Zero = 3'b101; // greater/equal than flag unsinged - end - endmodule \ No newline at end of file diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index 5016f0e..a55de92 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -7,7 +7,7 @@ module control ( output logic [2:0] ImmSrc, output logic [1:0] ResultSrc, output logic MemWrite, - output logic PCsrc, + output logic [1:0] PCsrc, output logic [2:0] funct3 ); @@ -39,42 +39,56 @@ module control ( .ALUctrl(ALUctrl) ); - if (Branch) begin - case(funct3) - 3'b000: begin // BEQ - if (EQ == 3'b000) begin - PCsrc = 1'b1; + always_comb begin + if (Branch) begin + case(funct3) + 3'b000: begin // BEQ + if (EQ == 3'b000) begin + PCsrc = 2'b01; + end end - end - 3'b001: begin // BNE - if (EQ == 3'b001) begin - PCsrc = 1'b1; + 3'b001: begin // BNE + if (EQ == 3'b001) begin + PCsrc = 2'b01; + end end - end - 3'b100: begin // BLT - if (EQ == 3'b010) begin - PCsrc = 1'b1; + 3'b100: begin // BLT + if (EQ == 3'b010) begin + PCsrc = 2'b01; + end end - end - 3'b101: begin // BGE - if (EQ == 3'b011) begin - PCsrc = 1'b1; + 3'b101: begin // BGE + if (EQ == 3'b011) begin + PCsrc = 2'b01; + end end - end - 3'b110: begin // BLTU - if (EQ == 3'b100) begin - PCsrc = 1'b1; + 3'b110: begin // BLTU + if (EQ == 3'b100) begin + PCsrc = 2'b01; + end end - end - 3'b111: begin // BGEU - if (EQ == 3'b101) begin - PCsrc = 1'b1; + 3'b111: begin // BGEU + if (EQ == 3'b101) begin + PCsrc = 2'b01; + end end + default: begin + PCsrc = 2'b00; + end + endcase + end + + case(opcode) + 7'b1101111: begin // JAL + PCsrc = 2'b01; + end + 7'b1100111: begin // JALR + PCsrc = 2'b10; end default: begin - PCsrc = 1'b0; + PCsrc = 2'b00; end endcase end -endmodule +endmodule diff --git a/repo/rtl/data_unit.sv b/repo/rtl/data_unit.sv index f908d79..4bdbfef 100644 --- a/repo/rtl/data_unit.sv +++ b/repo/rtl/data_unit.sv @@ -11,13 +11,16 @@ module data_unit #( input logic MemWrite, // write enable to memory input logic ALUctrl, // ALU control input logic ALUsrc, // select imm or reg - input logic ResultSrc, // select ALU or mem data + input logic [1:0] ResultSrc, // select ALU or mem data input logic [2:0] funct3, // for memory access size + input logic [DATA_WIDTH-1:0] PCtarget, // branch target address + input logic [DATA_WIDTH-1:0] PC, + input loguc [6:0] opcode, output logic [2:0] EQ, // ALU equality flag output logic [DATA_WIDTH-1:0] a0 // x10 output + output loguc [DATA_WIDTH-1:0] ALUout // ALU result ); -logic [DATA_WIDTH-1:0] ALUout; // ALU result logic [DATA_WIDTH-1:0] ALUop1; // ALU operand 1 logic [DATA_WIDTH-1:0] ALUop2; // ALU operand 2 logic [DATA_WIDTH-1:0] WriteData; // register file output 2 @@ -51,7 +54,8 @@ alu alu ( .alu_op2(ALUop2), .alu_ctrl(ALUctrl), .alu_out(ALUout), - .eq(EQ) + .eq(EQ), + .PC(PC) ); // memory @@ -64,11 +68,11 @@ data_mem data_mem ( .funct3(funct3) ); -mux mux2 ( - .in0(ALUout), - .in1(ReadData), - .sel(ResultSrc), - .out(result) -); +case (ResultSrc) + 2'b00: assign ALUout = ALUout; // ALU result + 2'b01: assign ALUout = ReadData; // Memory data + 2'b10: assign ALUout = PCtarget; // PC + 4 for JAL/JALR + default: assign ALUout = ALUout; // Default to ALU result +endcase endmodule diff --git a/repo/rtl/main_decoder.sv b/repo/rtl/main_decoder.sv index f0b968b..47744f2 100644 --- a/repo/rtl/main_decoder.sv +++ b/repo/rtl/main_decoder.sv @@ -1,7 +1,7 @@ module main_decoder ( input logic [6:0] opcode, // 7-bit opcode field from the instruction - output logic ResultSrc, // selects data written to register file (ALU result or memory data) + output logic [1:0] ResultSrc, // selects data written to register file (ALU result or memory data) output logic MemWrite, // enable writing to data memory output logic ALUsrc, // selects ALU second operand (0 = register, 1 = immediate) output logic RegWrite, // enable writing to register file @@ -13,7 +13,7 @@ module main_decoder ( // combinational logic to decode opcode and generate control signals always_comb begin // default values (safe defaults) - ResultSrc = 0; + ResultSrc = 2'b00; MemWrite = 0; ALUsrc = 0; RegWrite = 0; @@ -26,7 +26,7 @@ always_comb begin // load instructions: LB, LH, LW, LBU, LHU // opcode = 0000011 7'b0000011: begin - ResultSrc = 1; // load data from memory + ResultSrc = 2'b01; // load data from memory MemWrite = 0; ALUsrc = 1; // use immediate for address RegWrite = 1; @@ -38,7 +38,7 @@ always_comb begin // store instructions: SB, SH, SW S-type // opcode = 0100011 7'b0100011: begin - ResultSrc = 0; // don't care + ResultSrc = 2'b00; // don't care MemWrite = 1; // write to data memory ALUsrc = 1; // use immediate for address RegWrite = 0; @@ -50,7 +50,7 @@ always_comb begin // R-type instructions: ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND // opcode = 0110011 7'b0110011: begin - ResultSrc = 0; + ResultSrc = 2'b00; MemWrite = 0; ALUsrc = 0; // second operand from register RegWrite = 1; @@ -62,7 +62,7 @@ always_comb begin // B-type instructions: BEQ, BNE, BLT, BGE, BLTU, BGEU // opcode = 1100011 7'b1100011: begin - ResultSrc = 0; // don't care + ResultSrc = 2'b00; // don't care MemWrite = 0; ALUsrc = 0; // use registers RegWrite = 0; @@ -74,7 +74,7 @@ always_comb begin // I-type arithmetic: ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI // opcode = 0010011 7'b0010011: begin - ResultSrc = 0; + ResultSrc = 2'b00; MemWrite = 0; ALUsrc = 1; // use immediate RegWrite = 1; @@ -86,7 +86,7 @@ always_comb begin // AUIPC (U-type) // opcode = 0010111 7'b0010111: begin - ResultSrc = 0; + ResultSrc = 2'b00; MemWrite = 0; ALUsrc = 1; RegWrite = 1; @@ -98,7 +98,7 @@ always_comb begin // LUI (U-type) // opcode = 0110111 7'b0110111: begin - ResultSrc = 0; + ResultSrc = 2'b00; MemWrite = 0; ALUsrc = 1; RegWrite = 1; @@ -110,7 +110,7 @@ always_comb begin // JAL (J-type) // opcode = 1101111 7'b1101111: begin - ResultSrc = 0; // return address is PC+4 (handled in datapath) + ResultSrc = 2'b10; // return address is PC+4 (handled in datapath) MemWrite = 0; ALUsrc = 1; RegWrite = 1; // write x[rd] = PC+4 @@ -122,7 +122,7 @@ always_comb begin // JALR (I-type) // opcode = 1100111 7'b1100111: begin - ResultSrc = 0; + ResultSrc = 2'b10; MemWrite = 0; ALUsrc = 1; RegWrite = 1; @@ -132,7 +132,7 @@ always_comb begin end default: begin - ResultSrc = 0; + ResultSrc = 2'b00; MemWrite = 0; ALUsrc = 0; RegWrite = 0; diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index 8b5ae92..43d6e06 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -13,7 +13,7 @@ logic ALUSrc; logic [2:0] ALUctrl; // 3-bit ALU control logic [2:0] ImmSrc; // 2-bit immediate logic [1:0] ResultSrc; -logic PCsrc; +logic [1:0] PCsrc; logic MemWrite; logic [2:0] EQ; logic [2:0] funct3; @@ -23,7 +23,9 @@ logic [DATA_WIDTH-1:0] pc; logic [DATA_WIDTH-1:0] instr; logic [DATA_WIDTH-1:0] ImmOp; logic [DATA_WIDTH-1:0] PCtarget; +logic [DATA_WIDTH-1:0] ALUout; +logic [6:0] opcode = instr[6:0]; // register file address fields logic [ADDRESS_WIDTH-1:0] rs1; logic [ADDRESS_WIDTH-1:0] rs2; @@ -41,7 +43,8 @@ PC pc_module ( .rst(rst), .PCsrc(PCsrc), .ImmOp(PCtarget), - .pc(pc) + .pc(pc), + .JALRjump(ALUout) ); // instruction memory: fetch instruction at PC @@ -85,7 +88,12 @@ data_unit data_unit ( .MemWrite(MemWrite), .EQ(EQ), .a0(a0), - .funct3(funct3) + .funct3(funct3), + .PCtarget(PCtarget), + .ALUout(ALUout), + .PC(pc), + .opcode(opcode) + ); endmodule From d8764d02c5bac756f8a012f63f20b7b5020513b3 Mon Sep 17 00:00:00 2001 From: Sicovo Date: Wed, 26 Nov 2025 12:53:13 +0000 Subject: [PATCH 36/65] I/O Updated --- repo/rtl/main_decoder.sv | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/repo/rtl/main_decoder.sv b/repo/rtl/main_decoder.sv index 47744f2..55d9615 100644 --- a/repo/rtl/main_decoder.sv +++ b/repo/rtl/main_decoder.sv @@ -1,13 +1,16 @@ module main_decoder ( input logic [6:0] opcode, // 7-bit opcode field from the instruction - output logic [1:0] ResultSrc, // selects data written to register file (ALU result or memory data) + output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4) + output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) output logic MemWrite, // enable writing to data memory - output logic ALUsrc, // selects ALU second operand (0 = register, 1 = immediate) + output logic ALUSrc, // selects ALU second operand (0 = register, 1 = immediate) output logic RegWrite, // enable writing to register file output logic Branch, // indicates branch instruction - output logic [2:0] ImmSrc, // selects type of immediate + output logic Jump, + output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, U = 011, J = 100) output logic [1:0] ALUOp, // encodes ALU operation type (passed to ALU control) + output logic [2:0] AddressingControl ); // combinational logic to decode opcode and generate control signals @@ -15,7 +18,7 @@ always_comb begin // default values (safe defaults) ResultSrc = 2'b00; MemWrite = 0; - ALUsrc = 0; + ALUSrc = 0; RegWrite = 0; Branch = 0; ImmSrc = 3'b000; @@ -28,7 +31,7 @@ always_comb begin 7'b0000011: begin ResultSrc = 2'b01; // load data from memory MemWrite = 0; - ALUsrc = 1; // use immediate for address + ALUSrc = 1; // use immediate for address RegWrite = 1; Branch = 0; ImmSrc = 3'b000; // I-type immediate @@ -40,7 +43,7 @@ always_comb begin 7'b0100011: begin ResultSrc = 2'b00; // don't care MemWrite = 1; // write to data memory - ALUsrc = 1; // use immediate for address + ALUSrc = 1; // use immediate for address RegWrite = 0; Branch = 0; ImmSrc = 3'b001; // S-type immediate @@ -52,7 +55,7 @@ always_comb begin 7'b0110011: begin ResultSrc = 2'b00; MemWrite = 0; - ALUsrc = 0; // second operand from register + ALUSrc = 0; // second operand from register RegWrite = 1; Branch = 0; ImmSrc = 3'b000; // don't care @@ -64,7 +67,7 @@ always_comb begin 7'b1100011: begin ResultSrc = 2'b00; // don't care MemWrite = 0; - ALUsrc = 0; // use registers + ALUSrc = 0; // use registers RegWrite = 0; Branch = 1; // enable branch logic ImmSrc = 3'b010; // B-type immediate @@ -76,7 +79,7 @@ always_comb begin 7'b0010011: begin ResultSrc = 2'b00; MemWrite = 0; - ALUsrc = 1; // use immediate + ALUSrc = 1; // use immediate RegWrite = 1; Branch = 0; ImmSrc = 3'b000; // I-type immediate @@ -88,7 +91,7 @@ always_comb begin 7'b0010111: begin ResultSrc = 2'b00; MemWrite = 0; - ALUsrc = 1; + ALUSrc = 1; RegWrite = 1; Branch = 0; ImmSrc = 3'b011; // U-type immediate @@ -100,7 +103,7 @@ always_comb begin 7'b0110111: begin ResultSrc = 2'b00; MemWrite = 0; - ALUsrc = 1; + ALUSrc = 1; RegWrite = 1; Branch = 0; ImmSrc = 3'b011; // U-type immediate @@ -112,7 +115,7 @@ always_comb begin 7'b1101111: begin ResultSrc = 2'b10; // return address is PC+4 (handled in datapath) MemWrite = 0; - ALUsrc = 1; + ALUSrc = 1; RegWrite = 1; // write x[rd] = PC+4 Branch = 0; ImmSrc = 3'b100; @@ -124,7 +127,7 @@ always_comb begin 7'b1100111: begin ResultSrc = 2'b10; MemWrite = 0; - ALUsrc = 1; + ALUSrc = 1; RegWrite = 1; Branch = 0; ImmSrc = 3'b000; @@ -134,7 +137,7 @@ always_comb begin default: begin ResultSrc = 2'b00; MemWrite = 0; - ALUsrc = 0; + ALUSrc = 0; RegWrite = 0; Branch = 0; ImmSrc = 3'b000; From 42b217f1f03adddb752668202ec1702c10dd756d Mon Sep 17 00:00:00 2001 From: Sicovo Date: Wed, 26 Nov 2025 13:59:57 +0000 Subject: [PATCH 37/65] Full ISA Supported --- repo/rtl/main_decoder.sv | 133 +++++++++++++++------------------------ 1 file changed, 51 insertions(+), 82 deletions(-) diff --git a/repo/rtl/main_decoder.sv b/repo/rtl/main_decoder.sv index 55d9615..501c927 100644 --- a/repo/rtl/main_decoder.sv +++ b/repo/rtl/main_decoder.sv @@ -1,39 +1,39 @@ module main_decoder ( input logic [6:0] opcode, // 7-bit opcode field from the instruction - - output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4) - output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) - output logic MemWrite, // enable writing to data memory - output logic ALUSrc, // selects ALU second operand (0 = register, 1 = immediate) + output logic RegWrite, // enable writing to register file + output logic ALUSrc, // selects ALU second operand (0 = register, 1 = immediate) + output logic MemWrite, // enable writing to data memory + output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4, 11 = imm) + output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) output logic Branch, // indicates branch instruction - output logic Jump, - output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, U = 011, J = 100) - output logic [1:0] ALUOp, // encodes ALU operation type (passed to ALU control) - output logic [2:0] AddressingControl + output logic Jump, // indicates jump instruction + output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) + output logic [1:0] ALUOp // encodes ALU operation type (00 = ADD category(load/store/addi/auipc/jalr), 01 = SUB category(branch), 10 = R-type/I-type) + ); // combinational logic to decode opcode and generate control signals always_comb begin // default values (safe defaults) + RegWrite = 1'b0; + ALUSrc = 1'b0; + MemWrite = 1'b0; ResultSrc = 2'b00; - MemWrite = 0; - ALUSrc = 0; - RegWrite = 0; - Branch = 0; - ImmSrc = 3'b000; - ALUOp = 2'b00; + PCSrc = 2'b00; + Branch = 1'b0; + Jump = 1'b0; + ImmSrc = 3'b000; + ALUOp = 2'b00; case(opcode) // load instructions: LB, LH, LW, LBU, LHU // opcode = 0000011 7'b0000011: begin + RegWrite = 1'b1; + ALUSrc = 1'b1; ResultSrc = 2'b01; // load data from memory - MemWrite = 0; - ALUSrc = 1; // use immediate for address - RegWrite = 1; - Branch = 0; ImmSrc = 3'b000; // I-type immediate ALUOp = 2'b00; // ALU does ADD for address end @@ -41,107 +41,76 @@ always_comb begin // store instructions: SB, SH, SW S-type // opcode = 0100011 7'b0100011: begin - ResultSrc = 2'b00; // don't care - MemWrite = 1; // write to data memory - ALUSrc = 1; // use immediate for address - RegWrite = 0; - Branch = 0; - ImmSrc = 3'b001; // S-type immediate - ALUOp = 2'b00; // ALU does ADD for address + MemWrite = 1'b1; + ALUSrc = 1'b1; + ImmSrc = 3'b001; // S-type immediate end // R-type instructions: ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND // opcode = 0110011 7'b0110011: begin - ResultSrc = 2'b00; - MemWrite = 0; - ALUSrc = 0; // second operand from register - RegWrite = 1; - Branch = 0; - ImmSrc = 3'b000; // don't care - ALUOp = 2'b10; // R-type ALU decoding + RegWrite = 1'b1; + ALUSrc = 1'b0; + ALUOp = 2'b10; end // B-type instructions: BEQ, BNE, BLT, BGE, BLTU, BGEU // opcode = 1100011 7'b1100011: begin - ResultSrc = 2'b00; // don't care - MemWrite = 0; - ALUSrc = 0; // use registers - RegWrite = 0; - Branch = 1; // enable branch logic + Branch = 1'b1; ImmSrc = 3'b010; // B-type immediate - ALUOp = 2'b01; // ALU subtracts for comparison + ALUOp = 2'b01; // ALU does SUB for comparison end // I-type arithmetic: ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI // opcode = 0010011 7'b0010011: begin - ResultSrc = 2'b00; - MemWrite = 0; - ALUSrc = 1; // use immediate - RegWrite = 1; - Branch = 0; - ImmSrc = 3'b000; // I-type immediate - ALUOp = 2'b11; // I-type ALU (distinct from R-type) + RegWrite = 1'b1; + ALUSrc = 1'b1; + ALUOp = 2'b10; + ImmSrc = 3'b000; // I-type immediate end // AUIPC (U-type) // opcode = 0010111 7'b0010111: begin - ResultSrc = 2'b00; - MemWrite = 0; - ALUSrc = 1; - RegWrite = 1; - Branch = 0; - ImmSrc = 3'b011; // U-type immediate + RegWrite = 1'b1; + ImmSrc = 3'b100; // U-type immediate + ALUSrc = 1'b1; ALUOp = 2'b00; + ResultSrc = 2'b00; end // LUI (U-type) // opcode = 0110111 7'b0110111: begin + RegWrite = 1'b1; + ImmSrc = 3'b100; // U-type immediate ResultSrc = 2'b00; - MemWrite = 0; - ALUSrc = 1; - RegWrite = 1; - Branch = 0; - ImmSrc = 3'b011; // U-type immediate - ALUOp = 2'b00; + ALUSrc = 1'b1; + ALUOp = 2'b00; //ALU does ADD with 0 + imm end // JAL (J-type) // opcode = 1101111 7'b1101111: begin - ResultSrc = 2'b10; // return address is PC+4 (handled in datapath) - MemWrite = 0; - ALUSrc = 1; - RegWrite = 1; // write x[rd] = PC+4 - Branch = 0; - ImmSrc = 3'b100; - ALUOp = 2'b00; + RegWrite = 1'b1; + Jump = 1'b1; + ResultSrc = 2'b10; // return address is PC+4 written to rd + ImmSrc = 3'b011; // J-type immediate + PCSrc = 2'b01; // PC + imm end // JALR (I-type) // opcode = 1100111 7'b1100111: begin - ResultSrc = 2'b10; - MemWrite = 0; - ALUSrc = 1; - RegWrite = 1; - Branch = 0; - ImmSrc = 3'b000; - ALUOp = 2'b00; - end - - default: begin - ResultSrc = 2'b00; - MemWrite = 0; - ALUSrc = 0; - RegWrite = 0; - Branch = 0; - ImmSrc = 3'b000; - ALUOp = 2'b00; + RegWrite = 1'b1; + Jump = 1'b1; + ResultSrc = 2'b10; // return address is PC+4 written to rd + ImmSrc = 3'b000; // I-type immediate + ALUSrc = 1'b1; + ALUOp = 2'b00; // ALU does ADD for address calculation + PCSrc = 2'b10; // ALU result (rs1 + imm) end endcase end From 6859162677dfe33eb24bb89de5100ca4abc0ec2c Mon Sep 17 00:00:00 2001 From: Sicovo Date: Wed, 26 Nov 2025 21:59:03 +0000 Subject: [PATCH 38/65] ALUOp = 10 for I-type/R-type for better implementation in pipeline --- repo/rtl/alu_decoder.sv | 80 +++++++++++++++++----------------------- repo/rtl/main_decoder.sv | 8 +++- 2 files changed, 40 insertions(+), 48 deletions(-) diff --git a/repo/rtl/alu_decoder.sv b/repo/rtl/alu_decoder.sv index a8beed5..dadab97 100644 --- a/repo/rtl/alu_decoder.sv +++ b/repo/rtl/alu_decoder.sv @@ -1,57 +1,44 @@ module alu_decoder ( - input logic [1:0] ALUOp, - input logic [2:0] funct3, - input logic funct75, // funct7[5] - output logic [3:0] ALUControl // extended to 4 bits + input logic [1:0] ALUOp, + input logic [2:0] funct3, + input logic [6:0] funct7, + output logic [3:0] ALUControl ); - // ALUControl encoding (4 bits) - // 0000 = ADD - // 0001 = SUB - // 0010 = AND - // 0011 = OR - // 0100 = XOR - // 0101 = SLL - // 0110 = SRL - // 0111 = SRA - // 1000 = SLT (signed) - // 1001 = SLTU (unsigned) - // (leave others for future) + logic funct7_5; + assign funct7_5 = funct7[5]; always_comb begin - unique case (ALUOp) - // Load/Store/AUIPC: always ADD (address calculation) - 2'b00: ALUControl = 4'b0000; // ADD + case (ALUOp) + + 2'b00: ALUControl = 4'b0000; // add for lw/sw/addi/auipc/jalr/ - // Branch comparison: set to SUB (we also use Zero and SLT flags) - 2'b01: ALUControl = 4'b0001; // SUB + 2'b01: ALUControl = 4'b0001; // sub for beq/bne - // R-type: decode by funct3 + funct7 - 2'b10: begin + 2'b10: begin // r-type/i-type unique case (funct3) - 3'b000: ALUControl = funct75 ? 4'b0001 : 4'b0000; // SUB : ADD - 3'b001: ALUControl = 4'b0101; // SLL - 3'b010: ALUControl = 4'b1000; // SLT (signed) - 3'b011: ALUControl = 4'b1001; // SLTU (unsigned) - 3'b100: ALUControl = 4'b0100; // XOR - 3'b101: ALUControl = funct75 ? 4'b0111 : 4'b0110; // SRA : SRL - 3'b110: ALUControl = 4'b0011; // OR - 3'b111: ALUControl = 4'b0010; // AND - default: ALUControl = 4'b0000; - endcase - end + 3'b000: begin + if ({funct7_5} == 1'b1) + ALUControl = 4'b0001; // sub + else + ALUControl = 4'b0000; // add + end + + 3'b001: ALUControl = 4'b0101; // sll + + 3'b010: ALUControl = 4'b1000; // slt + + 3'b011: ALUControl = 4'b1001; // sltu + 3'b100: ALUControl = 4'b0100; // xor + 3'b101: begin // SRL / SRA / SRLI / SRAI + if (funct7_5 == 1'b1) + ALUControl = 4'b0111; // sra + else + ALUControl = 4'b0110; // srl + end + 3'b110: ALUControl = 4'b0011; // or + 3'b111: ALUControl = 4'b0010; // and - // I-type: similar to R-type but shifts use funct7[5] as well - 2'b11: begin - unique case (funct3) - 3'b000: ALUControl = 4'b0000; // ADDI - 3'b001: ALUControl = 4'b0101; // SLLI (shamt) - 3'b010: ALUControl = 4'b1000; // SLTI - 3'b011: ALUControl = 4'b1001; // SLTIU - 3'b100: ALUControl = 4'b0100; // XORI - 3'b101: ALUControl = funct75 ? 4'b0111 : 4'b0110; // SRAI : SRLI - 3'b110: ALUControl = 4'b0011; // ORI - 3'b111: ALUControl = 4'b0010; // ANDI default: ALUControl = 4'b0000; endcase end @@ -59,5 +46,4 @@ module alu_decoder ( default: ALUControl = 4'b0000; endcase end - -endmodule +endmodule \ No newline at end of file diff --git a/repo/rtl/main_decoder.sv b/repo/rtl/main_decoder.sv index 501c927..89a4840 100644 --- a/repo/rtl/main_decoder.sv +++ b/repo/rtl/main_decoder.sv @@ -67,8 +67,14 @@ always_comb begin 7'b0010011: begin RegWrite = 1'b1; ALUSrc = 1'b1; - ALUOp = 2'b10; ImmSrc = 3'b000; // I-type immediate + + case (funct3) + 3'b000: ALUOp = 2'b00; + + default: ALUOp = 2'b10; + + endcase end // AUIPC (U-type) From 682eec0bd9e4360ef3e6ba3d42d5c0b5182fd3d0 Mon Sep 17 00:00:00 2001 From: Sicovo Date: Thu, 27 Nov 2025 12:16:50 +0000 Subject: [PATCH 39/65] Control path for all ISA --- repo/rtl/alu_decoder.sv | 12 ++++- repo/rtl/control.sv | 103 +++++++++++++++------------------------ repo/rtl/main_decoder.sv | 7 +-- 3 files changed, 50 insertions(+), 72 deletions(-) diff --git a/repo/rtl/alu_decoder.sv b/repo/rtl/alu_decoder.sv index dadab97..1236ba4 100644 --- a/repo/rtl/alu_decoder.sv +++ b/repo/rtl/alu_decoder.sv @@ -11,9 +11,17 @@ module alu_decoder ( always_comb begin case (ALUOp) - 2'b00: ALUControl = 4'b0000; // add for lw/sw/addi/auipc/jalr/ + 2'b00: ALUControl = 4'b0000; // add for lw/sw/addi/auipc/jalr/lui(0 + imm) - 2'b01: ALUControl = 4'b0001; // sub for beq/bne + 2'b01: begin + unique case (funct3) + 3'b100: ALUControl = 4'b1000; // slt for blt + 3'b101: ALUControl = 4'b1000; // !slt for bge + 3'b110: ALUControl = 4'b1001; // sltu for bltu + 3'b111: ALUControl = 4'b1001; // !sltu for bgeu + default: ALUControl = 4'b0001; // sub + endcase + end 2'b10: begin // r-type/i-type unique case (funct3) diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index a55de92..3d9089d 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -1,94 +1,67 @@ module control ( - input logic [31:0] instr, - input logic [2:0] EQ, - output logic RegWrite, - output logic ALUSrc, - output logic [2:0] ALUctrl, - output logic [2:0] ImmSrc, - output logic [1:0] ResultSrc, - output logic MemWrite, - output logic [1:0] PCsrc, - output logic [2:0] funct3 + input logic [31:0] Instr, + input logic Zero, + + output logic [2:0] AddressingControl, // hand to data memory for bit selection (000 = lb/sb, 001 = lh/sh, 010 = lw/sw, 100 = lbu, 101 = lhu) + output logic RegWrite, // enable writing to register file + output logic ALUSrc, // selects ALU second operand (0 = register, 1 = immediate) + output logic MemWrite, // enable writing to data memory + output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4, 11 = imm) + output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + output logic Branch, // indicates branch instruction + output logic Jump, // indicates jump instruction + output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) + output logic [3:0] ALUControl // selects ALU operation ); - // fields - logic [6:0] opcode = instr[6:0]; - logic [6:0] funct7 = instr[31:25]; - assign funct3 = instr[14:12]; + logic [6:0] opcode; + logic [2:0] funct3; + logic [6:0] funct7; + + assign opcode = Instr[6:0]; + assign funct3 = Instr[14:12]; + assign funct7 = Instr[31:25]; + assign AddressingControl = funct3; // store width + // wires between decoders - logic Branch; logic [1:0] ALUOp; - // instantiate main decoder main_decoder main_dec ( .opcode(opcode), + .funct3(funct3), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .ResultSrc(ResultSrc), .MemWrite(MemWrite), .ImmSrc(ImmSrc), .Branch(Branch), + .Jump(Jump), .ALUOp(ALUOp) ); - // instantiate ALU decoder alu_decoder alu_dec ( .ALUOp(ALUOp), .funct3(funct3), - .funct75(funct7[5]), - .ALUctrl(ALUctrl) + .funct7(funct7), + .ALUControl(ALUControl) ); always_comb begin + PCSrc = 2'b00; // default PC+4 + if (Branch) begin - case(funct3) - 3'b000: begin // BEQ - if (EQ == 3'b000) begin - PCsrc = 2'b01; - end - end - 3'b001: begin // BNE - if (EQ == 3'b001) begin - PCsrc = 2'b01; - end - end - 3'b100: begin // BLT - if (EQ == 3'b010) begin - PCsrc = 2'b01; - end - end - 3'b101: begin // BGE - if (EQ == 3'b011) begin - PCsrc = 2'b01; - end - end - 3'b110: begin // BLTU - if (EQ == 3'b100) begin - PCsrc = 2'b01; - end - end - 3'b111: begin // BGEU - if (EQ == 3'b101) begin - PCsrc = 2'b01; - end - end - default: begin - PCsrc = 2'b00; - end + unique case (funct3) + 3'b000: PCSrc = Zero ? 2'b01 : 2'b00; // BEQ + 3'b001: PCSrc = ~Zero ? 2'b01 : 2'b00; // BNE + 3'b100: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLT + 3'b101: PCSrc = Zero ? 2'b01 : 2'b00; // BGE + 3'b110: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLTU + 3'b111: PCSrc = Zero ? 2'b01 : 2'b00; // BGEU endcase end - - case(opcode) - 7'b1101111: begin // JAL - PCsrc = 2'b01; - end - 7'b1100111: begin // JALR - PCsrc = 2'b10; - end - default: begin - PCsrc = 2'b00; - end - endcase + + if (opcode == 7'b1101111) PCSrc = 2'b01; // JAL + if (opcode == 7'b1100111) PCSrc = 2'b10; // JALR end endmodule diff --git a/repo/rtl/main_decoder.sv b/repo/rtl/main_decoder.sv index 89a4840..7a768f9 100644 --- a/repo/rtl/main_decoder.sv +++ b/repo/rtl/main_decoder.sv @@ -1,11 +1,11 @@ module main_decoder ( input logic [6:0] opcode, // 7-bit opcode field from the instruction + input logic [2:0] funct3, // 3-bit funct3 field from the instruction output logic RegWrite, // enable writing to register file output logic ALUSrc, // selects ALU second operand (0 = register, 1 = immediate) output logic MemWrite, // enable writing to data memory output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4, 11 = imm) - output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) output logic Branch, // indicates branch instruction output logic Jump, // indicates jump instruction output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) @@ -20,7 +20,6 @@ always_comb begin ALUSrc = 1'b0; MemWrite = 1'b0; ResultSrc = 2'b00; - PCSrc = 2'b00; Branch = 1'b0; Jump = 1'b0; ImmSrc = 3'b000; @@ -59,7 +58,7 @@ always_comb begin 7'b1100011: begin Branch = 1'b1; ImmSrc = 3'b010; // B-type immediate - ALUOp = 2'b01; // ALU does SUB for comparison + ALUOp = 2'b01; // ALU does SUB for BEQ/BNE (other comparisons handled in ALU decoder) end // I-type arithmetic: ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI @@ -104,7 +103,6 @@ always_comb begin Jump = 1'b1; ResultSrc = 2'b10; // return address is PC+4 written to rd ImmSrc = 3'b011; // J-type immediate - PCSrc = 2'b01; // PC + imm end // JALR (I-type) @@ -116,7 +114,6 @@ always_comb begin ImmSrc = 3'b000; // I-type immediate ALUSrc = 1'b1; ALUOp = 2'b00; // ALU does ADD for address calculation - PCSrc = 2'b10; // ALU result (rs1 + imm) end endcase end From 54fd695da11e644287595f99ab1fef99bec6bc64 Mon Sep 17 00:00:00 2001 From: Sicovo Date: Thu, 27 Nov 2025 21:32:43 +0000 Subject: [PATCH 40/65] Single Cycle RV32I Processor --- repo/rtl/PC.sv | 43 ------ repo/rtl/alu.sv | 65 +++----- repo/rtl/alu_decoder.sv | 57 ------- repo/rtl/contol_path.sv | 54 +++++++ repo/rtl/control.sv | 230 ++++++++++++++++++++++------- repo/rtl/data_mem.sv | 80 +++++----- repo/rtl/data_path.sv | 84 +++++++++++ repo/rtl/data_unit.sv | 78 ---------- repo/rtl/{imem.sv => instr_mem.sv} | 12 +- repo/rtl/main_decoder.sv | 121 --------------- repo/rtl/mux.sv | 14 -- repo/rtl/pc.sv | 38 +++++ repo/rtl/pcsrc_unit.sv | 34 +++++ repo/rtl/reg_file.sv | 38 +++-- repo/rtl/register.sv | 12 -- repo/rtl/signext.sv | 52 ++----- repo/rtl/top.sv | 147 +++++++----------- 17 files changed, 523 insertions(+), 636 deletions(-) delete mode 100644 repo/rtl/PC.sv delete mode 100644 repo/rtl/alu_decoder.sv create mode 100644 repo/rtl/contol_path.sv create mode 100644 repo/rtl/data_path.sv delete mode 100644 repo/rtl/data_unit.sv rename repo/rtl/{imem.sv => instr_mem.sv} (53%) delete mode 100644 repo/rtl/main_decoder.sv delete mode 100644 repo/rtl/mux.sv create mode 100644 repo/rtl/pc.sv create mode 100644 repo/rtl/pcsrc_unit.sv delete mode 100644 repo/rtl/register.sv diff --git a/repo/rtl/PC.sv b/repo/rtl/PC.sv deleted file mode 100644 index 090778e..0000000 --- a/repo/rtl/PC.sv +++ /dev/null @@ -1,43 +0,0 @@ -module PC #( - parameter WIDTH = 32 -)( - input logic clk, // system clock - input logic rst, // asynchronous reset - input logic [1:0] PCsrc, // selects between sequential PC and branch target - input logic [WIDTH-1:0] ImmOp, // immediate offset for branch target - input logic [WIDTH-1:0] JALRjump, // current program counter input - output logic [WIDTH-1:0] pc // current program counter -); - -// compute PC+4 (normal sequential execution) -logic [WIDTH-1:0] inc_PC; - -// compute PC+immediate (branch target address) -logic [WIDTH-1:0] branch_PC; - -// next PC after the mux -logic [WIDTH-1:0] next_PC; - -// add 4 to PC for next instruction -assign inc_PC = pc + {{WIDTH-3{1'b0}}, 3'b100}; - -// add immediate offset to PC for branch target -assign branch_PC = pc + ImmOp; - -// select between sequential PC and branch PC and JALR target -case(PCsrc) - 2'b00: assign next_PC = inc_PC; // Next sequential instruction - 2'b01: assign next_PC = branch_PC; // Branch target - 2'b10: assign next_PC = JALRjump; // JALR target - default: assign next_PC = inc_PC; // Default to sequential -endcase - -// program counter register with asynchronous reset -always_ff @(posedge clk or posedge rst) begin - if (rst) - pc <= {WIDTH{1'b0}}; // Reset PC to 0 - else - pc <= next_PC; // Update PC normally -end - -endmodule diff --git a/repo/rtl/alu.sv b/repo/rtl/alu.sv index 24ad38d..5a0f2e4 100644 --- a/repo/rtl/alu.sv +++ b/repo/rtl/alu.sv @@ -8,65 +8,34 @@ // 0111 = SRA // 1000 = SLT (signed) // 1001 = SLTU (unsigned) + // 1111 = LUI operation module alu ( input logic [31:0] SrcA, input logic [31:0] SrcB, input logic [3:0] ALUControl, - input logic [31:0] PC, - input logic [6:0] opcode, output logic [31:0] ALUResult, - output logic [2:0] Zero + output logic Zero ); always_comb begin + case (ALUControl) + 4'b0000: ALUResult = SrcA + SrcB; // add + 4'b0001: ALUResult = SrcA - SrcB; // sub + 4'b0010: ALUResult = SrcA & SrcB; // and + 4'b0011: ALUResult = SrcA | SrcB; // or + 4'b0100: ALUResult = SrcA ^ SrcB; // xor - case(opcode) - 7'b0110111: begin // LUI - ALUResult = SrcB; // Load Upper Immediate - end - 7'b0010111: begin // AUIPC - ALUResult = PC + SrcB; // Add Upper Immediate to PC - end - default: begin - // perform ALU operation based on ALUControl signal + 4'b0101: ALUResult = SrcA << SrcB[4:0]; // sll + 4'b0110: ALUResult = SrcA >> SrcB[4:0]; // srl + 4'b0111: ALUResult = $signed(SrcA) >>> SrcB[4:0]; // sra + 4'b1000: ALUResult = ($signed(SrcA) < $signed(SrcB)) ? 32'b1 : 32'b0; //slt + 4'b1001: ALUResult = (SrcA < SrcB) ? 32'b1 : 32'b0; //sltu + 4'b1111: ALUResult = SrcB; // LUI operation (Load Upper Immediate) - case (ALUControl) - 4'b0000: ALUResult = SrcA + SrcB; // add - 4'b0001: ALUResult = SrcA - SrcB; // sub - 4'b0010: ALUResult = SrcA & SrcB; // and - 4'b0011: ALUResult = SrcA | SrcB; // or - 4'b0100: ALUResult = SrcA ^ SrcB; // xor - - 4'b0101 : ALUResult = SrcA << SrcB[4:0]; // sll - 4'b0110: ALUResult = SrcA >> SrcB[4:0]; // srl - 4'b0111: ALUResult = $signed(SrcA) >>> SrcB[4:0]; // sra - 4'b1000: ALUResult = ($signed(SrcA) < $signed(SrcB)) ? 32'b1 : 32'b0; //slt - 4'b1001: ALUResult = (SrcA < SrcB) ? 32'b1 : 32'b0; //sltu - default: ALUResult = 32'b0; - - endcase - - if ($signed(SrcA) == $signed(SrcB)) begin - assign Zero = 3'b000; // zero flag - end - if ($signed(SrcA) != $signed(SrcB)) begin - assign Zero = 3'b001; // not equal - end - if ($signed(SrcA) < $signed(SrcB)) begin - assign Zero = 3'b010; // less than flag - end - if ($signed(SrcA) >= $signed(SrcB)) begin - assign Zero = 3'b011; // greater/equal than flag - end - if ($unsigned(SrcA) < $unsigned(SrcB)) begin - assign Zero = 3'b100; // less than flag unsigned - end - if ($unsigned(SrcA) >= $unsigned(SrcB)) begin - assign Zero = 3'b101; // greater/equal than flag unsinged - end - - end + default: ALUResult = 32'b0; endcase + + Zero = (ALUResult == 32'd0); end endmodule \ No newline at end of file diff --git a/repo/rtl/alu_decoder.sv b/repo/rtl/alu_decoder.sv deleted file mode 100644 index 1236ba4..0000000 --- a/repo/rtl/alu_decoder.sv +++ /dev/null @@ -1,57 +0,0 @@ -module alu_decoder ( - input logic [1:0] ALUOp, - input logic [2:0] funct3, - input logic [6:0] funct7, - output logic [3:0] ALUControl -); - - logic funct7_5; - assign funct7_5 = funct7[5]; - - always_comb begin - case (ALUOp) - - 2'b00: ALUControl = 4'b0000; // add for lw/sw/addi/auipc/jalr/lui(0 + imm) - - 2'b01: begin - unique case (funct3) - 3'b100: ALUControl = 4'b1000; // slt for blt - 3'b101: ALUControl = 4'b1000; // !slt for bge - 3'b110: ALUControl = 4'b1001; // sltu for bltu - 3'b111: ALUControl = 4'b1001; // !sltu for bgeu - default: ALUControl = 4'b0001; // sub - endcase - end - - 2'b10: begin // r-type/i-type - unique case (funct3) - 3'b000: begin - if ({funct7_5} == 1'b1) - ALUControl = 4'b0001; // sub - else - ALUControl = 4'b0000; // add - end - - 3'b001: ALUControl = 4'b0101; // sll - - 3'b010: ALUControl = 4'b1000; // slt - - 3'b011: ALUControl = 4'b1001; // sltu - 3'b100: ALUControl = 4'b0100; // xor - 3'b101: begin // SRL / SRA / SRLI / SRAI - if (funct7_5 == 1'b1) - ALUControl = 4'b0111; // sra - else - ALUControl = 4'b0110; // srl - end - 3'b110: ALUControl = 4'b0011; // or - 3'b111: ALUControl = 4'b0010; // and - - default: ALUControl = 4'b0000; - endcase - end - - default: ALUControl = 4'b0000; - endcase - end -endmodule \ No newline at end of file diff --git a/repo/rtl/contol_path.sv b/repo/rtl/contol_path.sv new file mode 100644 index 0000000..181eb21 --- /dev/null +++ b/repo/rtl/contol_path.sv @@ -0,0 +1,54 @@ +module control_path #( + input logic [31:0] Instr, + input logic Zero, + + output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + output logic RegWrite, // enable write to register + output logic [3:0] ALUControl, // control operation in ALU + output logic ALUSrcA, // choose PC (1) or register (0) for ALU operand A + output logic ALUSrcB, // choose immediate (1) or register (0) operand + output logic MemWrite, // enable write into the data memory + // output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4) + output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) + output logic [2:0] AddressingControl // choose which type of load/store instruction to perform +); + + logic Branch; + logic [2:0] BranchType; + logic [1:0] Jump; + + logic [6:0] opcode; + logic [2:0] funct3; + logic [6:0] funct7; + + assign opcode = Instr[6:0]; + assign funct3 = Instr[14:12]; + assign funct7 = Instr[31:25]; + + control control_unit ( + .opcode(opcode), + .funct3(funct3), + .funct7(funct7), + .RegWrite(RegWrite), + .ALUControl(ALUControl), + .ALUSrcA(ALUSrcA), + .ALUSrcB(ALUSrcB), + .MemWrite(MemWrite), + .ResultSrc(ResultSrc), + .Branch(Branch), + .BranchType(BranchType), + .Jump(Jump), + .ImmSrc(ImmSrc), + .AddressingControl(AddressingControl) + ); + + pcsrc_unit pcsrc_unit_inst ( + .Jump(Jump), + .Branch(Branch), + .Zero(Zero), + .BranchType(BranchType), + .PCSrc(PCSrc) + ); + +endmodule \ No newline at end of file diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index 3d9089d..01b35ef 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -1,67 +1,185 @@ -module control ( - input logic [31:0] Instr, - input logic Zero, - - output logic [2:0] AddressingControl, // hand to data memory for bit selection (000 = lb/sb, 001 = lh/sh, 010 = lw/sw, 100 = lbu, 101 = lhu) - output logic RegWrite, // enable writing to register file - output logic ALUSrc, // selects ALU second operand (0 = register, 1 = immediate) - output logic MemWrite, // enable writing to data memory - output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4, 11 = imm) - output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) - output logic Branch, // indicates branch instruction - output logic Jump, // indicates jump instruction - output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) - output logic [3:0] ALUControl // selects ALU operation +module control #( + input logic [6:0] opcode, + input logic [2:0] funct3, + input logic [6:0] funct7, + + output logic RegWrite, // enable write to register + output logic [3:0] ALUControl, // control operation in ALU + output logic ALUSrcA, // choose PC (1) or register (0) for ALU operand A + output logic ALUSrcB, // choose immediate (1) or register (0) operand + output logic MemWrite, // enable write into the data memory + // output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4) + output logic Branch, + output logic [2:0] BranchType, + output logic [1:0] Jump, // indicates jump instruction (00 = no jump, 01 = JAL, 10 = JALR) + output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) + output logic [2:0] AddressingControl // choose which type of load/store instruction to perform ); - logic [6:0] opcode; - logic [2:0] funct3; - logic [6:0] funct7; + // logic [6:0] opcode; + // logic [2:0] funct3; + // logic [6:0] funct7; - assign opcode = Instr[6:0]; - assign funct3 = Instr[14:12]; - assign funct7 = Instr[31:25]; + // assign opcode = Instr[6:0]; + // assign funct3 = Instr[14:12]; + // assign funct7 = Instr[31:25]; assign AddressingControl = funct3; // store width - // wires between decoders - logic [1:0] ALUOp; + always_comb begin + // Default values to prevent latches + RegWrite = 1'b0; + ALUControl = 4'b0000; + ALUSrcA = 1'b0; + ALUSrcB = 1'b0; + MemWrite = 1'b0; + ResultSrc = 2'b00; + Branch = 1'b0; + BranchType = 3'b000; + Jump = 2'b00; + ImmSrc = 3'b000; + AddressingControl = 3'b000; - main_decoder main_dec ( - .opcode(opcode), - .funct3(funct3), - .RegWrite(RegWrite), - .ALUSrc(ALUSrc), - .ResultSrc(ResultSrc), - .MemWrite(MemWrite), - .ImmSrc(ImmSrc), - .Branch(Branch), - .Jump(Jump), - .ALUOp(ALUOp) - ); - alu_decoder alu_dec ( - .ALUOp(ALUOp), - .funct3(funct3), - .funct7(funct7), - .ALUControl(ALUControl) - ); + case(opcode) + // R-type instructions + 7'b0110011: begin + RegWrite = 1'b1; + ALUSrc = 1'b0; + + case(funct3) + 3'b000: begin + case(funct7) + 7'b0000000: ALUControl = 4'b0000; // add + 7'b0100000: ALUControl = 4'b0001; // sub + default: ALUControl = 4'b0000; + endcase + end + 3'b001: ALUControl = 4'b0101; // sll + 3'b010: ALUControl = 4'b1000; // slt + 3'b011: ALUControl = 4'b1001; // sltu + 3'b100: ALUControl = 4'b0100; // xor + 3'b101: begin + case(funct7) + 7'b0000000: ALUControl = 4'b0110; // srl + 7'b0100000: ALUControl = 4'b0111; // sra + default: ALUControl = 4'b0110; + endcase + end + 3'b110: ALUControl = 4'b0011; // or + 3'b111: ALUControl = 4'b0010; // and - always_comb begin - PCSrc = 2'b00; // default PC+4 + default: ALUControl = 4'b0000; + endcase + end - if (Branch) begin - unique case (funct3) - 3'b000: PCSrc = Zero ? 2'b01 : 2'b00; // BEQ - 3'b001: PCSrc = ~Zero ? 2'b01 : 2'b00; // BNE - 3'b100: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLT - 3'b101: PCSrc = Zero ? 2'b01 : 2'b00; // BGE - 3'b110: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLTU - 3'b111: PCSrc = Zero ? 2'b01 : 2'b00; // BGEU - endcase - end + // I-type instructions (Arithmetic/Logic) + 7'b0010011: begin + RegWrite = 1'b1; + ImmSrc = 3'b000; // I-type imm + ALUSrcB = 1'b1; + + case(funct3) + 3'b000: ALUControl = 4'b0000; // addi + 3'b001: ALUControl = 4'b0101; // slli + 3'b010: ALUControl = 4'b1000; // slti (Added) + 3'b011: ALUControl = 4'b1001; // sltiu (Added) + 3'b100: ALUControl = 4'b0100; // xori + 3'b101: begin + case(funct7) + 7'b0000000: ALUControl = 4'b0110; // srli + 7'b0100000: ALUControl = 4'b0111; // srai + default: ALUControl = 4'b0110; + endcase + end + 3'b110: ALUControl = 4'b0011; // ori + 3'b111: ALUControl = 4'b0010; // andi + default: ALUControl = 4'b0000; + endcase + end - if (opcode == 7'b1101111) PCSrc = 2'b01; // JAL - if (opcode == 7'b1100111) PCSrc = 2'b10; // JALR - end + // I-type Load instructions + 7'b0000011: begin + RegWrite = 1'b1; + ALUSrcB = 1'b1; // SrcB = imm + ResultSrc = 2'b01; // From Memory + ImmSrc = 3'b000; // I-type imm + AddressingControl = funct3; + ALUControl = 4'b0000; // Add for address + end + + // S-type Store instructions + 7'b0100011: begin + MemWrite = 1'b1; + ALUSrcB = 1'b1; // read from immediate + ImmSrc = 3'b001; // S-type immediate + ALUControl = 4'b0000; // Add for address + AddressingControl = funct3; + end -endmodule + // B-type Branch instructions + 7'b1100011: begin + Branch = 1'b1; + ImmSrc = 3'b010; // B-type imm + BranchType = funct3; + + case(funct3) + // BEQ, BNE: ALU does SUB (0001) + // If A == B, Result = 0, Zero = 1 + 3'b000: ALUControl = 4'b0001; // beq + 3'b001: ALUControl = 4'b0001; // bne + + // BLT, BGE: ALU does SLT (1000) + // If A < B: Result = 1, Zero = 0. If A >= B: Result = 0, Zero = 1. + 3'b100: ALUControl = 4'b1000; // blt + 3'b101: ALUControl = 4'b1000; // bge + + // BLTU, BGEU: ALU does SLTU (1001) + 3'b110: ALUControl = 4'b1001; // bltu + 3'b111: ALUControl = 4'b1001; // bgeu + endcase + end + + // J-type JAL + 7'b1101111: begin + RegWrite = 1'b1; + ResultSrc = 2'b10; // PC+4 + ImmSrc = 3'b011; // J-type imm + Jump = 2'b01; + end + + // I-type JALR + 7'b1100111: begin + RegWrite = 1'b1; + ALUSrcB = 1'b1; // SrcB = imm + ResultSrc = 2'b10; // PC+4 + ImmSrc = 3'b000; // I-type imm + Jump = 2'b10; + // ALUControl = 4'b0000; // Add for target address + end + + // U-type LUI + 7'b0110111: begin + RegWrite = 1'b1; + ALUSrcB = 1'b1; + ResultSrc = 2'b00; + ImmSrc = 3'b100; // U-type imm + ALUControl = 4'b1111; // LUI operation (0 + imm shifted) + end + + // U-type AUIPC rd <- PC + imm << 12 + 7'b0010111: begin + RegWrite = 1'b1; + MemWrite = 1'b0; + ALUSrcA = 1'b1; // Select PC + ALUSrcB = 1'b1; // Select Imm + ImmSrc = 3'b100; // U-type imm + ALUControl = 4'b000; // AUIPC operation (PC + imm shifted) + end + + default: begin + // Already handled by defaults at top + end + endcase + end +endmodule \ No newline at end of file diff --git a/repo/rtl/data_mem.sv b/repo/rtl/data_mem.sv index b21fe1d..25ced8f 100644 --- a/repo/rtl/data_mem.sv +++ b/repo/rtl/data_mem.sv @@ -1,57 +1,49 @@ module data_mem #( - parameter DATA_WIDTH = 32, - ADDRESS_WIDTH = 32 + parameter XLEN = 32, + parameter ADDRESS_WIDTH = 16, + parameter DATA_WIDTH = 8 ) ( - input logic clk, - input logic en, // write enable - input logic [ADDRESS_WIDTH-1:0] wr_addr, // memory address - input logic [DATA_WIDTH-1:0] din, // data to write - input logic [2:0] funct3, // for byte/halfword/word selection - output logic [DATA_WIDTH-1:0] dout // data read + input logic clk, + input logic WE, // write enable + input logic [XLEN-1:0] A, // memory address + input logic [XLEN-1:0] WD, // data to write + input logic [2:0] AddressingControl, // funct3 to determine load/store type + output logic [XLEN-1:0] RD // data read ); + logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; // 64KB data memory - // 2^32 32-bit memory locations - logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; + logic [ADDRESS_WIDTH-1:0] addr; + assign addr = A[ADDRESS_WIDTH-1:0]; // use lower ADDRESS_WIDTH bits of address - case(funct3) - 3'b000: begin // LB - assign dout = {{24{ram_array[wr_addr][7]}}, ram_array[wr_addr][7:0]}; - end - 3'b001: begin // LH - assign dout = {{16{ram_array[wr_addr][15]}}, ram_array[wr_addr][15:0]}; - end - 3'b010: begin // LW - assign dout = ram_array[wr_addr]; - end - 3'b100: begin // LBU - assign dout = {24'b0, ram_array[wr_addr][7:0]}; - end - 3'b101: begin // LHU - assign dout = {16'b0, ram_array[wr_addr][15:0]}; - end - default: begin - assign dout = ram_array[wr_addr]; // read data from memory assynchronously - - end - endcase - always_ff @(posedge clk) begin - if (en == 1'b1) begin - case(funct3) - 3'b000: begin // SB - ram_array[wr_addr][7:0] <= din[7:0]; - end - 3'b001: begin // SH - ram_array[wr_addr][15:0] <= din[15:0]; - end - 3'b010: begin // SW - ram_array[wr_addr] <= din; + if (WE) begin + case (AddressingControl) + 3'b000: ram_array[addr] <= WD[7:0]; // SB + 3'b001: begin // SH + ram_array[addr] <= WD[7:0]; + ram_array[addr+1] <= WD[15:8]; end - default: begin - ram_array[wr_addr] <= din; // write data to memory synchronously + 3'b010: begin // SW + ram_array[addr] <= WD[7:0]; + ram_array[addr+1] <= WD[15:8]; + ram_array[addr+2] <= WD[23:16]; + ram_array[addr+3] <= WD[31:24]; end + default: ; // ignore other funct3 endcase end end + always_comb begin + case (AddressingControl) + 3'b000: RD = {{24{ram_array[addr][7]}}, ram_array[addr]}; // LB (signed) + 3'b001: RD = {{16{ram_array[addr+1][7]}}, ram_array[addr+1], ram_array[addr]}; // LH (signed) + 3'b010: RD = {ram_array[addr+3], ram_array[addr+2], ram_array[addr+1], ram_array[addr]}; // LW + 3'b100: RD = {24'b0, ram_array[addr]}; // LBU + 3'b101: RD = {16'b0, ram_array[addr+1], ram_array[addr]}; // LHU + default: RD = 32'b0; + endcase + end + + endmodule \ No newline at end of file diff --git a/repo/rtl/data_path.sv b/repo/rtl/data_path.sv new file mode 100644 index 0000000..4ac4f5e --- /dev/null +++ b/repo/rtl/data_path.sv @@ -0,0 +1,84 @@ +module data_path ( + input logic clk, + input logic rst, + + input logic [1:0] PCSrc, + input logic RegWrite, + input logic [3:0] ALUControl, + input logic ALUSrcA, + input logic ALUSrcB, + input logic MemWrite, + input logic [1:0] ResultSrc, + input logic [2:0] ImmSrc, + input logic [2:0] AddressingControl, + + output logic [31:0] Instr, + output logic Zero +); + + logic [31:0] PC, PCPlus4, ImmExt, MemData, ALUResult, SrcA, SrcB, ReadData1, ReadData2, ResultData; + + assign SrcA = ALUSrcA ? PC : ReadData1; + assign SrcB = ALUSrcB ? ImmExt : ReadData2; + + + pc pc_inst( + .clk(clk), + .rst(rst), + .PCSrc(PCSrc), + .ImmExt(ImmExt), + .ALUResult(ALUResult), + .PCPlus4(PCPlus4), + .PC(PC) + ); + + alu alu_inst( + .SrcA(SrcA), + .SrcB(SrcB), + .ALUControl(ALUControl), + .ALUResult(ALUResult), + .Zero(Zero) + ); + + instr_mem instr_mem_inst( + .A(PC), + .RD(Instr) + ); + + data_mem data_mem_inst( + .clk(clk), + .WE(MemWrite), + .A(ALUResult), + .WD(ReadData2), + .AddressingControl(AddressingControl), + .RD(MemData) + ); + + reg_file reg_file_inst( + .clk(clk), + .AD1(Instr[19:15]), + .AD2(Instr[24:20]), + .AD3(Instr[11:7]), + .WD3(ResultData), + .WE3(RegWrite), + .RD1(ReadData1), + .RD2(ReadData2) + ); + + signext signext_inst( + .Imm(Instr[31:7]), + .ImmSrc(ImmSrc), + .ImmExt(ImmExt) + ); + + always_comb begin + case (ResultSrc) + 2'b00: ResultData = ALUResult; + 2'b01: ResultData = MemData; + 2'b10: ResultData = PCPlus4; + default: ResultData = 32'b0; + endcase + end + + +endmodule \ No newline at end of file diff --git a/repo/rtl/data_unit.sv b/repo/rtl/data_unit.sv deleted file mode 100644 index 4bdbfef..0000000 --- a/repo/rtl/data_unit.sv +++ /dev/null @@ -1,78 +0,0 @@ -module data_unit #( - parameter DATA_WIDTH = 32, - ADDRESS_WIDTH = 5 -) ( - input logic clk, - input logic [ADDRESS_WIDTH-1:0] AD1, // rs1 address - input logic [ADDRESS_WIDTH-1:0] AD2, // rs2 address - input logic [ADDRESS_WIDTH-1:0] AD3, // rd address - input logic [DATA_WIDTH-1:0] ImmOp, // immediate value - input logic RegWrite, // write enable to register file - input logic MemWrite, // write enable to memory - input logic ALUctrl, // ALU control - input logic ALUsrc, // select imm or reg - input logic [1:0] ResultSrc, // select ALU or mem data - input logic [2:0] funct3, // for memory access size - input logic [DATA_WIDTH-1:0] PCtarget, // branch target address - input logic [DATA_WIDTH-1:0] PC, - input loguc [6:0] opcode, - output logic [2:0] EQ, // ALU equality flag - output logic [DATA_WIDTH-1:0] a0 // x10 output - output loguc [DATA_WIDTH-1:0] ALUout // ALU result -); - -logic [DATA_WIDTH-1:0] ALUop1; // ALU operand 1 -logic [DATA_WIDTH-1:0] ALUop2; // ALU operand 2 -logic [DATA_WIDTH-1:0] WriteData; // register file output 2 -logic [DATA_WIDTH-1:0] ReadData; // data memory output -logic [DATA_WIDTH-1:0] result; // data to write back to register file - -// register file: read rs1/rs2, write rd -reg_file reg_file ( - .clk(clk), - .read_addr1(AD1), - .read_addr2(AD2), - .write_addr(AD3), - .wd3(ALUout), - .we3(RegWrite), - .dout1(ALUop1), - .dout2(WriteData), - .a0(a0) -); - -// select ALU operand 2: register or immediate -mux mux1 ( - .in0(WriteData), - .in1(ImmOp), - .sel(ALUsrc), - .out(ALUop2) -); - -// ALU executes operation and sets EQ -alu alu ( - .alu_op1(ALUop1), - .alu_op2(ALUop2), - .alu_ctrl(ALUctrl), - .alu_out(ALUout), - .eq(EQ), - .PC(PC) -); - -// memory -data_mem data_mem ( - .clk(clk), - .en(MemWrite), - .wr_addr(ALUout), - .din(WriteData), - .dout(ReadData), - .funct3(funct3) -); - -case (ResultSrc) - 2'b00: assign ALUout = ALUout; // ALU result - 2'b01: assign ALUout = ReadData; // Memory data - 2'b10: assign ALUout = PCtarget; // PC + 4 for JAL/JALR - default: assign ALUout = ALUout; // Default to ALU result -endcase - -endmodule diff --git a/repo/rtl/imem.sv b/repo/rtl/instr_mem.sv similarity index 53% rename from repo/rtl/imem.sv rename to repo/rtl/instr_mem.sv index 20d0a3f..7967c15 100644 --- a/repo/rtl/imem.sv +++ b/repo/rtl/instr_mem.sv @@ -1,18 +1,18 @@ -module imem ( +module instr_mem #( /* verilator lint_off UNUSED */ - input logic [31:0] addr, // byte address from the program counter (PC) - output logic [31:0] instr // 32-bit instruction read from memory + input logic [31:0] A, + output logic [31:0] RD /* verilator lint_on UNUSED */ ); // instruction memory array: 256 instructions, each 32 bits wide - logic [31:0] mem [0:255]; + logic [31:0] rom_array [0:255]; // preload instructions from an external hex file at simulation start initial begin - $readmemh("../rtl/program.hex", mem); + $readmemh("../rtl/program.hex", rom_array); end // output the instruction corresponding to the PC address - assign instr = mem[addr[9:2]]; + assign RD = rom_array[A[9:2]]; endmodule diff --git a/repo/rtl/main_decoder.sv b/repo/rtl/main_decoder.sv deleted file mode 100644 index 7a768f9..0000000 --- a/repo/rtl/main_decoder.sv +++ /dev/null @@ -1,121 +0,0 @@ -module main_decoder ( - input logic [6:0] opcode, // 7-bit opcode field from the instruction - input logic [2:0] funct3, // 3-bit funct3 field from the instruction - - output logic RegWrite, // enable writing to register file - output logic ALUSrc, // selects ALU second operand (0 = register, 1 = immediate) - output logic MemWrite, // enable writing to data memory - output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4, 11 = imm) - output logic Branch, // indicates branch instruction - output logic Jump, // indicates jump instruction - output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) - output logic [1:0] ALUOp // encodes ALU operation type (00 = ADD category(load/store/addi/auipc/jalr), 01 = SUB category(branch), 10 = R-type/I-type) - -); - -// combinational logic to decode opcode and generate control signals -always_comb begin - // default values (safe defaults) - RegWrite = 1'b0; - ALUSrc = 1'b0; - MemWrite = 1'b0; - ResultSrc = 2'b00; - Branch = 1'b0; - Jump = 1'b0; - ImmSrc = 3'b000; - ALUOp = 2'b00; - - case(opcode) - - // load instructions: LB, LH, LW, LBU, LHU - // opcode = 0000011 - 7'b0000011: begin - RegWrite = 1'b1; - ALUSrc = 1'b1; - ResultSrc = 2'b01; // load data from memory - ImmSrc = 3'b000; // I-type immediate - ALUOp = 2'b00; // ALU does ADD for address - end - - // store instructions: SB, SH, SW S-type - // opcode = 0100011 - 7'b0100011: begin - MemWrite = 1'b1; - ALUSrc = 1'b1; - ImmSrc = 3'b001; // S-type immediate - end - - // R-type instructions: ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND - // opcode = 0110011 - 7'b0110011: begin - RegWrite = 1'b1; - ALUSrc = 1'b0; - ALUOp = 2'b10; - end - - // B-type instructions: BEQ, BNE, BLT, BGE, BLTU, BGEU - // opcode = 1100011 - 7'b1100011: begin - Branch = 1'b1; - ImmSrc = 3'b010; // B-type immediate - ALUOp = 2'b01; // ALU does SUB for BEQ/BNE (other comparisons handled in ALU decoder) - end - - // I-type arithmetic: ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI - // opcode = 0010011 - 7'b0010011: begin - RegWrite = 1'b1; - ALUSrc = 1'b1; - ImmSrc = 3'b000; // I-type immediate - - case (funct3) - 3'b000: ALUOp = 2'b00; - - default: ALUOp = 2'b10; - - endcase - end - - // AUIPC (U-type) - // opcode = 0010111 - 7'b0010111: begin - RegWrite = 1'b1; - ImmSrc = 3'b100; // U-type immediate - ALUSrc = 1'b1; - ALUOp = 2'b00; - ResultSrc = 2'b00; - end - - // LUI (U-type) - // opcode = 0110111 - 7'b0110111: begin - RegWrite = 1'b1; - ImmSrc = 3'b100; // U-type immediate - ResultSrc = 2'b00; - ALUSrc = 1'b1; - ALUOp = 2'b00; //ALU does ADD with 0 + imm - end - - // JAL (J-type) - // opcode = 1101111 - 7'b1101111: begin - RegWrite = 1'b1; - Jump = 1'b1; - ResultSrc = 2'b10; // return address is PC+4 written to rd - ImmSrc = 3'b011; // J-type immediate - end - - // JALR (I-type) - // opcode = 1100111 - 7'b1100111: begin - RegWrite = 1'b1; - Jump = 1'b1; - ResultSrc = 2'b10; // return address is PC+4 written to rd - ImmSrc = 3'b000; // I-type immediate - ALUSrc = 1'b1; - ALUOp = 2'b00; // ALU does ADD for address calculation - end - endcase -end - -endmodule \ No newline at end of file diff --git a/repo/rtl/mux.sv b/repo/rtl/mux.sv deleted file mode 100644 index 648a387..0000000 --- a/repo/rtl/mux.sv +++ /dev/null @@ -1,14 +0,0 @@ -module mux #( - parameter DATA_WIDTH = 32 -) ( - input logic [DATA_WIDTH-1:0] in0, // first input (selected when sel = 0) - input logic [DATA_WIDTH-1:0] in1, // second input (selected when sel = 1) - input logic sel, // control signal to choose input - output logic [DATA_WIDTH-1:0] out // output of the multiplexer -); - - // combinational assignment: - // if sel == 1, output in1; otherwise, output in0 - assign out = sel ? in1 : in0; - -endmodule \ No newline at end of file diff --git a/repo/rtl/pc.sv b/repo/rtl/pc.sv new file mode 100644 index 0000000..6405913 --- /dev/null +++ b/repo/rtl/pc.sv @@ -0,0 +1,38 @@ +module pc #( + parameter WIDTH = 32 +)( + input logic clk, // system clock + input logic rst, // asynchronous reset + input logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + input logic [WIDTH-1:0] ImmExt, // immediate offset for branch target + input logic [WIDTH-1:0] ALUResult, + output logic [WIDTH-1:0] PCPlus4, // PC + 4 + output logic [WIDTH-1:0] PC // current program counter +); + +// next PC after the mux +logic [WIDTH-1:0] PCNext; + +logic [WIDTH-1:0] PCTarget; + +always_comb begin + PCPlus4 = PC + 4; + PCTarget = PC + ImmExt; + + case(PCSrc) + 2'b00: PCNext = PCPlus4; + 2'b01: PCNext = PCTarget; + 2'b10: PCNext = {ALUResult[31:2], 2'b00}; // word addressed << 2 + endcase + +end + +// program counter register with asynchronous reset +always_ff @(posedge clk or posedge rst) begin + if (rst) + PC <= {WIDTH{1'b0}}; // Reset PC to 0 + else + PC <= PCNext; // Update PC normally +end + +endmodule diff --git a/repo/rtl/pcsrc_unit.sv b/repo/rtl/pcsrc_unit.sv new file mode 100644 index 0000000..78cc1f3 --- /dev/null +++ b/repo/rtl/pcsrc_unit.sv @@ -0,0 +1,34 @@ +module pcsrc_unit ( + input logic [1:0] Jump, + input logic Branch, + input logic Zero, + input logic [2:0] BranchType, + output logic [1:0] PCSrc // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) +); + + always_comb begin + // default + PCSrc = 2'b00; + + // handle jumps first + case (Jump) + 2'b01: PCSrc = 2'b01; // JAL + 2'b10: PCSrc = 2'b10; // JALR + 2'b00: begin + // if jump==00 then check branches + if (Branch) begin + case (BranchType) + 3'b000: PCSrc = Zero ? 2'b01 : 2'b00; // BEQ + 3'b001: PCSrc = ~Zero ? 2'b01 : 2'b00; // BNE + 3'b100: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLT + 3'b101: PCSrc = Zero ? 2'b01 : 2'b00; // BGE + 3'b110: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLTU + 3'b111: PCSrc = Zero ? 2'b01 : 2'b00; // BGEU + default: PCSrc = 2'b00; + endcase + end + end + endcase + end + +endmodule diff --git a/repo/rtl/reg_file.sv b/repo/rtl/reg_file.sv index 324eb4e..6ff2149 100644 --- a/repo/rtl/reg_file.sv +++ b/repo/rtl/reg_file.sv @@ -3,30 +3,26 @@ module reg_file #( DATA_WIDTH = 32 // 32-bits )( input logic clk, // clock - input logic [ADDRESS_WIDTH-1:0] write_addr, // destination register - input logic [ADDRESS_WIDTH-1:0] read_addr1, // source register 1 address (rs1) - input logic [ADDRESS_WIDTH-1:0] read_addr2, // source register 2 address (rs2) - input logic [DATA_WIDTH-1:0] wd3, // write data - input logic we3, // write enable - output logic [DATA_WIDTH-1:0] dout1, // register file output for rs1 - output logic [DATA_WIDTH-1:0] dout2, // register file output for rs2 - output logic [DATA_WIDTH-1:0] a0 // special output for register x10 (a0) + input logic [ADDRESS_WIDTH-1:0] AD3, // destination register + input logic [ADDRESS_WIDTH-1:0] AD1, // source register 1 address (rs1) + input logic [ADDRESS_WIDTH-1:0] AD2, // source register 2 address (rs2) + input logic [DATA_WIDTH-1:0] WD3, // write data + input logic WE3, // write enable + output logic [DATA_WIDTH-1:0] RD1, // register file output for rs1 + output logic [DATA_WIDTH-1:0] RD2, // register file output for rs2 ); -// 32 32-bit registers -logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; + // 32 32-bit registers + logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; -// write operation (synchronous) -> writes occur only if we3 is asserted -always_ff @(posedge clk) begin - if (we3 == 1'b1 && write_addr != 0) - ram_array[write_addr] <= wd3; -end + // write operation (synchronous) -> writes occur only if WE3 is asserted + always_ff @(posedge clk) begin + if (WE3 == 1'b1 && AD3 != 0) + ram_array[AD3] <= WD3; + end -// read operations (combinational) -> outputs change immediately when read_addr changes -assign dout1 = ram_array[read_addr1]; -assign dout2 = ram_array[read_addr2]; - -// special readout of x10 (a0) -assign a0 = ram_array[10]; + // read operations (combinational) -> outputs change immediately when read_addr changes + assign RD1 = ram_array[AD1]; + assign RD2 = ram_array[AD2]; endmodule diff --git a/repo/rtl/register.sv b/repo/rtl/register.sv deleted file mode 100644 index 386bf62..0000000 --- a/repo/rtl/register.sv +++ /dev/null @@ -1,12 +0,0 @@ -module register( - - input logic clk, // clock signal - input logic [31:0] d, // input data - output logic [31:0] q // stored output data -); - - // simple D-flip-flop register -> on every rising edge of clk, q updates to the value of d - always_ff @(posedge clk) - q <= d; - -endmodule diff --git a/repo/rtl/signext.sv b/repo/rtl/signext.sv index e968c5c..9aaa8b9 100644 --- a/repo/rtl/signext.sv +++ b/repo/rtl/signext.sv @@ -1,47 +1,17 @@ -module signext ( - input logic [31:0] instr, - input logic [2:0] ImmSrc, - output logic [31:0] ImmOp +module signext #( + input logic [31:7] Imm, + input logic [2:0] ImmSrc, + output logic [31:0] ImmExt ); - logic [31:0] immI, immS, immB, immU, immJ; - - // I-type - assign immI = {{20{instr[31]}}, instr[31:20]}; - - // S-type - assign immS = {{20{instr[31]}}, - instr[31:25], - instr[11:7]}; - - // B-type - assign immB = {{19{instr[31]}}, - instr[31], // imm[12] - instr[7], // imm[11] - instr[30:25], // imm[10:5] - instr[11:8], // imm[4:1] - 1'b0}; // imm[0] = 0 - - // U-type (LUI, AUIPC) - assign immU = {instr[31:12], 12'b0}; - - // J-type (JAL) - assign immJ = {{11{instr[31]}}, - instr[31], // imm[20] - instr[19:12], // imm[19:12] - instr[20], // imm[11] - instr[30:21], // imm[10:1] - 1'b0}; // imm[0] = 0 - - // MUX between immediate types always_comb begin - unique case (ImmSrc) - 3'b000: ImmOp = immI; // I-type - 3'b001: ImmOp = immS; // S-type - 3'b010: ImmOp = immB; // B-type - 3'b011: ImmOp = immU; // U-type - 3'b100: ImmOp = immJ; // J-type - default: ImmOp = 32'b0; + case (ImmSrc) + 3'b000: ImmExt = {{20{Imm[31]}}, Imm[31:20]}; // I-type + 3'b001: ImmExt = {{20{Imm[31]}}, Imm[31:25], Imm[11:7]}; // S-type + 3'b010: ImmExt = {{20{Imm[31]}}, Imm[7], Imm[30:25], Imm[11:8], 1'b0}; // B-type + 3'b011: ImmExt = {{12{Imm[31]}}, Imm[19:12], Imm[20], Imm[30:21], 1'b0}; // J-type + 3'b100: ImmExt = {Imm[31:12], 12'b0}; // U-type + default: ImmExt = 32'b0; endcase end endmodule \ No newline at end of file diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index 43d6e06..fd2a132 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -1,99 +1,56 @@ -module top #( - parameter DATA_WIDTH = 32, - parameter ADDRESS_WIDTH = 5 -) ( - input logic clk, - input logic rst, - output logic [DATA_WIDTH-1:0] a0 // x10 output +module top ( + input logic clk, + input logic rst ); -// control signals -logic RegWrite; -logic ALUSrc; -logic [2:0] ALUctrl; // 3-bit ALU control -logic [2:0] ImmSrc; // 2-bit immediate -logic [1:0] ResultSrc; -logic [1:0] PCsrc; -logic MemWrite; -logic [2:0] EQ; -logic [2:0] funct3; - -// data wires -logic [DATA_WIDTH-1:0] pc; -logic [DATA_WIDTH-1:0] instr; -logic [DATA_WIDTH-1:0] ImmOp; -logic [DATA_WIDTH-1:0] PCtarget; -logic [DATA_WIDTH-1:0] ALUout; - -logic [6:0] opcode = instr[6:0]; -// register file address fields -logic [ADDRESS_WIDTH-1:0] rs1; -logic [ADDRESS_WIDTH-1:0] rs2; -logic [ADDRESS_WIDTH-1:0] rd; - -assign pc_next = pc + ImmOp; // PC + immediate for branch target -// decode instruction fields -assign rs1 = instr[19:15]; // source register 1 -assign rs2 = instr[24:20]; // source register 2 -assign rd = instr[11:7]; // destination register - -// program Counter: holds current instruction address -PC pc_module ( - .clk(clk), - .rst(rst), - .PCsrc(PCsrc), - .ImmOp(PCtarget), - .pc(pc), - .JALRjump(ALUout) -); - -// instruction memory: fetch instruction at PC -imem imem ( - .addr(pc), - .instr(instr) -); - -// control unit: generate control signals based on opcode -control control ( - .instr(instr), - .EQ(EQ), - .RegWrite(RegWrite), - .ALUSrc(ALUSrc), - .ALUctrl(ALUctrl), - .ImmSrc(ImmSrc), - .ResultSrc(ResultSrc), - .MemWrite(MemWrite), - .PCsrc(PCsrc), - .funct3(funct3) -); - -// sign-extension unit: generate immediate values -signext signext ( - .instr(instr), - .ImmSrc(ImmSrc), - .ImmOp(ImmOp) -); - -// datapath unit: ALU + register file + muxes -data_unit data_unit ( - .clk(clk), - .AD1(rs1), - .AD2(rs2), - .AD3(rd), - .RegWrite(RegWrite), - .ImmOp(ImmOp), - .ALUSrc(ALUSrc), - .ALUctrl(ALUctrl), - .ResultSrc(ResultSrc), - .MemWrite(MemWrite), - .EQ(EQ), - .a0(a0), - .funct3(funct3), - .PCtarget(PCtarget), - .ALUout(ALUout), - .PC(pc), - .opcode(opcode) - -); + // Control signals + logic [1:0] PCSrc; + logic RegWrite; + logic [3:0] ALUControl; + logic ALUSrcA; + logic ALUSrcB; + logic MemWrite; + logic [1:0] ResultSrc; + logic [2:0] ImmSrc; + logic [2:0] AddressingControl; + + // Datapath outputs + logic [31:0] Instr; + logic Zero; + + // Datapath + data_path dp_inst ( + .clk(clk), + .rst(rst), + + .PCSrc(PCSrc), + .RegWrite(RegWrite), + .ALUControl(ALUControl), + .ALUSrcA(ALUSrcA), + .ALUSrcB(ALUSrcB), + .MemWrite(MemWrite), + .ResultSrc(ResultSrc), + .ImmSrc(ImmSrc), + .AddressingControl(AddressingControl), + + .Instr(Instr), + .Zero(Zero) + ); + + // Control path + control_path ctrl_inst ( + .Instr(Instr), + .Zero(Zero), + + .PCSrc(PCSrc), + .RegWrite(RegWrite), + .ALUControl(ALUControl), + .ALUSrcA(ALUSrcA), + .ALUSrcB(ALUSrcB), + .MemWrite(MemWrite), + .ResultSrc(ResultSrc), + .ImmSrc(ImmSrc), + .AddressingControl(AddressingControl) + ); endmodule From 4dcc04cce9dec1d46eccb23bbcdf3f179aa4e129 Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Thu, 27 Nov 2025 22:50:07 +0000 Subject: [PATCH 41/65] errors fixed --- repo/rtl/alu.sv | 2 +- repo/rtl/control.sv | 6 +-- repo/rtl/control_path.sv | 54 ++++++++++++++++++++++++++ repo/rtl/data_mem.sv | 2 +- repo/rtl/data_path.sv | 2 +- repo/rtl/data_unit.sv | 82 ++++++++++++++++++++++++++++++++++++++++ repo/rtl/instr_mem.sv | 2 +- repo/rtl/signext.sv | 4 +- 8 files changed, 145 insertions(+), 9 deletions(-) create mode 100644 repo/rtl/control_path.sv create mode 100644 repo/rtl/data_unit.sv diff --git a/repo/rtl/alu.sv b/repo/rtl/alu.sv index 5a0f2e4..188c20e 100644 --- a/repo/rtl/alu.sv +++ b/repo/rtl/alu.sv @@ -38,4 +38,4 @@ module alu ( Zero = (ALUResult == 32'd0); end -endmodule \ No newline at end of file +endmodule diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index 01b35ef..4fc7269 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -1,4 +1,4 @@ -module control #( +module control( input logic [6:0] opcode, input logic [2:0] funct3, input logic [6:0] funct7, @@ -45,7 +45,7 @@ module control #( // R-type instructions 7'b0110011: begin RegWrite = 1'b1; - ALUSrc = 1'b0; + ALUSrcB = 1'b0; case(funct3) 3'b000: begin @@ -182,4 +182,4 @@ module control #( end endcase end -endmodule \ No newline at end of file +endmodule diff --git a/repo/rtl/control_path.sv b/repo/rtl/control_path.sv new file mode 100644 index 0000000..1ec9609 --- /dev/null +++ b/repo/rtl/control_path.sv @@ -0,0 +1,54 @@ +module control_path( + input logic [31:0] Instr, + input logic Zero, + + output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + output logic RegWrite, // enable write to register + output logic [3:0] ALUControl, // control operation in ALU + output logic ALUSrcA, // choose PC (1) or register (0) for ALU operand A + output logic ALUSrcB, // choose immediate (1) or register (0) operand + output logic MemWrite, // enable write into the data memory + // output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4) + output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) + output logic [2:0] AddressingControl // choose which type of load/store instruction to perform +); + + logic Branch; + logic [2:0] BranchType; + logic [1:0] Jump; + + logic [6:0] opcode; + logic [2:0] funct3; + logic [6:0] funct7; + + assign opcode = Instr[6:0]; + assign funct3 = Instr[14:12]; + assign funct7 = Instr[31:25]; + + control control_unit ( + .opcode(opcode), + .funct3(funct3), + .funct7(funct7), + .RegWrite(RegWrite), + .ALUControl(ALUControl), + .ALUSrcA(ALUSrcA), + .ALUSrcB(ALUSrcB), + .MemWrite(MemWrite), + .ResultSrc(ResultSrc), + .Branch(Branch), + .BranchType(BranchType), + .Jump(Jump), + .ImmSrc(ImmSrc), + .AddressingControl(AddressingControl) + ); + + pcsrc_unit pcsrc_unit_inst ( + .Jump(Jump), + .Branch(Branch), + .Zero(Zero), + .BranchType(BranchType), + .PCSrc(PCSrc) + ); + +endmodule diff --git a/repo/rtl/data_mem.sv b/repo/rtl/data_mem.sv index 25ced8f..fe1b5c0 100644 --- a/repo/rtl/data_mem.sv +++ b/repo/rtl/data_mem.sv @@ -46,4 +46,4 @@ module data_mem #( end -endmodule \ No newline at end of file +endmodule diff --git a/repo/rtl/data_path.sv b/repo/rtl/data_path.sv index 4ac4f5e..e621c2a 100644 --- a/repo/rtl/data_path.sv +++ b/repo/rtl/data_path.sv @@ -81,4 +81,4 @@ module data_path ( end -endmodule \ No newline at end of file +endmodule diff --git a/repo/rtl/data_unit.sv b/repo/rtl/data_unit.sv new file mode 100644 index 0000000..bfdc3dc --- /dev/null +++ b/repo/rtl/data_unit.sv @@ -0,0 +1,82 @@ +module data_unit #( + parameter DATA_WIDTH = 32, + ADDRESS_WIDTH = 5 +) ( + input logic clk, + input logic [ADDRESS_WIDTH-1:0] AD1, // rs1 address + input logic [ADDRESS_WIDTH-1:0] AD2, // rs2 address + input logic [ADDRESS_WIDTH-1:0] AD3, // rd address + input logic [DATA_WIDTH-1:0] ImmOp, // immediate value + input logic RegWrite, // write enable to register file + input logic MemWrite, // write enable to memory + input logic ALUctrl, // ALU control + input logic ALUsrc, // select imm or reg + input logic [1:0] ResultSrc, // select ALU or mem data + input logic [2:0] funct3, // for memory access size + input logic [DATA_WIDTH-1:0] PCtarget, // branch target address + input logic [DATA_WIDTH-1:0] PC, + input logic [6:0] opcode, + output logic [2:0] EQ, // ALU equality flag + output logic [DATA_WIDTH-1:0] a0, // x10 output + output logic [DATA_WIDTH-1:0] ALUout // ALU result +); + +logic [DATA_WIDTH-1:0] ALUop1; // ALU operand 1 +logic [DATA_WIDTH-1:0] ALUop2; // ALU operand 2 +logic [DATA_WIDTH-1:0] WriteData; // register file output 2 +logic [DATA_WIDTH-1:0] ReadData; // data memory output +logic [DATA_WIDTH-1:0] result; // data to write back to register file + +// register file: read rs1/rs2, write rd +reg_file reg_file ( + .clk(clk), + .read_addr1(AD1), + .read_addr2(AD2), + .write_addr(AD3), + .wd3(ALUout), + .we3(RegWrite), + .dout1(ALUop1), + .dout2(WriteData), + .a0(a0) +); + +// select ALU operand 2: register or immediate +mux mux1 ( + .in0(WriteData), + .in1(ImmOp), + .sel(ALUsrc), + .out(ALUop2) +); + +// ALU executes operation and sets EQ +alu alu ( + .alu_op1(ALUop1), + .alu_op2(ALUop2), + .alu_ctrl(ALUctrl), + .alu_out(ALUout), + .eq(EQ), + .PC(PC) +); + +// memory +data_mem data_mem ( + .clk(clk), + .en(MemWrite), + .wr_addr(ALUout), + .din(WriteData), + .dout(ReadData), + .funct3(funct3) +); + +always_comb begin + + case (ResultSrc) + 2'b00: assign ALUout = ALUout; // ALU result + 2'b01: assign ALUout = ReadData; // Memory data + 2'b10: assign ALUout = PCtarget; // PC + 4 for JAL/JALR + default: assign ALUout = ALUout; // Default to ALU result + endcase + +end + +endmodule diff --git a/repo/rtl/instr_mem.sv b/repo/rtl/instr_mem.sv index 7967c15..54dbf7a 100644 --- a/repo/rtl/instr_mem.sv +++ b/repo/rtl/instr_mem.sv @@ -1,4 +1,4 @@ -module instr_mem #( +module instr_mem ( /* verilator lint_off UNUSED */ input logic [31:0] A, output logic [31:0] RD diff --git a/repo/rtl/signext.sv b/repo/rtl/signext.sv index 9aaa8b9..d2c6ae2 100644 --- a/repo/rtl/signext.sv +++ b/repo/rtl/signext.sv @@ -1,4 +1,4 @@ -module signext #( +module signext ( input logic [31:7] Imm, input logic [2:0] ImmSrc, output logic [31:0] ImmExt @@ -14,4 +14,4 @@ module signext #( default: ImmExt = 32'b0; endcase end -endmodule \ No newline at end of file +endmodule From 9eb89d0673795e47e07e3c9f55c0654660f72878 Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Thu, 27 Nov 2025 22:51:25 +0000 Subject: [PATCH 42/65] contol_path.sv deleted --- repo/rtl/contol_path.sv | 54 ----------------------------------------- 1 file changed, 54 deletions(-) delete mode 100644 repo/rtl/contol_path.sv diff --git a/repo/rtl/contol_path.sv b/repo/rtl/contol_path.sv deleted file mode 100644 index 181eb21..0000000 --- a/repo/rtl/contol_path.sv +++ /dev/null @@ -1,54 +0,0 @@ -module control_path #( - input logic [31:0] Instr, - input logic Zero, - - output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) - output logic RegWrite, // enable write to register - output logic [3:0] ALUControl, // control operation in ALU - output logic ALUSrcA, // choose PC (1) or register (0) for ALU operand A - output logic ALUSrcB, // choose immediate (1) or register (0) operand - output logic MemWrite, // enable write into the data memory - // output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) - output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4) - output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) - output logic [2:0] AddressingControl // choose which type of load/store instruction to perform -); - - logic Branch; - logic [2:0] BranchType; - logic [1:0] Jump; - - logic [6:0] opcode; - logic [2:0] funct3; - logic [6:0] funct7; - - assign opcode = Instr[6:0]; - assign funct3 = Instr[14:12]; - assign funct7 = Instr[31:25]; - - control control_unit ( - .opcode(opcode), - .funct3(funct3), - .funct7(funct7), - .RegWrite(RegWrite), - .ALUControl(ALUControl), - .ALUSrcA(ALUSrcA), - .ALUSrcB(ALUSrcB), - .MemWrite(MemWrite), - .ResultSrc(ResultSrc), - .Branch(Branch), - .BranchType(BranchType), - .Jump(Jump), - .ImmSrc(ImmSrc), - .AddressingControl(AddressingControl) - ); - - pcsrc_unit pcsrc_unit_inst ( - .Jump(Jump), - .Branch(Branch), - .Zero(Zero), - .BranchType(BranchType), - .PCSrc(PCSrc) - ); - -endmodule \ No newline at end of file From 8c91968ff0ea42e2fd6bcc1ff9f3208a992dfc14 Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Fri, 28 Nov 2025 02:48:06 +0000 Subject: [PATCH 43/65] testbench nearly done --- repo/rtl/alu.sv | 4 ++-- repo/rtl/control.sv | 2 +- repo/rtl/control_path.sv | 4 ++-- repo/rtl/data_path.sv | 7 ++++--- repo/rtl/reg_file.sv | 3 ++- repo/rtl/top.sv | 11 +++++++---- repo/tb/doit.sh | 3 ++- repo/tb/tests/cpu_testbench.h | 14 ++++++++------ 8 files changed, 28 insertions(+), 20 deletions(-) mode change 100644 => 100755 repo/tb/doit.sh diff --git a/repo/rtl/alu.sv b/repo/rtl/alu.sv index 188c20e..9bdc83c 100644 --- a/repo/rtl/alu.sv +++ b/repo/rtl/alu.sv @@ -15,7 +15,7 @@ module alu ( input logic [31:0] SrcB, input logic [3:0] ALUControl, output logic [31:0] ALUResult, - output logic Zero + output logic [31:0] Zero ); always_comb begin @@ -36,6 +36,6 @@ module alu ( default: ALUResult = 32'b0; endcase - Zero = (ALUResult == 32'd0); + Zero = 32'b0; end endmodule diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index 4fc7269..4b220c1 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -24,7 +24,7 @@ module control( // assign opcode = Instr[6:0]; // assign funct3 = Instr[14:12]; // assign funct7 = Instr[31:25]; - assign AddressingControl = funct3; // store width + // assign AddressingControl = funct3; // store width always_comb begin // Default values to prevent latches diff --git a/repo/rtl/control_path.sv b/repo/rtl/control_path.sv index 1ec9609..bd768ed 100644 --- a/repo/rtl/control_path.sv +++ b/repo/rtl/control_path.sv @@ -1,6 +1,6 @@ module control_path( - input logic [31:0] Instr, - input logic Zero, + output logic [31:0] Instr, + input logic [31:0] Zero, output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) output logic RegWrite, // enable write to register diff --git a/repo/rtl/data_path.sv b/repo/rtl/data_path.sv index e621c2a..04b9ffb 100644 --- a/repo/rtl/data_path.sv +++ b/repo/rtl/data_path.sv @@ -11,16 +11,17 @@ module data_path ( input logic [1:0] ResultSrc, input logic [2:0] ImmSrc, input logic [2:0] AddressingControl, - + output logic [31:0] Instr, - output logic Zero + output logic [31:0] Zero, + output logic [31:0] a0 ); logic [31:0] PC, PCPlus4, ImmExt, MemData, ALUResult, SrcA, SrcB, ReadData1, ReadData2, ResultData; assign SrcA = ALUSrcA ? PC : ReadData1; assign SrcB = ALUSrcB ? ImmExt : ReadData2; - + assign a0 = ALUResult; pc pc_inst( .clk(clk), diff --git a/repo/rtl/reg_file.sv b/repo/rtl/reg_file.sv index 6ff2149..c422341 100644 --- a/repo/rtl/reg_file.sv +++ b/repo/rtl/reg_file.sv @@ -9,7 +9,8 @@ module reg_file #( input logic [DATA_WIDTH-1:0] WD3, // write data input logic WE3, // write enable output logic [DATA_WIDTH-1:0] RD1, // register file output for rs1 - output logic [DATA_WIDTH-1:0] RD2, // register file output for rs2 + output logic [DATA_WIDTH-1:0] RD2 // register file output for rs2 + ); // 32 32-bit registers diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index fd2a132..38e69a2 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -1,6 +1,8 @@ module top ( input logic clk, - input logic rst + input logic rst, + input logic trigger, + output logic [31:0] a0 ); // Control signals @@ -15,8 +17,8 @@ module top ( logic [2:0] AddressingControl; // Datapath outputs - logic [31:0] Instr; - logic Zero; + logic [31:0] Zero; + logic [31:0] Instr1; // Datapath data_path dp_inst ( @@ -34,7 +36,8 @@ module top ( .AddressingControl(AddressingControl), .Instr(Instr), - .Zero(Zero) + .Zero(Zero), + .a0(a0) ); // Control path diff --git a/repo/tb/doit.sh b/repo/tb/doit.sh old mode 100644 new mode 100755 index 56c58a2..a8ff86a --- a/repo/tb/doit.sh +++ b/repo/tb/doit.sh @@ -45,7 +45,8 @@ for file in "${files[@]}"; do -y ${RTL_FOLDER} \ --prefix "Vdut" \ -o Vdut \ - -LDFLAGS "-lgtest -lgtest_main -lpthread" + -CFLAGS "-std=c++17 -isystem /opt/homebrew/Cellar/googletest/1.17.0/include"\ + -LDFLAGS "-L/opt/homebrew/Cellar/googletest/1.17.0/lib -lgtest -lgtest_main -lpthread" \ # Build C++ project with automatically generated Makefile make -j -C obj_dir/ -f Vdut.mk diff --git a/repo/tb/tests/cpu_testbench.h b/repo/tb/tests/cpu_testbench.h index b60333a..4873847 100644 --- a/repo/tb/tests/cpu_testbench.h +++ b/repo/tb/tests/cpu_testbench.h @@ -44,7 +44,7 @@ class CpuTestbench : public ::testing::Test top_->clk = 1; top_->rst = 1; top_->trigger = 0; - runSimulation(10); // Process reset + runSimulation(10); // Process reset top_->rst = 0; } @@ -75,8 +75,10 @@ class CpuTestbench : public ::testing::Test tfp_->close(); // Free memory - if (top_) delete top_; - if (tfp_) delete tfp_; + if (top_) + delete top_; + if (tfp_) + delete tfp_; delete context_; // Save data and program memory files to test_out directory @@ -91,9 +93,9 @@ class CpuTestbench : public ::testing::Test } protected: - VerilatedContext* context_; - Vdut* top_; - VerilatedVcdC* tfp_; + VerilatedContext *context_; + Vdut *top_; + VerilatedVcdC *tfp_; std::string name_; unsigned int ticks_; }; From 75c2262daa5d3fceb875b7c20e37d240d83c994c Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Fri, 28 Nov 2025 09:47:44 +0000 Subject: [PATCH 44/65] fixing pcsrc --- repo/rtl/pcsrc_unit.sv | 15 ++++++++------- repo/rtl/top.sv | 2 +- repo/tb/assemble.sh | 0 3 files changed, 9 insertions(+), 8 deletions(-) mode change 100644 => 100755 repo/tb/assemble.sh diff --git a/repo/rtl/pcsrc_unit.sv b/repo/rtl/pcsrc_unit.sv index 78cc1f3..f54b868 100644 --- a/repo/rtl/pcsrc_unit.sv +++ b/repo/rtl/pcsrc_unit.sv @@ -1,8 +1,9 @@ module pcsrc_unit ( input logic [1:0] Jump, input logic Branch, - input logic Zero, + input logic [31:0] Zero, input logic [2:0] BranchType, + input logic [31:0] ALUResult, output logic [1:0] PCSrc // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) ); @@ -18,12 +19,12 @@ module pcsrc_unit ( // if jump==00 then check branches if (Branch) begin case (BranchType) - 3'b000: PCSrc = Zero ? 2'b01 : 2'b00; // BEQ - 3'b001: PCSrc = ~Zero ? 2'b01 : 2'b00; // BNE - 3'b100: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLT - 3'b101: PCSrc = Zero ? 2'b01 : 2'b00; // BGE - 3'b110: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLTU - 3'b111: PCSrc = Zero ? 2'b01 : 2'b00; // BGEU + 3'b000: PCSrc = ALUResult[0] ? 2'b01 : 2'b00; // BEQ + 3'b001: PCSrc = ~ALUResult[0] ? 2'b01 : 2'b00; // BNE + 3'b100: PCSrc = ~ALUResult[0] ? 2'b01 : 2'b00; // BLT + 3'b101: PCSrc = ALUResult[0] ? 2'b01 : 2'b00; // BGE + 3'b110: PCSrc = ~ALUResult[0] ? 2'b01 : 2'b00; // BLTU + 3'b111: PCSrc = ALUResult[0] ? 2'b01 : 2'b00; // BGEU default: PCSrc = 2'b00; endcase end diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index 38e69a2..3a26197 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -18,7 +18,7 @@ module top ( // Datapath outputs logic [31:0] Zero; - logic [31:0] Instr1; + logic [31:0] Instr; // Datapath data_path dp_inst ( diff --git a/repo/tb/assemble.sh b/repo/tb/assemble.sh old mode 100644 new mode 100755 From 4e49e5007d4bf79f11f30e92ed07923dfc56b93b Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Fri, 28 Nov 2025 09:57:28 +0000 Subject: [PATCH 45/65] fixing branch --- repo/rtl/control_path.sv | 3 ++- repo/rtl/pcsrc_unit.sv | 21 ++++++++++++++------- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/repo/rtl/control_path.sv b/repo/rtl/control_path.sv index bd768ed..ec6f59c 100644 --- a/repo/rtl/control_path.sv +++ b/repo/rtl/control_path.sv @@ -48,7 +48,8 @@ module control_path( .Branch(Branch), .Zero(Zero), .BranchType(BranchType), - .PCSrc(PCSrc) + .PCSrc(PCSrc), + .ALUResult(ALUResult) ); endmodule diff --git a/repo/rtl/pcsrc_unit.sv b/repo/rtl/pcsrc_unit.sv index f54b868..1ae1d09 100644 --- a/repo/rtl/pcsrc_unit.sv +++ b/repo/rtl/pcsrc_unit.sv @@ -7,10 +7,12 @@ module pcsrc_unit ( output logic [1:0] PCSrc // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) ); + logic TakeBranch; + always_comb begin // default PCSrc = 2'b00; - + TakeBranch = 1'b0; // handle jumps first case (Jump) 2'b01: PCSrc = 2'b01; // JAL @@ -18,13 +20,18 @@ module pcsrc_unit ( 2'b00: begin // if jump==00 then check branches if (Branch) begin + + if(TakeBranch)begin + TakeBranch = 1'b1; + end + case (BranchType) - 3'b000: PCSrc = ALUResult[0] ? 2'b01 : 2'b00; // BEQ - 3'b001: PCSrc = ~ALUResult[0] ? 2'b01 : 2'b00; // BNE - 3'b100: PCSrc = ~ALUResult[0] ? 2'b01 : 2'b00; // BLT - 3'b101: PCSrc = ALUResult[0] ? 2'b01 : 2'b00; // BGE - 3'b110: PCSrc = ~ALUResult[0] ? 2'b01 : 2'b00; // BLTU - 3'b111: PCSrc = ALUResult[0] ? 2'b01 : 2'b00; // BGEU + 3'b000: PCSrc = TakeBranch ? 2'b01 : 2'b00; // BEQ + 3'b001: PCSrc = ~TakeBranch ? 2'b01 : 2'b00; // BNE + 3'b100: PCSrc = ~TakeBranch ? 2'b01 : 2'b00; // BLT + 3'b101: PCSrc = TakeBranch ? 2'b01 : 2'b00; // BGE + 3'b110: PCSrc = ~TakeBranch ? 2'b01 : 2'b00; // BLTU + 3'b111: PCSrc = TakeBranch ? 2'b01 : 2'b00; // BGEU default: PCSrc = 2'b00; endcase end From 595f224274a8f0003eeb6577ad5926a9b3663225 Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Fri, 28 Nov 2025 10:06:37 +0000 Subject: [PATCH 46/65] fixes --- repo/rtl/alu.sv | 4 ++-- repo/rtl/control_path.sv | 2 +- repo/rtl/data_path.sv | 2 +- repo/rtl/pcsrc_unit.sv | 24 ++++++++---------------- repo/rtl/top.sv | 2 +- 5 files changed, 13 insertions(+), 21 deletions(-) diff --git a/repo/rtl/alu.sv b/repo/rtl/alu.sv index 9bdc83c..d955b5e 100644 --- a/repo/rtl/alu.sv +++ b/repo/rtl/alu.sv @@ -15,7 +15,7 @@ module alu ( input logic [31:0] SrcB, input logic [3:0] ALUControl, output logic [31:0] ALUResult, - output logic [31:0] Zero + output logic Zero ); always_comb begin @@ -36,6 +36,6 @@ module alu ( default: ALUResult = 32'b0; endcase - Zero = 32'b0; + Zero = 1'b0; end endmodule diff --git a/repo/rtl/control_path.sv b/repo/rtl/control_path.sv index ec6f59c..402a1f2 100644 --- a/repo/rtl/control_path.sv +++ b/repo/rtl/control_path.sv @@ -1,6 +1,6 @@ module control_path( output logic [31:0] Instr, - input logic [31:0] Zero, + input logic Zero, output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) output logic RegWrite, // enable write to register diff --git a/repo/rtl/data_path.sv b/repo/rtl/data_path.sv index 04b9ffb..47dbb90 100644 --- a/repo/rtl/data_path.sv +++ b/repo/rtl/data_path.sv @@ -13,7 +13,7 @@ module data_path ( input logic [2:0] AddressingControl, output logic [31:0] Instr, - output logic [31:0] Zero, + output logic Zero, output logic [31:0] a0 ); diff --git a/repo/rtl/pcsrc_unit.sv b/repo/rtl/pcsrc_unit.sv index 1ae1d09..78cc1f3 100644 --- a/repo/rtl/pcsrc_unit.sv +++ b/repo/rtl/pcsrc_unit.sv @@ -1,18 +1,15 @@ module pcsrc_unit ( input logic [1:0] Jump, input logic Branch, - input logic [31:0] Zero, + input logic Zero, input logic [2:0] BranchType, - input logic [31:0] ALUResult, output logic [1:0] PCSrc // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) ); - logic TakeBranch; - always_comb begin // default PCSrc = 2'b00; - TakeBranch = 1'b0; + // handle jumps first case (Jump) 2'b01: PCSrc = 2'b01; // JAL @@ -20,18 +17,13 @@ module pcsrc_unit ( 2'b00: begin // if jump==00 then check branches if (Branch) begin - - if(TakeBranch)begin - TakeBranch = 1'b1; - end - case (BranchType) - 3'b000: PCSrc = TakeBranch ? 2'b01 : 2'b00; // BEQ - 3'b001: PCSrc = ~TakeBranch ? 2'b01 : 2'b00; // BNE - 3'b100: PCSrc = ~TakeBranch ? 2'b01 : 2'b00; // BLT - 3'b101: PCSrc = TakeBranch ? 2'b01 : 2'b00; // BGE - 3'b110: PCSrc = ~TakeBranch ? 2'b01 : 2'b00; // BLTU - 3'b111: PCSrc = TakeBranch ? 2'b01 : 2'b00; // BGEU + 3'b000: PCSrc = Zero ? 2'b01 : 2'b00; // BEQ + 3'b001: PCSrc = ~Zero ? 2'b01 : 2'b00; // BNE + 3'b100: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLT + 3'b101: PCSrc = Zero ? 2'b01 : 2'b00; // BGE + 3'b110: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLTU + 3'b111: PCSrc = Zero ? 2'b01 : 2'b00; // BGEU default: PCSrc = 2'b00; endcase end diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index 3a26197..8625f2d 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -17,7 +17,7 @@ module top ( logic [2:0] AddressingControl; // Datapath outputs - logic [31:0] Zero; + logic Zero; logic [31:0] Instr; // Datapath From 805cad507447b981f073d91e2001b5b7a8196402 Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Fri, 28 Nov 2025 10:07:37 +0000 Subject: [PATCH 47/65] fixes --- repo/rtl/control_path.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/repo/rtl/control_path.sv b/repo/rtl/control_path.sv index 402a1f2..8342047 100644 --- a/repo/rtl/control_path.sv +++ b/repo/rtl/control_path.sv @@ -49,7 +49,6 @@ module control_path( .Zero(Zero), .BranchType(BranchType), .PCSrc(PCSrc), - .ALUResult(ALUResult) ); endmodule From 3c0b8650563e7d9fece823c2e0a26f1d5ee54954 Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Fri, 28 Nov 2025 10:08:02 +0000 Subject: [PATCH 48/65] fixes --- repo/rtl/control_path.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/repo/rtl/control_path.sv b/repo/rtl/control_path.sv index 8342047..94342ce 100644 --- a/repo/rtl/control_path.sv +++ b/repo/rtl/control_path.sv @@ -48,7 +48,7 @@ module control_path( .Branch(Branch), .Zero(Zero), .BranchType(BranchType), - .PCSrc(PCSrc), + .PCSrc(PCSrc) ); endmodule From 7f32a20b7764d40464f68435dc15386398034362 Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Fri, 28 Nov 2025 10:51:11 +0000 Subject: [PATCH 49/65] fixes --- repo/rtl/control_path.sv | 4 +++- repo/rtl/data_path.sv | 4 ++-- repo/rtl/pc.sv | 3 +++ repo/rtl/reg_file.sv | 4 +++- repo/rtl/top.sv | 2 ++ 5 files changed, 13 insertions(+), 4 deletions(-) diff --git a/repo/rtl/control_path.sv b/repo/rtl/control_path.sv index 94342ce..a419210 100644 --- a/repo/rtl/control_path.sv +++ b/repo/rtl/control_path.sv @@ -1,5 +1,7 @@ module control_path( - output logic [31:0] Instr, + /* verilator lint_off UNUSED */ + input logic [31:0] Instr, + /* verilator lint_on UNUSED */ input logic Zero, output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) diff --git a/repo/rtl/data_path.sv b/repo/rtl/data_path.sv index 47dbb90..5f89c15 100644 --- a/repo/rtl/data_path.sv +++ b/repo/rtl/data_path.sv @@ -21,7 +21,6 @@ module data_path ( assign SrcA = ALUSrcA ? PC : ReadData1; assign SrcB = ALUSrcB ? ImmExt : ReadData2; - assign a0 = ALUResult; pc pc_inst( .clk(clk), @@ -63,7 +62,8 @@ module data_path ( .WD3(ResultData), .WE3(RegWrite), .RD1(ReadData1), - .RD2(ReadData2) + .RD2(ReadData2), + .a0(a0) ); signext signext_inst( diff --git a/repo/rtl/pc.sv b/repo/rtl/pc.sv index 6405913..3043892 100644 --- a/repo/rtl/pc.sv +++ b/repo/rtl/pc.sv @@ -22,7 +22,10 @@ always_comb begin case(PCSrc) 2'b00: PCNext = PCPlus4; 2'b01: PCNext = PCTarget; + /* verilator lint_off UNUSED */ 2'b10: PCNext = {ALUResult[31:2], 2'b00}; // word addressed << 2 + /* verilator lint_on UNUSED */ + endcase end diff --git a/repo/rtl/reg_file.sv b/repo/rtl/reg_file.sv index c422341..084e03f 100644 --- a/repo/rtl/reg_file.sv +++ b/repo/rtl/reg_file.sv @@ -9,7 +9,8 @@ module reg_file #( input logic [DATA_WIDTH-1:0] WD3, // write data input logic WE3, // write enable output logic [DATA_WIDTH-1:0] RD1, // register file output for rs1 - output logic [DATA_WIDTH-1:0] RD2 // register file output for rs2 + output logic [DATA_WIDTH-1:0] RD2, // register file output for rs2 + output logic [DATA_WIDTH-1:0] a0 // register file output for testbenches ); @@ -25,5 +26,6 @@ module reg_file #( // read operations (combinational) -> outputs change immediately when read_addr changes assign RD1 = ram_array[AD1]; assign RD2 = ram_array[AD2]; + assign a0 = ram_array[5'b01010]; endmodule diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index 8625f2d..efccc5f 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -1,7 +1,9 @@ module top ( input logic clk, input logic rst, + /* verilator lint_off UNUSED */ input logic trigger, + /* verilator lint_on UNUSED */ output logic [31:0] a0 ); From a976adc74a70b740fb29bbea39cc650afe9a5b7d Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Fri, 28 Nov 2025 11:04:24 +0000 Subject: [PATCH 50/65] fixes --- repo/rtl/pc.sv | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/repo/rtl/pc.sv b/repo/rtl/pc.sv index 3043892..d08c272 100644 --- a/repo/rtl/pc.sv +++ b/repo/rtl/pc.sv @@ -5,7 +5,12 @@ module pc #( input logic rst, // asynchronous reset input logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) input logic [WIDTH-1:0] ImmExt, // immediate offset for branch target + + /* verilator lint_off UNUSED */ + input logic [WIDTH-1:0] ALUResult, + + /* verilator lint_on UNUSED */ output logic [WIDTH-1:0] PCPlus4, // PC + 4 output logic [WIDTH-1:0] PC // current program counter ); @@ -15,6 +20,7 @@ logic [WIDTH-1:0] PCNext; logic [WIDTH-1:0] PCTarget; + always_comb begin PCPlus4 = PC + 4; PCTarget = PC + ImmExt; @@ -22,14 +28,15 @@ always_comb begin case(PCSrc) 2'b00: PCNext = PCPlus4; 2'b01: PCNext = PCTarget; - /* verilator lint_off UNUSED */ + 2'b10: PCNext = {ALUResult[31:2], 2'b00}; // word addressed << 2 - /* verilator lint_on UNUSED */ + default: PCNext = PCPlus4; endcase - end + + // program counter register with asynchronous reset always_ff @(posedge clk or posedge rst) begin if (rst) From 1df77771ade4c5dcf27cffee9816a4e8d8158c0e Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Fri, 28 Nov 2025 11:13:23 +0000 Subject: [PATCH 51/65] data_unit deleted --- repo/rtl/control.sv | 2 ++ repo/rtl/data_mem.sv | 2 ++ repo/rtl/data_unit.sv | 82 ------------------------------------------ repo/rtl/pcsrc_unit.sv | 1 + 4 files changed, 5 insertions(+), 82 deletions(-) delete mode 100644 repo/rtl/data_unit.sv diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index 4b220c1..b9d60ee 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -137,6 +137,8 @@ module control( // BLTU, BGEU: ALU does SLTU (1001) 3'b110: ALUControl = 4'b1001; // bltu 3'b111: ALUControl = 4'b1001; // bgeu + default: ALUControl = 4'b0000; + endcase end diff --git a/repo/rtl/data_mem.sv b/repo/rtl/data_mem.sv index fe1b5c0..8c5ec7d 100644 --- a/repo/rtl/data_mem.sv +++ b/repo/rtl/data_mem.sv @@ -5,7 +5,9 @@ module data_mem #( ) ( input logic clk, input logic WE, // write enable + /* verilator lint_off UNUSED */ input logic [XLEN-1:0] A, // memory address + /* verilator lint_on UNUSED */ input logic [XLEN-1:0] WD, // data to write input logic [2:0] AddressingControl, // funct3 to determine load/store type output logic [XLEN-1:0] RD // data read diff --git a/repo/rtl/data_unit.sv b/repo/rtl/data_unit.sv deleted file mode 100644 index bfdc3dc..0000000 --- a/repo/rtl/data_unit.sv +++ /dev/null @@ -1,82 +0,0 @@ -module data_unit #( - parameter DATA_WIDTH = 32, - ADDRESS_WIDTH = 5 -) ( - input logic clk, - input logic [ADDRESS_WIDTH-1:0] AD1, // rs1 address - input logic [ADDRESS_WIDTH-1:0] AD2, // rs2 address - input logic [ADDRESS_WIDTH-1:0] AD3, // rd address - input logic [DATA_WIDTH-1:0] ImmOp, // immediate value - input logic RegWrite, // write enable to register file - input logic MemWrite, // write enable to memory - input logic ALUctrl, // ALU control - input logic ALUsrc, // select imm or reg - input logic [1:0] ResultSrc, // select ALU or mem data - input logic [2:0] funct3, // for memory access size - input logic [DATA_WIDTH-1:0] PCtarget, // branch target address - input logic [DATA_WIDTH-1:0] PC, - input logic [6:0] opcode, - output logic [2:0] EQ, // ALU equality flag - output logic [DATA_WIDTH-1:0] a0, // x10 output - output logic [DATA_WIDTH-1:0] ALUout // ALU result -); - -logic [DATA_WIDTH-1:0] ALUop1; // ALU operand 1 -logic [DATA_WIDTH-1:0] ALUop2; // ALU operand 2 -logic [DATA_WIDTH-1:0] WriteData; // register file output 2 -logic [DATA_WIDTH-1:0] ReadData; // data memory output -logic [DATA_WIDTH-1:0] result; // data to write back to register file - -// register file: read rs1/rs2, write rd -reg_file reg_file ( - .clk(clk), - .read_addr1(AD1), - .read_addr2(AD2), - .write_addr(AD3), - .wd3(ALUout), - .we3(RegWrite), - .dout1(ALUop1), - .dout2(WriteData), - .a0(a0) -); - -// select ALU operand 2: register or immediate -mux mux1 ( - .in0(WriteData), - .in1(ImmOp), - .sel(ALUsrc), - .out(ALUop2) -); - -// ALU executes operation and sets EQ -alu alu ( - .alu_op1(ALUop1), - .alu_op2(ALUop2), - .alu_ctrl(ALUctrl), - .alu_out(ALUout), - .eq(EQ), - .PC(PC) -); - -// memory -data_mem data_mem ( - .clk(clk), - .en(MemWrite), - .wr_addr(ALUout), - .din(WriteData), - .dout(ReadData), - .funct3(funct3) -); - -always_comb begin - - case (ResultSrc) - 2'b00: assign ALUout = ALUout; // ALU result - 2'b01: assign ALUout = ReadData; // Memory data - 2'b10: assign ALUout = PCtarget; // PC + 4 for JAL/JALR - default: assign ALUout = ALUout; // Default to ALU result - endcase - -end - -endmodule diff --git a/repo/rtl/pcsrc_unit.sv b/repo/rtl/pcsrc_unit.sv index 78cc1f3..f31e45f 100644 --- a/repo/rtl/pcsrc_unit.sv +++ b/repo/rtl/pcsrc_unit.sv @@ -12,6 +12,7 @@ module pcsrc_unit ( // handle jumps first case (Jump) + default: PCSrc = 2'b00; 2'b01: PCSrc = 2'b01; // JAL 2'b10: PCSrc = 2'b10; // JALR 2'b00: begin From f6a1535d84d71d2ff94b8730cc13ac8404cbbb3a Mon Sep 17 00:00:00 2001 From: Sicovo Date: Fri, 28 Nov 2025 11:15:25 +0000 Subject: [PATCH 52/65] Zero --- repo/rtl/alu.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/repo/rtl/alu.sv b/repo/rtl/alu.sv index d955b5e..dbad7c3 100644 --- a/repo/rtl/alu.sv +++ b/repo/rtl/alu.sv @@ -36,6 +36,6 @@ module alu ( default: ALUResult = 32'b0; endcase - Zero = 1'b0; + Zero = (ALUResult == 32'd0); end -endmodule +endmodule \ No newline at end of file From c4ee6a966ef739c08302ecc88a6325d350cf4421 Mon Sep 17 00:00:00 2001 From: Sicovo Date: Fri, 28 Nov 2025 11:18:08 +0000 Subject: [PATCH 53/65] AddressingCtrl --- repo/rtl/control.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index b9d60ee..586e1b3 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -24,7 +24,7 @@ module control( // assign opcode = Instr[6:0]; // assign funct3 = Instr[14:12]; // assign funct7 = Instr[31:25]; - // assign AddressingControl = funct3; // store width + assign AddressingControl = funct3; // store width always_comb begin // Default values to prevent latches From 5231813ed922af728b67f70590ae4575f2772898 Mon Sep 17 00:00:00 2001 From: Sicovo Date: Fri, 28 Nov 2025 11:22:32 +0000 Subject: [PATCH 54/65] Trigger Removerd --- repo/rtl copy/alu.sv | 41 ++++++++ repo/rtl copy/control.sv | 187 ++++++++++++++++++++++++++++++++++ repo/rtl copy/control_path.sv | 56 ++++++++++ repo/rtl copy/data_mem.sv | 51 ++++++++++ repo/rtl copy/data_path.sv | 85 ++++++++++++++++ repo/rtl copy/instr_mem.sv | 18 ++++ repo/rtl copy/pc.sv | 48 +++++++++ repo/rtl copy/pcsrc_unit.sv | 35 +++++++ repo/rtl copy/reg_file.sv | 31 ++++++ repo/rtl copy/signext.sv | 17 ++++ repo/rtl copy/top.sv | 61 +++++++++++ repo/rtl/top.sv | 3 - 12 files changed, 630 insertions(+), 3 deletions(-) create mode 100644 repo/rtl copy/alu.sv create mode 100644 repo/rtl copy/control.sv create mode 100644 repo/rtl copy/control_path.sv create mode 100644 repo/rtl copy/data_mem.sv create mode 100644 repo/rtl copy/data_path.sv create mode 100644 repo/rtl copy/instr_mem.sv create mode 100644 repo/rtl copy/pc.sv create mode 100644 repo/rtl copy/pcsrc_unit.sv create mode 100644 repo/rtl copy/reg_file.sv create mode 100644 repo/rtl copy/signext.sv create mode 100644 repo/rtl copy/top.sv diff --git a/repo/rtl copy/alu.sv b/repo/rtl copy/alu.sv new file mode 100644 index 0000000..dbad7c3 --- /dev/null +++ b/repo/rtl copy/alu.sv @@ -0,0 +1,41 @@ + // 0000 = ADD + // 0001 = SUB + // 0010 = AND + // 0011 = OR + // 0100 = XOR + // 0101 = SLL + // 0110 = SRL + // 0111 = SRA + // 1000 = SLT (signed) + // 1001 = SLTU (unsigned) + // 1111 = LUI operation + +module alu ( + input logic [31:0] SrcA, + input logic [31:0] SrcB, + input logic [3:0] ALUControl, + output logic [31:0] ALUResult, + output logic Zero +); + + always_comb begin + case (ALUControl) + 4'b0000: ALUResult = SrcA + SrcB; // add + 4'b0001: ALUResult = SrcA - SrcB; // sub + 4'b0010: ALUResult = SrcA & SrcB; // and + 4'b0011: ALUResult = SrcA | SrcB; // or + 4'b0100: ALUResult = SrcA ^ SrcB; // xor + + 4'b0101: ALUResult = SrcA << SrcB[4:0]; // sll + 4'b0110: ALUResult = SrcA >> SrcB[4:0]; // srl + 4'b0111: ALUResult = $signed(SrcA) >>> SrcB[4:0]; // sra + 4'b1000: ALUResult = ($signed(SrcA) < $signed(SrcB)) ? 32'b1 : 32'b0; //slt + 4'b1001: ALUResult = (SrcA < SrcB) ? 32'b1 : 32'b0; //sltu + 4'b1111: ALUResult = SrcB; // LUI operation (Load Upper Immediate) + + default: ALUResult = 32'b0; + endcase + + Zero = (ALUResult == 32'd0); + end +endmodule \ No newline at end of file diff --git a/repo/rtl copy/control.sv b/repo/rtl copy/control.sv new file mode 100644 index 0000000..586e1b3 --- /dev/null +++ b/repo/rtl copy/control.sv @@ -0,0 +1,187 @@ +module control( + input logic [6:0] opcode, + input logic [2:0] funct3, + input logic [6:0] funct7, + + output logic RegWrite, // enable write to register + output logic [3:0] ALUControl, // control operation in ALU + output logic ALUSrcA, // choose PC (1) or register (0) for ALU operand A + output logic ALUSrcB, // choose immediate (1) or register (0) operand + output logic MemWrite, // enable write into the data memory + // output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4) + output logic Branch, + output logic [2:0] BranchType, + output logic [1:0] Jump, // indicates jump instruction (00 = no jump, 01 = JAL, 10 = JALR) + output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) + output logic [2:0] AddressingControl // choose which type of load/store instruction to perform +); + + // logic [6:0] opcode; + // logic [2:0] funct3; + // logic [6:0] funct7; + + // assign opcode = Instr[6:0]; + // assign funct3 = Instr[14:12]; + // assign funct7 = Instr[31:25]; + assign AddressingControl = funct3; // store width + + always_comb begin + // Default values to prevent latches + RegWrite = 1'b0; + ALUControl = 4'b0000; + ALUSrcA = 1'b0; + ALUSrcB = 1'b0; + MemWrite = 1'b0; + ResultSrc = 2'b00; + Branch = 1'b0; + BranchType = 3'b000; + Jump = 2'b00; + ImmSrc = 3'b000; + AddressingControl = 3'b000; + + + case(opcode) + // R-type instructions + 7'b0110011: begin + RegWrite = 1'b1; + ALUSrcB = 1'b0; + + case(funct3) + 3'b000: begin + case(funct7) + 7'b0000000: ALUControl = 4'b0000; // add + 7'b0100000: ALUControl = 4'b0001; // sub + default: ALUControl = 4'b0000; + endcase + end + 3'b001: ALUControl = 4'b0101; // sll + 3'b010: ALUControl = 4'b1000; // slt + 3'b011: ALUControl = 4'b1001; // sltu + 3'b100: ALUControl = 4'b0100; // xor + 3'b101: begin + case(funct7) + 7'b0000000: ALUControl = 4'b0110; // srl + 7'b0100000: ALUControl = 4'b0111; // sra + default: ALUControl = 4'b0110; + endcase + end + 3'b110: ALUControl = 4'b0011; // or + 3'b111: ALUControl = 4'b0010; // and + + default: ALUControl = 4'b0000; + endcase + end + + // I-type instructions (Arithmetic/Logic) + 7'b0010011: begin + RegWrite = 1'b1; + ImmSrc = 3'b000; // I-type imm + ALUSrcB = 1'b1; + + case(funct3) + 3'b000: ALUControl = 4'b0000; // addi + 3'b001: ALUControl = 4'b0101; // slli + 3'b010: ALUControl = 4'b1000; // slti (Added) + 3'b011: ALUControl = 4'b1001; // sltiu (Added) + 3'b100: ALUControl = 4'b0100; // xori + 3'b101: begin + case(funct7) + 7'b0000000: ALUControl = 4'b0110; // srli + 7'b0100000: ALUControl = 4'b0111; // srai + default: ALUControl = 4'b0110; + endcase + end + 3'b110: ALUControl = 4'b0011; // ori + 3'b111: ALUControl = 4'b0010; // andi + default: ALUControl = 4'b0000; + endcase + end + + // I-type Load instructions + 7'b0000011: begin + RegWrite = 1'b1; + ALUSrcB = 1'b1; // SrcB = imm + ResultSrc = 2'b01; // From Memory + ImmSrc = 3'b000; // I-type imm + AddressingControl = funct3; + ALUControl = 4'b0000; // Add for address + end + + // S-type Store instructions + 7'b0100011: begin + MemWrite = 1'b1; + ALUSrcB = 1'b1; // read from immediate + ImmSrc = 3'b001; // S-type immediate + ALUControl = 4'b0000; // Add for address + AddressingControl = funct3; + end + + // B-type Branch instructions + 7'b1100011: begin + Branch = 1'b1; + ImmSrc = 3'b010; // B-type imm + BranchType = funct3; + + case(funct3) + // BEQ, BNE: ALU does SUB (0001) + // If A == B, Result = 0, Zero = 1 + 3'b000: ALUControl = 4'b0001; // beq + 3'b001: ALUControl = 4'b0001; // bne + + // BLT, BGE: ALU does SLT (1000) + // If A < B: Result = 1, Zero = 0. If A >= B: Result = 0, Zero = 1. + 3'b100: ALUControl = 4'b1000; // blt + 3'b101: ALUControl = 4'b1000; // bge + + // BLTU, BGEU: ALU does SLTU (1001) + 3'b110: ALUControl = 4'b1001; // bltu + 3'b111: ALUControl = 4'b1001; // bgeu + default: ALUControl = 4'b0000; + + endcase + end + + // J-type JAL + 7'b1101111: begin + RegWrite = 1'b1; + ResultSrc = 2'b10; // PC+4 + ImmSrc = 3'b011; // J-type imm + Jump = 2'b01; + end + + // I-type JALR + 7'b1100111: begin + RegWrite = 1'b1; + ALUSrcB = 1'b1; // SrcB = imm + ResultSrc = 2'b10; // PC+4 + ImmSrc = 3'b000; // I-type imm + Jump = 2'b10; + // ALUControl = 4'b0000; // Add for target address + end + + // U-type LUI + 7'b0110111: begin + RegWrite = 1'b1; + ALUSrcB = 1'b1; + ResultSrc = 2'b00; + ImmSrc = 3'b100; // U-type imm + ALUControl = 4'b1111; // LUI operation (0 + imm shifted) + end + + // U-type AUIPC rd <- PC + imm << 12 + 7'b0010111: begin + RegWrite = 1'b1; + MemWrite = 1'b0; + ALUSrcA = 1'b1; // Select PC + ALUSrcB = 1'b1; // Select Imm + ImmSrc = 3'b100; // U-type imm + ALUControl = 4'b000; // AUIPC operation (PC + imm shifted) + end + + default: begin + // Already handled by defaults at top + end + endcase + end +endmodule diff --git a/repo/rtl copy/control_path.sv b/repo/rtl copy/control_path.sv new file mode 100644 index 0000000..a419210 --- /dev/null +++ b/repo/rtl copy/control_path.sv @@ -0,0 +1,56 @@ +module control_path( + /* verilator lint_off UNUSED */ + input logic [31:0] Instr, + /* verilator lint_on UNUSED */ + input logic Zero, + + output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + output logic RegWrite, // enable write to register + output logic [3:0] ALUControl, // control operation in ALU + output logic ALUSrcA, // choose PC (1) or register (0) for ALU operand A + output logic ALUSrcB, // choose immediate (1) or register (0) operand + output logic MemWrite, // enable write into the data memory + // output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4) + output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) + output logic [2:0] AddressingControl // choose which type of load/store instruction to perform +); + + logic Branch; + logic [2:0] BranchType; + logic [1:0] Jump; + + logic [6:0] opcode; + logic [2:0] funct3; + logic [6:0] funct7; + + assign opcode = Instr[6:0]; + assign funct3 = Instr[14:12]; + assign funct7 = Instr[31:25]; + + control control_unit ( + .opcode(opcode), + .funct3(funct3), + .funct7(funct7), + .RegWrite(RegWrite), + .ALUControl(ALUControl), + .ALUSrcA(ALUSrcA), + .ALUSrcB(ALUSrcB), + .MemWrite(MemWrite), + .ResultSrc(ResultSrc), + .Branch(Branch), + .BranchType(BranchType), + .Jump(Jump), + .ImmSrc(ImmSrc), + .AddressingControl(AddressingControl) + ); + + pcsrc_unit pcsrc_unit_inst ( + .Jump(Jump), + .Branch(Branch), + .Zero(Zero), + .BranchType(BranchType), + .PCSrc(PCSrc) + ); + +endmodule diff --git a/repo/rtl copy/data_mem.sv b/repo/rtl copy/data_mem.sv new file mode 100644 index 0000000..8c5ec7d --- /dev/null +++ b/repo/rtl copy/data_mem.sv @@ -0,0 +1,51 @@ +module data_mem #( + parameter XLEN = 32, + parameter ADDRESS_WIDTH = 16, + parameter DATA_WIDTH = 8 +) ( + input logic clk, + input logic WE, // write enable + /* verilator lint_off UNUSED */ + input logic [XLEN-1:0] A, // memory address + /* verilator lint_on UNUSED */ + input logic [XLEN-1:0] WD, // data to write + input logic [2:0] AddressingControl, // funct3 to determine load/store type + output logic [XLEN-1:0] RD // data read +); + logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; // 64KB data memory + + logic [ADDRESS_WIDTH-1:0] addr; + assign addr = A[ADDRESS_WIDTH-1:0]; // use lower ADDRESS_WIDTH bits of address + + always_ff @(posedge clk) begin + if (WE) begin + case (AddressingControl) + 3'b000: ram_array[addr] <= WD[7:0]; // SB + 3'b001: begin // SH + ram_array[addr] <= WD[7:0]; + ram_array[addr+1] <= WD[15:8]; + end + 3'b010: begin // SW + ram_array[addr] <= WD[7:0]; + ram_array[addr+1] <= WD[15:8]; + ram_array[addr+2] <= WD[23:16]; + ram_array[addr+3] <= WD[31:24]; + end + default: ; // ignore other funct3 + endcase + end + end + + always_comb begin + case (AddressingControl) + 3'b000: RD = {{24{ram_array[addr][7]}}, ram_array[addr]}; // LB (signed) + 3'b001: RD = {{16{ram_array[addr+1][7]}}, ram_array[addr+1], ram_array[addr]}; // LH (signed) + 3'b010: RD = {ram_array[addr+3], ram_array[addr+2], ram_array[addr+1], ram_array[addr]}; // LW + 3'b100: RD = {24'b0, ram_array[addr]}; // LBU + 3'b101: RD = {16'b0, ram_array[addr+1], ram_array[addr]}; // LHU + default: RD = 32'b0; + endcase + end + + +endmodule diff --git a/repo/rtl copy/data_path.sv b/repo/rtl copy/data_path.sv new file mode 100644 index 0000000..5f89c15 --- /dev/null +++ b/repo/rtl copy/data_path.sv @@ -0,0 +1,85 @@ +module data_path ( + input logic clk, + input logic rst, + + input logic [1:0] PCSrc, + input logic RegWrite, + input logic [3:0] ALUControl, + input logic ALUSrcA, + input logic ALUSrcB, + input logic MemWrite, + input logic [1:0] ResultSrc, + input logic [2:0] ImmSrc, + input logic [2:0] AddressingControl, + + output logic [31:0] Instr, + output logic Zero, + output logic [31:0] a0 +); + + logic [31:0] PC, PCPlus4, ImmExt, MemData, ALUResult, SrcA, SrcB, ReadData1, ReadData2, ResultData; + + assign SrcA = ALUSrcA ? PC : ReadData1; + assign SrcB = ALUSrcB ? ImmExt : ReadData2; + + pc pc_inst( + .clk(clk), + .rst(rst), + .PCSrc(PCSrc), + .ImmExt(ImmExt), + .ALUResult(ALUResult), + .PCPlus4(PCPlus4), + .PC(PC) + ); + + alu alu_inst( + .SrcA(SrcA), + .SrcB(SrcB), + .ALUControl(ALUControl), + .ALUResult(ALUResult), + .Zero(Zero) + ); + + instr_mem instr_mem_inst( + .A(PC), + .RD(Instr) + ); + + data_mem data_mem_inst( + .clk(clk), + .WE(MemWrite), + .A(ALUResult), + .WD(ReadData2), + .AddressingControl(AddressingControl), + .RD(MemData) + ); + + reg_file reg_file_inst( + .clk(clk), + .AD1(Instr[19:15]), + .AD2(Instr[24:20]), + .AD3(Instr[11:7]), + .WD3(ResultData), + .WE3(RegWrite), + .RD1(ReadData1), + .RD2(ReadData2), + .a0(a0) + ); + + signext signext_inst( + .Imm(Instr[31:7]), + .ImmSrc(ImmSrc), + .ImmExt(ImmExt) + ); + + always_comb begin + case (ResultSrc) + 2'b00: ResultData = ALUResult; + 2'b01: ResultData = MemData; + 2'b10: ResultData = PCPlus4; + default: ResultData = 32'b0; + endcase + end + + +endmodule diff --git a/repo/rtl copy/instr_mem.sv b/repo/rtl copy/instr_mem.sv new file mode 100644 index 0000000..54dbf7a --- /dev/null +++ b/repo/rtl copy/instr_mem.sv @@ -0,0 +1,18 @@ +module instr_mem ( + /* verilator lint_off UNUSED */ + input logic [31:0] A, + output logic [31:0] RD + /* verilator lint_on UNUSED */ +); + + // instruction memory array: 256 instructions, each 32 bits wide + logic [31:0] rom_array [0:255]; + + // preload instructions from an external hex file at simulation start + initial begin + $readmemh("../rtl/program.hex", rom_array); + end + + // output the instruction corresponding to the PC address + assign RD = rom_array[A[9:2]]; +endmodule diff --git a/repo/rtl copy/pc.sv b/repo/rtl copy/pc.sv new file mode 100644 index 0000000..d08c272 --- /dev/null +++ b/repo/rtl copy/pc.sv @@ -0,0 +1,48 @@ +module pc #( + parameter WIDTH = 32 +)( + input logic clk, // system clock + input logic rst, // asynchronous reset + input logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + input logic [WIDTH-1:0] ImmExt, // immediate offset for branch target + + /* verilator lint_off UNUSED */ + + input logic [WIDTH-1:0] ALUResult, + + /* verilator lint_on UNUSED */ + output logic [WIDTH-1:0] PCPlus4, // PC + 4 + output logic [WIDTH-1:0] PC // current program counter +); + +// next PC after the mux +logic [WIDTH-1:0] PCNext; + +logic [WIDTH-1:0] PCTarget; + + +always_comb begin + PCPlus4 = PC + 4; + PCTarget = PC + ImmExt; + + case(PCSrc) + 2'b00: PCNext = PCPlus4; + 2'b01: PCNext = PCTarget; + + 2'b10: PCNext = {ALUResult[31:2], 2'b00}; // word addressed << 2 + + default: PCNext = PCPlus4; + endcase +end + + + +// program counter register with asynchronous reset +always_ff @(posedge clk or posedge rst) begin + if (rst) + PC <= {WIDTH{1'b0}}; // Reset PC to 0 + else + PC <= PCNext; // Update PC normally +end + +endmodule diff --git a/repo/rtl copy/pcsrc_unit.sv b/repo/rtl copy/pcsrc_unit.sv new file mode 100644 index 0000000..f31e45f --- /dev/null +++ b/repo/rtl copy/pcsrc_unit.sv @@ -0,0 +1,35 @@ +module pcsrc_unit ( + input logic [1:0] Jump, + input logic Branch, + input logic Zero, + input logic [2:0] BranchType, + output logic [1:0] PCSrc // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) +); + + always_comb begin + // default + PCSrc = 2'b00; + + // handle jumps first + case (Jump) + default: PCSrc = 2'b00; + 2'b01: PCSrc = 2'b01; // JAL + 2'b10: PCSrc = 2'b10; // JALR + 2'b00: begin + // if jump==00 then check branches + if (Branch) begin + case (BranchType) + 3'b000: PCSrc = Zero ? 2'b01 : 2'b00; // BEQ + 3'b001: PCSrc = ~Zero ? 2'b01 : 2'b00; // BNE + 3'b100: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLT + 3'b101: PCSrc = Zero ? 2'b01 : 2'b00; // BGE + 3'b110: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLTU + 3'b111: PCSrc = Zero ? 2'b01 : 2'b00; // BGEU + default: PCSrc = 2'b00; + endcase + end + end + endcase + end + +endmodule diff --git a/repo/rtl copy/reg_file.sv b/repo/rtl copy/reg_file.sv new file mode 100644 index 0000000..084e03f --- /dev/null +++ b/repo/rtl copy/reg_file.sv @@ -0,0 +1,31 @@ +module reg_file #( + parameter ADDRESS_WIDTH = 5, // 32 registers + DATA_WIDTH = 32 // 32-bits +)( + input logic clk, // clock + input logic [ADDRESS_WIDTH-1:0] AD3, // destination register + input logic [ADDRESS_WIDTH-1:0] AD1, // source register 1 address (rs1) + input logic [ADDRESS_WIDTH-1:0] AD2, // source register 2 address (rs2) + input logic [DATA_WIDTH-1:0] WD3, // write data + input logic WE3, // write enable + output logic [DATA_WIDTH-1:0] RD1, // register file output for rs1 + output logic [DATA_WIDTH-1:0] RD2, // register file output for rs2 + output logic [DATA_WIDTH-1:0] a0 // register file output for testbenches + +); + + // 32 32-bit registers + logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; + + // write operation (synchronous) -> writes occur only if WE3 is asserted + always_ff @(posedge clk) begin + if (WE3 == 1'b1 && AD3 != 0) + ram_array[AD3] <= WD3; + end + + // read operations (combinational) -> outputs change immediately when read_addr changes + assign RD1 = ram_array[AD1]; + assign RD2 = ram_array[AD2]; + assign a0 = ram_array[5'b01010]; + +endmodule diff --git a/repo/rtl copy/signext.sv b/repo/rtl copy/signext.sv new file mode 100644 index 0000000..d2c6ae2 --- /dev/null +++ b/repo/rtl copy/signext.sv @@ -0,0 +1,17 @@ +module signext ( + input logic [31:7] Imm, + input logic [2:0] ImmSrc, + output logic [31:0] ImmExt +); + + always_comb begin + case (ImmSrc) + 3'b000: ImmExt = {{20{Imm[31]}}, Imm[31:20]}; // I-type + 3'b001: ImmExt = {{20{Imm[31]}}, Imm[31:25], Imm[11:7]}; // S-type + 3'b010: ImmExt = {{20{Imm[31]}}, Imm[7], Imm[30:25], Imm[11:8], 1'b0}; // B-type + 3'b011: ImmExt = {{12{Imm[31]}}, Imm[19:12], Imm[20], Imm[30:21], 1'b0}; // J-type + 3'b100: ImmExt = {Imm[31:12], 12'b0}; // U-type + default: ImmExt = 32'b0; + endcase + end +endmodule diff --git a/repo/rtl copy/top.sv b/repo/rtl copy/top.sv new file mode 100644 index 0000000..efccc5f --- /dev/null +++ b/repo/rtl copy/top.sv @@ -0,0 +1,61 @@ +module top ( + input logic clk, + input logic rst, + /* verilator lint_off UNUSED */ + input logic trigger, + /* verilator lint_on UNUSED */ + output logic [31:0] a0 +); + + // Control signals + logic [1:0] PCSrc; + logic RegWrite; + logic [3:0] ALUControl; + logic ALUSrcA; + logic ALUSrcB; + logic MemWrite; + logic [1:0] ResultSrc; + logic [2:0] ImmSrc; + logic [2:0] AddressingControl; + + // Datapath outputs + logic Zero; + logic [31:0] Instr; + + // Datapath + data_path dp_inst ( + .clk(clk), + .rst(rst), + + .PCSrc(PCSrc), + .RegWrite(RegWrite), + .ALUControl(ALUControl), + .ALUSrcA(ALUSrcA), + .ALUSrcB(ALUSrcB), + .MemWrite(MemWrite), + .ResultSrc(ResultSrc), + .ImmSrc(ImmSrc), + .AddressingControl(AddressingControl), + + .Instr(Instr), + .Zero(Zero), + .a0(a0) + ); + + // Control path + control_path ctrl_inst ( + .Instr(Instr), + .Zero(Zero), + + .PCSrc(PCSrc), + .RegWrite(RegWrite), + .ALUControl(ALUControl), + .ALUSrcA(ALUSrcA), + .ALUSrcB(ALUSrcB), + .MemWrite(MemWrite), + .ResultSrc(ResultSrc), + .ImmSrc(ImmSrc), + .AddressingControl(AddressingControl) + ); + +endmodule diff --git a/repo/rtl/top.sv b/repo/rtl/top.sv index efccc5f..d763023 100644 --- a/repo/rtl/top.sv +++ b/repo/rtl/top.sv @@ -1,9 +1,6 @@ module top ( input logic clk, input logic rst, - /* verilator lint_off UNUSED */ - input logic trigger, - /* verilator lint_on UNUSED */ output logic [31:0] a0 ); From 8c0ad3775ba862ea59fd1390ed8c13ce10c1537a Mon Sep 17 00:00:00 2001 From: Sicovo Date: Fri, 28 Nov 2025 11:23:51 +0000 Subject: [PATCH 55/65] sig_ext --- repo/rtl/data_path.sv | 2 +- repo/rtl/{signext.sv => sign_ext.sv} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename repo/rtl/{signext.sv => sign_ext.sv} (100%) diff --git a/repo/rtl/data_path.sv b/repo/rtl/data_path.sv index 5f89c15..8d1cf62 100644 --- a/repo/rtl/data_path.sv +++ b/repo/rtl/data_path.sv @@ -66,7 +66,7 @@ module data_path ( .a0(a0) ); - signext signext_inst( + sign_ext sign_ext_inst( .Imm(Instr[31:7]), .ImmSrc(ImmSrc), .ImmExt(ImmExt) diff --git a/repo/rtl/signext.sv b/repo/rtl/sign_ext.sv similarity index 100% rename from repo/rtl/signext.sv rename to repo/rtl/sign_ext.sv From b405fea5dfd8da20d3ad2a421a809b09e244895e Mon Sep 17 00:00:00 2001 From: Sicovo Date: Fri, 28 Nov 2025 11:26:54 +0000 Subject: [PATCH 56/65] rtl_pipelined --- repo/{rtl copy => rtl_pipelined}/alu.sv | 0 repo/{rtl copy => rtl_pipelined}/control.sv | 0 repo/{rtl copy => rtl_pipelined}/control_path.sv | 0 repo/{rtl copy => rtl_pipelined}/data_mem.sv | 0 repo/{rtl copy => rtl_pipelined}/data_path.sv | 0 repo/{rtl copy => rtl_pipelined}/instr_mem.sv | 0 repo/{rtl copy => rtl_pipelined}/pc.sv | 0 repo/{rtl copy => rtl_pipelined}/pcsrc_unit.sv | 0 repo/{rtl copy => rtl_pipelined}/reg_file.sv | 0 repo/{rtl copy => rtl_pipelined}/signext.sv | 0 repo/{rtl copy => rtl_pipelined}/top.sv | 0 11 files changed, 0 insertions(+), 0 deletions(-) rename repo/{rtl copy => rtl_pipelined}/alu.sv (100%) rename repo/{rtl copy => rtl_pipelined}/control.sv (100%) rename repo/{rtl copy => rtl_pipelined}/control_path.sv (100%) rename repo/{rtl copy => rtl_pipelined}/data_mem.sv (100%) rename repo/{rtl copy => rtl_pipelined}/data_path.sv (100%) rename repo/{rtl copy => rtl_pipelined}/instr_mem.sv (100%) rename repo/{rtl copy => rtl_pipelined}/pc.sv (100%) rename repo/{rtl copy => rtl_pipelined}/pcsrc_unit.sv (100%) rename repo/{rtl copy => rtl_pipelined}/reg_file.sv (100%) rename repo/{rtl copy => rtl_pipelined}/signext.sv (100%) rename repo/{rtl copy => rtl_pipelined}/top.sv (100%) diff --git a/repo/rtl copy/alu.sv b/repo/rtl_pipelined/alu.sv similarity index 100% rename from repo/rtl copy/alu.sv rename to repo/rtl_pipelined/alu.sv diff --git a/repo/rtl copy/control.sv b/repo/rtl_pipelined/control.sv similarity index 100% rename from repo/rtl copy/control.sv rename to repo/rtl_pipelined/control.sv diff --git a/repo/rtl copy/control_path.sv b/repo/rtl_pipelined/control_path.sv similarity index 100% rename from repo/rtl copy/control_path.sv rename to repo/rtl_pipelined/control_path.sv diff --git a/repo/rtl copy/data_mem.sv b/repo/rtl_pipelined/data_mem.sv similarity index 100% rename from repo/rtl copy/data_mem.sv rename to repo/rtl_pipelined/data_mem.sv diff --git a/repo/rtl copy/data_path.sv b/repo/rtl_pipelined/data_path.sv similarity index 100% rename from repo/rtl copy/data_path.sv rename to repo/rtl_pipelined/data_path.sv diff --git a/repo/rtl copy/instr_mem.sv b/repo/rtl_pipelined/instr_mem.sv similarity index 100% rename from repo/rtl copy/instr_mem.sv rename to repo/rtl_pipelined/instr_mem.sv diff --git a/repo/rtl copy/pc.sv b/repo/rtl_pipelined/pc.sv similarity index 100% rename from repo/rtl copy/pc.sv rename to repo/rtl_pipelined/pc.sv diff --git a/repo/rtl copy/pcsrc_unit.sv b/repo/rtl_pipelined/pcsrc_unit.sv similarity index 100% rename from repo/rtl copy/pcsrc_unit.sv rename to repo/rtl_pipelined/pcsrc_unit.sv diff --git a/repo/rtl copy/reg_file.sv b/repo/rtl_pipelined/reg_file.sv similarity index 100% rename from repo/rtl copy/reg_file.sv rename to repo/rtl_pipelined/reg_file.sv diff --git a/repo/rtl copy/signext.sv b/repo/rtl_pipelined/signext.sv similarity index 100% rename from repo/rtl copy/signext.sv rename to repo/rtl_pipelined/signext.sv diff --git a/repo/rtl copy/top.sv b/repo/rtl_pipelined/top.sv similarity index 100% rename from repo/rtl copy/top.sv rename to repo/rtl_pipelined/top.sv From c52e20ceb6b3c92559260f3fdb9ad232870b62f4 Mon Sep 17 00:00:00 2001 From: Sicovo Date: Fri, 28 Nov 2025 11:29:38 +0000 Subject: [PATCH 57/65] sign_ext --- repo/rtl/alu.sv | 2 +- repo/rtl/sign_ext.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/repo/rtl/alu.sv b/repo/rtl/alu.sv index dbad7c3..497dae5 100644 --- a/repo/rtl/alu.sv +++ b/repo/rtl/alu.sv @@ -38,4 +38,4 @@ module alu ( Zero = (ALUResult == 32'd0); end -endmodule \ No newline at end of file +endmodule diff --git a/repo/rtl/sign_ext.sv b/repo/rtl/sign_ext.sv index d2c6ae2..10834a9 100644 --- a/repo/rtl/sign_ext.sv +++ b/repo/rtl/sign_ext.sv @@ -1,4 +1,4 @@ -module signext ( +module sign_ext ( input logic [31:7] Imm, input logic [2:0] ImmSrc, output logic [31:0] ImmExt From 40902a692e82c1a5058a5c2cd4536f12106218d0 Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Fri, 28 Nov 2025 11:19:24 +0000 Subject: [PATCH 58/65] single_cycle_design_folder --- repo/single_cycle_design/rtl/alu.sv | 41 ++++ repo/single_cycle_design/rtl/control.sv | 187 +++++++++++++++++++ repo/single_cycle_design/rtl/control_path.sv | 56 ++++++ repo/single_cycle_design/rtl/data_mem.sv | 51 +++++ repo/single_cycle_design/rtl/data_path.sv | 85 +++++++++ repo/single_cycle_design/rtl/instr_mem.sv | 18 ++ repo/single_cycle_design/rtl/pc.sv | 48 +++++ repo/single_cycle_design/rtl/pcsrc_unit.sv | 35 ++++ repo/single_cycle_design/rtl/reg_file.sv | 31 +++ repo/single_cycle_design/rtl/signext.sv | 17 ++ repo/single_cycle_design/rtl/top.sv | 61 ++++++ 11 files changed, 630 insertions(+) create mode 100644 repo/single_cycle_design/rtl/alu.sv create mode 100644 repo/single_cycle_design/rtl/control.sv create mode 100644 repo/single_cycle_design/rtl/control_path.sv create mode 100644 repo/single_cycle_design/rtl/data_mem.sv create mode 100644 repo/single_cycle_design/rtl/data_path.sv create mode 100644 repo/single_cycle_design/rtl/instr_mem.sv create mode 100644 repo/single_cycle_design/rtl/pc.sv create mode 100644 repo/single_cycle_design/rtl/pcsrc_unit.sv create mode 100644 repo/single_cycle_design/rtl/reg_file.sv create mode 100644 repo/single_cycle_design/rtl/signext.sv create mode 100644 repo/single_cycle_design/rtl/top.sv diff --git a/repo/single_cycle_design/rtl/alu.sv b/repo/single_cycle_design/rtl/alu.sv new file mode 100644 index 0000000..d955b5e --- /dev/null +++ b/repo/single_cycle_design/rtl/alu.sv @@ -0,0 +1,41 @@ + // 0000 = ADD + // 0001 = SUB + // 0010 = AND + // 0011 = OR + // 0100 = XOR + // 0101 = SLL + // 0110 = SRL + // 0111 = SRA + // 1000 = SLT (signed) + // 1001 = SLTU (unsigned) + // 1111 = LUI operation + +module alu ( + input logic [31:0] SrcA, + input logic [31:0] SrcB, + input logic [3:0] ALUControl, + output logic [31:0] ALUResult, + output logic Zero +); + + always_comb begin + case (ALUControl) + 4'b0000: ALUResult = SrcA + SrcB; // add + 4'b0001: ALUResult = SrcA - SrcB; // sub + 4'b0010: ALUResult = SrcA & SrcB; // and + 4'b0011: ALUResult = SrcA | SrcB; // or + 4'b0100: ALUResult = SrcA ^ SrcB; // xor + + 4'b0101: ALUResult = SrcA << SrcB[4:0]; // sll + 4'b0110: ALUResult = SrcA >> SrcB[4:0]; // srl + 4'b0111: ALUResult = $signed(SrcA) >>> SrcB[4:0]; // sra + 4'b1000: ALUResult = ($signed(SrcA) < $signed(SrcB)) ? 32'b1 : 32'b0; //slt + 4'b1001: ALUResult = (SrcA < SrcB) ? 32'b1 : 32'b0; //sltu + 4'b1111: ALUResult = SrcB; // LUI operation (Load Upper Immediate) + + default: ALUResult = 32'b0; + endcase + + Zero = 1'b0; + end +endmodule diff --git a/repo/single_cycle_design/rtl/control.sv b/repo/single_cycle_design/rtl/control.sv new file mode 100644 index 0000000..b9d60ee --- /dev/null +++ b/repo/single_cycle_design/rtl/control.sv @@ -0,0 +1,187 @@ +module control( + input logic [6:0] opcode, + input logic [2:0] funct3, + input logic [6:0] funct7, + + output logic RegWrite, // enable write to register + output logic [3:0] ALUControl, // control operation in ALU + output logic ALUSrcA, // choose PC (1) or register (0) for ALU operand A + output logic ALUSrcB, // choose immediate (1) or register (0) operand + output logic MemWrite, // enable write into the data memory + // output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4) + output logic Branch, + output logic [2:0] BranchType, + output logic [1:0] Jump, // indicates jump instruction (00 = no jump, 01 = JAL, 10 = JALR) + output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) + output logic [2:0] AddressingControl // choose which type of load/store instruction to perform +); + + // logic [6:0] opcode; + // logic [2:0] funct3; + // logic [6:0] funct7; + + // assign opcode = Instr[6:0]; + // assign funct3 = Instr[14:12]; + // assign funct7 = Instr[31:25]; + // assign AddressingControl = funct3; // store width + + always_comb begin + // Default values to prevent latches + RegWrite = 1'b0; + ALUControl = 4'b0000; + ALUSrcA = 1'b0; + ALUSrcB = 1'b0; + MemWrite = 1'b0; + ResultSrc = 2'b00; + Branch = 1'b0; + BranchType = 3'b000; + Jump = 2'b00; + ImmSrc = 3'b000; + AddressingControl = 3'b000; + + + case(opcode) + // R-type instructions + 7'b0110011: begin + RegWrite = 1'b1; + ALUSrcB = 1'b0; + + case(funct3) + 3'b000: begin + case(funct7) + 7'b0000000: ALUControl = 4'b0000; // add + 7'b0100000: ALUControl = 4'b0001; // sub + default: ALUControl = 4'b0000; + endcase + end + 3'b001: ALUControl = 4'b0101; // sll + 3'b010: ALUControl = 4'b1000; // slt + 3'b011: ALUControl = 4'b1001; // sltu + 3'b100: ALUControl = 4'b0100; // xor + 3'b101: begin + case(funct7) + 7'b0000000: ALUControl = 4'b0110; // srl + 7'b0100000: ALUControl = 4'b0111; // sra + default: ALUControl = 4'b0110; + endcase + end + 3'b110: ALUControl = 4'b0011; // or + 3'b111: ALUControl = 4'b0010; // and + + default: ALUControl = 4'b0000; + endcase + end + + // I-type instructions (Arithmetic/Logic) + 7'b0010011: begin + RegWrite = 1'b1; + ImmSrc = 3'b000; // I-type imm + ALUSrcB = 1'b1; + + case(funct3) + 3'b000: ALUControl = 4'b0000; // addi + 3'b001: ALUControl = 4'b0101; // slli + 3'b010: ALUControl = 4'b1000; // slti (Added) + 3'b011: ALUControl = 4'b1001; // sltiu (Added) + 3'b100: ALUControl = 4'b0100; // xori + 3'b101: begin + case(funct7) + 7'b0000000: ALUControl = 4'b0110; // srli + 7'b0100000: ALUControl = 4'b0111; // srai + default: ALUControl = 4'b0110; + endcase + end + 3'b110: ALUControl = 4'b0011; // ori + 3'b111: ALUControl = 4'b0010; // andi + default: ALUControl = 4'b0000; + endcase + end + + // I-type Load instructions + 7'b0000011: begin + RegWrite = 1'b1; + ALUSrcB = 1'b1; // SrcB = imm + ResultSrc = 2'b01; // From Memory + ImmSrc = 3'b000; // I-type imm + AddressingControl = funct3; + ALUControl = 4'b0000; // Add for address + end + + // S-type Store instructions + 7'b0100011: begin + MemWrite = 1'b1; + ALUSrcB = 1'b1; // read from immediate + ImmSrc = 3'b001; // S-type immediate + ALUControl = 4'b0000; // Add for address + AddressingControl = funct3; + end + + // B-type Branch instructions + 7'b1100011: begin + Branch = 1'b1; + ImmSrc = 3'b010; // B-type imm + BranchType = funct3; + + case(funct3) + // BEQ, BNE: ALU does SUB (0001) + // If A == B, Result = 0, Zero = 1 + 3'b000: ALUControl = 4'b0001; // beq + 3'b001: ALUControl = 4'b0001; // bne + + // BLT, BGE: ALU does SLT (1000) + // If A < B: Result = 1, Zero = 0. If A >= B: Result = 0, Zero = 1. + 3'b100: ALUControl = 4'b1000; // blt + 3'b101: ALUControl = 4'b1000; // bge + + // BLTU, BGEU: ALU does SLTU (1001) + 3'b110: ALUControl = 4'b1001; // bltu + 3'b111: ALUControl = 4'b1001; // bgeu + default: ALUControl = 4'b0000; + + endcase + end + + // J-type JAL + 7'b1101111: begin + RegWrite = 1'b1; + ResultSrc = 2'b10; // PC+4 + ImmSrc = 3'b011; // J-type imm + Jump = 2'b01; + end + + // I-type JALR + 7'b1100111: begin + RegWrite = 1'b1; + ALUSrcB = 1'b1; // SrcB = imm + ResultSrc = 2'b10; // PC+4 + ImmSrc = 3'b000; // I-type imm + Jump = 2'b10; + // ALUControl = 4'b0000; // Add for target address + end + + // U-type LUI + 7'b0110111: begin + RegWrite = 1'b1; + ALUSrcB = 1'b1; + ResultSrc = 2'b00; + ImmSrc = 3'b100; // U-type imm + ALUControl = 4'b1111; // LUI operation (0 + imm shifted) + end + + // U-type AUIPC rd <- PC + imm << 12 + 7'b0010111: begin + RegWrite = 1'b1; + MemWrite = 1'b0; + ALUSrcA = 1'b1; // Select PC + ALUSrcB = 1'b1; // Select Imm + ImmSrc = 3'b100; // U-type imm + ALUControl = 4'b000; // AUIPC operation (PC + imm shifted) + end + + default: begin + // Already handled by defaults at top + end + endcase + end +endmodule diff --git a/repo/single_cycle_design/rtl/control_path.sv b/repo/single_cycle_design/rtl/control_path.sv new file mode 100644 index 0000000..a419210 --- /dev/null +++ b/repo/single_cycle_design/rtl/control_path.sv @@ -0,0 +1,56 @@ +module control_path( + /* verilator lint_off UNUSED */ + input logic [31:0] Instr, + /* verilator lint_on UNUSED */ + input logic Zero, + + output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + output logic RegWrite, // enable write to register + output logic [3:0] ALUControl, // control operation in ALU + output logic ALUSrcA, // choose PC (1) or register (0) for ALU operand A + output logic ALUSrcB, // choose immediate (1) or register (0) operand + output logic MemWrite, // enable write into the data memory + // output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4) + output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) + output logic [2:0] AddressingControl // choose which type of load/store instruction to perform +); + + logic Branch; + logic [2:0] BranchType; + logic [1:0] Jump; + + logic [6:0] opcode; + logic [2:0] funct3; + logic [6:0] funct7; + + assign opcode = Instr[6:0]; + assign funct3 = Instr[14:12]; + assign funct7 = Instr[31:25]; + + control control_unit ( + .opcode(opcode), + .funct3(funct3), + .funct7(funct7), + .RegWrite(RegWrite), + .ALUControl(ALUControl), + .ALUSrcA(ALUSrcA), + .ALUSrcB(ALUSrcB), + .MemWrite(MemWrite), + .ResultSrc(ResultSrc), + .Branch(Branch), + .BranchType(BranchType), + .Jump(Jump), + .ImmSrc(ImmSrc), + .AddressingControl(AddressingControl) + ); + + pcsrc_unit pcsrc_unit_inst ( + .Jump(Jump), + .Branch(Branch), + .Zero(Zero), + .BranchType(BranchType), + .PCSrc(PCSrc) + ); + +endmodule diff --git a/repo/single_cycle_design/rtl/data_mem.sv b/repo/single_cycle_design/rtl/data_mem.sv new file mode 100644 index 0000000..8c5ec7d --- /dev/null +++ b/repo/single_cycle_design/rtl/data_mem.sv @@ -0,0 +1,51 @@ +module data_mem #( + parameter XLEN = 32, + parameter ADDRESS_WIDTH = 16, + parameter DATA_WIDTH = 8 +) ( + input logic clk, + input logic WE, // write enable + /* verilator lint_off UNUSED */ + input logic [XLEN-1:0] A, // memory address + /* verilator lint_on UNUSED */ + input logic [XLEN-1:0] WD, // data to write + input logic [2:0] AddressingControl, // funct3 to determine load/store type + output logic [XLEN-1:0] RD // data read +); + logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; // 64KB data memory + + logic [ADDRESS_WIDTH-1:0] addr; + assign addr = A[ADDRESS_WIDTH-1:0]; // use lower ADDRESS_WIDTH bits of address + + always_ff @(posedge clk) begin + if (WE) begin + case (AddressingControl) + 3'b000: ram_array[addr] <= WD[7:0]; // SB + 3'b001: begin // SH + ram_array[addr] <= WD[7:0]; + ram_array[addr+1] <= WD[15:8]; + end + 3'b010: begin // SW + ram_array[addr] <= WD[7:0]; + ram_array[addr+1] <= WD[15:8]; + ram_array[addr+2] <= WD[23:16]; + ram_array[addr+3] <= WD[31:24]; + end + default: ; // ignore other funct3 + endcase + end + end + + always_comb begin + case (AddressingControl) + 3'b000: RD = {{24{ram_array[addr][7]}}, ram_array[addr]}; // LB (signed) + 3'b001: RD = {{16{ram_array[addr+1][7]}}, ram_array[addr+1], ram_array[addr]}; // LH (signed) + 3'b010: RD = {ram_array[addr+3], ram_array[addr+2], ram_array[addr+1], ram_array[addr]}; // LW + 3'b100: RD = {24'b0, ram_array[addr]}; // LBU + 3'b101: RD = {16'b0, ram_array[addr+1], ram_array[addr]}; // LHU + default: RD = 32'b0; + endcase + end + + +endmodule diff --git a/repo/single_cycle_design/rtl/data_path.sv b/repo/single_cycle_design/rtl/data_path.sv new file mode 100644 index 0000000..5f89c15 --- /dev/null +++ b/repo/single_cycle_design/rtl/data_path.sv @@ -0,0 +1,85 @@ +module data_path ( + input logic clk, + input logic rst, + + input logic [1:0] PCSrc, + input logic RegWrite, + input logic [3:0] ALUControl, + input logic ALUSrcA, + input logic ALUSrcB, + input logic MemWrite, + input logic [1:0] ResultSrc, + input logic [2:0] ImmSrc, + input logic [2:0] AddressingControl, + + output logic [31:0] Instr, + output logic Zero, + output logic [31:0] a0 +); + + logic [31:0] PC, PCPlus4, ImmExt, MemData, ALUResult, SrcA, SrcB, ReadData1, ReadData2, ResultData; + + assign SrcA = ALUSrcA ? PC : ReadData1; + assign SrcB = ALUSrcB ? ImmExt : ReadData2; + + pc pc_inst( + .clk(clk), + .rst(rst), + .PCSrc(PCSrc), + .ImmExt(ImmExt), + .ALUResult(ALUResult), + .PCPlus4(PCPlus4), + .PC(PC) + ); + + alu alu_inst( + .SrcA(SrcA), + .SrcB(SrcB), + .ALUControl(ALUControl), + .ALUResult(ALUResult), + .Zero(Zero) + ); + + instr_mem instr_mem_inst( + .A(PC), + .RD(Instr) + ); + + data_mem data_mem_inst( + .clk(clk), + .WE(MemWrite), + .A(ALUResult), + .WD(ReadData2), + .AddressingControl(AddressingControl), + .RD(MemData) + ); + + reg_file reg_file_inst( + .clk(clk), + .AD1(Instr[19:15]), + .AD2(Instr[24:20]), + .AD3(Instr[11:7]), + .WD3(ResultData), + .WE3(RegWrite), + .RD1(ReadData1), + .RD2(ReadData2), + .a0(a0) + ); + + signext signext_inst( + .Imm(Instr[31:7]), + .ImmSrc(ImmSrc), + .ImmExt(ImmExt) + ); + + always_comb begin + case (ResultSrc) + 2'b00: ResultData = ALUResult; + 2'b01: ResultData = MemData; + 2'b10: ResultData = PCPlus4; + default: ResultData = 32'b0; + endcase + end + + +endmodule diff --git a/repo/single_cycle_design/rtl/instr_mem.sv b/repo/single_cycle_design/rtl/instr_mem.sv new file mode 100644 index 0000000..54dbf7a --- /dev/null +++ b/repo/single_cycle_design/rtl/instr_mem.sv @@ -0,0 +1,18 @@ +module instr_mem ( + /* verilator lint_off UNUSED */ + input logic [31:0] A, + output logic [31:0] RD + /* verilator lint_on UNUSED */ +); + + // instruction memory array: 256 instructions, each 32 bits wide + logic [31:0] rom_array [0:255]; + + // preload instructions from an external hex file at simulation start + initial begin + $readmemh("../rtl/program.hex", rom_array); + end + + // output the instruction corresponding to the PC address + assign RD = rom_array[A[9:2]]; +endmodule diff --git a/repo/single_cycle_design/rtl/pc.sv b/repo/single_cycle_design/rtl/pc.sv new file mode 100644 index 0000000..d08c272 --- /dev/null +++ b/repo/single_cycle_design/rtl/pc.sv @@ -0,0 +1,48 @@ +module pc #( + parameter WIDTH = 32 +)( + input logic clk, // system clock + input logic rst, // asynchronous reset + input logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) + input logic [WIDTH-1:0] ImmExt, // immediate offset for branch target + + /* verilator lint_off UNUSED */ + + input logic [WIDTH-1:0] ALUResult, + + /* verilator lint_on UNUSED */ + output logic [WIDTH-1:0] PCPlus4, // PC + 4 + output logic [WIDTH-1:0] PC // current program counter +); + +// next PC after the mux +logic [WIDTH-1:0] PCNext; + +logic [WIDTH-1:0] PCTarget; + + +always_comb begin + PCPlus4 = PC + 4; + PCTarget = PC + ImmExt; + + case(PCSrc) + 2'b00: PCNext = PCPlus4; + 2'b01: PCNext = PCTarget; + + 2'b10: PCNext = {ALUResult[31:2], 2'b00}; // word addressed << 2 + + default: PCNext = PCPlus4; + endcase +end + + + +// program counter register with asynchronous reset +always_ff @(posedge clk or posedge rst) begin + if (rst) + PC <= {WIDTH{1'b0}}; // Reset PC to 0 + else + PC <= PCNext; // Update PC normally +end + +endmodule diff --git a/repo/single_cycle_design/rtl/pcsrc_unit.sv b/repo/single_cycle_design/rtl/pcsrc_unit.sv new file mode 100644 index 0000000..f31e45f --- /dev/null +++ b/repo/single_cycle_design/rtl/pcsrc_unit.sv @@ -0,0 +1,35 @@ +module pcsrc_unit ( + input logic [1:0] Jump, + input logic Branch, + input logic Zero, + input logic [2:0] BranchType, + output logic [1:0] PCSrc // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) +); + + always_comb begin + // default + PCSrc = 2'b00; + + // handle jumps first + case (Jump) + default: PCSrc = 2'b00; + 2'b01: PCSrc = 2'b01; // JAL + 2'b10: PCSrc = 2'b10; // JALR + 2'b00: begin + // if jump==00 then check branches + if (Branch) begin + case (BranchType) + 3'b000: PCSrc = Zero ? 2'b01 : 2'b00; // BEQ + 3'b001: PCSrc = ~Zero ? 2'b01 : 2'b00; // BNE + 3'b100: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLT + 3'b101: PCSrc = Zero ? 2'b01 : 2'b00; // BGE + 3'b110: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLTU + 3'b111: PCSrc = Zero ? 2'b01 : 2'b00; // BGEU + default: PCSrc = 2'b00; + endcase + end + end + endcase + end + +endmodule diff --git a/repo/single_cycle_design/rtl/reg_file.sv b/repo/single_cycle_design/rtl/reg_file.sv new file mode 100644 index 0000000..084e03f --- /dev/null +++ b/repo/single_cycle_design/rtl/reg_file.sv @@ -0,0 +1,31 @@ +module reg_file #( + parameter ADDRESS_WIDTH = 5, // 32 registers + DATA_WIDTH = 32 // 32-bits +)( + input logic clk, // clock + input logic [ADDRESS_WIDTH-1:0] AD3, // destination register + input logic [ADDRESS_WIDTH-1:0] AD1, // source register 1 address (rs1) + input logic [ADDRESS_WIDTH-1:0] AD2, // source register 2 address (rs2) + input logic [DATA_WIDTH-1:0] WD3, // write data + input logic WE3, // write enable + output logic [DATA_WIDTH-1:0] RD1, // register file output for rs1 + output logic [DATA_WIDTH-1:0] RD2, // register file output for rs2 + output logic [DATA_WIDTH-1:0] a0 // register file output for testbenches + +); + + // 32 32-bit registers + logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; + + // write operation (synchronous) -> writes occur only if WE3 is asserted + always_ff @(posedge clk) begin + if (WE3 == 1'b1 && AD3 != 0) + ram_array[AD3] <= WD3; + end + + // read operations (combinational) -> outputs change immediately when read_addr changes + assign RD1 = ram_array[AD1]; + assign RD2 = ram_array[AD2]; + assign a0 = ram_array[5'b01010]; + +endmodule diff --git a/repo/single_cycle_design/rtl/signext.sv b/repo/single_cycle_design/rtl/signext.sv new file mode 100644 index 0000000..d2c6ae2 --- /dev/null +++ b/repo/single_cycle_design/rtl/signext.sv @@ -0,0 +1,17 @@ +module signext ( + input logic [31:7] Imm, + input logic [2:0] ImmSrc, + output logic [31:0] ImmExt +); + + always_comb begin + case (ImmSrc) + 3'b000: ImmExt = {{20{Imm[31]}}, Imm[31:20]}; // I-type + 3'b001: ImmExt = {{20{Imm[31]}}, Imm[31:25], Imm[11:7]}; // S-type + 3'b010: ImmExt = {{20{Imm[31]}}, Imm[7], Imm[30:25], Imm[11:8], 1'b0}; // B-type + 3'b011: ImmExt = {{12{Imm[31]}}, Imm[19:12], Imm[20], Imm[30:21], 1'b0}; // J-type + 3'b100: ImmExt = {Imm[31:12], 12'b0}; // U-type + default: ImmExt = 32'b0; + endcase + end +endmodule diff --git a/repo/single_cycle_design/rtl/top.sv b/repo/single_cycle_design/rtl/top.sv new file mode 100644 index 0000000..efccc5f --- /dev/null +++ b/repo/single_cycle_design/rtl/top.sv @@ -0,0 +1,61 @@ +module top ( + input logic clk, + input logic rst, + /* verilator lint_off UNUSED */ + input logic trigger, + /* verilator lint_on UNUSED */ + output logic [31:0] a0 +); + + // Control signals + logic [1:0] PCSrc; + logic RegWrite; + logic [3:0] ALUControl; + logic ALUSrcA; + logic ALUSrcB; + logic MemWrite; + logic [1:0] ResultSrc; + logic [2:0] ImmSrc; + logic [2:0] AddressingControl; + + // Datapath outputs + logic Zero; + logic [31:0] Instr; + + // Datapath + data_path dp_inst ( + .clk(clk), + .rst(rst), + + .PCSrc(PCSrc), + .RegWrite(RegWrite), + .ALUControl(ALUControl), + .ALUSrcA(ALUSrcA), + .ALUSrcB(ALUSrcB), + .MemWrite(MemWrite), + .ResultSrc(ResultSrc), + .ImmSrc(ImmSrc), + .AddressingControl(AddressingControl), + + .Instr(Instr), + .Zero(Zero), + .a0(a0) + ); + + // Control path + control_path ctrl_inst ( + .Instr(Instr), + .Zero(Zero), + + .PCSrc(PCSrc), + .RegWrite(RegWrite), + .ALUControl(ALUControl), + .ALUSrcA(ALUSrcA), + .ALUSrcB(ALUSrcB), + .MemWrite(MemWrite), + .ResultSrc(ResultSrc), + .ImmSrc(ImmSrc), + .AddressingControl(AddressingControl) + ); + +endmodule From 0a5148af92c4c701b878e07eb57f638639d799b0 Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Fri, 28 Nov 2025 11:32:51 +0000 Subject: [PATCH 59/65] removed folder --- repo/single_cycle_design/rtl/alu.sv | 41 ---- repo/single_cycle_design/rtl/control.sv | 187 ------------------- repo/single_cycle_design/rtl/control_path.sv | 56 ------ repo/single_cycle_design/rtl/data_mem.sv | 51 ----- repo/single_cycle_design/rtl/data_path.sv | 85 --------- repo/single_cycle_design/rtl/instr_mem.sv | 18 -- repo/single_cycle_design/rtl/pc.sv | 48 ----- repo/single_cycle_design/rtl/pcsrc_unit.sv | 35 ---- repo/single_cycle_design/rtl/reg_file.sv | 31 --- repo/single_cycle_design/rtl/signext.sv | 17 -- repo/single_cycle_design/rtl/top.sv | 61 ------ 11 files changed, 630 deletions(-) delete mode 100644 repo/single_cycle_design/rtl/alu.sv delete mode 100644 repo/single_cycle_design/rtl/control.sv delete mode 100644 repo/single_cycle_design/rtl/control_path.sv delete mode 100644 repo/single_cycle_design/rtl/data_mem.sv delete mode 100644 repo/single_cycle_design/rtl/data_path.sv delete mode 100644 repo/single_cycle_design/rtl/instr_mem.sv delete mode 100644 repo/single_cycle_design/rtl/pc.sv delete mode 100644 repo/single_cycle_design/rtl/pcsrc_unit.sv delete mode 100644 repo/single_cycle_design/rtl/reg_file.sv delete mode 100644 repo/single_cycle_design/rtl/signext.sv delete mode 100644 repo/single_cycle_design/rtl/top.sv diff --git a/repo/single_cycle_design/rtl/alu.sv b/repo/single_cycle_design/rtl/alu.sv deleted file mode 100644 index d955b5e..0000000 --- a/repo/single_cycle_design/rtl/alu.sv +++ /dev/null @@ -1,41 +0,0 @@ - // 0000 = ADD - // 0001 = SUB - // 0010 = AND - // 0011 = OR - // 0100 = XOR - // 0101 = SLL - // 0110 = SRL - // 0111 = SRA - // 1000 = SLT (signed) - // 1001 = SLTU (unsigned) - // 1111 = LUI operation - -module alu ( - input logic [31:0] SrcA, - input logic [31:0] SrcB, - input logic [3:0] ALUControl, - output logic [31:0] ALUResult, - output logic Zero -); - - always_comb begin - case (ALUControl) - 4'b0000: ALUResult = SrcA + SrcB; // add - 4'b0001: ALUResult = SrcA - SrcB; // sub - 4'b0010: ALUResult = SrcA & SrcB; // and - 4'b0011: ALUResult = SrcA | SrcB; // or - 4'b0100: ALUResult = SrcA ^ SrcB; // xor - - 4'b0101: ALUResult = SrcA << SrcB[4:0]; // sll - 4'b0110: ALUResult = SrcA >> SrcB[4:0]; // srl - 4'b0111: ALUResult = $signed(SrcA) >>> SrcB[4:0]; // sra - 4'b1000: ALUResult = ($signed(SrcA) < $signed(SrcB)) ? 32'b1 : 32'b0; //slt - 4'b1001: ALUResult = (SrcA < SrcB) ? 32'b1 : 32'b0; //sltu - 4'b1111: ALUResult = SrcB; // LUI operation (Load Upper Immediate) - - default: ALUResult = 32'b0; - endcase - - Zero = 1'b0; - end -endmodule diff --git a/repo/single_cycle_design/rtl/control.sv b/repo/single_cycle_design/rtl/control.sv deleted file mode 100644 index b9d60ee..0000000 --- a/repo/single_cycle_design/rtl/control.sv +++ /dev/null @@ -1,187 +0,0 @@ -module control( - input logic [6:0] opcode, - input logic [2:0] funct3, - input logic [6:0] funct7, - - output logic RegWrite, // enable write to register - output logic [3:0] ALUControl, // control operation in ALU - output logic ALUSrcA, // choose PC (1) or register (0) for ALU operand A - output logic ALUSrcB, // choose immediate (1) or register (0) operand - output logic MemWrite, // enable write into the data memory - // output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) - output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4) - output logic Branch, - output logic [2:0] BranchType, - output logic [1:0] Jump, // indicates jump instruction (00 = no jump, 01 = JAL, 10 = JALR) - output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) - output logic [2:0] AddressingControl // choose which type of load/store instruction to perform -); - - // logic [6:0] opcode; - // logic [2:0] funct3; - // logic [6:0] funct7; - - // assign opcode = Instr[6:0]; - // assign funct3 = Instr[14:12]; - // assign funct7 = Instr[31:25]; - // assign AddressingControl = funct3; // store width - - always_comb begin - // Default values to prevent latches - RegWrite = 1'b0; - ALUControl = 4'b0000; - ALUSrcA = 1'b0; - ALUSrcB = 1'b0; - MemWrite = 1'b0; - ResultSrc = 2'b00; - Branch = 1'b0; - BranchType = 3'b000; - Jump = 2'b00; - ImmSrc = 3'b000; - AddressingControl = 3'b000; - - - case(opcode) - // R-type instructions - 7'b0110011: begin - RegWrite = 1'b1; - ALUSrcB = 1'b0; - - case(funct3) - 3'b000: begin - case(funct7) - 7'b0000000: ALUControl = 4'b0000; // add - 7'b0100000: ALUControl = 4'b0001; // sub - default: ALUControl = 4'b0000; - endcase - end - 3'b001: ALUControl = 4'b0101; // sll - 3'b010: ALUControl = 4'b1000; // slt - 3'b011: ALUControl = 4'b1001; // sltu - 3'b100: ALUControl = 4'b0100; // xor - 3'b101: begin - case(funct7) - 7'b0000000: ALUControl = 4'b0110; // srl - 7'b0100000: ALUControl = 4'b0111; // sra - default: ALUControl = 4'b0110; - endcase - end - 3'b110: ALUControl = 4'b0011; // or - 3'b111: ALUControl = 4'b0010; // and - - default: ALUControl = 4'b0000; - endcase - end - - // I-type instructions (Arithmetic/Logic) - 7'b0010011: begin - RegWrite = 1'b1; - ImmSrc = 3'b000; // I-type imm - ALUSrcB = 1'b1; - - case(funct3) - 3'b000: ALUControl = 4'b0000; // addi - 3'b001: ALUControl = 4'b0101; // slli - 3'b010: ALUControl = 4'b1000; // slti (Added) - 3'b011: ALUControl = 4'b1001; // sltiu (Added) - 3'b100: ALUControl = 4'b0100; // xori - 3'b101: begin - case(funct7) - 7'b0000000: ALUControl = 4'b0110; // srli - 7'b0100000: ALUControl = 4'b0111; // srai - default: ALUControl = 4'b0110; - endcase - end - 3'b110: ALUControl = 4'b0011; // ori - 3'b111: ALUControl = 4'b0010; // andi - default: ALUControl = 4'b0000; - endcase - end - - // I-type Load instructions - 7'b0000011: begin - RegWrite = 1'b1; - ALUSrcB = 1'b1; // SrcB = imm - ResultSrc = 2'b01; // From Memory - ImmSrc = 3'b000; // I-type imm - AddressingControl = funct3; - ALUControl = 4'b0000; // Add for address - end - - // S-type Store instructions - 7'b0100011: begin - MemWrite = 1'b1; - ALUSrcB = 1'b1; // read from immediate - ImmSrc = 3'b001; // S-type immediate - ALUControl = 4'b0000; // Add for address - AddressingControl = funct3; - end - - // B-type Branch instructions - 7'b1100011: begin - Branch = 1'b1; - ImmSrc = 3'b010; // B-type imm - BranchType = funct3; - - case(funct3) - // BEQ, BNE: ALU does SUB (0001) - // If A == B, Result = 0, Zero = 1 - 3'b000: ALUControl = 4'b0001; // beq - 3'b001: ALUControl = 4'b0001; // bne - - // BLT, BGE: ALU does SLT (1000) - // If A < B: Result = 1, Zero = 0. If A >= B: Result = 0, Zero = 1. - 3'b100: ALUControl = 4'b1000; // blt - 3'b101: ALUControl = 4'b1000; // bge - - // BLTU, BGEU: ALU does SLTU (1001) - 3'b110: ALUControl = 4'b1001; // bltu - 3'b111: ALUControl = 4'b1001; // bgeu - default: ALUControl = 4'b0000; - - endcase - end - - // J-type JAL - 7'b1101111: begin - RegWrite = 1'b1; - ResultSrc = 2'b10; // PC+4 - ImmSrc = 3'b011; // J-type imm - Jump = 2'b01; - end - - // I-type JALR - 7'b1100111: begin - RegWrite = 1'b1; - ALUSrcB = 1'b1; // SrcB = imm - ResultSrc = 2'b10; // PC+4 - ImmSrc = 3'b000; // I-type imm - Jump = 2'b10; - // ALUControl = 4'b0000; // Add for target address - end - - // U-type LUI - 7'b0110111: begin - RegWrite = 1'b1; - ALUSrcB = 1'b1; - ResultSrc = 2'b00; - ImmSrc = 3'b100; // U-type imm - ALUControl = 4'b1111; // LUI operation (0 + imm shifted) - end - - // U-type AUIPC rd <- PC + imm << 12 - 7'b0010111: begin - RegWrite = 1'b1; - MemWrite = 1'b0; - ALUSrcA = 1'b1; // Select PC - ALUSrcB = 1'b1; // Select Imm - ImmSrc = 3'b100; // U-type imm - ALUControl = 4'b000; // AUIPC operation (PC + imm shifted) - end - - default: begin - // Already handled by defaults at top - end - endcase - end -endmodule diff --git a/repo/single_cycle_design/rtl/control_path.sv b/repo/single_cycle_design/rtl/control_path.sv deleted file mode 100644 index a419210..0000000 --- a/repo/single_cycle_design/rtl/control_path.sv +++ /dev/null @@ -1,56 +0,0 @@ -module control_path( - /* verilator lint_off UNUSED */ - input logic [31:0] Instr, - /* verilator lint_on UNUSED */ - input logic Zero, - - output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) - output logic RegWrite, // enable write to register - output logic [3:0] ALUControl, // control operation in ALU - output logic ALUSrcA, // choose PC (1) or register (0) for ALU operand A - output logic ALUSrcB, // choose immediate (1) or register (0) operand - output logic MemWrite, // enable write into the data memory - // output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) - output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4) - output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100) - output logic [2:0] AddressingControl // choose which type of load/store instruction to perform -); - - logic Branch; - logic [2:0] BranchType; - logic [1:0] Jump; - - logic [6:0] opcode; - logic [2:0] funct3; - logic [6:0] funct7; - - assign opcode = Instr[6:0]; - assign funct3 = Instr[14:12]; - assign funct7 = Instr[31:25]; - - control control_unit ( - .opcode(opcode), - .funct3(funct3), - .funct7(funct7), - .RegWrite(RegWrite), - .ALUControl(ALUControl), - .ALUSrcA(ALUSrcA), - .ALUSrcB(ALUSrcB), - .MemWrite(MemWrite), - .ResultSrc(ResultSrc), - .Branch(Branch), - .BranchType(BranchType), - .Jump(Jump), - .ImmSrc(ImmSrc), - .AddressingControl(AddressingControl) - ); - - pcsrc_unit pcsrc_unit_inst ( - .Jump(Jump), - .Branch(Branch), - .Zero(Zero), - .BranchType(BranchType), - .PCSrc(PCSrc) - ); - -endmodule diff --git a/repo/single_cycle_design/rtl/data_mem.sv b/repo/single_cycle_design/rtl/data_mem.sv deleted file mode 100644 index 8c5ec7d..0000000 --- a/repo/single_cycle_design/rtl/data_mem.sv +++ /dev/null @@ -1,51 +0,0 @@ -module data_mem #( - parameter XLEN = 32, - parameter ADDRESS_WIDTH = 16, - parameter DATA_WIDTH = 8 -) ( - input logic clk, - input logic WE, // write enable - /* verilator lint_off UNUSED */ - input logic [XLEN-1:0] A, // memory address - /* verilator lint_on UNUSED */ - input logic [XLEN-1:0] WD, // data to write - input logic [2:0] AddressingControl, // funct3 to determine load/store type - output logic [XLEN-1:0] RD // data read -); - logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; // 64KB data memory - - logic [ADDRESS_WIDTH-1:0] addr; - assign addr = A[ADDRESS_WIDTH-1:0]; // use lower ADDRESS_WIDTH bits of address - - always_ff @(posedge clk) begin - if (WE) begin - case (AddressingControl) - 3'b000: ram_array[addr] <= WD[7:0]; // SB - 3'b001: begin // SH - ram_array[addr] <= WD[7:0]; - ram_array[addr+1] <= WD[15:8]; - end - 3'b010: begin // SW - ram_array[addr] <= WD[7:0]; - ram_array[addr+1] <= WD[15:8]; - ram_array[addr+2] <= WD[23:16]; - ram_array[addr+3] <= WD[31:24]; - end - default: ; // ignore other funct3 - endcase - end - end - - always_comb begin - case (AddressingControl) - 3'b000: RD = {{24{ram_array[addr][7]}}, ram_array[addr]}; // LB (signed) - 3'b001: RD = {{16{ram_array[addr+1][7]}}, ram_array[addr+1], ram_array[addr]}; // LH (signed) - 3'b010: RD = {ram_array[addr+3], ram_array[addr+2], ram_array[addr+1], ram_array[addr]}; // LW - 3'b100: RD = {24'b0, ram_array[addr]}; // LBU - 3'b101: RD = {16'b0, ram_array[addr+1], ram_array[addr]}; // LHU - default: RD = 32'b0; - endcase - end - - -endmodule diff --git a/repo/single_cycle_design/rtl/data_path.sv b/repo/single_cycle_design/rtl/data_path.sv deleted file mode 100644 index 5f89c15..0000000 --- a/repo/single_cycle_design/rtl/data_path.sv +++ /dev/null @@ -1,85 +0,0 @@ -module data_path ( - input logic clk, - input logic rst, - - input logic [1:0] PCSrc, - input logic RegWrite, - input logic [3:0] ALUControl, - input logic ALUSrcA, - input logic ALUSrcB, - input logic MemWrite, - input logic [1:0] ResultSrc, - input logic [2:0] ImmSrc, - input logic [2:0] AddressingControl, - - output logic [31:0] Instr, - output logic Zero, - output logic [31:0] a0 -); - - logic [31:0] PC, PCPlus4, ImmExt, MemData, ALUResult, SrcA, SrcB, ReadData1, ReadData2, ResultData; - - assign SrcA = ALUSrcA ? PC : ReadData1; - assign SrcB = ALUSrcB ? ImmExt : ReadData2; - - pc pc_inst( - .clk(clk), - .rst(rst), - .PCSrc(PCSrc), - .ImmExt(ImmExt), - .ALUResult(ALUResult), - .PCPlus4(PCPlus4), - .PC(PC) - ); - - alu alu_inst( - .SrcA(SrcA), - .SrcB(SrcB), - .ALUControl(ALUControl), - .ALUResult(ALUResult), - .Zero(Zero) - ); - - instr_mem instr_mem_inst( - .A(PC), - .RD(Instr) - ); - - data_mem data_mem_inst( - .clk(clk), - .WE(MemWrite), - .A(ALUResult), - .WD(ReadData2), - .AddressingControl(AddressingControl), - .RD(MemData) - ); - - reg_file reg_file_inst( - .clk(clk), - .AD1(Instr[19:15]), - .AD2(Instr[24:20]), - .AD3(Instr[11:7]), - .WD3(ResultData), - .WE3(RegWrite), - .RD1(ReadData1), - .RD2(ReadData2), - .a0(a0) - ); - - signext signext_inst( - .Imm(Instr[31:7]), - .ImmSrc(ImmSrc), - .ImmExt(ImmExt) - ); - - always_comb begin - case (ResultSrc) - 2'b00: ResultData = ALUResult; - 2'b01: ResultData = MemData; - 2'b10: ResultData = PCPlus4; - default: ResultData = 32'b0; - endcase - end - - -endmodule diff --git a/repo/single_cycle_design/rtl/instr_mem.sv b/repo/single_cycle_design/rtl/instr_mem.sv deleted file mode 100644 index 54dbf7a..0000000 --- a/repo/single_cycle_design/rtl/instr_mem.sv +++ /dev/null @@ -1,18 +0,0 @@ -module instr_mem ( - /* verilator lint_off UNUSED */ - input logic [31:0] A, - output logic [31:0] RD - /* verilator lint_on UNUSED */ -); - - // instruction memory array: 256 instructions, each 32 bits wide - logic [31:0] rom_array [0:255]; - - // preload instructions from an external hex file at simulation start - initial begin - $readmemh("../rtl/program.hex", rom_array); - end - - // output the instruction corresponding to the PC address - assign RD = rom_array[A[9:2]]; -endmodule diff --git a/repo/single_cycle_design/rtl/pc.sv b/repo/single_cycle_design/rtl/pc.sv deleted file mode 100644 index d08c272..0000000 --- a/repo/single_cycle_design/rtl/pc.sv +++ /dev/null @@ -1,48 +0,0 @@ -module pc #( - parameter WIDTH = 32 -)( - input logic clk, // system clock - input logic rst, // asynchronous reset - input logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) - input logic [WIDTH-1:0] ImmExt, // immediate offset for branch target - - /* verilator lint_off UNUSED */ - - input logic [WIDTH-1:0] ALUResult, - - /* verilator lint_on UNUSED */ - output logic [WIDTH-1:0] PCPlus4, // PC + 4 - output logic [WIDTH-1:0] PC // current program counter -); - -// next PC after the mux -logic [WIDTH-1:0] PCNext; - -logic [WIDTH-1:0] PCTarget; - - -always_comb begin - PCPlus4 = PC + 4; - PCTarget = PC + ImmExt; - - case(PCSrc) - 2'b00: PCNext = PCPlus4; - 2'b01: PCNext = PCTarget; - - 2'b10: PCNext = {ALUResult[31:2], 2'b00}; // word addressed << 2 - - default: PCNext = PCPlus4; - endcase -end - - - -// program counter register with asynchronous reset -always_ff @(posedge clk or posedge rst) begin - if (rst) - PC <= {WIDTH{1'b0}}; // Reset PC to 0 - else - PC <= PCNext; // Update PC normally -end - -endmodule diff --git a/repo/single_cycle_design/rtl/pcsrc_unit.sv b/repo/single_cycle_design/rtl/pcsrc_unit.sv deleted file mode 100644 index f31e45f..0000000 --- a/repo/single_cycle_design/rtl/pcsrc_unit.sv +++ /dev/null @@ -1,35 +0,0 @@ -module pcsrc_unit ( - input logic [1:0] Jump, - input logic Branch, - input logic Zero, - input logic [2:0] BranchType, - output logic [1:0] PCSrc // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr)) -); - - always_comb begin - // default - PCSrc = 2'b00; - - // handle jumps first - case (Jump) - default: PCSrc = 2'b00; - 2'b01: PCSrc = 2'b01; // JAL - 2'b10: PCSrc = 2'b10; // JALR - 2'b00: begin - // if jump==00 then check branches - if (Branch) begin - case (BranchType) - 3'b000: PCSrc = Zero ? 2'b01 : 2'b00; // BEQ - 3'b001: PCSrc = ~Zero ? 2'b01 : 2'b00; // BNE - 3'b100: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLT - 3'b101: PCSrc = Zero ? 2'b01 : 2'b00; // BGE - 3'b110: PCSrc = ~Zero ? 2'b01 : 2'b00; // BLTU - 3'b111: PCSrc = Zero ? 2'b01 : 2'b00; // BGEU - default: PCSrc = 2'b00; - endcase - end - end - endcase - end - -endmodule diff --git a/repo/single_cycle_design/rtl/reg_file.sv b/repo/single_cycle_design/rtl/reg_file.sv deleted file mode 100644 index 084e03f..0000000 --- a/repo/single_cycle_design/rtl/reg_file.sv +++ /dev/null @@ -1,31 +0,0 @@ -module reg_file #( - parameter ADDRESS_WIDTH = 5, // 32 registers - DATA_WIDTH = 32 // 32-bits -)( - input logic clk, // clock - input logic [ADDRESS_WIDTH-1:0] AD3, // destination register - input logic [ADDRESS_WIDTH-1:0] AD1, // source register 1 address (rs1) - input logic [ADDRESS_WIDTH-1:0] AD2, // source register 2 address (rs2) - input logic [DATA_WIDTH-1:0] WD3, // write data - input logic WE3, // write enable - output logic [DATA_WIDTH-1:0] RD1, // register file output for rs1 - output logic [DATA_WIDTH-1:0] RD2, // register file output for rs2 - output logic [DATA_WIDTH-1:0] a0 // register file output for testbenches - -); - - // 32 32-bit registers - logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; - - // write operation (synchronous) -> writes occur only if WE3 is asserted - always_ff @(posedge clk) begin - if (WE3 == 1'b1 && AD3 != 0) - ram_array[AD3] <= WD3; - end - - // read operations (combinational) -> outputs change immediately when read_addr changes - assign RD1 = ram_array[AD1]; - assign RD2 = ram_array[AD2]; - assign a0 = ram_array[5'b01010]; - -endmodule diff --git a/repo/single_cycle_design/rtl/signext.sv b/repo/single_cycle_design/rtl/signext.sv deleted file mode 100644 index d2c6ae2..0000000 --- a/repo/single_cycle_design/rtl/signext.sv +++ /dev/null @@ -1,17 +0,0 @@ -module signext ( - input logic [31:7] Imm, - input logic [2:0] ImmSrc, - output logic [31:0] ImmExt -); - - always_comb begin - case (ImmSrc) - 3'b000: ImmExt = {{20{Imm[31]}}, Imm[31:20]}; // I-type - 3'b001: ImmExt = {{20{Imm[31]}}, Imm[31:25], Imm[11:7]}; // S-type - 3'b010: ImmExt = {{20{Imm[31]}}, Imm[7], Imm[30:25], Imm[11:8], 1'b0}; // B-type - 3'b011: ImmExt = {{12{Imm[31]}}, Imm[19:12], Imm[20], Imm[30:21], 1'b0}; // J-type - 3'b100: ImmExt = {Imm[31:12], 12'b0}; // U-type - default: ImmExt = 32'b0; - endcase - end -endmodule diff --git a/repo/single_cycle_design/rtl/top.sv b/repo/single_cycle_design/rtl/top.sv deleted file mode 100644 index efccc5f..0000000 --- a/repo/single_cycle_design/rtl/top.sv +++ /dev/null @@ -1,61 +0,0 @@ -module top ( - input logic clk, - input logic rst, - /* verilator lint_off UNUSED */ - input logic trigger, - /* verilator lint_on UNUSED */ - output logic [31:0] a0 -); - - // Control signals - logic [1:0] PCSrc; - logic RegWrite; - logic [3:0] ALUControl; - logic ALUSrcA; - logic ALUSrcB; - logic MemWrite; - logic [1:0] ResultSrc; - logic [2:0] ImmSrc; - logic [2:0] AddressingControl; - - // Datapath outputs - logic Zero; - logic [31:0] Instr; - - // Datapath - data_path dp_inst ( - .clk(clk), - .rst(rst), - - .PCSrc(PCSrc), - .RegWrite(RegWrite), - .ALUControl(ALUControl), - .ALUSrcA(ALUSrcA), - .ALUSrcB(ALUSrcB), - .MemWrite(MemWrite), - .ResultSrc(ResultSrc), - .ImmSrc(ImmSrc), - .AddressingControl(AddressingControl), - - .Instr(Instr), - .Zero(Zero), - .a0(a0) - ); - - // Control path - control_path ctrl_inst ( - .Instr(Instr), - .Zero(Zero), - - .PCSrc(PCSrc), - .RegWrite(RegWrite), - .ALUControl(ALUControl), - .ALUSrcA(ALUSrcA), - .ALUSrcB(ALUSrcB), - .MemWrite(MemWrite), - .ResultSrc(ResultSrc), - .ImmSrc(ImmSrc), - .AddressingControl(AddressingControl) - ); - -endmodule From 53432e95389b8083cb92d185ff742258c842fc26 Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Fri, 28 Nov 2025 11:38:18 +0000 Subject: [PATCH 60/65] trigger removed --- repo/tb/tests/cpu_testbench.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/repo/tb/tests/cpu_testbench.h b/repo/tb/tests/cpu_testbench.h index 4873847..a3ba948 100644 --- a/repo/tb/tests/cpu_testbench.h +++ b/repo/tb/tests/cpu_testbench.h @@ -43,7 +43,7 @@ class CpuTestbench : public ::testing::Test // Initialise inputs top_->clk = 1; top_->rst = 1; - top_->trigger = 0; + // top_->trigger = 0; runSimulation(10); // Process reset top_->rst = 0; } From d5ea9d5d5eed5f4129114f1cd1cded1a0cb445ac Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Fri, 28 Nov 2025 11:46:16 +0000 Subject: [PATCH 61/65] Added all RV32I Instruction tests --- repo/tb/asm/add_test.s | 15 +++++++++++++++ repo/tb/asm/addi_test.s | 14 ++++++++++++++ repo/tb/asm/and_test.s | 15 +++++++++++++++ repo/tb/asm/andi_test.s | 14 ++++++++++++++ repo/tb/asm/auipc_test.s | 16 ++++++++++++++++ repo/tb/asm/beq_test.s | 22 ++++++++++++++++++++++ repo/tb/asm/bge_test.s | 21 +++++++++++++++++++++ repo/tb/asm/bgeu_test.s | 18 ++++++++++++++++++ repo/tb/asm/blt_test.s | 21 +++++++++++++++++++++ repo/tb/asm/bltu_test.s | 21 +++++++++++++++++++++ repo/tb/asm/bne_test.s | 21 +++++++++++++++++++++ repo/tb/asm/jal_test.s | 17 +++++++++++++++++ repo/tb/asm/jalr_test.s | 17 +++++++++++++++++ repo/tb/asm/lb_test.s | 12 ++++++++++++ repo/tb/asm/lbu_test.s | 12 ++++++++++++ repo/tb/asm/lh_test.s | 12 ++++++++++++ repo/tb/asm/lhu_test.s | 12 ++++++++++++ repo/tb/asm/lui_test.s | 6 ++++++ repo/tb/asm/lw_test.s | 12 ++++++++++++ repo/tb/asm/or_test.s | 11 +++++++++++ repo/tb/asm/ori_test.s | 10 ++++++++++ repo/tb/asm/sb_test.s | 12 ++++++++++++ repo/tb/asm/sh_test.s | 12 ++++++++++++ repo/tb/asm/sll_test.s | 11 +++++++++++ repo/tb/asm/slli_test.s | 10 ++++++++++ repo/tb/asm/slt_test.s | 11 +++++++++++ repo/tb/asm/slti_test.s | 10 ++++++++++ repo/tb/asm/sltiu_test.s | 10 ++++++++++ repo/tb/asm/sltu_test.s | 11 +++++++++++ repo/tb/asm/sra_test.s | 11 +++++++++++ repo/tb/asm/srai_test.s | 10 ++++++++++ repo/tb/asm/srl_test.s | 11 +++++++++++ repo/tb/asm/srli_test.s | 10 ++++++++++ repo/tb/asm/sub_test.s | 11 +++++++++++ repo/tb/asm/sw_test.s | 12 ++++++++++++ repo/tb/asm/xor_test.s | 11 +++++++++++ repo/tb/asm/xori_test.s | 11 +++++++++++ 37 files changed, 493 insertions(+) create mode 100644 repo/tb/asm/add_test.s create mode 100644 repo/tb/asm/addi_test.s create mode 100644 repo/tb/asm/and_test.s create mode 100644 repo/tb/asm/andi_test.s create mode 100644 repo/tb/asm/auipc_test.s create mode 100644 repo/tb/asm/beq_test.s create mode 100644 repo/tb/asm/bge_test.s create mode 100644 repo/tb/asm/bgeu_test.s create mode 100644 repo/tb/asm/blt_test.s create mode 100644 repo/tb/asm/bltu_test.s create mode 100644 repo/tb/asm/bne_test.s create mode 100644 repo/tb/asm/jal_test.s create mode 100644 repo/tb/asm/jalr_test.s create mode 100644 repo/tb/asm/lb_test.s create mode 100644 repo/tb/asm/lbu_test.s create mode 100644 repo/tb/asm/lh_test.s create mode 100644 repo/tb/asm/lhu_test.s create mode 100644 repo/tb/asm/lui_test.s create mode 100644 repo/tb/asm/lw_test.s create mode 100644 repo/tb/asm/or_test.s create mode 100644 repo/tb/asm/ori_test.s create mode 100644 repo/tb/asm/sb_test.s create mode 100644 repo/tb/asm/sh_test.s create mode 100644 repo/tb/asm/sll_test.s create mode 100644 repo/tb/asm/slli_test.s create mode 100644 repo/tb/asm/slt_test.s create mode 100644 repo/tb/asm/slti_test.s create mode 100644 repo/tb/asm/sltiu_test.s create mode 100644 repo/tb/asm/sltu_test.s create mode 100644 repo/tb/asm/sra_test.s create mode 100644 repo/tb/asm/srai_test.s create mode 100644 repo/tb/asm/srl_test.s create mode 100644 repo/tb/asm/srli_test.s create mode 100644 repo/tb/asm/sub_test.s create mode 100644 repo/tb/asm/sw_test.s create mode 100644 repo/tb/asm/xor_test.s create mode 100644 repo/tb/asm/xori_test.s diff --git a/repo/tb/asm/add_test.s b/repo/tb/asm/add_test.s new file mode 100644 index 0000000..f27f20a --- /dev/null +++ b/repo/tb/asm/add_test.s @@ -0,0 +1,15 @@ +# Add the two registers and put the result in rd + +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li t0, 5 + li t1, 3 + add a0, t0, t1 # a0 = t0 + t1 + j finish + +# a0 = 8 \ No newline at end of file diff --git a/repo/tb/asm/addi_test.s b/repo/tb/asm/addi_test.s new file mode 100644 index 0000000..1c3bfa7 --- /dev/null +++ b/repo/tb/asm/addi_test.s @@ -0,0 +1,14 @@ +# Add an immediate value to a register and store the result in rd + +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li a0, 5 + addi a0, a0, 3 # a0 = 5 + 3 + j finish + +# a0 = 8 \ No newline at end of file diff --git a/repo/tb/asm/and_test.s b/repo/tb/asm/and_test.s new file mode 100644 index 0000000..4787eff --- /dev/null +++ b/repo/tb/asm/and_test.s @@ -0,0 +1,15 @@ +# Perform bitwise AND of two registers and store the result in rd + +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li t0, 5 # t0 = 5 (binary 0101) + li t1, 3 # t1 = 3 (binary 0011) + and a0, t0, t1 # a0 = t0 & t1 + j finish + +# a0 = 1 \ No newline at end of file diff --git a/repo/tb/asm/andi_test.s b/repo/tb/asm/andi_test.s new file mode 100644 index 0000000..6aa0d93 --- /dev/null +++ b/repo/tb/asm/andi_test.s @@ -0,0 +1,14 @@ +# Perform bitwise AND of a register with an immediate value and store the result in rd + +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li a0, 5 # a0 = 5 (binary 0101) + andi a0, a0, 3 # a0 = a0 & 3 + j finish + +# a0 = 1 \ No newline at end of file diff --git a/repo/tb/asm/auipc_test.s b/repo/tb/asm/auipc_test.s new file mode 100644 index 0000000..ac4415d --- /dev/null +++ b/repo/tb/asm/auipc_test.s @@ -0,0 +1,16 @@ +# Add the upper 20 bits of an immediate to the PC and store the result in rd + +.text +.globl main + +finish: + bne a0, zero, finish # loop forever + +main: + li a0, 1 # wrong output value + auipc t0, %hi(correct) + +.org 8192 +correct: + li a0, 2 # correct output value + j finish diff --git a/repo/tb/asm/beq_test.s b/repo/tb/asm/beq_test.s new file mode 100644 index 0000000..48e71b6 --- /dev/null +++ b/repo/tb/asm/beq_test.s @@ -0,0 +1,22 @@ +# Branch to a label if two registers are equal + +.text +.globl main + +main: + li t0, 5 # Set a0 to 5 + li t1, 5 # Set a1 to 5 (equal to a0) + beq t0, t1, pass # Branch to pass if a0 equals a1 + + j fail # If not equal, jump to fail + +pass: + li a0, 1 # Set a0 to 1 for success + j finish # Loop to check result + +fail: + li a0, 0 # Set a0 to 0 for failure + j finish # Loop to check result + +finish: + j finish # Loop forever \ No newline at end of file diff --git a/repo/tb/asm/bge_test.s b/repo/tb/asm/bge_test.s new file mode 100644 index 0000000..0868535 --- /dev/null +++ b/repo/tb/asm/bge_test.s @@ -0,0 +1,21 @@ +# Branch to a label if the first register is greater than or equal to the second register + +.text +.globl main + +main: + li t0, 5 + li t1, 5 + bge t0, t1, pass + j fail + +pass: + li a0, 1 + j finish + +fail: + li a0, 0 + j finish + +finish: + j finish \ No newline at end of file diff --git a/repo/tb/asm/bgeu_test.s b/repo/tb/asm/bgeu_test.s new file mode 100644 index 0000000..b1424f7 --- /dev/null +++ b/repo/tb/asm/bgeu_test.s @@ -0,0 +1,18 @@ +# Branch to a label if the first register is greater than or equal to the second register (unsigned comparison) + +.text +.globl main + +main: + li t0, 1 # 1 in both signed and unsigned + li t1, 0xFFFFFFFF # -1 in signed, but large in unsigned + bgeu t0, t1, fail # Should not branch because 1 !>= 0xFFFFFFFF in unsigned + li a0, 1 # If we don't branch to fail, it's a success + j finish + +fail: + li a0, 0 + j finish + +finish: + j finish \ No newline at end of file diff --git a/repo/tb/asm/blt_test.s b/repo/tb/asm/blt_test.s new file mode 100644 index 0000000..54fa328 --- /dev/null +++ b/repo/tb/asm/blt_test.s @@ -0,0 +1,21 @@ +# Branch to a label if the first register is less than the second register + +.text +.globl main + +main: + li t0, 3 + li t1, 5 + blt t0, t1, pass + j fail + +pass: + li a0, 1 + j finish + +fail: + li a0, 0 + j finish + +finish: + j finish \ No newline at end of file diff --git a/repo/tb/asm/bltu_test.s b/repo/tb/asm/bltu_test.s new file mode 100644 index 0000000..bc6ee8f --- /dev/null +++ b/repo/tb/asm/bltu_test.s @@ -0,0 +1,21 @@ +# Branch to a label if the first register is less than the second register (unsigned comparison) + +.text +.globl main + +main: + li t0, 0xFFFFFFFF # -1 in signed, but large in unsigned + li t1, 1 # 1 in both signed and unsigned + bltu t0, t1, fail # Should branch because 0xFFFFFFFF < 1 in unsigned comparison + j pass # If we don't branch, we fail the test + +pass: + li a0, 1 # Set to 1 for pass + j finish + +fail: + li a0, 0 # Set to 0 for fail + j finish + +finish: + j finish \ No newline at end of file diff --git a/repo/tb/asm/bne_test.s b/repo/tb/asm/bne_test.s new file mode 100644 index 0000000..42828e8 --- /dev/null +++ b/repo/tb/asm/bne_test.s @@ -0,0 +1,21 @@ +# Branch to a label if two registers are not equal + +.text +.globl main + +main: + li t0, 5 + li t1, 6 + bne t0, t1, pass + j fail + +pass: + li a0, 1 + j finish + +fail: + li a0, 0 + j finish + +finish: + j finish \ No newline at end of file diff --git a/repo/tb/asm/jal_test.s b/repo/tb/asm/jal_test.s new file mode 100644 index 0000000..bf5aad5 --- /dev/null +++ b/repo/tb/asm/jal_test.s @@ -0,0 +1,17 @@ +.text +.globl main + +finish: + bne a0, zero, finish # loop forever (if a0 != 0) + +main: + li a0, 1 # Wrong output value + jal ra, correct # Jump to 'correct' and save return address in 'ra' + + # This line should not be executed if 'correct' is reached + li a0, 99 # Wrong output value + +.org 8192 +correct: + li a0, 2 # Correct output value + j finish \ No newline at end of file diff --git a/repo/tb/asm/jalr_test.s b/repo/tb/asm/jalr_test.s new file mode 100644 index 0000000..55cb901 --- /dev/null +++ b/repo/tb/asm/jalr_test.s @@ -0,0 +1,17 @@ +.text +.globl main + +finish: + bne a0, zero, finish # Loop forever if a0 is not zero + +main: + li a0, 1 # Wrong output value + jal ra, correct # Jump to 'correct' and save return address in 'ra' + + # This line should not be executed if 'correct' is reached + li a0, 99 # Wrong output value + +.org 8192 +correct: + li a0, 2 # Correct output value + j finish \ No newline at end of file diff --git a/repo/tb/asm/lb_test.s b/repo/tb/asm/lb_test.s new file mode 100644 index 0000000..7693f7e --- /dev/null +++ b/repo/tb/asm/lb_test.s @@ -0,0 +1,12 @@ +.text +.globl main + +finish: + bne a0, zero, finish # Loop forever if a0 is not zero + +main: + li t0, 0x7F # 0x7F is the highest positive byte value, no sign extension + sb t0, 1(sp) + + lb a0, 1(sp) + j finish \ No newline at end of file diff --git a/repo/tb/asm/lbu_test.s b/repo/tb/asm/lbu_test.s new file mode 100644 index 0000000..da49ec9 --- /dev/null +++ b/repo/tb/asm/lbu_test.s @@ -0,0 +1,12 @@ +.text +.globl main + +finish: + bne a0, zero, finish # Loop forever if a0 is not zero + +main: + li a0, -1 # -1 is all 1s in binary (0xFF for byte) + sb a0, 0(sp) + + lbu a0, 0(sp) # Load byte unsigned back into a0, zero-extended + j finish \ No newline at end of file diff --git a/repo/tb/asm/lh_test.s b/repo/tb/asm/lh_test.s new file mode 100644 index 0000000..98ac3d7 --- /dev/null +++ b/repo/tb/asm/lh_test.s @@ -0,0 +1,12 @@ +.text +.globl main + +finish: + bne a0, zero, finish # Loop forever if a0 is not zero + +main: + li t0, 0x7FFF # 0x7FFF is the highest positive halfword value, no sign extension + sh t0, 2(sp) + + lh a0, 2(sp) + j finish \ No newline at end of file diff --git a/repo/tb/asm/lhu_test.s b/repo/tb/asm/lhu_test.s new file mode 100644 index 0000000..e1d7902 --- /dev/null +++ b/repo/tb/asm/lhu_test.s @@ -0,0 +1,12 @@ +.text +.globl main + +finish: + bne a0, zero, finish # Loop forever if a0 is not zero + +main: + li a0, -1 # -1 is all 1s in binary (0xFFFF for halfword) + sh a0, 0(sp) + + lhu a0, 0(sp) # Load halfword unsigned back into a0, zero-extended + j finish \ No newline at end of file diff --git a/repo/tb/asm/lui_test.s b/repo/tb/asm/lui_test.s new file mode 100644 index 0000000..ee7803d --- /dev/null +++ b/repo/tb/asm/lui_test.s @@ -0,0 +1,6 @@ +.text +.globl main +main: + lui t0, 0b10101010101010101010 # load top 20 bits + addi t0, t0, -1 # load bottom 12 bits + add a0, zero, t0 # output = 0b10101010101010101010 - 1 \ No newline at end of file diff --git a/repo/tb/asm/lw_test.s b/repo/tb/asm/lw_test.s new file mode 100644 index 0000000..e3b11c1 --- /dev/null +++ b/repo/tb/asm/lw_test.s @@ -0,0 +1,12 @@ +.text +.globl main + +finish: + bne a0, zero, finish # Loop forever if a0 is not zero + +main: + li a0, -1 # -1 is all 1s in binary (0xFFFFFFFF) + sw a0, 0(sp) + + lw a0, 0(sp) + j finish \ No newline at end of file diff --git a/repo/tb/asm/or_test.s b/repo/tb/asm/or_test.s new file mode 100644 index 0000000..35ff141 --- /dev/null +++ b/repo/tb/asm/or_test.s @@ -0,0 +1,11 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li t0, 5 + li t1, 3 + or a0, t0, t1 # a0 = t0 | t1 + j finish \ No newline at end of file diff --git a/repo/tb/asm/ori_test.s b/repo/tb/asm/ori_test.s new file mode 100644 index 0000000..59c99ad --- /dev/null +++ b/repo/tb/asm/ori_test.s @@ -0,0 +1,10 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li a0, 5 + ori a0, a0, 3 # a0 = 5 | 3 + j finish \ No newline at end of file diff --git a/repo/tb/asm/sb_test.s b/repo/tb/asm/sb_test.s new file mode 100644 index 0000000..7ffb56c --- /dev/null +++ b/repo/tb/asm/sb_test.s @@ -0,0 +1,12 @@ +.text +.globl main + +finish: + bne a0, zero, finish # Loop forever if a0 is not zero + +main: + li a0, -1 # -1 is all 1s in binary + sb a0, 0(sp) # Store byte on stack + + lw a0, 0(sp) # Load word to check only lower byte + j finish # Loop to check result \ No newline at end of file diff --git a/repo/tb/asm/sh_test.s b/repo/tb/asm/sh_test.s new file mode 100644 index 0000000..d22d35f --- /dev/null +++ b/repo/tb/asm/sh_test.s @@ -0,0 +1,12 @@ +.text +.globl main + +finish: + bne a0, zero, finish # Loop forever if a0 is not zero + +main: + li a0, -1 # -1 is all 1s in binary + sh a0, 0(sp) # Store halfword on stack + + lw a0, 0(sp) # Load word to check only lower halfword + j finish # Loop to check result \ No newline at end of file diff --git a/repo/tb/asm/sll_test.s b/repo/tb/asm/sll_test.s new file mode 100644 index 0000000..1972b42 --- /dev/null +++ b/repo/tb/asm/sll_test.s @@ -0,0 +1,11 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li t0, 5 + li t1, 2 + sll a0, t0, t1 # a0 = t0 << t1 + j finish \ No newline at end of file diff --git a/repo/tb/asm/slli_test.s b/repo/tb/asm/slli_test.s new file mode 100644 index 0000000..f65a600 --- /dev/null +++ b/repo/tb/asm/slli_test.s @@ -0,0 +1,10 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li a0, 5 + slli a0, a0, 2 # a0 = 5 << 2 + j finish \ No newline at end of file diff --git a/repo/tb/asm/slt_test.s b/repo/tb/asm/slt_test.s new file mode 100644 index 0000000..41649c0 --- /dev/null +++ b/repo/tb/asm/slt_test.s @@ -0,0 +1,11 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li t0, 5 + li t1, 10 + slt a0, t0, t1 # a0 = (t0 < t1) ? 1 : 0 + j finish \ No newline at end of file diff --git a/repo/tb/asm/slti_test.s b/repo/tb/asm/slti_test.s new file mode 100644 index 0000000..2af08d4 --- /dev/null +++ b/repo/tb/asm/slti_test.s @@ -0,0 +1,10 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li a0, 5 + slti a0, a0, 10 # a0 = (5 < 10) ? 1 : 0 + j finish \ No newline at end of file diff --git a/repo/tb/asm/sltiu_test.s b/repo/tb/asm/sltiu_test.s new file mode 100644 index 0000000..9230701 --- /dev/null +++ b/repo/tb/asm/sltiu_test.s @@ -0,0 +1,10 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li a0, 0xFFFFFFFF # -1 in signed, largest unsigned 32-bit number + sltiu a0, a0, 1 # a0 = (0xFFFFFFFF < 1) in unsigned compare ? 1 : 0 + j finish \ No newline at end of file diff --git a/repo/tb/asm/sltu_test.s b/repo/tb/asm/sltu_test.s new file mode 100644 index 0000000..2c3a08c --- /dev/null +++ b/repo/tb/asm/sltu_test.s @@ -0,0 +1,11 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li t0, 0xFFFFFFFF # -1 in signed, largest unsigned 32-bit number + li t1, 1 + sltu a0, t0, t1 # a0 = (t0 < t1) in unsigned compare ? 1 : 0 + j finish \ No newline at end of file diff --git a/repo/tb/asm/sra_test.s b/repo/tb/asm/sra_test.s new file mode 100644 index 0000000..5e214f7 --- /dev/null +++ b/repo/tb/asm/sra_test.s @@ -0,0 +1,11 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li t0, -8 # -8 in binary: 1111...1000 + li t1, 2 + sra a0, t0, t1 # a0 = t0 >> t1 (arithmetic, preserves sign) + j finish \ No newline at end of file diff --git a/repo/tb/asm/srai_test.s b/repo/tb/asm/srai_test.s new file mode 100644 index 0000000..d9e81d0 --- /dev/null +++ b/repo/tb/asm/srai_test.s @@ -0,0 +1,10 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li a0, -8 # -8 in binary: 1111...1000 + srai a0, a0, 2 # a0 = -8 >> 2 (arithmetic, preserves sign) + j finish \ No newline at end of file diff --git a/repo/tb/asm/srl_test.s b/repo/tb/asm/srl_test.s new file mode 100644 index 0000000..915d902 --- /dev/null +++ b/repo/tb/asm/srl_test.s @@ -0,0 +1,11 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li t0, -8 # -8 in binary: 1111...1000 + li t1, 2 + srl a0, t0, t1 # a0 = t0 >> t1 (logical, should not sign extend) + j finish \ No newline at end of file diff --git a/repo/tb/asm/srli_test.s b/repo/tb/asm/srli_test.s new file mode 100644 index 0000000..23ab1f7 --- /dev/null +++ b/repo/tb/asm/srli_test.s @@ -0,0 +1,10 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li a0, -8 # -8 in binary: 1111...1000 (assuming 32-bit) + srli a0, a0, 2 # a0 = -8 >> 2 (logical, should not sign extend) + j finish \ No newline at end of file diff --git a/repo/tb/asm/sub_test.s b/repo/tb/asm/sub_test.s new file mode 100644 index 0000000..d5ed649 --- /dev/null +++ b/repo/tb/asm/sub_test.s @@ -0,0 +1,11 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li t0, 5 + li t1, 3 + sub a0, t0, t1 # a0 = t0 - t1 + j finish \ No newline at end of file diff --git a/repo/tb/asm/sw_test.s b/repo/tb/asm/sw_test.s new file mode 100644 index 0000000..bd6215e --- /dev/null +++ b/repo/tb/asm/sw_test.s @@ -0,0 +1,12 @@ +.text +.globl main + +finish: + bne a0, zero, finish # Loop forever if a0 is not zero + +main: + li a0, -1 # -1 is all 1s + sw a0, 0(sp) # Store word + + lw a0, 0(sp) # Load word + j finish # Loop to check result \ No newline at end of file diff --git a/repo/tb/asm/xor_test.s b/repo/tb/asm/xor_test.s new file mode 100644 index 0000000..755ed1c --- /dev/null +++ b/repo/tb/asm/xor_test.s @@ -0,0 +1,11 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li t0, 5 + li t1, 3 + xor a0, t0, t1 # a0 = t0 ^ t1 + j finish \ No newline at end of file diff --git a/repo/tb/asm/xori_test.s b/repo/tb/asm/xori_test.s new file mode 100644 index 0000000..3c4accb --- /dev/null +++ b/repo/tb/asm/xori_test.s @@ -0,0 +1,11 @@ +.text +.globl main + +finish: + bne a0, zero, finish + +main: + li a0, 5 + xori a0, a0, 3 # a0 = 5 ^ 3 + j finish + \ No newline at end of file From 7d33dd6bd4a51c0ad29038eaf1d37fb9579a2b1b Mon Sep 17 00:00:00 2001 From: Preet Harquissandas Date: Fri, 28 Nov 2025 12:21:52 +0000 Subject: [PATCH 62/65] Completed the verify.cpp and testbench for each instruction --- repo/tb/asm/jal_test.s | 2 + repo/tb/asm/jalr_test.s | 2 + repo/tb/asm/lb_test.s | 2 + repo/tb/asm/lbu_test.s | 2 + repo/tb/asm/lh_test.s | 2 + repo/tb/asm/lhu_test.s | 2 + repo/tb/asm/lui_test.s | 2 + repo/tb/asm/lw_test.s | 2 + repo/tb/asm/or_test.s | 2 + repo/tb/asm/ori_test.s | 2 + repo/tb/asm/sb_test.s | 2 + repo/tb/asm/sh_test.s | 2 + repo/tb/asm/sll_test.s | 2 + repo/tb/asm/slli_test.s | 2 + repo/tb/asm/slt_test.s | 2 + repo/tb/asm/slti_test.s | 2 + repo/tb/asm/sltiu_test.s | 2 + repo/tb/asm/sltu_test.s | 2 + repo/tb/asm/sra_test.s | 2 + repo/tb/asm/srai_test.s | 2 + repo/tb/asm/srl_test.s | 2 + repo/tb/asm/srli_test.s | 2 + repo/tb/asm/sub_test.s | 2 + repo/tb/asm/sw_test.s | 2 + repo/tb/asm/xor_test.s | 2 + repo/tb/asm/xori_test.s | 2 + repo/tb/tests/verify.cpp | 267 +++++++++++++++++++++++++++++++++++++++ 27 files changed, 319 insertions(+) diff --git a/repo/tb/asm/jal_test.s b/repo/tb/asm/jal_test.s index bf5aad5..8210b72 100644 --- a/repo/tb/asm/jal_test.s +++ b/repo/tb/asm/jal_test.s @@ -1,3 +1,5 @@ +# Jump to a label and store the return address in rd (used for function calls) + .text .globl main diff --git a/repo/tb/asm/jalr_test.s b/repo/tb/asm/jalr_test.s index 55cb901..f88592a 100644 --- a/repo/tb/asm/jalr_test.s +++ b/repo/tb/asm/jalr_test.s @@ -1,3 +1,5 @@ +# Jump to an address in a register and store the return address in rd (used for indirect function calls) + .text .globl main diff --git a/repo/tb/asm/lb_test.s b/repo/tb/asm/lb_test.s index 7693f7e..7573815 100644 --- a/repo/tb/asm/lb_test.s +++ b/repo/tb/asm/lb_test.s @@ -1,3 +1,5 @@ +# Load a byte from memory into a register and sign-extend it to 32 bits + .text .globl main diff --git a/repo/tb/asm/lbu_test.s b/repo/tb/asm/lbu_test.s index da49ec9..8c4280e 100644 --- a/repo/tb/asm/lbu_test.s +++ b/repo/tb/asm/lbu_test.s @@ -1,3 +1,5 @@ +# Load a byte from memory into a register and zero-extend it to 32 bits + .text .globl main diff --git a/repo/tb/asm/lh_test.s b/repo/tb/asm/lh_test.s index 98ac3d7..895832a 100644 --- a/repo/tb/asm/lh_test.s +++ b/repo/tb/asm/lh_test.s @@ -1,3 +1,5 @@ +# Load a 16-bit halfword from memory into a register and sign-extend it to 32 bits + .text .globl main diff --git a/repo/tb/asm/lhu_test.s b/repo/tb/asm/lhu_test.s index e1d7902..d864ed3 100644 --- a/repo/tb/asm/lhu_test.s +++ b/repo/tb/asm/lhu_test.s @@ -1,3 +1,5 @@ +# Load a 16-bit halfword from memory into a register and zero-extend it to 32 bits + .text .globl main diff --git a/repo/tb/asm/lui_test.s b/repo/tb/asm/lui_test.s index ee7803d..2629ce1 100644 --- a/repo/tb/asm/lui_test.s +++ b/repo/tb/asm/lui_test.s @@ -1,3 +1,5 @@ +# Load a 20-bit immediate into the upper 20 bits of a register, setting the lower 12 bits to zero + .text .globl main main: diff --git a/repo/tb/asm/lw_test.s b/repo/tb/asm/lw_test.s index e3b11c1..aca16a0 100644 --- a/repo/tb/asm/lw_test.s +++ b/repo/tb/asm/lw_test.s @@ -1,3 +1,5 @@ +# Load a 32-bit word from memory into a register + .text .globl main diff --git a/repo/tb/asm/or_test.s b/repo/tb/asm/or_test.s index 35ff141..40d38c6 100644 --- a/repo/tb/asm/or_test.s +++ b/repo/tb/asm/or_test.s @@ -1,3 +1,5 @@ +# Perform bitwise OR of two registers and store the result in rd + .text .globl main diff --git a/repo/tb/asm/ori_test.s b/repo/tb/asm/ori_test.s index 59c99ad..6899f16 100644 --- a/repo/tb/asm/ori_test.s +++ b/repo/tb/asm/ori_test.s @@ -1,3 +1,5 @@ +# Perform bitwise OR of a register with an immediate value and store the result in rd + .text .globl main diff --git a/repo/tb/asm/sb_test.s b/repo/tb/asm/sb_test.s index 7ffb56c..9bc2f29 100644 --- a/repo/tb/asm/sb_test.s +++ b/repo/tb/asm/sb_test.s @@ -1,3 +1,5 @@ +# Store the least significant byte of a register into memory + .text .globl main diff --git a/repo/tb/asm/sh_test.s b/repo/tb/asm/sh_test.s index d22d35f..963f28c 100644 --- a/repo/tb/asm/sh_test.s +++ b/repo/tb/asm/sh_test.s @@ -1,3 +1,5 @@ +# Store the least significant 16 bits (halfword) of a register into memory + .text .globl main diff --git a/repo/tb/asm/sll_test.s b/repo/tb/asm/sll_test.s index 1972b42..2a69231 100644 --- a/repo/tb/asm/sll_test.s +++ b/repo/tb/asm/sll_test.s @@ -1,3 +1,5 @@ +# Shift the bits in a register left by a specified amount and store the result in rd + .text .globl main diff --git a/repo/tb/asm/slli_test.s b/repo/tb/asm/slli_test.s index f65a600..302b79f 100644 --- a/repo/tb/asm/slli_test.s +++ b/repo/tb/asm/slli_test.s @@ -1,3 +1,5 @@ +# Shift the bits in a register left by an immediate value and store the result in rd + .text .globl main diff --git a/repo/tb/asm/slt_test.s b/repo/tb/asm/slt_test.s index 41649c0..316579a 100644 --- a/repo/tb/asm/slt_test.s +++ b/repo/tb/asm/slt_test.s @@ -1,3 +1,5 @@ +# Set rd to 1 if the first register is less than the second register (signed comparison), otherwise set rd to 0 + .text .globl main diff --git a/repo/tb/asm/slti_test.s b/repo/tb/asm/slti_test.s index 2af08d4..1bd407c 100644 --- a/repo/tb/asm/slti_test.s +++ b/repo/tb/asm/slti_test.s @@ -1,3 +1,5 @@ +# Set rd to 1 if the register is less than an immediate value (signed comparison), otherwise set rd to 0 + .text .globl main diff --git a/repo/tb/asm/sltiu_test.s b/repo/tb/asm/sltiu_test.s index 9230701..128896e 100644 --- a/repo/tb/asm/sltiu_test.s +++ b/repo/tb/asm/sltiu_test.s @@ -1,3 +1,5 @@ +# Set rd to 1 if the register is less than an immediate value (unsigned comparison), otherwise set rd to 0 + .text .globl main diff --git a/repo/tb/asm/sltu_test.s b/repo/tb/asm/sltu_test.s index 2c3a08c..bbf7099 100644 --- a/repo/tb/asm/sltu_test.s +++ b/repo/tb/asm/sltu_test.s @@ -1,3 +1,5 @@ +# Set rd to 1 if the first register is less than the second register (unsigned comparison), otherwise set rd to 0 + .text .globl main diff --git a/repo/tb/asm/sra_test.s b/repo/tb/asm/sra_test.s index 5e214f7..8703b2a 100644 --- a/repo/tb/asm/sra_test.s +++ b/repo/tb/asm/sra_test.s @@ -1,3 +1,5 @@ +# Shift the bits in a register right arithmetically (preserving the sign) and store the result in rd + .text .globl main diff --git a/repo/tb/asm/srai_test.s b/repo/tb/asm/srai_test.s index d9e81d0..cca023d 100644 --- a/repo/tb/asm/srai_test.s +++ b/repo/tb/asm/srai_test.s @@ -1,3 +1,5 @@ +# Shift the bits in a register right arithmetically by an immediate value (preserving the sign) and store the result in rd + .text .globl main diff --git a/repo/tb/asm/srl_test.s b/repo/tb/asm/srl_test.s index 915d902..aa82b13 100644 --- a/repo/tb/asm/srl_test.s +++ b/repo/tb/asm/srl_test.s @@ -1,3 +1,5 @@ +# Shift the bits in a register right logically (fill with zeros) and store the result in rd + .text .globl main diff --git a/repo/tb/asm/srli_test.s b/repo/tb/asm/srli_test.s index 23ab1f7..75f2357 100644 --- a/repo/tb/asm/srli_test.s +++ b/repo/tb/asm/srli_test.s @@ -1,3 +1,5 @@ +# Shift the bits in a register right logically by an immediate value (fill with zeros) and store the result in rd + .text .globl main diff --git a/repo/tb/asm/sub_test.s b/repo/tb/asm/sub_test.s index d5ed649..ebc81eb 100644 --- a/repo/tb/asm/sub_test.s +++ b/repo/tb/asm/sub_test.s @@ -1,3 +1,5 @@ +# Subtract the second register from the first register and store the result in rd + .text .globl main diff --git a/repo/tb/asm/sw_test.s b/repo/tb/asm/sw_test.s index bd6215e..caa4e77 100644 --- a/repo/tb/asm/sw_test.s +++ b/repo/tb/asm/sw_test.s @@ -1,3 +1,5 @@ +# Store a 32-bit word from a register into memory + .text .globl main diff --git a/repo/tb/asm/xor_test.s b/repo/tb/asm/xor_test.s index 755ed1c..064878f 100644 --- a/repo/tb/asm/xor_test.s +++ b/repo/tb/asm/xor_test.s @@ -1,3 +1,5 @@ +# Perform bitwise XOR of two registers and store the result in rd + .text .globl main diff --git a/repo/tb/asm/xori_test.s b/repo/tb/asm/xori_test.s index 3c4accb..e4ca50a 100644 --- a/repo/tb/asm/xori_test.s +++ b/repo/tb/asm/xori_test.s @@ -1,3 +1,5 @@ +# Perform bitwise XOR of a register with an immediate value and store the result in rd + .text .globl main diff --git a/repo/tb/tests/verify.cpp b/repo/tb/tests/verify.cpp index ba210ae..78e2323 100644 --- a/repo/tb/tests/verify.cpp +++ b/repo/tb/tests/verify.cpp @@ -46,6 +46,273 @@ TEST_F(CpuTestbench, TestPdf) EXPECT_EQ(top_->a0, 15363); } +/* Instruction Coverage */ + +// Upper and Jump/Link Instructions +TEST_F(CpuTestbench, TestLUI){ + setupTest("lui_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, (0b1010'1010'1010'1010'1010'0000'0000'0000) - 1); +} + +TEST_F(CpuTestbench, TestAUIPC){ + setupTest("auipc_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 2); +} + +TEST_F(CpuTestbench, TestJAL){ + setupTest("jal_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 2); +} + +TEST_F(CpuTestbench, TestJALR){ +setupTest("jalr_test"); +initSimulation(); +runSimulation(CYCLES); +EXPECT_EQ(top_->a0, 2); +} + +// PC-relative Branch Instructions +TEST_F(CpuTestbench, TestBEQ){ + setupTest("beq_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 1); +} + +TEST_F(CpuTestbench, TestBNE){ + setupTest("bne_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 1); +} + +TEST_F(CpuTestbench, TestBLT){ + setupTest("blt_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 1); +} + +TEST_F(CpuTestbench, TestBGE){ + setupTest("bge_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 1); +} + +TEST_F(CpuTestbench, TestBLTU){ + setupTest("bltu_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 1); +} + +TEST_F(CpuTestbench, TestBGEU){ + setupTest("bgeu_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 1); +} + +// Load Instructions +TEST_F(CpuTestbench, TestLB){ + setupTest("lb_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 0x7F); +} + +TEST_F(CpuTestbench, TestLH){ + setupTest("lh_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 0x7FFF); +} + +TEST_F(CpuTestbench, TestLW){ + setupTest("lw_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, -1); +} + +TEST_F(CpuTestbench, TestLBU){ + setupTest("lbu_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 0xFF); +} + +TEST_F(CpuTestbench, TestLHU){ + setupTest("lhu_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 0xFFFF); +} + +// Store Instructions +TEST_F(CpuTestbench, TestSB){ + setupTest("sb_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 0xFF); +} + +TEST_F(CpuTestbench, TestSH){ + setupTest("sh_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 0xFFFF); +} + +TEST_F(CpuTestbench, TestSW){ + setupTest("sw_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, -1); +} + +// Immediate Instructions +TEST_F(CpuTestbench, TestADDI){ + setupTest("addi_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 8); // 5 + 3 +} + +TEST_F(CpuTestbench, TestSLTI){ + setupTest("slti_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 1); // 5 < 10, so true (1) +} + +TEST_F(CpuTestbench, TestSLTIU){ + setupTest("sltiu_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 0); // 0xFFFFFFFF < 1 in unsigned compare, so true (1) +} + +TEST_F(CpuTestbench, TestXORI){ + setupTest("xori_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 6); // 5 ^ 3 = 6 +} + +TEST_F(CpuTestbench, TestORI){ + setupTest("ori_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 7); // 5 | 3 = 7 +} + +TEST_F(CpuTestbench, TestANDI){ + setupTest("andi_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 1); // 5 & 3 = 1 +} + +TEST_F(CpuTestbench, TestSLLI){ + setupTest("slli_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 20); // 5 << 2 = 20 +} + +TEST_F(CpuTestbench, TestSRLI){ + setupTest("srli_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, (uint32_t) -8 >> 2); +} + +TEST_F(CpuTestbench, TestSRAI){ + setupTest("srai_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, -2); // -8 >> 2 = -2 (arithmetic, preserves sign) +} + +// Register-Register Instructions +TEST_F(CpuTestbench, TestADD){ + setupTest("add_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 8); // 5 + 3 +} + +TEST_F(CpuTestbench, TestSUB){ + setupTest("sub_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 2); // 5 - 3 +} + +TEST_F(CpuTestbench, TestXOR){ + setupTest("xor_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 6); // 5 ^ 3 = 6 +} + +TEST_F(CpuTestbench, TestSLL){ + setupTest("sll_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 20); // 5 << 2 = 20 +} + +TEST_F(CpuTestbench, TestSLT){ + setupTest("slt_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 1); // 5 < 10, so true (1) +} + +TEST_F(CpuTestbench, TestSLTU){ + setupTest("sltu_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 0); // 0xFFFFFFFF is not less than 1 in unsigned compare, so false (0) +} + +TEST_F(CpuTestbench, TestSRL){ + setupTest("srl_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, (uint32_t) -8 >> 2); +} + +TEST_F(CpuTestbench, TestSRA){ + setupTest("sra_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, -2); // -8 >> 2 = -2 (arithmetic, preserves sign) +} + +TEST_F(CpuTestbench, TestOR){ + setupTest("or_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 7); // 5 | 3 = 7 +} + +TEST_F(CpuTestbench, TestAND){ + setupTest("and_test"); + initSimulation(); + runSimulation(CYCLES); + EXPECT_EQ(top_->a0, 1); // 5 & 3 = 1 +} + int main(int argc, char **argv) { testing::InitGoogleTest(&argc, argv); From 0273080ba668f37c0dea022ad436a47443c3da8a Mon Sep 17 00:00:00 2001 From: minimish1 Date: Fri, 28 Nov 2025 12:31:26 +0000 Subject: [PATCH 63/65] Added fetch and decode pipeline registers --- .../decode_to_execute_register.sv | 69 +++++++++++++++++++ .../rtl_pipelined/fetch_to_decode_register.sv | 17 +++++ 2 files changed, 86 insertions(+) create mode 100644 repo/rtl_pipelined/decode_to_execute_register.sv create mode 100644 repo/rtl_pipelined/fetch_to_decode_register.sv diff --git a/repo/rtl_pipelined/decode_to_execute_register.sv b/repo/rtl_pipelined/decode_to_execute_register.sv new file mode 100644 index 0000000..4fe342e --- /dev/null +++ b/repo/rtl_pipelined/decode_to_execute_register.sv @@ -0,0 +1,69 @@ +module fetch_to_decode_register( + + input logic clk, + input logic RegWriteD, + input logic [1:0] ResultSrcD, + input logic MemWriteD, + input logic [1:0] JumpD, + input logic BranchD, + input logic [3:0] ALUControlD, + input logic ALUSrcAD, + input logic ALUSrcBD, + input logic [2:0] ImmSrcD, + input logic [2:0] AddressingControlD, + input logic [2:0] BranchTypeD, + + input logic [31:0] RD1D, + input logic [31:0] RD2D, + input logic [31:0] PCD, + input logic [4:0] Rs1D, + input logic [4:0] Rs2D, + input logic [4:0] RdD + input logic [31:0] ImmExtD, + input logic [31:0] PCPlus4D, + + output logic RegWriteE, + output logic [1:0] ResultSrcE, + output logic MemWriteE, + output logic [1:0] JumpE, + output logic BranchE, + output logic [3:0] ALUControlE, + output logic ALUSrcAE, + output logic ALUSrcBE, + output logic [2:0] ImmSrcE, + output logic [2:0] AddressingControlE, + output logic [2:0] BranchTypeE + + output logic [31:0] RD1E, + output logic [31:0] RD2E, + output logic [31:0] PCE, + output logic [4:0] Rs1E, + output logic [4:0] Rs2E, + output logic [4:0] RdE, + output logic [31:0] ImmExtE, + output logic [31:0] PCPlus4E +); + always_ff @(posedge clk) begin + RegWriteE <= RegWriteD; + ResultSrcE <= ResultSrcD; + MemWriteE <= MemWriteD; + JumpE <= JumpD; + BranchE <= BranchD; + ALUControlE <= ALUControlD; + ALUSrcAE <= ALUSrcAD; + ALUSrcBE <= ALUSrcBD; + ImmSrcE <= ImmSrcD; + AddressingControlE <= AddressingControlD; + BranchTypeE <= BranchTypeD; + + RD1E <= RD1D; + RD2E <= RD2D; + PCE <= PCD; + Rs1E <= Rs1D; + Rs2E <= Rs2D; + RdE <= RdD; + ImmExtE <= ImmExtD; + PCPlus4E <= PCPlus4D; + end + +endmodule diff --git a/repo/rtl_pipelined/fetch_to_decode_register.sv b/repo/rtl_pipelined/fetch_to_decode_register.sv new file mode 100644 index 0000000..456bc65 --- /dev/null +++ b/repo/rtl_pipelined/fetch_to_decode_register.sv @@ -0,0 +1,17 @@ +module fetch_to_decode_register( + + input logic clk, + input logic [31:0] PCF, + input logic [31:0] PCPlus4F, + input logic [31:0] InstrF, + output logic [31:0] PCD, + output logic [31:0] PCPlus4D, + output logic [31:0] InstrD +); + always_ff @(posedge clk) begin + PCD <= PCF; + PCPlus4D <= PCPlus4F; + InstrD <= InstrF; + end + +endmodule From ca6c35f253fc9cf9667f12faf30b7f71ab6b2638 Mon Sep 17 00:00:00 2001 From: Sicovo Date: Fri, 28 Nov 2025 12:38:39 +0000 Subject: [PATCH 64/65] doit/assemble --- repo/tb/assemble.sh | 32 +++++++++++++++++++++---------- repo/tb/doit.sh | 46 ++++++++++++++++++++++++++++++++++----------- 2 files changed, 57 insertions(+), 21 deletions(-) diff --git a/repo/tb/assemble.sh b/repo/tb/assemble.sh index f837ef3..1d3a146 100755 --- a/repo/tb/assemble.sh +++ b/repo/tb/assemble.sh @@ -1,14 +1,14 @@ #!/bin/bash -# Usage: ./assemble.sh +# Usage: ./compile.sh # Default vars SCRIPT_DIR=$(dirname "$(realpath "$0")") -output_file="$SCRIPT_DIR/program.hex" +output_file="../rtl/program.hex" # Handle terminal arguments if [[ $# -eq 0 ]]; then - echo "Usage: ./assemble.sh " + echo "Usage: ./compile.sh " exit 1 fi @@ -16,13 +16,25 @@ input_file=$1 basename=$(basename "$input_file" | sed 's/\.[^.]*$//') parent=$(dirname "$input_file") file_extension="${input_file##*.}" -LOG_DIR="$SCRIPT_DIR/test_out/$basename" -# Create output directory for disassembly, hex and waveforms -mkdir -p $LOG_DIR +# Compile the C code if necessary. +if [ $file_extension == "c" ]; then + # IMPORTANT: MUST NOT OPTIMIZE COMPILER! Or instructions could be lost! + riscv64-unknown-elf-gcc -S -g -O0 -fno-builtin -static \ + -march=rv32im -mabi=ilp32 \ + -o "${basename}.s" $input_file \ + -Wno-unused-result + # To get test case 24 passing, you need to modify ^^^^ + input_file="${basename}.s" +fi riscv64-unknown-elf-as -R -march=rv32im -mabi=ilp32 \ - -o "a.out" "$input_file" + -o "a.out" "${input_file}" + +# Remove the .s file if necessary +if [ $file_extension == "c" ]; then + rm ${input_file} +fi riscv64-unknown-elf-ld -melf32lriscv \ -e 0xBFC00000 \ @@ -37,11 +49,11 @@ rm *dis 2>/dev/null # This generates a disassembly file # Memory in wrong place, but makes it easier to read (should be main = 0xbfc00000) riscv64-unknown-elf-objdump -f -d --source -m riscv \ - a.out.reloc > ${LOG_DIR}/program.dis + a.out.reloc > ${SCRIPT_DIR}/${basename}.dis # Formats into a hex file -od -v -An -t x1 "a.bin" | tr -s '\n' | awk '{$1=$1};1' > "${output_file}" +od -v -An -t x4 "a.bin" | sed 's/^[ \t]*//' > "${output_file}" rm "a.out.reloc" rm "a.out" -rm "a.bin" +rm "a.bin" \ No newline at end of file diff --git a/repo/tb/doit.sh b/repo/tb/doit.sh index a8ff86a..d7256e2 100755 --- a/repo/tb/doit.sh +++ b/repo/tb/doit.sh @@ -24,20 +24,37 @@ else files=("$@") fi -cd $SCRIPT_DIR +# Cleanup +rm -rf obj_dir -# Wipe previous test output -rm -rf test_out/* +cd $SCRIPT_DIR # Iterate through files for file in "${files[@]}"; do name=$(basename "$file" _tb.cpp | cut -f1 -d\-) - + # If verify.cpp -> we are testing the top module if [ $name == "verify.cpp" ]; then name="top" fi + + # # Automatically detect latest GoogleTest installation under Homebrew（macOS) + # GTEST_BASE=$(brew --prefix googletest 2>/dev/null) + # if [ -z "$GTEST_BASE" ]; then + # echo "${RED}Error: GoogleTest not found via Homebrew.${RESET}" + # exit 1 + # fi + + # --- GoogleTest for Ubuntu --- + # gtest headers and static libs installed via apt (libgtest-dev) + GTEST_INCLUDE="/usr/include" + GTEST_LIB="/usr/lib" + + # Construct include and lib paths dynamically + GTEST_INCLUDE="$GTEST_BASE/include" + GTEST_LIB="$GTEST_BASE/lib" + # Translate Verilog -> C++ including testbench verilator -Wall --trace \ -cc ${RTL_FOLDER}/${name}.sv \ @@ -45,23 +62,30 @@ for file in "${files[@]}"; do -y ${RTL_FOLDER} \ --prefix "Vdut" \ -o Vdut \ - -CFLAGS "-std=c++17 -isystem /opt/homebrew/Cellar/googletest/1.17.0/include"\ - -LDFLAGS "-L/opt/homebrew/Cellar/googletest/1.17.0/lib -lgtest -lgtest_main -lpthread" \ + -CFLAGS "-std=c++17 -isystem ${GTEST_INCLUDE}" \ + -LDFLAGS "-L${GTEST_LIB} -lgtest -lgtest_main -lpthread" # Build C++ project with automatically generated Makefile make -j -C obj_dir/ -f Vdut.mk - + # Run executable simulation file ./obj_dir/Vdut - + # Check if the test succeeded or not if [ $? -eq 0 ]; then ((passes++)) else ((fails++)) fi - + done -# Save obj_dir in test_out -mv obj_dir test_out/ +# Exit as a pass or fail (for CI purposes) +if [ $fails -eq 0 ]; then + echo "${GREEN}Success! All ${passes} test(s) passed!" + exit 0 +else + total=$((passes + fails)) + echo "${RED}Failure! Only ${passes} test(s) passed out of ${total}." + exit 1 +fi \ No newline at end of file From a6b4e07fa71c470ddfa21e6cbb8f2dc950e5da9a Mon Sep 17 00:00:00 2001 From: ojas-parikh Date: Sat, 29 Nov 2025 19:45:52 +0000 Subject: [PATCH 65/65] trying to fix testing for mac modified: ../rtl/control.sv --- repo/rtl/control.sv | 2 +- repo/rtl/instr_mem.sv | 4 +- repo/tb/assemble.sh | 77 +++++++---- repo/tb/doit.sh | 82 ++++++------ repo/tb/tests/verify.cpp | 273 +-------------------------------------- 5 files changed, 95 insertions(+), 343 deletions(-) diff --git a/repo/rtl/control.sv b/repo/rtl/control.sv index 586e1b3..b9d60ee 100644 --- a/repo/rtl/control.sv +++ b/repo/rtl/control.sv @@ -24,7 +24,7 @@ module control( // assign opcode = Instr[6:0]; // assign funct3 = Instr[14:12]; // assign funct7 = Instr[31:25]; - assign AddressingControl = funct3; // store width + // assign AddressingControl = funct3; // store width always_comb begin // Default values to prevent latches diff --git a/repo/rtl/instr_mem.sv b/repo/rtl/instr_mem.sv index 54dbf7a..e66f08e 100644 --- a/repo/rtl/instr_mem.sv +++ b/repo/rtl/instr_mem.sv @@ -6,7 +6,7 @@ module instr_mem ( ); // instruction memory array: 256 instructions, each 32 bits wide - logic [31:0] rom_array [0:255]; + logic [31:0] rom_array [0:4095]; // preload instructions from an external hex file at simulation start initial begin @@ -14,5 +14,5 @@ module instr_mem ( end // output the instruction corresponding to the PC address - assign RD = rom_array[A[9:2]]; + assign RD = rom_array[A[13:2]]; endmodule diff --git a/repo/tb/assemble.sh b/repo/tb/assemble.sh index 1d3a146..ffba434 100755 --- a/repo/tb/assemble.sh +++ b/repo/tb/assemble.sh @@ -1,40 +1,40 @@ #!/bin/bash -# Usage: ./compile.sh +# Usage: ./assemble.sh # Default vars -SCRIPT_DIR=$(dirname "$(realpath "$0")") -output_file="../rtl/program.hex" +SCRIPT_DIR=$(dirname "$(realpath "$0")") #SCRIPT_DIR is variable, $ accesses value of variable, $0 is the name of the script executing, realpath gives absolute path of this file, dirname get rid of file portion and gives directory part only +output_file="$SCRIPT_DIR/program.hex" #giving path of output file +PROGRAM_FOLDER=$(realpath "$SCRIPT_DIR/../rtl/program.hex") # Handle terminal arguments -if [[ $# -eq 0 ]]; then - echo "Usage: ./compile.sh " +if [[ $# -eq 0 ]]; then # $# gives number of arguments, this checks if number of arguments in command is equal to zero if so we need to tell user to give more arguments + echo "Usage: ./assemble.sh " exit 1 fi -input_file=$1 -basename=$(basename "$input_file" | sed 's/\.[^.]*$//') -parent=$(dirname "$input_file") -file_extension="${input_file##*.}" - -# Compile the C code if necessary. -if [ $file_extension == "c" ]; then - # IMPORTANT: MUST NOT OPTIMIZE COMPILER! Or instructions could be lost! - riscv64-unknown-elf-gcc -S -g -O0 -fno-builtin -static \ - -march=rv32im -mabi=ilp32 \ - -o "${basename}.s" $input_file \ - -Wno-unused-result - # To get test case 24 passing, you need to modify ^^^^ - input_file="${basename}.s" -fi +input_file=$1 #$1 is the first argument sent to the script +basename=$(basename "$input_file" | sed 's/\.[^.]*$//') #basename removes anything including and past the last slash, here we have sed which is doing a substitution hence s, \.[^.]*$ are replaced with a / +parent=$(dirname "$input_file") +file_extension="${input_file##*.}" #${input_file##*.} is the value of input_file's path with only whats after the . in the path kept and the rest removed +LOG_DIR="$SCRIPT_DIR/test_out/$basename" #LOG_DIR has value of script_dir followed by /test_out /value of basename -riscv64-unknown-elf-as -R -march=rv32im -mabi=ilp32 \ - -o "a.out" "${input_file}" +# Create output directory for disassembly, hex and waveforms +mkdir -p $LOG_DIR #makes a directory called value of LOG_DIR, with any non-existent intermediate directories created as necessary -# Remove the .s file if necessary -if [ $file_extension == "c" ]; then - rm ${input_file} -fi +#risc64-unknown-elf-as is an assembler for riscv +#-march=rv32im sets the ISA to be used in this case / the instructions that will be accepted +#-mabi=ilp32 sets the ABI (application binary interface) which defines the purpose of specific registers, its set to ILP32 here +#riscv64-unknown-elf-ld is the gnu linker it links together different files to create an executable file +# -o "a.out" "input_file" says the output of the assembler will be stored in the file a.out and the source code file is $input_file +#the linker will output to a.out.reloc with the source file being a.out, Ttext specifies the text start address, melf32lriscv tells the linker +#the objects being linked are 32-bit RISC-V code +# a.out.reloc is the executable that can be loaded to the processor's instruction memory +#-e is the entry point, the address where the execution of the program begins - i.e. i think at what addresses to begin writing the output +#-O binary means we write the output file in binary format +#-j .text "a.out.reloc" "a.bin" copies only sections matching .text from a.out.reloc and writes it to a.bin +riscv64-unknown-elf-as -R -march=rv32im -mabi=ilp32 \ + -o "a.out" "$input_file" riscv64-unknown-elf-ld -melf32lriscv \ -e 0xBFC00000 \ @@ -45,15 +45,36 @@ riscv64-unknown-elf-objcopy -O binary \ -j .text "a.out.reloc" "a.bin" rm *dis 2>/dev/null +#rm means remove, 2> redirects stderr to the file /dev/null, dis stands for dissambler, not sure yet what this means # This generates a disassembly file # Memory in wrong place, but makes it easier to read (should be main = 0xbfc00000) + +#objdump displays information from object files +# -f means display summary infromation from the overall header of each of the objfile files +# -d means disassemble, it displays the assembler mnemonics for the machine instructions from the input file +# --source displays soruce code intermixed with disassembly +# -m specifies the architecture to use when disassembling the object files in this case riscv +# I believe we disassemble a.out.reloc and write this into the program.dis file riscv64-unknown-elf-objdump -f -d --source -m riscv \ - a.out.reloc > ${SCRIPT_DIR}/${basename}.dis + a.out.reloc > ${LOG_DIR}/program.dis # Formats into a hex file -od -v -An -t x4 "a.bin" | sed 's/^[ \t]*//' > "${output_file}" +# od -v means we will write all input data even if its duplicated, -An specifies the input address base as no address +#-t is to specify the output format, x1 means x = hexadecimal and 1 is the size specifier here its 1 which represents the byte count, so we will +#output the hex two hex digits at a time +#"a.bin" is the input file +#tr is translate +#awk scans through the input file for lines matching a set of specified paterns +#$1 denotes a field, with an input line being made up of fields seperated by white space or by the regular expressions +#awk '{$1=$1};1' rewrites a.bin removing whitespace and outputs it to ${output_file} +od -v -An -t x1 "a.bin" | tr -s '\n' | awk '{$1=$1};1' > "${PROGRAM_FOLDER}" +#od -v -An -t x1 "a.bin" | tr -s '\n' | awk '{$1=$1};1' > "${output_file}" + + + +#this part removes the following files rm "a.out.reloc" rm "a.out" rm "a.bin" \ No newline at end of file diff --git a/repo/tb/doit.sh b/repo/tb/doit.sh index d7256e2..b53bca1 100755 --- a/repo/tb/doit.sh +++ b/repo/tb/doit.sh @@ -4,56 +4,55 @@ # Usage: ./doit.sh # Constants -SCRIPT_DIR=$(dirname "$(realpath "$0")") -TEST_FOLDER=$(realpath "$SCRIPT_DIR/tests") -RTL_FOLDER=$(realpath "$SCRIPT_DIR/../rtl") -GREEN=$(tput setaf 2) -RED=$(tput setaf 1) -RESET=$(tput sgr0) +SCRIPT_DIR=$(dirname "$(realpath "$0")") #SCRIPT_DIR is the directory this file is in +TEST_FOLDER=$(realpath "$SCRIPT_DIR/tests") #test folder is a folder in this directory with name tests +RTL_FOLDER=$(realpath "$SCRIPT_DIR/../rtl") #RTL_FOLDER is set to a file called rtl from the directory above this one +GREEN=$(tput setaf 2) #setting terminal text colour to green +RED=$(tput setaf 1) #setting terminal text colour to red +RESET=$(tput sgr0) #resets terminal text to black and white # Variables passes=0 fails=0 # Handle terminal arguments +# $# gives number of arguments, this checks if number of arguments in command is equal to zero +# if so we run all the tests in the /test folder, so we set files equal to all the files ending in .cpp +# not sure how this works exactly is files a vector? if [[ $# -eq 0 ]]; then # If no arguments provided, run all tests files=(${TEST_FOLDER}/*.cpp) else # If arguments provided, use them as input files - files=("$@") + files=("$@") #$@ is an array of all arguments given to the script fi -# Cleanup -rm -rf obj_dir - +#change directory to this directory cd $SCRIPT_DIR +# Wipe previous test output +# -r rmoves file hierachy rooted in each file argument +# -f attempts to remove files regardless of file permissions +# test_out/* means we remove the files in test_out directory +rm -rf test_out/* + # Iterate through files for file in "${files[@]}"; do - name=$(basename "$file" _tb.cpp | cut -f1 -d\-) - + name=$(basename "$file" _tb.cpp | cut -f1 -d\-) #basename ouptuts the filename with _tb.cpp chopped of + #cut -f1 takes just column 1 with the delimiters being \ and - is this correct? + # If verify.cpp -> we are testing the top module if [ $name == "verify.cpp" ]; then name="top" fi - - # # Automatically detect latest GoogleTest installation under Homebrew（macOS) - # GTEST_BASE=$(brew --prefix googletest 2>/dev/null) - # if [ -z "$GTEST_BASE" ]; then - # echo "${RED}Error: GoogleTest not found via Homebrew.${RESET}" - # exit 1 - # fi - - # --- GoogleTest for Ubuntu --- - # gtest headers and static libs installed via apt (libgtest-dev) - GTEST_INCLUDE="/usr/include" - GTEST_LIB="/usr/lib" - - # Construct include and lib paths dynamically - GTEST_INCLUDE="$GTEST_BASE/include" - GTEST_LIB="$GTEST_BASE/lib" + #exe generates an executable + #y specifies the directory to search for the modules + #cc creates C++ output? + #prefix specifies name of top-level class and makefile + #name of final executable built if using --exe + #CFLAGS C++ compiler arguments for makefile + #LDFLAGS Linker pre-object arguments for makefile # Translate Verilog -> C++ including testbench verilator -Wall --trace \ @@ -62,30 +61,29 @@ for file in "${files[@]}"; do -y ${RTL_FOLDER} \ --prefix "Vdut" \ -o Vdut \ - -CFLAGS "-std=c++17 -isystem ${GTEST_INCLUDE}" \ - -LDFLAGS "-L${GTEST_LIB} -lgtest -lgtest_main -lpthread" + -CFLAGS "-std=c++17 -isystem /opt/homebrew/Cellar/googletest/1.17.0/include"\ + -LDFLAGS "-L/opt/homebrew/Cellar/googletest/1.17.0/lib -lgtest -lgtest_main -lpthread" \ # Build C++ project with automatically generated Makefile + #-j specifies number of jobs, no argument is given so there is no limit + #-C changes the directory to obj_dir/ in this case + #-f specifes the make file which is Vdut.mk here make -j -C obj_dir/ -f Vdut.mk - + # Run executable simulation file ./obj_dir/Vdut - + # Check if the test succeeded or not + #$? is the exit status of the command, zero means success of sorts + if [ $? -eq 0 ]; then ((passes++)) else ((fails++)) fi - + done -# Exit as a pass or fail (for CI purposes) -if [ $fails -eq 0 ]; then - echo "${GREEN}Success! All ${passes} test(s) passed!" - exit 0 -else - total=$((passes + fails)) - echo "${RED}Failure! Only ${passes} test(s) passed out of ${total}." - exit 1 -fi \ No newline at end of file +# Save obj_dir in test_out +#mv means move files, we move obj_dir files to test_out directory +mv obj_dir test_out/ \ No newline at end of file diff --git a/repo/tb/tests/verify.cpp b/repo/tb/tests/verify.cpp index 78e2323..99e8fd1 100644 --- a/repo/tb/tests/verify.cpp +++ b/repo/tb/tests/verify.cpp @@ -37,285 +37,18 @@ TEST_F(CpuTestbench, TestJalRet) EXPECT_EQ(top_->a0, 53); } -TEST_F(CpuTestbench, TestPdf) +/*TEST_F(CpuTestbench, TestPdf) { setupTest("5_pdf"); setData("reference/gaussian.mem"); initSimulation(); runSimulation(CYCLES * 100); EXPECT_EQ(top_->a0, 15363); -} - -/* Instruction Coverage */ - -// Upper and Jump/Link Instructions -TEST_F(CpuTestbench, TestLUI){ - setupTest("lui_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, (0b1010'1010'1010'1010'1010'0000'0000'0000) - 1); -} - -TEST_F(CpuTestbench, TestAUIPC){ - setupTest("auipc_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 2); -} - -TEST_F(CpuTestbench, TestJAL){ - setupTest("jal_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 2); -} - -TEST_F(CpuTestbench, TestJALR){ -setupTest("jalr_test"); -initSimulation(); -runSimulation(CYCLES); -EXPECT_EQ(top_->a0, 2); -} - -// PC-relative Branch Instructions -TEST_F(CpuTestbench, TestBEQ){ - setupTest("beq_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 1); -} - -TEST_F(CpuTestbench, TestBNE){ - setupTest("bne_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 1); -} - -TEST_F(CpuTestbench, TestBLT){ - setupTest("blt_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 1); -} - -TEST_F(CpuTestbench, TestBGE){ - setupTest("bge_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 1); -} - -TEST_F(CpuTestbench, TestBLTU){ - setupTest("bltu_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 1); -} - -TEST_F(CpuTestbench, TestBGEU){ - setupTest("bgeu_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 1); -} - -// Load Instructions -TEST_F(CpuTestbench, TestLB){ - setupTest("lb_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 0x7F); -} - -TEST_F(CpuTestbench, TestLH){ - setupTest("lh_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 0x7FFF); -} - -TEST_F(CpuTestbench, TestLW){ - setupTest("lw_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, -1); -} - -TEST_F(CpuTestbench, TestLBU){ - setupTest("lbu_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 0xFF); -} - -TEST_F(CpuTestbench, TestLHU){ - setupTest("lhu_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 0xFFFF); -} - -// Store Instructions -TEST_F(CpuTestbench, TestSB){ - setupTest("sb_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 0xFF); -} - -TEST_F(CpuTestbench, TestSH){ - setupTest("sh_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 0xFFFF); -} - -TEST_F(CpuTestbench, TestSW){ - setupTest("sw_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, -1); -} - -// Immediate Instructions -TEST_F(CpuTestbench, TestADDI){ - setupTest("addi_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 8); // 5 + 3 -} - -TEST_F(CpuTestbench, TestSLTI){ - setupTest("slti_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 1); // 5 < 10, so true (1) -} - -TEST_F(CpuTestbench, TestSLTIU){ - setupTest("sltiu_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 0); // 0xFFFFFFFF < 1 in unsigned compare, so true (1) -} - -TEST_F(CpuTestbench, TestXORI){ - setupTest("xori_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 6); // 5 ^ 3 = 6 -} - -TEST_F(CpuTestbench, TestORI){ - setupTest("ori_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 7); // 5 | 3 = 7 -} - -TEST_F(CpuTestbench, TestANDI){ - setupTest("andi_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 1); // 5 & 3 = 1 -} - -TEST_F(CpuTestbench, TestSLLI){ - setupTest("slli_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 20); // 5 << 2 = 20 -} - -TEST_F(CpuTestbench, TestSRLI){ - setupTest("srli_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, (uint32_t) -8 >> 2); -} - -TEST_F(CpuTestbench, TestSRAI){ - setupTest("srai_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, -2); // -8 >> 2 = -2 (arithmetic, preserves sign) -} - -// Register-Register Instructions -TEST_F(CpuTestbench, TestADD){ - setupTest("add_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 8); // 5 + 3 -} - -TEST_F(CpuTestbench, TestSUB){ - setupTest("sub_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 2); // 5 - 3 -} - -TEST_F(CpuTestbench, TestXOR){ - setupTest("xor_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 6); // 5 ^ 3 = 6 -} - -TEST_F(CpuTestbench, TestSLL){ - setupTest("sll_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 20); // 5 << 2 = 20 -} - -TEST_F(CpuTestbench, TestSLT){ - setupTest("slt_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 1); // 5 < 10, so true (1) -} - -TEST_F(CpuTestbench, TestSLTU){ - setupTest("sltu_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 0); // 0xFFFFFFFF is not less than 1 in unsigned compare, so false (0) -} - -TEST_F(CpuTestbench, TestSRL){ - setupTest("srl_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, (uint32_t) -8 >> 2); -} - -TEST_F(CpuTestbench, TestSRA){ - setupTest("sra_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, -2); // -8 >> 2 = -2 (arithmetic, preserves sign) -} - -TEST_F(CpuTestbench, TestOR){ - setupTest("or_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 7); // 5 | 3 = 7 -} - -TEST_F(CpuTestbench, TestAND){ - setupTest("and_test"); - initSimulation(); - runSimulation(CYCLES); - EXPECT_EQ(top_->a0, 1); // 5 & 3 = 1 -} +}*/ int main(int argc, char **argv) { testing::InitGoogleTest(&argc, argv); auto res = RUN_ALL_TESTS(); return res; -} +} \ No newline at end of file