From f451e9349708100a2e5da8bc7cbf2bb7ab2f4469 Mon Sep 17 00:00:00 2001
From: xgk <xuguokai@ucas.com.cn>
Date: Sun, 20 Apr 2025 18:02:57 +0800
Subject: [PATCH] Enable spi0-m2-cs0,uart3-m1,pwm7-m3 in default dts on
 rock-5b-plus board

---
 .../boot/dts/rockchip/rk3588-rock-5b-plus.dts | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts
index b42c0c267c8f8..0ad7770d94265 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts
@@ -1280,4 +1280,30 @@
 		"", "", "", "",
 		/* GPIO4_D4-D7 */
 		"", "", "", "";
+};
+
+&spi0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>;
+	max-freq = <50000000>;
+
+	spidev@0 {
+		compatible = "rockchip,spidev";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&uart3 {
+	status = "okay";
+	pinctrl-0 = <&uart3m1_xfer>;
+};
+
+&pwm7 {
+	status = "okay";
+	pinctrl-0 = <&pwm7m3_pins>;
 };
\ No newline at end of file