Review Layout

[Informaticore]

Schematic Level

• Change GND pins position on J9/J10 (Improve +3.3V usage and Shielding)
• Add more "Net Label" to improve the routing process (especially near the DC-DC converters/charger)
• Add one 2pts connector/pads for each ouput voltage (+3.3V, +3.3V_MCU and +5V). We need to have the possibility to power sensors, external boards, display, etc. (even if the ESP board is connected)
• Update R6/R7 values to limit the USB current to 1.5A (D1 can support 2A max and Board load current is limited to 500mA by the LTC4162)

Board Setup

• The copper layer 2 should be defined as a "Power Plane"

Copper Layers

• Remove any tracks on layer 2 (GND Power Plane)

Footprints

• ESP-WROOM32 module need 12 vias on the GND Power shape (pin 39). (recommended Layout)
• Update the ESP-WROOM32 footprint (EPAD need 3x3 PAD matrix -> see Datasheet for the recommended pattern)
• Update the QFN28 footprint of the CP2102N USB chip (use thermal vias version + increase hole diameters to 0.3mm)
• TPS63070 : Solve the issue (Pin 12&13 soldermask & solderpast, SMT instead THT and remove any solderpast layer on PADs)

Clearance

• Replace Mouting Hole footprint near the ESP antenna by one without any copper shape to respect recommanded clearances.

Routing

• Re-route the Vdd net (use wider copper tracks and copper shape)
• LTC4162-L : Apply the recommended rules from the Datasheet (p. 35) and Demo Board layout
• USB Data lines : Use a differential pair and apply the recommended rules

Silkscreen

• add version/revision and date
• Add Silkscreen RefDes for Connectors
• Update the max input voltage (20V ->15V). TPS63070 only accepts 16V max.

[MantaRayDeeJay]

I think that we should improve the GND pins position on J9/J10

The goal is to do +3.3V and GND pins close together and to add a " virtual shield" between I2C signals and USB signals

[MantaRayDeeJay]

The copper layer 2 should be defined as a "Power Plane"

[MantaRayDeeJay]

The Layer 2 is defined as a power plane and should be a TRUE power plane without any tracks.
The GND plane must clean to avoid any "loop" effect.

On the ESP board, move the track on layer 3 or layer 4.
On the Charger board, move the track on layer 4.

[MantaRayDeeJay]

3v3_I2C plane shape could be optimized. Only draw the area you need. It will increase insulation distance between other power plane shapes.

[MantaRayDeeJay]

SilkScreen Layer : Max input Voltage can't be +20V (TPS63070 only accept 16V max).
PS : I have specified +15V max on the schematic.

[Informaticore]

Add Silkscreen RefDes for Connectors

@MantaRayDeeJay they all got naming and description do you really need the ref?

Add more "Net Label" to improve the routing process (especially near the DC-DC converters/charger)

I don't understand what you mean with "Net Label", what are you referring to?

Add one 2pts connector/pads for each ouput voltage (+3.3V, +3.3V_MCU and +5V). We need to have the possibility to power sensors, external boards, display, etc. (even if the ESP board is connected)

I will try to add some

[MantaRayDeeJay]

@Informaticore

Add more "Net Label" to improve the routing process (especially near the DC-DC converters/charger)

I don't understand what you mean with "Net Label", what are you referring to?

ANSWER
An example below (with one of the 2 DC-DC converters).
PS : It should be great to do it for the 2 DC-DC converters and for the LTC4162L charger chip
Then, I could continue the review easily on these 3 critical layouts.

[Informaticore]

okay - got it

[MantaRayDeeJay]

@Informaticore

Add Silkscreen RefDes for Connectors

@MantaRayDeeJay they all got naming and description do you really need the ref?

ANSWER
I think mainly about 2pts connectors because there are 4 on the board.
To avoid any confusion, I should recommend to add it. (sometimes, text on silkscreen and text on schematic are not always synchronized). The Ref. Des. stay the only unique ID for each component.

PS : Always think about newbies. (it should be easy for everyone !!!)

[MantaRayDeeJay]

@Informaticore

ESP32 module :
The recommanded layout use 12 vias on the Power GND Pad, I can see only one on the board.
I think, vias should be added at the footprint level.

[Informaticore]

@MantaRayDeeJay do you know how to add vias in a footprint?

I didn't try it yet.
I think that you could have a look on the footprint used by the LTC4162L to see how it is build (there are vias)

[MantaRayDeeJay]

ESP32 Module : Antenna Clearance

I can see that the recommanded clearances are not fully respected.
It should be 15mm min distance (not only 5mm)

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Possible solution : Use a Mouting Hole without any copper shape and avoid the usage of metal screw (Nylon should be good).

[Informaticore]

We can go back to M2 holes but then we have to go everywhere, also on the charger board.