From dbf98e35c542ed9c04b51eddf646cf24121c0693 Mon Sep 17 00:00:00 2001 From: Mario 64 Date: Wed, 29 Oct 2025 17:24:27 +0100 Subject: [PATCH] update to zig 0.15.2 --- .gitignore | 2 - README.md | 16 ++------ build.zig | 56 +++++++++++++++----------- build.zig.zon | 10 ++--- src/asm.zig | 3 +- src/cpu.zig | 33 ++++++++------- src/examples/cpu-writebyte_example.zig | 23 +++++------ src/examples/loadprg_example.zig | 13 +++--- src/examples/sid_trace_example.zig | 21 +++++++--- src/mem.zig | 1 - src/sid.zig | 27 +++++++++---- src/vic.zig | 20 ++++----- src/zig64.zig | 45 +++++++++++---------- 13 files changed, 144 insertions(+), 126 deletions(-) delete mode 100644 .gitignore diff --git a/.gitignore b/.gitignore deleted file mode 100644 index d8c8979..0000000 --- a/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -.zig-cache -zig-out diff --git a/README.md b/README.md index 85d560c..3755995 100644 --- a/README.md +++ b/README.md @@ -1,10 +1,10 @@ # Commodore 64 MOS 6510 Emulator Core ![Tests](https://github.com/M64GitHub/zig64/actions/workflows/test.yml/badge.svg) -![Version](https://img.shields.io/badge/version-0.4.0-007bff?style=flat) +![Version](https://img.shields.io/badge/version-0.5.0-007bff?style=flat) ![Status](https://img.shields.io/badge/status-active-00cc00?style=flat) ![License](https://img.shields.io/badge/license-MIT-brightgreen?style=flat) -![Zig](https://img.shields.io/badge/Zig-0.14.0-orange?style=flat) +![Zig](https://img.shields.io/badge/Zig-0.15.2-orange?style=flat) A **Commodore 64 MOS 6510 emulator core** implemented in **Zig**, engineered for precision, flexibility, and seamless integration into C64-focused projects. This emulator delivers cycle-accurate CPU execution, detailed raster beam emulation for PAL and NTSC video synchronization, and advanced SID register tracking with change decoding, making it an ideal foundation for C64 software analysis, dissecting SID player routines, analyzing register manipulations, and debugging. @@ -418,16 +418,7 @@ zig build test ## Using zig64 In Your Project To add `zig64` as a dependency, use: ```sh -zig fetch --save https://github.com/M64GitHub/zig64/archive/refs/tags/v0.4.0.tar.gz -``` -This will add the dependency to your `build.zig.zon`: -```zig -.dependencies = .{ - .zig64 = .{ - .url = "https://github.com/M64GitHub/zig64/archive/refs/tags/v0.4.0.tar.gz", - .hash = "zig64-0.4.0-v6Fnevh-BADQQLrOWxSwFPI_uzYK_c75MpZtAyP2zosT", - }, -}, +zig fetch --save https://github.com/M64GitHub/zig64/archive/refs/tags/v0.5.0.tar.gz ``` In your `build.zig`, add the module as follows: @@ -470,7 +461,6 @@ git clone https://github.com/M64GitHub/zig64.git cd zig64 zig build ``` -Enjoy bringing the **C64 CPU to life in Zig!** diff --git a/build.zig b/build.zig index ee6205c..a348835 100644 --- a/build.zig +++ b/build.zig @@ -13,40 +13,46 @@ pub fn build(b: *std.Build) void { const mod_flagz = dep_flagz.module("flagz"); // -- Example loadprg - const exe_loadprg = b.addExecutable(.{ - .name = "loadprg-example", - .root_source_file = b.path( - "src/examples/loadprg_example.zig", - ), + const exe_loadprg_mod = b.addModule("exe_loadprg", .{ + .root_source_file = b.path("src/examples/loadprg_example.zig"), .target = target, .optimize = optimize, }); - exe_loadprg.root_module.addImport("flagz", mod_flagz); - exe_loadprg.root_module.addImport("zig64", mod_zig64); + exe_loadprg_mod.addImport("flagz", mod_flagz); + exe_loadprg_mod.addImport("zig64", mod_zig64); + + const exe_loadprg = b.addExecutable(.{ + .name = "loadprg-example", + .root_module = exe_loadprg_mod, + }); b.installArtifact(exe_loadprg); // -- Example cpu-writebyte - const exe_writebyte = b.addExecutable(.{ - .name = "writebyte-example", - .root_source_file = b.path( - "src/examples/cpu-writebyte_example.zig", - ), + const exe_writebyte_mod = b.addModule("exe_writebyte", .{ + .root_source_file = b.path("src/examples/cpu-writebyte_example.zig"), .target = target, .optimize = optimize, }); - exe_writebyte.root_module.addImport("zig64", mod_zig64); + exe_writebyte_mod.addImport("zig64", mod_zig64); + + const exe_writebyte = b.addExecutable(.{ + .name = "writebyte-example", + .root_module = exe_writebyte_mod, + }); b.installArtifact(exe_writebyte); // -- Example sid-trace - const exe_sidtrace = b.addExecutable(.{ - .name = "sidtrace-example", - .root_source_file = b.path( - "src/examples/sid_trace_example.zig", - ), + const exe_sidtrace_mod = b.addModule("exe_sidtrace", .{ + .root_source_file = b.path("src/examples/sid_trace_example.zig"), .target = target, .optimize = optimize, }); - exe_sidtrace.root_module.addImport("zig64", mod_zig64); + exe_sidtrace_mod.addImport("zig64", mod_zig64); + + const exe_sidtrace = b.addExecutable(.{ + .name = "sidtrace-example", + .root_module = exe_sidtrace_mod, + }); b.installArtifact(exe_sidtrace); // -- Run steps for all @@ -82,14 +88,16 @@ pub fn build(b: *std.Build) void { run_cmd_sidtrace.step.dependOn(b.getInstallStep()); // -- Test (Cpu) - const test_exe = b.addTest(.{ - .root_source_file = b.path( - "src/test/test-cpu.zig", - ), + const test_mod = b.addModule("test", .{ + .root_source_file = b.path("src/test/test-cpu.zig"), .target = target, .optimize = optimize, }); - test_exe.root_module.addImport("zig64", mod_zig64); + test_mod.addImport("zig64", mod_zig64); + + const test_exe = b.addTest(.{ + .root_module = test_mod, + }); const test_run = b.addRunArtifact(test_exe); test_run.step.dependOn(b.getInstallStep()); diff --git a/build.zig.zon b/build.zig.zon index 40a5481..08fc228 100644 --- a/build.zig.zon +++ b/build.zig.zon @@ -1,12 +1,12 @@ .{ .name = .zig64, - .version = "0.4.0", - .fingerprint = 0xd65e0f9f7a67a1bf, - .minimum_zig_version = "0.14.0", + .version = "0.5.0", + .minimum_zig_version = "0.15.0", + .fingerprint = 0xd65e0f9f3ad8ba3a, .dependencies = .{ .flagz = .{ - .url = "https://github.com/M64GitHub/flagZ/archive/refs/tags/v1.0.0.tar.gz", - .hash = "flagz-1.0.0-vdU1bCRQAQD3QOyKf6gAVpJuhTnlOoA10UmxO_XTycHm", + .url = "https://github.com/M64GitHub/flagZ/archive/refs/tags/v1.1.0.tar.gz", + .hash = "flagz-1.1.0-vdU1bLhJAQBcZ9qTy1SfJBLoYihjq32fjHjVLR9x_WXV", }, }, .paths = .{ diff --git a/src/asm.zig b/src/asm.zig index 850e6bf..86db790 100644 --- a/src/asm.zig +++ b/src/asm.zig @@ -1,5 +1,4 @@ const std = @import("std"); -const stdout = std.io.getStdOut().writer(); pub const Asm = @This(); @@ -104,7 +103,7 @@ pub fn disassembleForward(mem: []u8, pc_start: u16, count: usize) !void { const insn = decodeInstruction(&bytes); var obuf: [32]u8 = undefined; const str = try disassembleCodeLine(&obuf, pc, insn); - stdout.print("{s}\n", .{str}) catch {}; + std.debug.print("{s}\n", .{str}); pc = pc +% getInstructionSize(insn); } } diff --git a/src/cpu.zig b/src/cpu.zig index 2afebf4..42507bc 100644 --- a/src/cpu.zig +++ b/src/cpu.zig @@ -1,5 +1,4 @@ const std = @import("std"); -const stdout = std.io.getStdOut().writer(); const Ram64k = @import("mem.zig"); const Sid = @import("sid.zig"); @@ -106,11 +105,11 @@ fn doHardReset(cpu: *Cpu) void { pub fn reset(cpu: *Cpu, hard: bool) void { if (hard) { if (cpu.dbg_enabled) - stdout.print("[cpu] hard reset\n", .{}) catch {}; + std.debug.print("[cpu] hard reset\n", .{}); cpu.doHardReset(); } else { if (cpu.dbg_enabled) - stdout.print("[cpu] reset\n", .{}) catch {}; + std.debug.print("[cpu] reset\n", .{}); cpu.reset(); } } @@ -163,7 +162,7 @@ pub fn printStatus(cpu: *Cpu) void { const insn_size = Asm.getInstructionSize(insn); - stdout.print("[cpu] PC: {X:0>4} | {s} | {s} | A: {X:0>2} | X: {X:0>2} | Y: {X:0>2} | SP: {X:0>2} | Cycl: {d:0>2} | Cycl-TT: {d} | ", .{ + std.debug.print("[cpu] PC: {X:0>4} | {s} | {s} | A: {X:0>2} | X: {X:0>2} | Y: {X:0>2} | SP: {X:0>2} | Cycl: {d:0>2} | Cycl-TT: {d} | ", .{ cpu.pc, bytesToHex(&cpu.mem.data, cpu.pc, insn_size), padTo16(disasm, 12, &buf_disasm_pad), @@ -173,13 +172,13 @@ pub fn printStatus(cpu: *Cpu) void { cpu.sp, cpu.cycles_last_step, cpu.cycles_executed, - }) catch {}; + }); printFlags(cpu); - stdout.print("\n", .{}) catch {}; + std.debug.print("\n", .{}); } pub fn printTrace(cpu: *Cpu) void { - stdout.print("PC: {X:0>4} OP: {X:0>2} {X:0>2} {X:0>2} A:{X:0>2} X:{X:0>2} Y:{X:0>2} FL:{X:0>2}", .{ + std.debug.print("PC: {X:0>4} OP: {X:0>2} {X:0>2} {X:0>2} A:{X:0>2} X:{X:0>2} Y:{X:0>2} FL:{X:0>2}", .{ cpu.pc, cpu.mem.data[cpu.pc], cpu.mem.data[cpu.pc + 1], @@ -188,13 +187,13 @@ pub fn printTrace(cpu: *Cpu) void { cpu.x, cpu.y, cpu.status, - }) catch {}; - stdout.print("\n", .{}) catch {}; + }); + std.debug.print("\n", .{}); } pub fn printFlags(cpu: *Cpu) void { cpu.flagsToPS(); - stdout.print("FL: {b:0>8}", .{cpu.status}) catch {}; + std.debug.print("FL: {b:0>8}", .{cpu.status}); } pub fn readByte(cpu: *Cpu, addr: u16) u8 { @@ -877,17 +876,17 @@ pub fn runStep(cpu: *Cpu) u8 { cpu.pc = jsr_addr; cpu.cycles_executed +%= 1; // Matches 6 cycles with fetch and push if (cpu.dbg_enabled) { - stdout.print("[cpu] JSR {X:0>4}, return to {X:0>4}\n", .{ + std.debug.print("[cpu] JSR {X:0>4}, return to {X:0>4}\n", .{ jsr_addr, ret_addr, - }) catch {}; + }); } }, Asm.rts.opcode => { if (cpu.sp == 0xFF) { if (cpu.dbg_enabled) { - stdout.print("[cpu] RTS EXIT!\n", .{}) catch {}; + std.debug.print("[cpu] RTS EXIT!\n", .{}); } cpu.cycles_last_step = @as(u8, @truncate(cpu.cycles_executed -% cycles_now)); @@ -898,9 +897,9 @@ pub fn runStep(cpu: *Cpu) u8 { cpu.pc = ret_addr + 1; cpu.cycles_executed +%= 2; if (cpu.dbg_enabled) { - stdout.print("[cpu] RTS to {X:0>4}\n", .{ + std.debug.print("[cpu] RTS to {X:0>4}\n", .{ ret_addr + 1, - }) catch {}; + }); } }, @@ -908,7 +907,7 @@ pub fn runStep(cpu: *Cpu) u8 { const addr: u16 = addrAbs(cpu); cpu.pc = addr; if (cpu.dbg_enabled) { - stdout.print("[cpu] JMP {X:0>4}\n", .{addr}) catch {}; + std.debug.print("[cpu] JMP {X:0>4}\n", .{addr}); } }, @@ -1394,7 +1393,7 @@ pub fn runStep(cpu: *Cpu) u8 { if ((cpu.mem.data[0x01] & 0x07) != 0x5 and ((cpu.pc == 0xea31) or (cpu.pc == 0xea81))) { - stdout.print("[cpu] RTI\n", .{}) catch {}; + std.debug.print("[cpu] RTI\n", .{}); return 0; } diff --git a/src/examples/cpu-writebyte_example.zig b/src/examples/cpu-writebyte_example.zig index 778f336..1b63c20 100644 --- a/src/examples/cpu-writebyte_example.zig +++ b/src/examples/cpu-writebyte_example.zig @@ -5,19 +5,18 @@ const Asm = C64.Asm; pub fn main() !void { const allocator = std.heap.page_allocator; - const stdout = std.io.getStdOut().writer(); // Initialize the C64 emulator at $0800 with PAL VIC var c64 = try C64.init(allocator, C64.Vic.Model.pal, 0x0800); defer c64.deinit(allocator); // Print initial emulator state - try stdout.print("CPU start address: ${X:0>4}\n", .{c64.cpu.pc}); - try stdout.print("VIC model: {s}\n", .{@tagName(c64.vic.model)}); - try stdout.print("SID base address: ${X:0>4}\n", .{c64.sid.base_address}); + std.debug.print("CPU start address: ${X:0>4}\n", .{c64.cpu.pc}); + std.debug.print("VIC model: {s}\n", .{@tagName(c64.vic.model)}); + std.debug.print("SID base address: ${X:0>4}\n", .{c64.sid.base_address}); // Write a SID register sweep program to $0800 - try stdout.print("\nWriting SID sweep program to $0800...\n", .{}); + std.debug.print("\nWriting SID sweep program to $0800...\n", .{}); c64.cpu.writeByte(Asm.lda_imm.opcode, 0x0800); // LDA #$0A ; Load initial value 10 c64.cpu.writeByte(0x0A, 0x0801); c64.cpu.writeByte(Asm.tax.opcode, 0x0802); // TAX ; X = A (index for SID regs) @@ -38,10 +37,10 @@ pub fn main() !void { c64.sid.dbg_enabled = true; // Step through the program, analyzing SID changes - try stdout.print("\nExecuting SID sweep step-by-step...\n", .{}); + std.debug.print("\nExecuting SID sweep step-by-step...\n", .{}); while (c64.cpu.runStep() != 0) { if (c64.sid.last_change) |change| { - try stdout.print( + std.debug.print( "SID register {s} changed!\n", .{@tagName(change.meaning)}, ); @@ -52,27 +51,27 @@ pub fn main() !void { Sid.FilterModeVolume.fromValue(change.old_value).volume; const new_vol = Sid.FilterModeVolume.fromValue(change.new_value).volume; - try stdout.print( + std.debug.print( "Volume changed: {d} => {d}\n", .{ old_vol, new_vol }, ); } if (change.oscWaveformChanged(1)) { const wf = Sid.WaveformControl.fromValue(change.new_value); - try stdout.print( + std.debug.print( "Osc1 waveform updated: Pulse={}\n", .{wf.pulse}, ); } if (change.oscFreqChanged(1)) { - try stdout.print( + std.debug.print( "Osc1 freq updated: {X:02} => {X:02}\n", .{ change.old_value, change.new_value }, ); } if (change.oscAttackDecayChanged(1)) { const ad = Sid.AttackDecay.fromValue(change.new_value); - try stdout.print( + std.debug.print( "Osc1 attack/decay: A={d}, D={d}\n", .{ ad.attack, ad.decay }, ); @@ -81,6 +80,6 @@ pub fn main() !void { } // Final SID state - try stdout.print("\nFinal SID registers:\n", .{}); + std.debug.print("\nFinal SID registers:\n", .{}); c64.sid.printRegisters(); } diff --git a/src/examples/loadprg_example.zig b/src/examples/loadprg_example.zig index 51179b1..0d465f9 100644 --- a/src/examples/loadprg_example.zig +++ b/src/examples/loadprg_example.zig @@ -10,7 +10,6 @@ pub fn main() !void { var gpa = std.heap.GeneralPurposeAllocator(.{}){}; defer _ = gpa.deinit(); const allocator = gpa.allocator(); - const stdout = std.io.getStdOut().writer(); const Args = struct { prg: []const u8, @@ -19,7 +18,7 @@ pub fn main() !void { const args = try flagz.parse(Args, allocator); defer flagz.deinit(args, allocator); - try stdout.print("[EXE] initializing emulator\n", .{}); + std.debug.print("[EXE] initializing emulator\n", .{}); var c64 = try C64.init(allocator, C64.Vic.Model.pal, 0x0000); defer c64.deinit(allocator); @@ -30,14 +29,14 @@ pub fn main() !void { // c64.sid.dbg_enabled = true; // load a .prg file from disk - try stdout.print("[EXE] Loading '{s}'\n", .{args.prg}); + std.debug.print("[EXE] Loading '{s}'\n", .{args.prg}); const load_address = try c64.loadPrg(allocator, args.prg, true); - try stdout.print("[EXE] Load address: {X:0>4}\n\n", .{load_address}); + std.debug.print("[EXE] Load address: {X:0>4}\n\n", .{load_address}); - try stdout.print("[EXE] Disassembling from: {X:0>4}\n", .{load_address}); + std.debug.print("[EXE] Disassembling from: {X:0>4}\n", .{load_address}); try Asm.disassembleForward(&c64.mem.data, load_address, 31); - try stdout.print("\n\n", .{}); + std.debug.print("\n\n", .{}); - try stdout.print("[EXE] RUN\n", .{}); + std.debug.print("[EXE] RUN\n", .{}); c64.run(); } diff --git a/src/examples/sid_trace_example.zig b/src/examples/sid_trace_example.zig index cd0324f..323d63c 100644 --- a/src/examples/sid_trace_example.zig +++ b/src/examples/sid_trace_example.zig @@ -120,8 +120,8 @@ pub fn main() !void { c64.sid.dbg_enabled = true; // Master list for all changes - var all_changes = std.ArrayList(C64.Sid.RegisterChange).init(allocator); - defer all_changes.deinit(); + var all_changes = std.ArrayList(C64.Sid.RegisterChange){}; + defer all_changes.deinit(allocator); // Run each routine with callSidTrace const routines = [_]u16{ 0x0800, 0x0900, 0x0A00 }; @@ -132,13 +132,24 @@ pub fn main() !void { const changes = try c64.callSidTrace(addr, allocator); defer allocator.free(changes); - try C64.appendSidChanges(&all_changes, changes); // Static call! - std.debug.print("Traced {d} SID changes from ${X:0>4}\n", .{ changes.len, addr }); + try C64.appendSidChanges(&all_changes, changes, allocator); + std.debug.print( + "Traced {d} SID changes from ${X:0>4}\n", + .{ changes.len, addr }, + ); } // Print all collected changes std.debug.print("\nTotal SID changes: {d}\n", .{all_changes.items.len}); for (all_changes.items) |change| { - std.debug.print("Cycle {d}: {s} changed {X:02} => {X:02}\n", .{ change.cycle, @tagName(change.meaning), change.old_value, change.new_value }); + std.debug.print( + "Cycle {d}: {s} changed {X:02} => {X:02}\n", + .{ + change.cycle, + @tagName(change.meaning), + change.old_value, + change.new_value, + }, + ); } } diff --git a/src/mem.zig b/src/mem.zig index f30508a..44c56ba 100644 --- a/src/mem.zig +++ b/src/mem.zig @@ -1,5 +1,4 @@ const std = @import("std"); -const stdout = std.io.getStdOut().writer(); pub const Ram64k = @This(); diff --git a/src/sid.zig b/src/sid.zig index 9dd911c..6aa33f2 100644 --- a/src/sid.zig +++ b/src/sid.zig @@ -1,5 +1,4 @@ const std = @import("std"); -const stdout = std.io.getStdOut().writer(); pub const Sid = @This(); @@ -255,10 +254,16 @@ pub fn writeRegister(sid: *Sid, reg: usize, val: u8) void { .filter_mode_volume => .{ .filter_mode = FilterModeVolume.fromValue(val), }, - .osc1_attack_decay, .osc2_attack_decay, .osc3_attack_decay => .{ + .osc1_attack_decay, + .osc2_attack_decay, + .osc3_attack_decay, + => .{ .attack_decay = AttackDecay.fromValue(val), }, - .osc1_sustain_release, .osc2_sustain_release, .osc3_sustain_release => .{ + .osc1_sustain_release, + .osc2_sustain_release, + .osc3_sustain_release, + => .{ .sustain_release = SustainRelease.fromValue(val), }, else => .{ .raw = val }, @@ -321,10 +326,16 @@ pub fn writeRegisterCycle(sid: *Sid, reg: usize, val: u8, cycle: usize) void { .filter_mode_volume => .{ .filter_mode = FilterModeVolume.fromValue(val), }, - .osc1_attack_decay, .osc2_attack_decay, .osc3_attack_decay => .{ + .osc1_attack_decay, + .osc2_attack_decay, + .osc3_attack_decay, + => .{ .attack_decay = AttackDecay.fromValue(val), }, - .osc1_sustain_release, .osc2_sustain_release, .osc3_sustain_release => .{ + .osc1_sustain_release, + .osc2_sustain_release, + .osc3_sustain_release, + => .{ .sustain_release = SustainRelease.fromValue(val), }, else => .{ .raw = val }, @@ -351,11 +362,11 @@ pub fn writeRegisterCycle(sid: *Sid, reg: usize, val: u8, cycle: usize) void { } pub fn printRegisters(sid: *Sid) void { - stdout.print("[sid] registers: ", .{}) catch {}; + std.debug.print("[sid] registers: ", .{}); for (sid.registers) |v| { - stdout.print("{X:0>2} ", .{v}) catch {}; + std.debug.print("{X:0>2} ", .{v}); } - stdout.print("\n", .{}) catch {}; + std.debug.print("\n", .{}); } fn printChange(sid: *Sid, meaning: RegisterMeaning, val: u8) void { diff --git a/src/vic.zig b/src/vic.zig index 81f0a3c..bba42a9 100644 --- a/src/vic.zig +++ b/src/vic.zig @@ -1,5 +1,4 @@ const std = @import("std"); -const stdout = std.io.getStdOut().writer(); const Ram64k = @import("mem.zig"); const Cpu = @import("cpu.zig"); @@ -120,12 +119,15 @@ pub fn emulate(vic: *Vic, cycles_last_step: u8) u8 { } pub fn printStatus(vic: *Vic) void { - stdout.print("[vic] RL: {X:0>4} | VSYNC: {} | HSYNC: {} | BL: {} | RL-CHG: {} | FRM: {d}\n", .{ - vic.rasterline, - vic.vsync_happened, - vic.hsync_happened, - vic.badline_happened, - vic.rasterline_changed, - vic.frame_ctr, - }) catch {}; + std.debug.print( + "[vic] RL: {X:0>4} | VSYNC: {} | HSYNC: {} | BL: {} | RL-CHG: {} | FRM: {d}\n", + .{ + vic.rasterline, + vic.vsync_happened, + vic.hsync_happened, + vic.badline_happened, + vic.rasterline_changed, + vic.frame_ctr, + }, + ); } diff --git a/src/zig64.zig b/src/zig64.zig index 107c91f..24224fc 100644 --- a/src/zig64.zig +++ b/src/zig64.zig @@ -1,7 +1,5 @@ -pub const version = "0.4.0"; - +pub const version = "0.5.0"; const std = @import("std"); -const stdout = std.io.getStdOut().writer(); pub const Cpu = @import("cpu.zig"); pub const Ram64k = @import("mem.zig"); @@ -49,9 +47,9 @@ pub fn call(c64: *C64, address: u16) void { c64.sid.ext_reg_written = false; c64.cpu.pc = address; if (c64.dbg_enabled) { - stdout.print("[c64] calling address: {X:0>4}\n", .{ + std.debug.print("[c64] calling address: {X:0>4}\n", .{ address, - }) catch {}; + }); } while (c64.cpu.runStep() != 0) {} c64.sid.reg_written = c64.sid.ext_reg_written; @@ -71,17 +69,17 @@ pub fn callSidTrace( c64.cpu.pc = address; if (c64.dbg_enabled) { - stdout.print("[c64] tracing SID from address: {X:0>4}\n", .{address}) catch {}; + std.debug.print("[c64] tracing SID from address: {X:0>4}\n", .{address}); } // ArrayList to collect RegisterChange instances - var changes = std.ArrayList(Sid.RegisterChange).init(allocator); - defer changes.deinit(); // Frees the list memory, not the items + var changes = std.ArrayList(Sid.RegisterChange){}; + defer changes.deinit(allocator); // Frees the list memory, not the items // Run the program, collecting SID changes while (c64.cpu.runStep() != 0) { if (c64.sid.last_change) |change| { - try changes.append(change); // Add the change to the array + try changes.append(allocator, change); // Add the change to the array } } @@ -89,7 +87,7 @@ pub fn callSidTrace( c64.sid.reg_changed = c64.sid.ext_reg_changed; // Return the owned slice of changes - return changes.toOwnedSlice(); + return changes.toOwnedSlice(allocator); } pub fn loadPrg( @@ -102,7 +100,7 @@ pub fn loadPrg( defer file.close(); if (c64.dbg_enabled) { - try stdout.print("[c64] loading file: '{s}'\n", .{ + std.debug.print("[c64] loading file: '{s}'\n", .{ file_name, }); } @@ -152,7 +150,7 @@ pub fn setPrg(c64: *C64, program: []const u8, pc_to_loadaddr: bool) !u16 { load_address = @as(u16, lo) | @as(u16, hi); if (c64.dbg_enabled) { - try stdout.print("[c64] file load address: ${X:0>4}\n", .{ + std.debug.print("[c64] file load address: ${X:0>4}\n", .{ load_address, }); } @@ -161,11 +159,14 @@ pub fn setPrg(c64: *C64, program: []const u8, pc_to_loadaddr: bool) !u16 { while (i < (load_address +% program.len -% 2)) : (i +%= 1) { c64.mem.data[i] = program[offs]; if (c64.dbg_enabled) - stdout.print("[c64] writing mem: {X:0>4} offs: {X:0>4} data: {X:0>2}\n", .{ - i, - offs, - program[offs], - }) catch {}; + std.debug.print( + "[c64] writing mem: {X:0>4} offs: {X:0>4} data: {X:0>2}\n", + .{ + i, + offs, + program[offs], + }, + ); offs += 1; } } @@ -173,8 +174,10 @@ pub fn setPrg(c64: *C64, program: []const u8, pc_to_loadaddr: bool) !u16 { return load_address; } -pub fn appendSidChanges(existing_changes: *std.ArrayList( - Sid.RegisterChange, -), new_changes: []Sid.RegisterChange) !void { - try existing_changes.appendSlice(new_changes); +pub fn appendSidChanges( + existing_changes: *std.ArrayList(Sid.RegisterChange), + new_changes: []Sid.RegisterChange, + allocator: std.mem.Allocator, +) !void { + try existing_changes.appendSlice(allocator, new_changes); }