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Allow specifying constraints on encoding fields/operands #96

@PhilippvK

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@PhilippvK

Currently, constraints on operands/fields in the encoding are evaluated in the behavior block by explicitly raising an Illegal Instruction. It would be great if we could find a way to define those conditions somewhere else.

Examples:

  • RV32E: Hardwire the MSB of register operands to zero. (See #?)
  • Zpfsoperand: 64bit register pair operands made up of an even and odd register (rd & rd+1 where rd%2==0 and (optionally )non-overlapping constraints between source and dest registers)
  • Excluding reserved values in encoding fields
  • RVP: Implement SUNPKD810,SUNPKD820,SUNPKD830,SUNPKD831,SUNPKD832 in a single instruction block (see Add Mnemonic field to CoreDSL Syntax #80)
  • RVV: implement Vector Load/Stores in a more compact fashion (See Add Mnemonic field to CoreDSL Syntax #80, Allowing us to cut down >150 instruction blocks to less than 20)

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