From 2d535ffb7372648a86be0c03243049f6424c7eb7 Mon Sep 17 00:00:00 2001 From: Johannes Wirth Date: Thu, 15 May 2025 20:10:25 +0200 Subject: [PATCH 01/10] L2Cache: Split tags_ram into loaded/valid bit and rest --- .../lib/bus/tilelink/coherent/Cache.scala | 33 ++++++++++++++----- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala index a556a4d0fa..42a2b5f17f 100644 --- a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala +++ b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala @@ -164,7 +164,6 @@ class Cache(val p : CacheParam) extends Component { } case class Tags(val withData : Boolean) extends Bundle { - val loaded = Bool() val tag = UInt(tagRange.size bits) val dirty = withData generate Bool() val trunk = Bool() @@ -184,20 +183,30 @@ class Cache(val p : CacheParam) extends Component { val tags = new Area { val ram = Mem.fill(sets)(Vec.fill(ways)(Tags(withData))) - if(GlobalData.get.config.device == Device.ASIC) - ram.technology = registerFile + val loaded = Mem.fill(sets)(Vec.fill(ways)(Bool())) + loaded.init(List.fill(ram.wordCount)(Vec.fill(ways)(False))) + if(GlobalData.get.config.device == Device.ASIC) { + loaded.technology = registerFile + } val read = ram.readSyncPort + val readLoaded = loaded.readSyncPort val writeRaw = ram.writePortWithMask(ways) + val writeLoadedRaw = loaded.writePortWithMask(ways) val write = new Area{ val valid = Bool() val address = ram.addressType() val mask = Bits(ways bits) val data = Tags(withData) + val loaded = Bool() writeRaw.valid := valid writeRaw.address := address writeRaw.mask := mask writeRaw.data.foreach(_:= data) + writeLoadedRaw.valid := valid + writeLoadedRaw.address := address + writeLoadedRaw.mask := mask + writeLoadedRaw.data.foreach(_:= loaded) assert(!(valid && data.trunk && data.owners === 0)) } @@ -721,7 +730,10 @@ class Cache(val p : CacheParam) extends Component { cache.tags.read.cmd.valid := addressStage.isFireing cache.tags.read.cmd.payload := addressStage(CTRL_CMD).address(lineRange) + cache.tags.readLoaded.cmd.valid := addressStage.isFireing + cache.tags.readLoaded.cmd.payload := addressStage(CTRL_CMD).address(lineRange) val CACHE_TAGS = dataStage.insert(cache.tags.read.rsp) + val CACHE_LOADED = dataStage.insert(cache.tags.readLoaded.rsp) cache.plru.read.cmd.valid := addressStage.isFireing cache.plru.read.cmd.payload := addressStage(CTRL_CMD).address(setsRange) @@ -730,9 +742,11 @@ class Cache(val p : CacheParam) extends Component { val tags = new Area{ import tagStage._ - val read = tagStage(CACHE_TAGS) - val CACHE_HITS = insert(read.map(t => t.loaded && t.tag === CTRL_CMD.address(tagRange)).asBits) - val SOURCE_HITS = insert(read.map(t => (t.owners & inserter.SOURCE_OH).orR).asBits) + val readTags = tagStage(CACHE_TAGS) + val readLoaded = tagStage(CACHE_LOADED) + val read = readTags zip readLoaded + val CACHE_HITS = insert(read.map { case (t, l) => l && t.tag === CTRL_CMD.address(tagRange)}.asBits) + val SOURCE_HITS = insert(read.map { case (t, _) => (t.owners & inserter.SOURCE_OH).orR}.asBits) } val preCtrl = new Area{ @@ -891,6 +905,7 @@ class Cache(val p : CacheParam) extends Component { val unlocked = CombInit(!preCtrl.GS_HIT) //Pessimistic, as way check could help reduce conflict val wayId = CombInit(plru.io.evict.id) val tags = CACHE_TAGS(wayId) + val loaded = CACHE_LOADED(wayId) val address = tags.tag @@ CTRL_CMD.address(setsRange) @@ U(0, log2Up(blockSize) bits) } @@ -899,7 +914,7 @@ class Cache(val p : CacheParam) extends Component { cache.tags.write.valid := tags.CACHE_HITS.orR || askAllocate cache.tags.write.address := CTRL_CMD.address(setsRange) cache.tags.write.mask := tags.CACHE_HITS | UIntToOh(olderWay.wayId).andMask(askAllocate) - cache.tags.write.data.loaded := True + cache.tags.write.loaded := True cache.tags.write.data.tag := CTRL_CMD.address(tagRange) cache.tags.write.data.dirty := CACHE_LINE.dirty && !askAllocate cache.tags.write.data.trunk := CACHE_LINE.trunk @@ -987,7 +1002,7 @@ class Cache(val p : CacheParam) extends Component { toOrdering >> io.ordering.ctrlProcess //Generate a victim - when(askAllocate && olderWay.tags.loaded){ + when(askAllocate && olderWay.loaded){ when(olderWay.tags.owners.orR) { askProbe := True gsPendingVictim := True @@ -1031,7 +1046,7 @@ class Cache(val p : CacheParam) extends Component { if(withFlush) when(preCtrl.IS_FLUSH){ gsPendingPrimary := False - cache.tags.write.data.loaded := False + cache.tags.write.loaded := False when(CACHE_HIT) { when(CACHE_LINE.owners.orR) { askProbe := True From 60b38523121c372b7912ceebfea1322952cf4eba Mon Sep 17 00:00:00 2001 From: Johannes Wirth Date: Thu, 15 May 2025 20:10:48 +0200 Subject: [PATCH 02/10] Add padding to tags mem to use old SRAMs --- lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala index 42a2b5f17f..75079d1c22 100644 --- a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala +++ b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala @@ -164,6 +164,7 @@ class Cache(val p : CacheParam) extends Component { } case class Tags(val withData : Boolean) extends Bundle { + val _padding = Bool() val tag = UInt(tagRange.size bits) val dirty = withData generate Bool() val trunk = Bool() @@ -915,6 +916,7 @@ class Cache(val p : CacheParam) extends Component { cache.tags.write.address := CTRL_CMD.address(setsRange) cache.tags.write.mask := tags.CACHE_HITS | UIntToOh(olderWay.wayId).andMask(askAllocate) cache.tags.write.loaded := True + cache.tags.write.data._padding := True cache.tags.write.data.tag := CTRL_CMD.address(tagRange) cache.tags.write.data.dirty := CACHE_LINE.dirty && !askAllocate cache.tags.write.data.trunk := CACHE_LINE.trunk From d93fa557bcf73bc974a47c84335acf8cccef2a57 Mon Sep 17 00:00:00 2001 From: Johannes Wirth Date: Wed, 11 Jun 2025 11:39:16 +0200 Subject: [PATCH 03/10] StreamFIFO async: prevent X at output in idle cycles --- lib/src/main/scala/spinal/lib/Stream.scala | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/src/main/scala/spinal/lib/Stream.scala b/lib/src/main/scala/spinal/lib/Stream.scala index 42caaf69b8..c02ef7c20b 100644 --- a/lib/src/main/scala/spinal/lib/Stream.scala +++ b/lib/src/main/scala/spinal/lib/Stream.scala @@ -1485,6 +1485,9 @@ class StreamFifo[T <: Data](val dataType: HardType[T], case true => vec.read(addressGen.payload) case false => ram.readAsync(addressGen.payload) } + when (ptr.empty) { + readed.clearAll() + } io.pop << addressGen.translateWith(readed) ptr.popOnIo := ptr.pop From 670a9c6c5017e337ea986b251f73e2edc37ee54b Mon Sep 17 00:00:00 2001 From: Johannes Wirth Date: Wed, 11 Jun 2025 11:39:30 +0200 Subject: [PATCH 04/10] init regfile in contextbuffer --- .../main/scala/spinal/lib/bus/tilelink/ContextBuffer.scala | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/src/main/scala/spinal/lib/bus/tilelink/ContextBuffer.scala b/lib/src/main/scala/spinal/lib/bus/tilelink/ContextBuffer.scala index b2a85f79e1..dd05b730ff 100644 --- a/lib/src/main/scala/spinal/lib/bus/tilelink/ContextBuffer.scala +++ b/lib/src/main/scala/spinal/lib/bus/tilelink/ContextBuffer.scala @@ -48,6 +48,10 @@ object ContextAsyncBufferFull extends ContextAsyncBufferFactory{ } class ContextAsyncBufferFull[T <: Data](idWidth : Int, contextType : HardType[T]) extends ContextAsyncBufferBase[T](idWidth, contextType){ val contexts = Mem.fill(1 << idWidth)(contextType) + contexts.initBigInt(List.fill(contexts.wordCount)(0)) + if(GlobalData.get.config.device == Device.ASIC) { + contexts.technology = registerFile + } val write = contexts.writePort() write.valid := io.add.valid write.address := io.add.id From b1cc52a0c2000b5211f93622761974ae91099d1a Mon Sep 17 00:00:00 2001 From: Johannes Wirth Date: Wed, 11 Jun 2025 11:42:26 +0200 Subject: [PATCH 05/10] Remove separate regfile for loaded(valid) bit --- .../lib/bus/tilelink/coherent/Cache.scala | 34 +++++-------------- 1 file changed, 8 insertions(+), 26 deletions(-) diff --git a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala index 75079d1c22..97c2cccf93 100644 --- a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala +++ b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala @@ -163,8 +163,9 @@ class Cache(val p : CacheParam) extends Component { } } + case class Tags(val withData : Boolean) extends Bundle { - val _padding = Bool() + val loaded = Bool() val tag = UInt(tagRange.size bits) val dirty = withData generate Bool() val trunk = Bool() @@ -184,30 +185,18 @@ class Cache(val p : CacheParam) extends Component { val tags = new Area { val ram = Mem.fill(sets)(Vec.fill(ways)(Tags(withData))) - val loaded = Mem.fill(sets)(Vec.fill(ways)(Bool())) - loaded.init(List.fill(ram.wordCount)(Vec.fill(ways)(False))) - if(GlobalData.get.config.device == Device.ASIC) { - loaded.technology = registerFile - } val read = ram.readSyncPort - val readLoaded = loaded.readSyncPort val writeRaw = ram.writePortWithMask(ways) - val writeLoadedRaw = loaded.writePortWithMask(ways) val write = new Area{ val valid = Bool() val address = ram.addressType() val mask = Bits(ways bits) val data = Tags(withData) - val loaded = Bool() writeRaw.valid := valid writeRaw.address := address writeRaw.mask := mask writeRaw.data.foreach(_:= data) - writeLoadedRaw.valid := valid - writeLoadedRaw.address := address - writeLoadedRaw.mask := mask - writeLoadedRaw.data.foreach(_:= loaded) assert(!(valid && data.trunk && data.owners === 0)) } @@ -731,10 +720,7 @@ class Cache(val p : CacheParam) extends Component { cache.tags.read.cmd.valid := addressStage.isFireing cache.tags.read.cmd.payload := addressStage(CTRL_CMD).address(lineRange) - cache.tags.readLoaded.cmd.valid := addressStage.isFireing - cache.tags.readLoaded.cmd.payload := addressStage(CTRL_CMD).address(lineRange) val CACHE_TAGS = dataStage.insert(cache.tags.read.rsp) - val CACHE_LOADED = dataStage.insert(cache.tags.readLoaded.rsp) cache.plru.read.cmd.valid := addressStage.isFireing cache.plru.read.cmd.payload := addressStage(CTRL_CMD).address(setsRange) @@ -743,11 +729,9 @@ class Cache(val p : CacheParam) extends Component { val tags = new Area{ import tagStage._ - val readTags = tagStage(CACHE_TAGS) - val readLoaded = tagStage(CACHE_LOADED) - val read = readTags zip readLoaded - val CACHE_HITS = insert(read.map { case (t, l) => l && t.tag === CTRL_CMD.address(tagRange)}.asBits) - val SOURCE_HITS = insert(read.map { case (t, _) => (t.owners & inserter.SOURCE_OH).orR}.asBits) + val read = tagStage(CACHE_TAGS) + val CACHE_HITS = insert(read.map { t => t.loaded && t.tag === CTRL_CMD.address(tagRange)}.asBits) + val SOURCE_HITS = insert(read.map { t => (t.owners & inserter.SOURCE_OH).orR}.asBits) } val preCtrl = new Area{ @@ -906,7 +890,6 @@ class Cache(val p : CacheParam) extends Component { val unlocked = CombInit(!preCtrl.GS_HIT) //Pessimistic, as way check could help reduce conflict val wayId = CombInit(plru.io.evict.id) val tags = CACHE_TAGS(wayId) - val loaded = CACHE_LOADED(wayId) val address = tags.tag @@ CTRL_CMD.address(setsRange) @@ U(0, log2Up(blockSize) bits) } @@ -915,8 +898,7 @@ class Cache(val p : CacheParam) extends Component { cache.tags.write.valid := tags.CACHE_HITS.orR || askAllocate cache.tags.write.address := CTRL_CMD.address(setsRange) cache.tags.write.mask := tags.CACHE_HITS | UIntToOh(olderWay.wayId).andMask(askAllocate) - cache.tags.write.loaded := True - cache.tags.write.data._padding := True + cache.tags.write.data.loaded := True cache.tags.write.data.tag := CTRL_CMD.address(tagRange) cache.tags.write.data.dirty := CACHE_LINE.dirty && !askAllocate cache.tags.write.data.trunk := CACHE_LINE.trunk @@ -1004,7 +986,7 @@ class Cache(val p : CacheParam) extends Component { toOrdering >> io.ordering.ctrlProcess //Generate a victim - when(askAllocate && olderWay.loaded){ + when(askAllocate && olderWay.tags.loaded){ when(olderWay.tags.owners.orR) { askProbe := True gsPendingVictim := True @@ -1048,7 +1030,7 @@ class Cache(val p : CacheParam) extends Component { if(withFlush) when(preCtrl.IS_FLUSH){ gsPendingPrimary := False - cache.tags.write.loaded := False + cache.tags.write.data.loaded := False when(CACHE_HIT) { when(CACHE_LINE.owners.orR) { askProbe := True From 6995a99424a410fcb3269705adcae1ea5e49722d Mon Sep 17 00:00:00 2001 From: Johannes Wirth Date: Wed, 11 Jun 2025 11:43:01 +0200 Subject: [PATCH 06/10] Init regfiles --- .../spinal/lib/bus/tilelink/coherent/Cache.scala | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala index 97c2cccf93..2389f74429 100644 --- a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala +++ b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala @@ -180,6 +180,10 @@ class Cache(val p : CacheParam) extends Component { val plru = new Area{ val ram = Mem.fill(sets)(Plru.State(cacheWays)) val read = ram.readSyncPort + ram.initBigInt(List.fill(ram.wordCount)(0)) + if(GlobalData.get.config.device == Device.ASIC) { + ram.technology = registerFile + } val write = ram.writePort } @@ -372,6 +376,10 @@ class Cache(val p : CacheParam) extends Component { val gs = new SlotPool(generalSlotCount)(new GeneralSlot){ val ctxDownD = new Area{ val ram = Mem.fill(generalSlotCount)(CtxDownD()) + ram.initBigInt(List.fill(generalSlotCount)(0)) + if(GlobalData.get.config.device == Device.ASIC) { + ram.technology = registerFile + } val write = ram.writePort() } val fullUpA = slots.dropRight(p.generalSlotCountUpCOnly).map(_.valid).andR @@ -524,6 +532,10 @@ class Cache(val p : CacheParam) extends Component { val prober = new SlotPool(probeCount)(new ProberSlot){ val ctx = new Area{ val ram = Mem.fill(probeCount)(new CtrlCmd()) + ram.initBigInt(List.fill(ram.wordCount)(0)) + if(GlobalData.get.config.device == Device.ASIC) { + ram.technology = registerFile + } val write = ram.writePort() } From 774b0cdbd32bacc9b7f08e87a44d308c719c76a0 Mon Sep 17 00:00:00 2001 From: Johannes Wirth Date: Wed, 11 Jun 2025 11:45:23 +0200 Subject: [PATCH 07/10] Prevent X at mem output in off-cycles --- lib/src/main/scala/spinal/lib/Mem.scala | 9 +++++++++ .../scala/spinal/lib/bus/tilelink/coherent/Cache.scala | 6 +++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/lib/src/main/scala/spinal/lib/Mem.scala b/lib/src/main/scala/spinal/lib/Mem.scala index ccfc3bb89a..201268b63f 100644 --- a/lib/src/main/scala/spinal/lib/Mem.scala +++ b/lib/src/main/scala/spinal/lib/Mem.scala @@ -121,6 +121,15 @@ class MemPimped[T <: Data](mem: Mem[T]) { ret } + def readSyncPortMuxed(readUnderWrite: ReadUnderWritePolicy = dontCare, clockCrossing: Boolean = false) : MemReadPort[T] = { + val ret : MemReadPort[T] = MemReadPort(mem.wordType(),mem.addressWidth) + ret.rsp := mem.readSync(ret.cmd.payload,ret.cmd.valid, readUnderWrite, clockCrossing) + when (!ret.cmd.valid) { + ret.rsp.assignDontCare() + } + ret + } + def readAsyncPort() : MemReadPortAsync[T] = { val ret : MemReadPortAsync[T] = MemReadPortAsync(mem.wordType(),mem.addressWidth) ret.data := mem.readAsync(ret.address) diff --git a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala index 2389f74429..93fef34250 100644 --- a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala +++ b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala @@ -179,11 +179,11 @@ class Cache(val p : CacheParam) extends Component { val sets = bytes / blockSize / ways val plru = new Area{ val ram = Mem.fill(sets)(Plru.State(cacheWays)) - val read = ram.readSyncPort ram.initBigInt(List.fill(ram.wordCount)(0)) if(GlobalData.get.config.device == Device.ASIC) { ram.technology = registerFile } + val read = ram.readSyncPortMuxed() val write = ram.writePort } @@ -508,7 +508,7 @@ class Cache(val p : CacheParam) extends Component { val victimBuffer = new Area{ val ram = Mem.fill(generalSlotCount*wordsPerLine)(io.up.p.data()) val write = ram.writePort() - val read = ram.readSyncPort() + val read = ram.readSyncPortMuxed() } @@ -1593,7 +1593,7 @@ class Cache(val p : CacheParam) extends Component { import inserter._ val readPort = gs.ctxDownD.ram.readSyncPort() - readPort.cmd.valid := fetchStage.isFireing + readPort.cmd.valid := True //fetchStage.isFireing readPort.cmd.payload := fetchStage(CMD).source.resized readStage(CTX) := readPort.rsp From 18e8093e883b1f9ec3660944ba6ecc06036778d1 Mon Sep 17 00:00:00 2001 From: Johannes Wirth Date: Wed, 11 Jun 2025 11:46:25 +0200 Subject: [PATCH 08/10] Add idle register for flusher --- .../scala/spinal/lib/bus/tilelink/coherent/Cache.scala | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala index 93fef34250..b16df46dbd 100644 --- a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala +++ b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala @@ -388,6 +388,7 @@ class Cache(val p : CacheParam) extends Component { val flush = withFlush generate new Area { val reserved = RegInit(False) + val idle = RegInit(True) val address, upTo = Reg(ubp.address()) val start = False @@ -398,7 +399,10 @@ class Cache(val p : CacheParam) extends Component { val inflight = CounterUpDown(generalSlotCount + ctrlLoopbackDepth + 4) val gsMask = Reg(Bits(generalSlotCount bits)) - IDLE.whenIsActive(when(start)(goto(CMD))) + IDLE.whenIsActive(when(start) { + idle := False + goto(CMD) + }) CMD whenIsActive { when(cmd.fire) { @@ -420,6 +424,7 @@ class Cache(val p : CacheParam) extends Component { GS whenIsActive { when(gsMask === 0) { reserved := False + idle := True goto(IDLE) } } @@ -466,6 +471,7 @@ class Cache(val p : CacheParam) extends Component { mapper.read(flush.reserved || withSelfFlush.mux(selfFlusher.isActive(selfFlusher.CMD), False), 0x08) mapper.writeMultiWord(flush.address, 0x10) mapper.writeMultiWord(flush.upTo, 0x18) + mapper.read(flush.idle, 0x20) } val fromUpA = new Area{ From 8ae7e1549965747f13cd7ee6a95271e22a9a1fc6 Mon Sep 17 00:00:00 2001 From: Johannes Wirth Date: Wed, 11 Jun 2025 16:14:52 +0200 Subject: [PATCH 09/10] Add flushActive output to cache. This is then used in L1 to stall Also adds a delay at the start of the flush to wait for the stall to take effect --- .../spinal/lib/bus/tilelink/coherent/Cache.scala | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala index b16df46dbd..dd653915d2 100644 --- a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala +++ b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala @@ -128,6 +128,7 @@ class Cache(val p : CacheParam) extends Component { val ctrlProcess, writeBackend = master(Flow(OrderingCmd(up.p.sizeBytes))) def all = List(ctrlProcess, writeBackend) } + val flushActive = withFlush generate out Bool() } this.addTags(io.ordering.all.map(OrderingTag(_))) @@ -392,6 +393,8 @@ class Cache(val p : CacheParam) extends Component { val address, upTo = Reg(ubp.address()) val start = False + io.flushActive := !idle + val cmd = Stream(new CtrlCmd()) val fsm = new StateMachine { val IDLE, CMD, INFLIGHT, GS = new State() @@ -399,9 +402,15 @@ class Cache(val p : CacheParam) extends Component { val inflight = CounterUpDown(generalSlotCount + ctrlLoopbackDepth + 4) val gsMask = Reg(Bits(generalSlotCount bits)) + val WAIT = new StateDelay(cyclesCount = 50) { + whenCompleted { + goto(CMD) + } + } + IDLE.whenIsActive(when(start) { idle := False - goto(CMD) + goto(WAIT) }) CMD whenIsActive { From b7fda7ded31f71874eeaaa4a83f98700464da3ae Mon Sep 17 00:00:00 2001 From: Johannes Wirth Date: Wed, 11 Jun 2025 16:24:16 +0200 Subject: [PATCH 10/10] Fix failing tests --- .../main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala index dd653915d2..a451179b76 100644 --- a/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala +++ b/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala @@ -523,7 +523,7 @@ class Cache(val p : CacheParam) extends Component { val victimBuffer = new Area{ val ram = Mem.fill(generalSlotCount*wordsPerLine)(io.up.p.data()) val write = ram.writePort() - val read = ram.readSyncPortMuxed() + val read = ram.readSyncPort() } @@ -1608,7 +1608,7 @@ class Cache(val p : CacheParam) extends Component { import inserter._ val readPort = gs.ctxDownD.ram.readSyncPort() - readPort.cmd.valid := True //fetchStage.isFireing + readPort.cmd.valid := fetchStage.isFireing readPort.cmd.payload := fetchStage(CMD).source.resized readStage(CTX) := readPort.rsp