From fe339f46714cd692fd760ab7ab43266a1f85fb1e Mon Sep 17 00:00:00 2001 From: "Murphy, Peter J" Date: Thu, 14 Mar 2024 12:19:25 -0700 Subject: [PATCH 1/5] creating branch to fix the combinational loop error in modelsim --- .../01_pim_ifc/dma/hw/rtl/dma_write_engine.sv | 21 +++++++++++-------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv index 26e7037..3bc1c62 100644 --- a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv +++ b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv @@ -1,8 +1,10 @@ // Copyright (C) 2022 Intel Corporation // SPDX-License-Identifier: MIT +// `include "ofs_plat_if.vh" +`timescale 1ns/1ns module dma_write_engine #( parameter DATA_W = 512 @@ -101,12 +103,13 @@ module dma_write_engine #( end state[ADDR_SETUP_BIT]: - if (!need_more_wlast) next = WAIT_FOR_WR_RSP; + if (!need_more_wlast & dest_mem.awready) next = WAIT_FOR_WR_RSP; else next = SEND_WR_REQ; state[SEND_WR_REQ_BIT]: - if (dest_mem.awvalid & dest_mem.awready) next = FIFO_EMPTY; - else next = SEND_WR_REQ; + next = FIFO_EMPTY; + //if (dest_mem.awvalid) next = FIFO_EMPTY; + //else next = SEND_WR_REQ; state[FIFO_EMPTY_NOT_READY_BIT]: if (packet_complete & (!need_more_wlast)) next = WAIT_FOR_WR_RSP; @@ -256,8 +259,8 @@ module dma_write_engine #( dest_mem.awvalid = 1'b0; packet_complete = 1'b0; dest_mem_wlast = 1'b0; - rd_fifo_if.rd_en = dest_mem.wready & rd_fifo_if.not_empty; dest_mem_wvalid = dest_mem.wready & rd_fifo_if.not_empty; + rd_fifo_if.rd_en = dest_mem.wready & rd_fifo_if.not_empty; {packet_complete, dest_mem_wlast, @@ -275,9 +278,9 @@ module dma_write_engine #( end state[SEND_WR_REQ_BIT]:begin - dest_mem.awvalid = dest_mem.awready; - rd_fifo_if.rd_en = 1'b0; - dest_mem_wvalid = 1'b0; + dest_mem.awvalid = 1'b1; + rd_fifo_if.rd_en = 1'b0; + dest_mem_wvalid = 1'b0; end state[FIFO_EMPTY_NOT_READY_BIT]: begin end @@ -287,8 +290,8 @@ module dma_write_engine #( state[NOT_READY_BIT]:begin end state[RD_FIFO_WR_DEST_BIT]: begin - rd_fifo_if.rd_en = dest_mem.wready & rd_fifo_if.not_empty & (!next[ADDR_SETUP_BIT]); - dest_mem_wvalid = dest_mem.wready & rd_fifo_if.not_empty & (!next[ADDR_SETUP_BIT]); + rd_fifo_if.rd_en = dest_mem.wready & rd_fifo_if.not_empty & !(wlast_valid & need_more_wlast); + dest_mem_wvalid = dest_mem.wready & rd_fifo_if.not_empty & !(wlast_valid & need_more_wlast); end state[WAIT_FOR_WR_RSP_BIT]: begin From b900eebcc37396d32028b14e55c52b41fff61b11 Mon Sep 17 00:00:00 2001 From: "Murphy, Peter J" Date: Thu, 14 Mar 2024 12:23:54 -0700 Subject: [PATCH 2/5] Cleaning up changes to fix DMA Loop Error in ModelSim --- .../afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv index 3bc1c62..04f7dce 100644 --- a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv +++ b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv @@ -1,11 +1,8 @@ // Copyright (C) 2022 Intel Corporation // SPDX-License-Identifier: MIT -// `include "ofs_plat_if.vh" -`timescale 1ns/1ns - module dma_write_engine #( parameter DATA_W = 512 )( @@ -108,8 +105,6 @@ module dma_write_engine #( state[SEND_WR_REQ_BIT]: next = FIFO_EMPTY; - //if (dest_mem.awvalid) next = FIFO_EMPTY; - //else next = SEND_WR_REQ; state[FIFO_EMPTY_NOT_READY_BIT]: if (packet_complete & (!need_more_wlast)) next = WAIT_FOR_WR_RSP; @@ -259,8 +254,8 @@ module dma_write_engine #( dest_mem.awvalid = 1'b0; packet_complete = 1'b0; dest_mem_wlast = 1'b0; - dest_mem_wvalid = dest_mem.wready & rd_fifo_if.not_empty; rd_fifo_if.rd_en = dest_mem.wready & rd_fifo_if.not_empty; + dest_mem_wvalid = dest_mem.wready & rd_fifo_if.not_empty; {packet_complete, dest_mem_wlast, From 5bbb06b782222f8273669f8fa16b7ec140ef9f7e Mon Sep 17 00:00:00 2001 From: "Murphy, Peter J" Date: Thu, 14 Mar 2024 12:24:40 -0700 Subject: [PATCH 3/5] Cleaning up whitespaces --- tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv index 04f7dce..b96b589 100644 --- a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv +++ b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv @@ -274,8 +274,8 @@ module dma_write_engine #( state[SEND_WR_REQ_BIT]:begin dest_mem.awvalid = 1'b1; - rd_fifo_if.rd_en = 1'b0; - dest_mem_wvalid = 1'b0; + rd_fifo_if.rd_en = 1'b0; + dest_mem_wvalid = 1'b0; end state[FIFO_EMPTY_NOT_READY_BIT]: begin end From aaace6d4293a393801f22db9a817d4f08e6a7c9b Mon Sep 17 00:00:00 2001 From: "Murphy, Peter J" Date: Thu, 14 Mar 2024 12:59:04 -0700 Subject: [PATCH 4/5] Cleaning up whitespaces. Reverting unecessary change --- .../01_pim_ifc/dma/hw/rtl/dma_write_engine.sv | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv index b96b589..fc2b80e 100644 --- a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv +++ b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv @@ -99,12 +99,14 @@ module dma_write_engine #( else next = IDLE; end - state[ADDR_SETUP_BIT]: - if (!need_more_wlast & dest_mem.awready) next = WAIT_FOR_WR_RSP; - else next = SEND_WR_REQ; - + state[ADDR_SETUP_BIT]:= + if (!need_more_wlast) next = WAIT_FOR_WR_RSP; + else next = SEND_WR_REQ; + + state[SEND_WR_REQ_BIT]: - next = FIFO_EMPTY; + if (dest_mem.awvalid & dest_mem.awready) next = FIFO_EMPTY; + else next = SEND_WR_REQ; state[FIFO_EMPTY_NOT_READY_BIT]: if (packet_complete & (!need_more_wlast)) next = WAIT_FOR_WR_RSP; @@ -273,7 +275,7 @@ module dma_write_engine #( end state[SEND_WR_REQ_BIT]:begin - dest_mem.awvalid = 1'b1; + dest_mem.awvalid = dest_mem.awready; rd_fifo_if.rd_en = 1'b0; dest_mem_wvalid = 1'b0; end From fa0f9d0abf9dd270d3b342898a9325f9b82b0866 Mon Sep 17 00:00:00 2001 From: "Murphy, Peter J" Date: Thu, 14 Mar 2024 13:01:39 -0700 Subject: [PATCH 5/5] Cleaning up whitespaces. Reverting unecessary change --- .../afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv index fc2b80e..f4703f2 100644 --- a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv +++ b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv @@ -3,6 +3,7 @@ `include "ofs_plat_if.vh" + module dma_write_engine #( parameter DATA_W = 512 )( @@ -99,11 +100,10 @@ module dma_write_engine #( else next = IDLE; end - state[ADDR_SETUP_BIT]:= + state[ADDR_SETUP_BIT]: if (!need_more_wlast) next = WAIT_FOR_WR_RSP; else next = SEND_WR_REQ; - - + state[SEND_WR_REQ_BIT]: if (dest_mem.awvalid & dest_mem.awready) next = FIFO_EMPTY; else next = SEND_WR_REQ;