gem5_examples/TestBenchSystem.py at main · Will-Shaddix/gem5_examples · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
from __future__ import print_function
from __future__ import absolute_import

import m5
from m5.objects import *
from common import ObjectList

import math

class TestBenchSystem(System):

    def __init__(self, options):
        super(TestBenchSystem, self).__init__()
        if options.mem_type == 'HBM':
            self._mem_type = HBM_1000_4H_1x128
            self._addr_mapping = HBM_1000_4H_1x128.addr_mapping
            self._paging_policy = HBM_1000_4H_1x128.page_policy
        elif options.mem_type == 'DDR':
            self._mem_type = DDR3_1600_8x8
            self._addr_mapping = DDR3_1600_8x8.addr_mapping
            self._paging_policy = DDR3_1600_8x8.page_policy
        else:
            fatal('Memory type not supported.')
        self._num_chnls = options.num_chnls
        self._num_tgens = options.num_tgens

        self._mem_size = str(512 * options.num_chnls) + 'MB'
        self._addr_range = AddrRange(self._mem_size)

        self.clk_domain = SrcClockDomain()
        self.clk_domain.clock = '4GHz'
        self.clk_domain.voltage_domain = VoltageDomain()
        self.cache_line_size = 64

        self.mmap_using_noreserve = True
        self.mem_mode = 'timing'
        self.mem_ranges = [self._addr_range]

        self.tgens = [PyTrafficGen() for i in range(self._num_tgens)]
        self.createMemoryCtrl()
        self.connectComponents()
        ####
        # self.membuses = [SystemXBar(width = 64, max_routing_table_size = 16777216) for i in range(self._num_tgens)]
        # self.scheds = [MemScheduler(resp_buffer_size = 64) for i in range(self._num_chnls)]

        # for i, tgen in enumerate(self.tgens):
        #     tgen.port = self.membuses[i].cpu_side_ports

        # for i, membus in enumerate(self.membuses):
        #     for sched in self.scheds:
        #         sched.cpu_side[i] = membus.mem_side_ports

        # for i in range(self._num_chnls):
        #     for j in range(i * 8, (i + 1) * 8):
        #         self.scheds[i].mem_side[j - i * 8] = self.mem_ctrls[j].port

        # self.system_port = self.membuses[0].slave

    def createMemoryCtrl(self):
        mem_ctrls = []
        bpc = 0
        cls = self._mem_type
        addr_range = self._addr_range
        addr_map = self._addr_mapping
        page_policy = self._paging_policy
        if self._mem_type == HBM_1000_4H_1x128:
            num_chnls = self._num_chnls
        elif self._mem_type == DDR3_1600_8x8:
            num_chnls = self._num_chnls
        else:
            fatal('Memory type not supported.')

        intlv_size = self.cache_line_size
        if addr_map == 'RoRaBaChCo':
            rowbuffer_size = cls.device_rowbuffer_size.value * \
                            cls.devices_per_rank.value
            intlv_low_bit = int(math.log(rowbuffer_size, 2))
        else:
            intlv_low_bit = int(math.log(intlv_size, 2))
        intlv_bits = intlv_bits = int(math.log(num_chnls, 2))

        for chnl in range(num_chnls):
            interface = cls()
            interface.range = AddrRange(addr_range.start, size = addr_range.size(),
                        intlvHighBit = intlv_low_bit + intlv_bits - 1,
                        xorHighBit = 0,
                        intlvBits = intlv_bits,
                        intlvMatch = chnl)

            # interface.read_buffer_size = 32
            # interface.write_buffer_size = 16

            ctrl = MemCtrl()
            ctrl.dram = interface

            ctrl.dram.null = True
            ctrl.dram.addr_mapping = addr_map
            ctrl.dram.page_policy = page_policy

            mem_ctrls.append(ctrl)


        self.mem_ctrls = mem_ctrls
    def connectComponents(self):

        if self._mem_type == HBM_1000_4H_1x128:
            self.membuses = SystemXBar(width = 64, max_routing_table_size = 16777216)
            for tgen in self.tgens:
                tgen.port = self.membuses.cpu_side_ports
            for mem_ctrl in self.mem_ctrls:
                self.membuses.mem_side_ports = mem_ctrl.port
            self.system_port = self.membuses[0].cpu_side_ports

        elif self._mem_type == DDR3_1600_8x8:
            self.membuses = SystemXBar(width = 64, max_routing_table_size = 16777216)
            for tgen in self.tgens:
                tgen.port = self.membuses.cpu_side_ports
            for mem_ctrl in self.mem_ctrls:
                self.membuses.mem_side_ports = mem_ctrl.port
            self.system_port = self.membuses[0].cpu_side_ports
        else:
            fatal('Memory type not supported.')