DRAM Model Clarification

[jzhou1318]

Hello,
I'm trying to understand how DRAM capacity is represented in the memory model.

In the A100 configs, the row/bank/channel/column bit allocations correspond to only a few hundred MB to a few GB of modeled DRAM capacity. (228)/(10243) = 0.25 * 40 (n_mem) = 10 GB
This is much smaller than the real A100’s 40 GB / 80 GB HBM2e.

Is the scaled-down DRAM capacity intentional for simulation performance reasons?
If so, is there a recommended or assumed “target capacity” that the default configs represent (e.g., a few GB), or is capacity considered arbitrary as long as contention and timing behavior are preserved? Wouldn't increased or decreased capacity affect the placement and thus row hit/miss timing of the workloads?

[JRPan]

dram capacity is not modeled. CPU-GPU transfer is not modeled, thus there is no point in modeling dram capacity. Everything is assumed to be within dram when a kernel starts, which is typical of how you would launch a kernel.

That being said, the dram model does not accurately represent contemporary HBMs. It's still modeling HBM1, and we scale the number of channels to match HBM3 BW. Right now, there is nothing we can release as an accurate contemporary HBM3.
There are other projects that integrate gpgpu-sim and more accurate DRAM models, such as Ramulator. With some hacks, it should be easily adapted to Accel-Sim.