diff --git a/designs/asap7/NyuziProcessor/config.mk b/designs/asap7/NyuziProcessor/config.mk index 3b151bb..867b6f5 100644 --- a/designs/asap7/NyuziProcessor/config.mk +++ b/designs/asap7/NyuziProcessor/config.mk @@ -5,33 +5,13 @@ export PLATFORM = asap7 export SYNTH_HIERARCHICAL = 1 -export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_1x256_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_16x52_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_18x256_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_20x64_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_20x64_2r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_32x128_2r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_512x256_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_512x2048_1r1w.lef - -export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_1x256_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_16x52_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_20x64_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_18x256_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_20x64_2r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_32x128_2r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_512x256_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_512x2048_1r1w.lib - -export ABC_AREA = 1 - export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc -export CORE_AREA = 5 5 655 655 -export DIE_AREA = 0 0 660 660 +export CORE_AREA = 3 3 500 497 +export DIE_AREA = 0 0 500 497 -export PLACE_DENSITY_LB_ADDON = 0.15 +export PLACE_DENSITY_LB_ADDON = 0.22 -export MACRO_PLACE_HALO = 5 5 +export MACRO_PLACE_HALO = 6 6 export TNS_END_PERCENT = 100 \ No newline at end of file diff --git a/designs/asap7/NyuziProcessor/constraint.sdc b/designs/asap7/NyuziProcessor/constraint.sdc index 1f25d2c..4665389 100644 --- a/designs/asap7/NyuziProcessor/constraint.sdc +++ b/designs/asap7/NyuziProcessor/constraint.sdc @@ -2,14 +2,17 @@ current_design NyuziProcessor set clk_name clk set clk_port_name clk -set clk_period 2400 -set clk_io_pct 0.15 +set clk_period 1000 +set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [lsearch -inline -all -regexp [all_inputs]] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +set outputs [lsearch -inline -all-regexp [all_outputs]] + +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [lsearch -inline -all -exact $outputs $clk_name] + +set_false_path -from [get_ports reset] diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_16x52_1r1w.lef b/designs/asap7/NyuziProcessor/sram/lef/fakeram_16x52_1r1w.lef index 4641970..66d8ecd 100644 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_16x52_1r1w.lef +++ b/designs/asap7/NyuziProcessor/sram/lef/fakeram_16x52_1r1w.lef @@ -3,15 +3,159 @@ BUSBITCHARS "[]" ; MACRO fakeram_16x52_1r1w FOREIGN fakeram_16x52_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 8.295 BY 5.184 ; + SIZE 10.203 BY 12.753 ; CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 0.276 10.203 0.300 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 1.140 10.203 1.164 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 2.004 10.203 2.028 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 2.868 10.203 2.892 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 12.699 0.225 12.753 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.639 12.699 0.657 12.753 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 12.699 1.089 12.753 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.503 12.699 1.521 12.753 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 12.699 1.953 12.753 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 12.699 2.385 12.753 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 12.699 2.817 12.753 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 12.699 3.249 12.753 ; + END + END w0_wmask_in[15] PIN w0_wd_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; + RECT 0.000 3.732 0.072 3.756 ; END END w0_wd_in[0] PIN w0_wd_in[1] @@ -20,7 +164,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.708 0.024 0.732 ; + RECT 0.000 4.596 0.072 4.620 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +173,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.140 0.024 1.164 ; + RECT 0.000 5.460 0.072 5.484 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +182,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.572 0.024 1.596 ; + RECT 0.000 6.324 0.072 6.348 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +191,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 0.276 8.295 0.300 ; + RECT 10.131 3.732 10.203 3.756 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +200,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 0.708 8.295 0.732 ; + RECT 10.131 4.596 10.203 4.620 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +209,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 1.140 8.295 1.164 ; + RECT 10.131 5.460 10.203 5.484 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +218,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 1.572 8.295 1.596 ; + RECT 10.131 6.324 10.203 6.348 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +227,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; + RECT 0.207 0.000 0.225 0.054 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,7 +236,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.675 0.000 0.693 0.018 ; + RECT 0.783 0.000 0.801 0.054 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,7 +245,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.143 0.000 1.161 0.018 ; + RECT 1.359 0.000 1.377 0.054 ; END END w0_wd_in[10] PIN w0_wd_in[11] @@ -110,7 +254,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.611 0.000 1.629 0.018 ; + RECT 1.935 0.000 1.953 0.054 ; END END w0_wd_in[11] PIN w0_wd_in[12] @@ -119,7 +263,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.079 0.000 2.097 0.018 ; + RECT 2.511 0.000 2.529 0.054 ; END END w0_wd_in[12] PIN w0_wd_in[13] @@ -128,7 +272,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.547 0.000 2.565 0.018 ; + RECT 3.087 0.000 3.105 0.054 ; END END w0_wd_in[13] PIN w0_wd_in[14] @@ -137,7 +281,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.015 0.000 3.033 0.018 ; + RECT 3.663 0.000 3.681 0.054 ; END END w0_wd_in[14] PIN w0_wd_in[15] @@ -146,7 +290,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.483 0.000 3.501 0.018 ; + RECT 4.239 0.000 4.257 0.054 ; END END w0_wd_in[15] PIN r0_rd_out[0] @@ -155,7 +299,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.951 0.000 3.969 0.018 ; + RECT 4.815 0.000 4.833 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -164,7 +308,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.419 0.000 4.437 0.018 ; + RECT 5.391 0.000 5.409 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -173,7 +317,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.887 0.000 4.905 0.018 ; + RECT 5.967 0.000 5.985 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -182,7 +326,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.355 0.000 5.373 0.018 ; + RECT 6.543 0.000 6.561 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -191,7 +335,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.823 0.000 5.841 0.018 ; + RECT 7.119 0.000 7.137 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -200,7 +344,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.291 0.000 6.309 0.018 ; + RECT 7.695 0.000 7.713 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -209,7 +353,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.759 0.000 6.777 0.018 ; + RECT 8.271 0.000 8.289 0.054 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -218,7 +362,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.227 0.000 7.245 0.018 ; + RECT 8.847 0.000 8.865 0.054 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -227,7 +371,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 5.166 0.225 5.184 ; + RECT 3.663 12.699 3.681 12.753 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -236,7 +380,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.783 5.166 0.801 5.184 ; + RECT 4.095 12.699 4.113 12.753 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -245,7 +389,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.359 5.166 1.377 5.184 ; + RECT 4.527 12.699 4.545 12.753 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -254,7 +398,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.935 5.166 1.953 5.184 ; + RECT 4.959 12.699 4.977 12.753 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -263,7 +407,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.511 5.166 2.529 5.184 ; + RECT 5.391 12.699 5.409 12.753 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -272,7 +416,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.087 5.166 3.105 5.184 ; + RECT 5.823 12.699 5.841 12.753 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -281,7 +425,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.663 5.166 3.681 5.184 ; + RECT 6.255 12.699 6.273 12.753 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -290,7 +434,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.239 5.166 4.257 5.184 ; + RECT 6.687 12.699 6.705 12.753 ; END END r0_rd_out[15] PIN w0_addr_in[0] @@ -299,7 +443,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.004 0.024 2.028 ; + RECT 0.000 7.188 0.072 7.212 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -308,7 +452,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.436 0.024 2.460 ; + RECT 0.000 8.052 0.072 8.076 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -317,7 +461,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.868 0.024 2.892 ; + RECT 0.000 8.916 0.072 8.940 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -326,7 +470,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 2.004 8.295 2.028 ; + RECT 10.131 7.188 10.203 7.212 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -335,7 +479,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 2.436 8.295 2.460 ; + RECT 10.131 8.052 10.203 8.076 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -344,7 +488,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 2.868 8.295 2.892 ; + RECT 10.131 8.916 10.203 8.940 ; END END w0_addr_in[5] PIN r0_addr_in[0] @@ -353,7 +497,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.300 0.024 3.324 ; + RECT 0.000 9.780 0.072 9.804 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -362,7 +506,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.732 0.024 3.756 ; + RECT 0.000 10.644 0.072 10.668 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -371,7 +515,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.164 0.024 4.188 ; + RECT 0.000 11.508 0.072 11.532 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -380,7 +524,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 3.300 8.295 3.324 ; + RECT 10.131 9.780 10.203 9.804 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -389,7 +533,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 3.732 8.295 3.756 ; + RECT 10.131 10.644 10.203 10.668 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -398,7 +542,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 4.164 8.295 4.188 ; + RECT 10.131 11.508 10.203 11.532 ; END END r0_addr_in[5] PIN w0_we_in @@ -407,7 +551,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.815 5.166 4.833 5.184 ; + RECT 7.119 12.699 7.137 12.753 ; END END w0_we_in PIN w0_ce_in @@ -416,7 +560,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.391 5.166 5.409 5.184 ; + RECT 7.551 12.699 7.569 12.753 ; END END w0_ce_in PIN w0_clk @@ -425,7 +569,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.967 5.166 5.985 5.184 ; + RECT 7.983 12.699 8.001 12.753 ; END END w0_clk PIN r0_ce_in @@ -434,7 +578,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.543 5.166 6.561 5.184 ; + RECT 8.415 12.699 8.433 12.753 ; END END r0_ce_in PIN r0_clk @@ -443,7 +587,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.119 5.166 7.137 5.184 ; + RECT 8.847 12.699 8.865 12.753 ; END END r0_clk PIN VSS @@ -451,13 +595,23 @@ MACRO fakeram_16x52_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.108 0.192 8.187 0.288 ; - RECT 0.108 0.960 8.187 1.056 ; - RECT 0.108 1.728 8.187 1.824 ; - RECT 0.108 2.496 8.187 2.592 ; - RECT 0.108 3.264 8.187 3.360 ; - RECT 0.108 4.032 8.187 4.128 ; - RECT 0.108 4.800 8.187 4.896 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; END END VSS PIN VDD @@ -465,24 +619,34 @@ MACRO fakeram_16x52_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.108 0.192 8.187 0.288 ; - RECT 0.108 0.960 8.187 1.056 ; - RECT 0.108 1.728 8.187 1.824 ; - RECT 0.108 2.496 8.187 2.592 ; - RECT 0.108 3.264 8.187 3.360 ; - RECT 0.108 4.032 8.187 4.128 ; - RECT 0.108 4.800 8.187 4.896 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; END END VDD OBS LAYER M1 ; - RECT 0 0 8.295 5.184 ; + RECT 0 0 10.203 12.753 ; LAYER M2 ; - RECT 0 0 8.295 5.184 ; + RECT 0 0 10.203 12.753 ; LAYER M3 ; - RECT 0 0 8.295 5.184 ; + RECT 0 0 10.203 12.753 ; LAYER M4 ; - RECT 0 0 8.295 5.184 ; + RECT 0 0 10.203 12.753 ; END END fakeram_16x52_1r1w diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_18x256_1r1w.lef b/designs/asap7/NyuziProcessor/sram/lef/fakeram_18x256_1r1w.lef index 70786c2..51e7c42 100644 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_18x256_1r1w.lef +++ b/designs/asap7/NyuziProcessor/sram/lef/fakeram_18x256_1r1w.lef @@ -3,15 +3,177 @@ BUSBITCHARS "[]" ; MACRO fakeram_18x256_1r1w FOREIGN fakeram_18x256_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 9.332 BY 20.736 ; + SIZE 10.203 BY 46.937 ; CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 0.276 10.203 0.300 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 2.964 10.203 2.988 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 5.652 10.203 5.676 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 8.340 10.203 8.364 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 46.883 0.225 46.937 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.603 46.883 0.621 46.937 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.999 46.883 1.017 46.937 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.395 46.883 1.413 46.937 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.791 46.883 1.809 46.937 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.187 46.883 2.205 46.937 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.583 46.883 2.601 46.937 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.979 46.883 2.997 46.937 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 46.883 3.393 46.937 ; + END + END w0_wmask_in[17] PIN w0_wd_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; + RECT 0.000 13.716 0.072 13.740 ; END END w0_wd_in[0] PIN w0_wd_in[1] @@ -20,7 +182,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.812 0.024 1.836 ; + RECT 0.000 16.404 0.072 16.428 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +191,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.348 0.024 3.372 ; + RECT 0.000 19.092 0.072 19.116 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +200,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.884 0.024 4.908 ; + RECT 0.000 21.780 0.072 21.804 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +209,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.420 0.024 6.444 ; + RECT 0.000 24.468 0.072 24.492 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +218,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 0.276 9.332 0.300 ; + RECT 10.131 11.028 10.203 11.052 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +227,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 1.812 9.332 1.836 ; + RECT 10.131 13.716 10.203 13.740 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +236,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 3.348 9.332 3.372 ; + RECT 10.131 16.404 10.203 16.428 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +245,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 4.884 9.332 4.908 ; + RECT 10.131 19.092 10.203 19.116 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,7 +254,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; + RECT 0.207 0.000 0.225 0.054 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,7 +263,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.675 0.000 0.693 0.018 ; + RECT 0.747 0.000 0.765 0.054 ; END END w0_wd_in[10] PIN w0_wd_in[11] @@ -110,7 +272,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.143 0.000 1.161 0.018 ; + RECT 1.287 0.000 1.305 0.054 ; END END w0_wd_in[11] PIN w0_wd_in[12] @@ -119,7 +281,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.611 0.000 1.629 0.018 ; + RECT 1.827 0.000 1.845 0.054 ; END END w0_wd_in[12] PIN w0_wd_in[13] @@ -128,7 +290,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.079 0.000 2.097 0.018 ; + RECT 2.367 0.000 2.385 0.054 ; END END w0_wd_in[13] PIN w0_wd_in[14] @@ -137,7 +299,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.547 0.000 2.565 0.018 ; + RECT 2.907 0.000 2.925 0.054 ; END END w0_wd_in[14] PIN w0_wd_in[15] @@ -146,7 +308,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.015 0.000 3.033 0.018 ; + RECT 3.447 0.000 3.465 0.054 ; END END w0_wd_in[15] PIN w0_wd_in[16] @@ -155,7 +317,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.483 0.000 3.501 0.018 ; + RECT 3.987 0.000 4.005 0.054 ; END END w0_wd_in[16] PIN w0_wd_in[17] @@ -164,7 +326,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.951 0.000 3.969 0.018 ; + RECT 4.527 0.000 4.545 0.054 ; END END w0_wd_in[17] PIN r0_rd_out[0] @@ -173,7 +335,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.419 0.000 4.437 0.018 ; + RECT 5.067 0.000 5.085 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -182,7 +344,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.887 0.000 4.905 0.018 ; + RECT 5.607 0.000 5.625 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -191,7 +353,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.355 0.000 5.373 0.018 ; + RECT 6.147 0.000 6.165 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -200,7 +362,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.823 0.000 5.841 0.018 ; + RECT 6.687 0.000 6.705 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -209,7 +371,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.291 0.000 6.309 0.018 ; + RECT 7.227 0.000 7.245 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -218,7 +380,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.759 0.000 6.777 0.018 ; + RECT 7.767 0.000 7.785 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -227,7 +389,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.227 0.000 7.245 0.018 ; + RECT 8.307 0.000 8.325 0.054 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -236,7 +398,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.695 0.000 7.713 0.018 ; + RECT 8.847 0.000 8.865 0.054 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -245,7 +407,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.163 0.000 8.181 0.018 ; + RECT 9.387 0.000 9.405 0.054 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -254,7 +416,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 20.718 0.225 20.736 ; + RECT 3.771 46.883 3.789 46.937 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -263,7 +425,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.819 20.718 0.837 20.736 ; + RECT 4.167 46.883 4.185 46.937 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -272,7 +434,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.431 20.718 1.449 20.736 ; + RECT 4.563 46.883 4.581 46.937 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -281,7 +443,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.043 20.718 2.061 20.736 ; + RECT 4.959 46.883 4.977 46.937 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -290,7 +452,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.655 20.718 2.673 20.736 ; + RECT 5.355 46.883 5.373 46.937 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -299,7 +461,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.267 20.718 3.285 20.736 ; + RECT 5.751 46.883 5.769 46.937 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -308,7 +470,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.879 20.718 3.897 20.736 ; + RECT 6.147 46.883 6.165 46.937 ; END END r0_rd_out[15] PIN r0_rd_out[16] @@ -317,7 +479,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.491 20.718 4.509 20.736 ; + RECT 6.543 46.883 6.561 46.937 ; END END r0_rd_out[16] PIN r0_rd_out[17] @@ -326,7 +488,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.103 20.718 5.121 20.736 ; + RECT 6.939 46.883 6.957 46.937 ; END END r0_rd_out[17] PIN w0_addr_in[0] @@ -335,7 +497,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.956 0.024 7.980 ; + RECT 0.000 27.156 0.072 27.180 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -344,7 +506,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.492 0.024 9.516 ; + RECT 0.000 29.844 0.072 29.868 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -353,7 +515,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 11.028 0.024 11.052 ; + RECT 0.000 32.532 0.072 32.556 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -362,7 +524,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 12.564 0.024 12.588 ; + RECT 0.000 35.220 0.072 35.244 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -371,7 +533,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 6.420 9.332 6.444 ; + RECT 10.131 21.780 10.203 21.804 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -380,7 +542,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 7.956 9.332 7.980 ; + RECT 10.131 24.468 10.203 24.492 ; END END w0_addr_in[5] PIN w0_addr_in[6] @@ -389,7 +551,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 9.492 9.332 9.516 ; + RECT 10.131 27.156 10.203 27.180 ; END END w0_addr_in[6] PIN w0_addr_in[7] @@ -398,7 +560,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 11.028 9.332 11.052 ; + RECT 10.131 29.844 10.203 29.868 ; END END w0_addr_in[7] PIN r0_addr_in[0] @@ -407,7 +569,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 14.100 0.024 14.124 ; + RECT 0.000 37.908 0.072 37.932 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -416,7 +578,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 15.636 0.024 15.660 ; + RECT 0.000 40.596 0.072 40.620 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -425,7 +587,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 17.172 0.024 17.196 ; + RECT 0.000 43.284 0.072 43.308 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -434,7 +596,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 18.708 0.024 18.732 ; + RECT 0.000 45.972 0.072 45.996 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -443,7 +605,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 12.564 9.332 12.588 ; + RECT 10.131 32.532 10.203 32.556 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -452,7 +614,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 14.100 9.332 14.124 ; + RECT 10.131 35.220 10.203 35.244 ; END END r0_addr_in[5] PIN r0_addr_in[6] @@ -461,7 +623,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 15.636 9.332 15.660 ; + RECT 10.131 37.908 10.203 37.932 ; END END r0_addr_in[6] PIN r0_addr_in[7] @@ -470,7 +632,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 17.172 9.332 17.196 ; + RECT 10.131 40.596 10.203 40.620 ; END END r0_addr_in[7] PIN w0_we_in @@ -479,7 +641,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.715 20.718 5.733 20.736 ; + RECT 7.335 46.883 7.353 46.937 ; END END w0_we_in PIN w0_ce_in @@ -488,7 +650,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.327 20.718 6.345 20.736 ; + RECT 7.731 46.883 7.749 46.937 ; END END w0_ce_in PIN w0_clk @@ -497,7 +659,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.939 20.718 6.957 20.736 ; + RECT 8.127 46.883 8.145 46.937 ; END END w0_clk PIN r0_ce_in @@ -506,7 +668,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.551 20.718 7.569 20.736 ; + RECT 8.523 46.883 8.541 46.937 ; END END r0_ce_in PIN r0_clk @@ -515,7 +677,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.163 20.718 8.181 20.736 ; + RECT 8.919 46.883 8.937 46.937 ; END END r0_clk PIN VSS @@ -523,33 +685,67 @@ MACRO fakeram_18x256_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.108 0.192 9.224 0.288 ; - RECT 0.108 0.960 9.224 1.056 ; - RECT 0.108 1.728 9.224 1.824 ; - RECT 0.108 2.496 9.224 2.592 ; - RECT 0.108 3.264 9.224 3.360 ; - RECT 0.108 4.032 9.224 4.128 ; - RECT 0.108 4.800 9.224 4.896 ; - RECT 0.108 5.568 9.224 5.664 ; - RECT 0.108 6.336 9.224 6.432 ; - RECT 0.108 7.104 9.224 7.200 ; - RECT 0.108 7.872 9.224 7.968 ; - RECT 0.108 8.640 9.224 8.736 ; - RECT 0.108 9.408 9.224 9.504 ; - RECT 0.108 10.176 9.224 10.272 ; - RECT 0.108 10.944 9.224 11.040 ; - RECT 0.108 11.712 9.224 11.808 ; - RECT 0.108 12.480 9.224 12.576 ; - RECT 0.108 13.248 9.224 13.344 ; - RECT 0.108 14.016 9.224 14.112 ; - RECT 0.108 14.784 9.224 14.880 ; - RECT 0.108 15.552 9.224 15.648 ; - RECT 0.108 16.320 9.224 16.416 ; - RECT 0.108 17.088 9.224 17.184 ; - RECT 0.108 17.856 9.224 17.952 ; - RECT 0.108 18.624 9.224 18.720 ; - RECT 0.108 19.392 9.224 19.488 ; - RECT 0.108 20.160 9.224 20.256 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; + RECT 0.216 13.296 9.987 13.392 ; + RECT 0.216 14.064 9.987 14.160 ; + RECT 0.216 14.832 9.987 14.928 ; + RECT 0.216 15.600 9.987 15.696 ; + RECT 0.216 16.368 9.987 16.464 ; + RECT 0.216 17.136 9.987 17.232 ; + RECT 0.216 17.904 9.987 18.000 ; + RECT 0.216 18.672 9.987 18.768 ; + RECT 0.216 19.440 9.987 19.536 ; + RECT 0.216 20.208 9.987 20.304 ; + RECT 0.216 20.976 9.987 21.072 ; + RECT 0.216 21.744 9.987 21.840 ; + RECT 0.216 22.512 9.987 22.608 ; + RECT 0.216 23.280 9.987 23.376 ; + RECT 0.216 24.048 9.987 24.144 ; + RECT 0.216 24.816 9.987 24.912 ; + RECT 0.216 25.584 9.987 25.680 ; + RECT 0.216 26.352 9.987 26.448 ; + RECT 0.216 27.120 9.987 27.216 ; + RECT 0.216 27.888 9.987 27.984 ; + RECT 0.216 28.656 9.987 28.752 ; + RECT 0.216 29.424 9.987 29.520 ; + RECT 0.216 30.192 9.987 30.288 ; + RECT 0.216 30.960 9.987 31.056 ; + RECT 0.216 31.728 9.987 31.824 ; + RECT 0.216 32.496 9.987 32.592 ; + RECT 0.216 33.264 9.987 33.360 ; + RECT 0.216 34.032 9.987 34.128 ; + RECT 0.216 34.800 9.987 34.896 ; + RECT 0.216 35.568 9.987 35.664 ; + RECT 0.216 36.336 9.987 36.432 ; + RECT 0.216 37.104 9.987 37.200 ; + RECT 0.216 37.872 9.987 37.968 ; + RECT 0.216 38.640 9.987 38.736 ; + RECT 0.216 39.408 9.987 39.504 ; + RECT 0.216 40.176 9.987 40.272 ; + RECT 0.216 40.944 9.987 41.040 ; + RECT 0.216 41.712 9.987 41.808 ; + RECT 0.216 42.480 9.987 42.576 ; + RECT 0.216 43.248 9.987 43.344 ; + RECT 0.216 44.016 9.987 44.112 ; + RECT 0.216 44.784 9.987 44.880 ; + RECT 0.216 45.552 9.987 45.648 ; + RECT 0.216 46.320 9.987 46.416 ; END END VSS PIN VDD @@ -557,44 +753,78 @@ MACRO fakeram_18x256_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.108 0.192 9.224 0.288 ; - RECT 0.108 0.960 9.224 1.056 ; - RECT 0.108 1.728 9.224 1.824 ; - RECT 0.108 2.496 9.224 2.592 ; - RECT 0.108 3.264 9.224 3.360 ; - RECT 0.108 4.032 9.224 4.128 ; - RECT 0.108 4.800 9.224 4.896 ; - RECT 0.108 5.568 9.224 5.664 ; - RECT 0.108 6.336 9.224 6.432 ; - RECT 0.108 7.104 9.224 7.200 ; - RECT 0.108 7.872 9.224 7.968 ; - RECT 0.108 8.640 9.224 8.736 ; - RECT 0.108 9.408 9.224 9.504 ; - RECT 0.108 10.176 9.224 10.272 ; - RECT 0.108 10.944 9.224 11.040 ; - RECT 0.108 11.712 9.224 11.808 ; - RECT 0.108 12.480 9.224 12.576 ; - RECT 0.108 13.248 9.224 13.344 ; - RECT 0.108 14.016 9.224 14.112 ; - RECT 0.108 14.784 9.224 14.880 ; - RECT 0.108 15.552 9.224 15.648 ; - RECT 0.108 16.320 9.224 16.416 ; - RECT 0.108 17.088 9.224 17.184 ; - RECT 0.108 17.856 9.224 17.952 ; - RECT 0.108 18.624 9.224 18.720 ; - RECT 0.108 19.392 9.224 19.488 ; - RECT 0.108 20.160 9.224 20.256 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; + RECT 0.216 13.296 9.987 13.392 ; + RECT 0.216 14.064 9.987 14.160 ; + RECT 0.216 14.832 9.987 14.928 ; + RECT 0.216 15.600 9.987 15.696 ; + RECT 0.216 16.368 9.987 16.464 ; + RECT 0.216 17.136 9.987 17.232 ; + RECT 0.216 17.904 9.987 18.000 ; + RECT 0.216 18.672 9.987 18.768 ; + RECT 0.216 19.440 9.987 19.536 ; + RECT 0.216 20.208 9.987 20.304 ; + RECT 0.216 20.976 9.987 21.072 ; + RECT 0.216 21.744 9.987 21.840 ; + RECT 0.216 22.512 9.987 22.608 ; + RECT 0.216 23.280 9.987 23.376 ; + RECT 0.216 24.048 9.987 24.144 ; + RECT 0.216 24.816 9.987 24.912 ; + RECT 0.216 25.584 9.987 25.680 ; + RECT 0.216 26.352 9.987 26.448 ; + RECT 0.216 27.120 9.987 27.216 ; + RECT 0.216 27.888 9.987 27.984 ; + RECT 0.216 28.656 9.987 28.752 ; + RECT 0.216 29.424 9.987 29.520 ; + RECT 0.216 30.192 9.987 30.288 ; + RECT 0.216 30.960 9.987 31.056 ; + RECT 0.216 31.728 9.987 31.824 ; + RECT 0.216 32.496 9.987 32.592 ; + RECT 0.216 33.264 9.987 33.360 ; + RECT 0.216 34.032 9.987 34.128 ; + RECT 0.216 34.800 9.987 34.896 ; + RECT 0.216 35.568 9.987 35.664 ; + RECT 0.216 36.336 9.987 36.432 ; + RECT 0.216 37.104 9.987 37.200 ; + RECT 0.216 37.872 9.987 37.968 ; + RECT 0.216 38.640 9.987 38.736 ; + RECT 0.216 39.408 9.987 39.504 ; + RECT 0.216 40.176 9.987 40.272 ; + RECT 0.216 40.944 9.987 41.040 ; + RECT 0.216 41.712 9.987 41.808 ; + RECT 0.216 42.480 9.987 42.576 ; + RECT 0.216 43.248 9.987 43.344 ; + RECT 0.216 44.016 9.987 44.112 ; + RECT 0.216 44.784 9.987 44.880 ; + RECT 0.216 45.552 9.987 45.648 ; + RECT 0.216 46.320 9.987 46.416 ; END END VDD OBS LAYER M1 ; - RECT 0 0 9.332 20.736 ; + RECT 0 0 10.203 46.937 ; LAYER M2 ; - RECT 0 0 9.332 20.736 ; + RECT 0 0 10.203 46.937 ; LAYER M3 ; - RECT 0 0 9.332 20.736 ; + RECT 0 0 10.203 46.937 ; LAYER M4 ; - RECT 0 0 9.332 20.736 ; + RECT 0 0 10.203 46.937 ; END END fakeram_18x256_1r1w diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_1x256_1r1w.lef b/designs/asap7/NyuziProcessor/sram/lef/fakeram_1x256_1r1w.lef index ccfafef..23a3f06 100644 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_1x256_1r1w.lef +++ b/designs/asap7/NyuziProcessor/sram/lef/fakeram_1x256_1r1w.lef @@ -3,15 +3,24 @@ BUSBITCHARS "[]" ; MACRO fakeram_1x256_1r1w FOREIGN fakeram_1x256_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 5.184 BY 20.736 ; + SIZE 10.203 BY 45.432 ; CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] PIN w0_wd_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; + RECT 0.000 5.220 0.072 5.244 ; END END w0_wd_in[0] PIN r0_rd_out[0] @@ -20,7 +29,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; + RECT 0.207 0.000 0.225 0.054 ; END END r0_rd_out[0] PIN w0_addr_in[0] @@ -29,7 +38,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.484 0.024 2.508 ; + RECT 0.000 10.164 0.072 10.188 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -38,7 +47,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.692 0.024 4.716 ; + RECT 0.000 15.108 0.072 15.132 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -47,7 +56,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.900 0.024 6.924 ; + RECT 0.000 20.052 0.072 20.076 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -56,7 +65,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.108 0.024 9.132 ; + RECT 0.000 24.996 0.072 25.020 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -65,7 +74,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 5.160 0.276 5.184 0.300 ; + RECT 10.131 0.276 10.203 0.300 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -74,7 +83,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 5.160 2.484 5.184 2.508 ; + RECT 10.131 5.220 10.203 5.244 ; END END w0_addr_in[5] PIN w0_addr_in[6] @@ -83,7 +92,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 5.160 4.692 5.184 4.716 ; + RECT 10.131 10.164 10.203 10.188 ; END END w0_addr_in[6] PIN w0_addr_in[7] @@ -92,7 +101,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 5.160 6.900 5.184 6.924 ; + RECT 10.131 15.108 10.203 15.132 ; END END w0_addr_in[7] PIN r0_addr_in[0] @@ -101,7 +110,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 11.316 0.024 11.340 ; + RECT 0.000 29.940 0.072 29.964 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -110,7 +119,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 13.524 0.024 13.548 ; + RECT 0.000 34.884 0.072 34.908 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -119,7 +128,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 15.732 0.024 15.756 ; + RECT 0.000 39.828 0.072 39.852 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -128,7 +137,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 17.940 0.024 17.964 ; + RECT 0.000 44.772 0.072 44.796 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -137,7 +146,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 5.160 9.108 5.184 9.132 ; + RECT 10.131 20.052 10.203 20.076 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -146,7 +155,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 5.160 11.316 5.184 11.340 ; + RECT 10.131 24.996 10.203 25.020 ; END END r0_addr_in[5] PIN r0_addr_in[6] @@ -155,7 +164,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 5.160 13.524 5.184 13.548 ; + RECT 10.131 29.940 10.203 29.964 ; END END r0_addr_in[6] PIN r0_addr_in[7] @@ -164,7 +173,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 5.160 15.732 5.184 15.756 ; + RECT 10.131 34.884 10.203 34.908 ; END END r0_addr_in[7] PIN w0_we_in @@ -173,7 +182,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 20.718 0.225 20.736 ; + RECT 0.207 45.378 0.225 45.432 ; END END w0_we_in PIN w0_ce_in @@ -182,7 +191,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.963 20.718 0.981 20.736 ; + RECT 1.575 45.378 1.593 45.432 ; END END w0_ce_in PIN w0_clk @@ -191,7 +200,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.719 20.718 1.737 20.736 ; + RECT 2.943 45.378 2.961 45.432 ; END END w0_clk PIN r0_ce_in @@ -200,7 +209,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.475 20.718 2.493 20.736 ; + RECT 4.311 45.378 4.329 45.432 ; END END r0_ce_in PIN r0_clk @@ -209,7 +218,7 @@ MACRO fakeram_1x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.231 20.718 3.249 20.736 ; + RECT 5.679 45.378 5.697 45.432 ; END END r0_clk PIN VSS @@ -217,33 +226,65 @@ MACRO fakeram_1x256_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.108 0.192 5.076 0.288 ; - RECT 0.108 0.960 5.076 1.056 ; - RECT 0.108 1.728 5.076 1.824 ; - RECT 0.108 2.496 5.076 2.592 ; - RECT 0.108 3.264 5.076 3.360 ; - RECT 0.108 4.032 5.076 4.128 ; - RECT 0.108 4.800 5.076 4.896 ; - RECT 0.108 5.568 5.076 5.664 ; - RECT 0.108 6.336 5.076 6.432 ; - RECT 0.108 7.104 5.076 7.200 ; - RECT 0.108 7.872 5.076 7.968 ; - RECT 0.108 8.640 5.076 8.736 ; - RECT 0.108 9.408 5.076 9.504 ; - RECT 0.108 10.176 5.076 10.272 ; - RECT 0.108 10.944 5.076 11.040 ; - RECT 0.108 11.712 5.076 11.808 ; - RECT 0.108 12.480 5.076 12.576 ; - RECT 0.108 13.248 5.076 13.344 ; - RECT 0.108 14.016 5.076 14.112 ; - RECT 0.108 14.784 5.076 14.880 ; - RECT 0.108 15.552 5.076 15.648 ; - RECT 0.108 16.320 5.076 16.416 ; - RECT 0.108 17.088 5.076 17.184 ; - RECT 0.108 17.856 5.076 17.952 ; - RECT 0.108 18.624 5.076 18.720 ; - RECT 0.108 19.392 5.076 19.488 ; - RECT 0.108 20.160 5.076 20.256 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; + RECT 0.216 13.296 9.987 13.392 ; + RECT 0.216 14.064 9.987 14.160 ; + RECT 0.216 14.832 9.987 14.928 ; + RECT 0.216 15.600 9.987 15.696 ; + RECT 0.216 16.368 9.987 16.464 ; + RECT 0.216 17.136 9.987 17.232 ; + RECT 0.216 17.904 9.987 18.000 ; + RECT 0.216 18.672 9.987 18.768 ; + RECT 0.216 19.440 9.987 19.536 ; + RECT 0.216 20.208 9.987 20.304 ; + RECT 0.216 20.976 9.987 21.072 ; + RECT 0.216 21.744 9.987 21.840 ; + RECT 0.216 22.512 9.987 22.608 ; + RECT 0.216 23.280 9.987 23.376 ; + RECT 0.216 24.048 9.987 24.144 ; + RECT 0.216 24.816 9.987 24.912 ; + RECT 0.216 25.584 9.987 25.680 ; + RECT 0.216 26.352 9.987 26.448 ; + RECT 0.216 27.120 9.987 27.216 ; + RECT 0.216 27.888 9.987 27.984 ; + RECT 0.216 28.656 9.987 28.752 ; + RECT 0.216 29.424 9.987 29.520 ; + RECT 0.216 30.192 9.987 30.288 ; + RECT 0.216 30.960 9.987 31.056 ; + RECT 0.216 31.728 9.987 31.824 ; + RECT 0.216 32.496 9.987 32.592 ; + RECT 0.216 33.264 9.987 33.360 ; + RECT 0.216 34.032 9.987 34.128 ; + RECT 0.216 34.800 9.987 34.896 ; + RECT 0.216 35.568 9.987 35.664 ; + RECT 0.216 36.336 9.987 36.432 ; + RECT 0.216 37.104 9.987 37.200 ; + RECT 0.216 37.872 9.987 37.968 ; + RECT 0.216 38.640 9.987 38.736 ; + RECT 0.216 39.408 9.987 39.504 ; + RECT 0.216 40.176 9.987 40.272 ; + RECT 0.216 40.944 9.987 41.040 ; + RECT 0.216 41.712 9.987 41.808 ; + RECT 0.216 42.480 9.987 42.576 ; + RECT 0.216 43.248 9.987 43.344 ; + RECT 0.216 44.016 9.987 44.112 ; + RECT 0.216 44.784 9.987 44.880 ; END END VSS PIN VDD @@ -251,44 +292,76 @@ MACRO fakeram_1x256_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.108 0.192 5.076 0.288 ; - RECT 0.108 0.960 5.076 1.056 ; - RECT 0.108 1.728 5.076 1.824 ; - RECT 0.108 2.496 5.076 2.592 ; - RECT 0.108 3.264 5.076 3.360 ; - RECT 0.108 4.032 5.076 4.128 ; - RECT 0.108 4.800 5.076 4.896 ; - RECT 0.108 5.568 5.076 5.664 ; - RECT 0.108 6.336 5.076 6.432 ; - RECT 0.108 7.104 5.076 7.200 ; - RECT 0.108 7.872 5.076 7.968 ; - RECT 0.108 8.640 5.076 8.736 ; - RECT 0.108 9.408 5.076 9.504 ; - RECT 0.108 10.176 5.076 10.272 ; - RECT 0.108 10.944 5.076 11.040 ; - RECT 0.108 11.712 5.076 11.808 ; - RECT 0.108 12.480 5.076 12.576 ; - RECT 0.108 13.248 5.076 13.344 ; - RECT 0.108 14.016 5.076 14.112 ; - RECT 0.108 14.784 5.076 14.880 ; - RECT 0.108 15.552 5.076 15.648 ; - RECT 0.108 16.320 5.076 16.416 ; - RECT 0.108 17.088 5.076 17.184 ; - RECT 0.108 17.856 5.076 17.952 ; - RECT 0.108 18.624 5.076 18.720 ; - RECT 0.108 19.392 5.076 19.488 ; - RECT 0.108 20.160 5.076 20.256 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; + RECT 0.216 13.296 9.987 13.392 ; + RECT 0.216 14.064 9.987 14.160 ; + RECT 0.216 14.832 9.987 14.928 ; + RECT 0.216 15.600 9.987 15.696 ; + RECT 0.216 16.368 9.987 16.464 ; + RECT 0.216 17.136 9.987 17.232 ; + RECT 0.216 17.904 9.987 18.000 ; + RECT 0.216 18.672 9.987 18.768 ; + RECT 0.216 19.440 9.987 19.536 ; + RECT 0.216 20.208 9.987 20.304 ; + RECT 0.216 20.976 9.987 21.072 ; + RECT 0.216 21.744 9.987 21.840 ; + RECT 0.216 22.512 9.987 22.608 ; + RECT 0.216 23.280 9.987 23.376 ; + RECT 0.216 24.048 9.987 24.144 ; + RECT 0.216 24.816 9.987 24.912 ; + RECT 0.216 25.584 9.987 25.680 ; + RECT 0.216 26.352 9.987 26.448 ; + RECT 0.216 27.120 9.987 27.216 ; + RECT 0.216 27.888 9.987 27.984 ; + RECT 0.216 28.656 9.987 28.752 ; + RECT 0.216 29.424 9.987 29.520 ; + RECT 0.216 30.192 9.987 30.288 ; + RECT 0.216 30.960 9.987 31.056 ; + RECT 0.216 31.728 9.987 31.824 ; + RECT 0.216 32.496 9.987 32.592 ; + RECT 0.216 33.264 9.987 33.360 ; + RECT 0.216 34.032 9.987 34.128 ; + RECT 0.216 34.800 9.987 34.896 ; + RECT 0.216 35.568 9.987 35.664 ; + RECT 0.216 36.336 9.987 36.432 ; + RECT 0.216 37.104 9.987 37.200 ; + RECT 0.216 37.872 9.987 37.968 ; + RECT 0.216 38.640 9.987 38.736 ; + RECT 0.216 39.408 9.987 39.504 ; + RECT 0.216 40.176 9.987 40.272 ; + RECT 0.216 40.944 9.987 41.040 ; + RECT 0.216 41.712 9.987 41.808 ; + RECT 0.216 42.480 9.987 42.576 ; + RECT 0.216 43.248 9.987 43.344 ; + RECT 0.216 44.016 9.987 44.112 ; + RECT 0.216 44.784 9.987 44.880 ; END END VDD OBS LAYER M1 ; - RECT 0 0 5.184 20.736 ; + RECT 0 0 10.203 45.432 ; LAYER M2 ; - RECT 0 0 5.184 20.736 ; + RECT 0 0 10.203 45.432 ; LAYER M3 ; - RECT 0 0 5.184 20.736 ; + RECT 0 0 10.203 45.432 ; LAYER M4 ; - RECT 0 0 5.184 20.736 ; + RECT 0 0 10.203 45.432 ; END END fakeram_1x256_1r1w diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_1r1w.lef b/designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_1r1w.lef index 4431806..89cf753 100644 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_1r1w.lef +++ b/designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_1r1w.lef @@ -3,15 +3,195 @@ BUSBITCHARS "[]" ; MACRO fakeram_20x64_1r1w FOREIGN fakeram_20x64_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 10.368 BY 5.184 ; + SIZE 10.203 BY 13.107 ; CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.044 0.072 1.068 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.812 0.072 1.836 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.348 0.072 3.372 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 0.276 10.203 0.300 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 1.044 10.203 1.068 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 1.812 10.203 1.836 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 2.580 10.203 2.604 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 3.348 10.203 3.372 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 13.053 0.225 13.107 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.567 13.053 0.585 13.107 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 13.053 0.945 13.107 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 13.053 1.305 13.107 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 13.053 1.665 13.107 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 13.053 2.025 13.107 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 13.053 2.385 13.107 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 13.053 2.745 13.107 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 13.053 3.105 13.107 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 13.053 3.465 13.107 ; + END + END w0_wmask_in[19] PIN w0_wd_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; + RECT 0.000 4.116 0.072 4.140 ; END END w0_wd_in[0] PIN w0_wd_in[1] @@ -20,7 +200,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.660 0.024 0.684 ; + RECT 0.000 4.884 0.072 4.908 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +209,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.044 0.024 1.068 ; + RECT 0.000 5.652 0.072 5.676 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +218,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.428 0.024 1.452 ; + RECT 0.000 6.420 0.072 6.444 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +227,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.812 0.024 1.836 ; + RECT 0.000 7.188 0.072 7.212 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +236,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 0.276 10.368 0.300 ; + RECT 10.131 4.116 10.203 4.140 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +245,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 0.660 10.368 0.684 ; + RECT 10.131 4.884 10.203 4.908 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +254,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 1.044 10.368 1.068 ; + RECT 10.131 5.652 10.203 5.676 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +263,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 1.428 10.368 1.452 ; + RECT 10.131 6.420 10.203 6.444 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,7 +272,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 1.812 10.368 1.836 ; + RECT 10.131 7.188 10.203 7.212 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,7 +281,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; + RECT 0.207 0.000 0.225 0.054 ; END END w0_wd_in[10] PIN w0_wd_in[11] @@ -110,7 +290,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.675 0.000 0.693 0.018 ; + RECT 0.675 0.000 0.693 0.054 ; END END w0_wd_in[11] PIN w0_wd_in[12] @@ -119,7 +299,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.143 0.000 1.161 0.018 ; + RECT 1.143 0.000 1.161 0.054 ; END END w0_wd_in[12] PIN w0_wd_in[13] @@ -128,7 +308,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.611 0.000 1.629 0.018 ; + RECT 1.611 0.000 1.629 0.054 ; END END w0_wd_in[13] PIN w0_wd_in[14] @@ -137,7 +317,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.079 0.000 2.097 0.018 ; + RECT 2.079 0.000 2.097 0.054 ; END END w0_wd_in[14] PIN w0_wd_in[15] @@ -146,7 +326,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.547 0.000 2.565 0.018 ; + RECT 2.547 0.000 2.565 0.054 ; END END w0_wd_in[15] PIN w0_wd_in[16] @@ -155,7 +335,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.015 0.000 3.033 0.018 ; + RECT 3.015 0.000 3.033 0.054 ; END END w0_wd_in[16] PIN w0_wd_in[17] @@ -164,7 +344,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.483 0.000 3.501 0.018 ; + RECT 3.483 0.000 3.501 0.054 ; END END w0_wd_in[17] PIN w0_wd_in[18] @@ -173,7 +353,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.951 0.000 3.969 0.018 ; + RECT 3.951 0.000 3.969 0.054 ; END END w0_wd_in[18] PIN w0_wd_in[19] @@ -182,7 +362,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.419 0.000 4.437 0.018 ; + RECT 4.419 0.000 4.437 0.054 ; END END w0_wd_in[19] PIN r0_rd_out[0] @@ -191,7 +371,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.887 0.000 4.905 0.018 ; + RECT 4.887 0.000 4.905 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -200,7 +380,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.355 0.000 5.373 0.018 ; + RECT 5.355 0.000 5.373 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -209,7 +389,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.823 0.000 5.841 0.018 ; + RECT 5.823 0.000 5.841 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -218,7 +398,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.291 0.000 6.309 0.018 ; + RECT 6.291 0.000 6.309 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -227,7 +407,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.759 0.000 6.777 0.018 ; + RECT 6.759 0.000 6.777 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -236,7 +416,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.227 0.000 7.245 0.018 ; + RECT 7.227 0.000 7.245 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -245,7 +425,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.695 0.000 7.713 0.018 ; + RECT 7.695 0.000 7.713 0.054 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -254,7 +434,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.163 0.000 8.181 0.018 ; + RECT 8.163 0.000 8.181 0.054 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -263,7 +443,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.631 0.000 8.649 0.018 ; + RECT 8.631 0.000 8.649 0.054 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -272,7 +452,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.099 0.000 9.117 0.018 ; + RECT 9.099 0.000 9.117 0.054 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -281,7 +461,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 5.166 0.225 5.184 ; + RECT 3.807 13.053 3.825 13.107 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -290,7 +470,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.855 5.166 0.873 5.184 ; + RECT 4.167 13.053 4.185 13.107 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -299,7 +479,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.503 5.166 1.521 5.184 ; + RECT 4.527 13.053 4.545 13.107 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -308,7 +488,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.151 5.166 2.169 5.184 ; + RECT 4.887 13.053 4.905 13.107 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -317,7 +497,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.799 5.166 2.817 5.184 ; + RECT 5.247 13.053 5.265 13.107 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -326,7 +506,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.447 5.166 3.465 5.184 ; + RECT 5.607 13.053 5.625 13.107 ; END END r0_rd_out[15] PIN r0_rd_out[16] @@ -335,7 +515,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.095 5.166 4.113 5.184 ; + RECT 5.967 13.053 5.985 13.107 ; END END r0_rd_out[16] PIN r0_rd_out[17] @@ -344,7 +524,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.743 5.166 4.761 5.184 ; + RECT 6.327 13.053 6.345 13.107 ; END END r0_rd_out[17] PIN r0_rd_out[18] @@ -353,7 +533,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.391 5.166 5.409 5.184 ; + RECT 6.687 13.053 6.705 13.107 ; END END r0_rd_out[18] PIN r0_rd_out[19] @@ -362,7 +542,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.039 5.166 6.057 5.184 ; + RECT 7.047 13.053 7.065 13.107 ; END END r0_rd_out[19] PIN w0_addr_in[0] @@ -371,7 +551,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.196 0.024 2.220 ; + RECT 0.000 7.956 0.072 7.980 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -380,7 +560,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.580 0.024 2.604 ; + RECT 0.000 8.724 0.072 8.748 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -389,7 +569,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.964 0.024 2.988 ; + RECT 0.000 9.492 0.072 9.516 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -398,7 +578,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 2.196 10.368 2.220 ; + RECT 10.131 7.956 10.203 7.980 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -407,7 +587,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 2.580 10.368 2.604 ; + RECT 10.131 8.724 10.203 8.748 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -416,7 +596,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 2.964 10.368 2.988 ; + RECT 10.131 9.492 10.203 9.516 ; END END w0_addr_in[5] PIN r0_addr_in[0] @@ -425,7 +605,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.348 0.024 3.372 ; + RECT 0.000 10.260 0.072 10.284 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -434,7 +614,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.732 0.024 3.756 ; + RECT 0.000 11.028 0.072 11.052 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -443,7 +623,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.116 0.024 4.140 ; + RECT 0.000 11.796 0.072 11.820 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -452,7 +632,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 3.348 10.368 3.372 ; + RECT 10.131 10.260 10.203 10.284 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -461,7 +641,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 3.732 10.368 3.756 ; + RECT 10.131 11.028 10.203 11.052 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -470,7 +650,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 4.116 10.368 4.140 ; + RECT 10.131 11.796 10.203 11.820 ; END END r0_addr_in[5] PIN w0_we_in @@ -479,7 +659,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.687 5.166 6.705 5.184 ; + RECT 7.407 13.053 7.425 13.107 ; END END w0_we_in PIN w0_ce_in @@ -488,7 +668,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.335 5.166 7.353 5.184 ; + RECT 7.767 13.053 7.785 13.107 ; END END w0_ce_in PIN w0_clk @@ -497,7 +677,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.983 5.166 8.001 5.184 ; + RECT 8.127 13.053 8.145 13.107 ; END END w0_clk PIN r0_ce_in @@ -506,7 +686,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.631 5.166 8.649 5.184 ; + RECT 8.487 13.053 8.505 13.107 ; END END r0_ce_in PIN r0_clk @@ -515,7 +695,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.279 5.166 9.297 5.184 ; + RECT 8.847 13.053 8.865 13.107 ; END END r0_clk PIN VSS @@ -523,13 +703,23 @@ MACRO fakeram_20x64_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.108 0.192 10.260 0.288 ; - RECT 0.108 0.960 10.260 1.056 ; - RECT 0.108 1.728 10.260 1.824 ; - RECT 0.108 2.496 10.260 2.592 ; - RECT 0.108 3.264 10.260 3.360 ; - RECT 0.108 4.032 10.260 4.128 ; - RECT 0.108 4.800 10.260 4.896 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; END END VSS PIN VDD @@ -537,24 +727,34 @@ MACRO fakeram_20x64_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.108 0.192 10.260 0.288 ; - RECT 0.108 0.960 10.260 1.056 ; - RECT 0.108 1.728 10.260 1.824 ; - RECT 0.108 2.496 10.260 2.592 ; - RECT 0.108 3.264 10.260 3.360 ; - RECT 0.108 4.032 10.260 4.128 ; - RECT 0.108 4.800 10.260 4.896 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; END END VDD OBS LAYER M1 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 10.203 13.107 ; LAYER M2 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 10.203 13.107 ; LAYER M3 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 10.203 13.107 ; LAYER M4 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 10.203 13.107 ; END END fakeram_20x64_1r1w diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_2r1w.lef b/designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_2r1w.lef index 06ae066..d7226c4 100644 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_2r1w.lef +++ b/designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_2r1w.lef @@ -3,15 +3,195 @@ BUSBITCHARS "[]" ; MACRO fakeram_20x64_2r1w FOREIGN fakeram_20x64_2r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 10.368 BY 5.184 ; + SIZE 12.069 BY 15.505 ; CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.044 0.072 1.068 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.812 0.072 1.836 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.348 0.072 3.372 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.997 0.276 12.069 0.300 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.997 1.044 12.069 1.068 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.997 1.812 12.069 1.836 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.997 2.580 12.069 2.604 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.997 3.348 12.069 3.372 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 15.451 0.225 15.505 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 15.451 0.513 15.505 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 15.451 0.801 15.505 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 15.451 1.089 15.505 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 15.451 1.377 15.505 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 15.451 1.665 15.505 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 15.451 1.953 15.505 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 15.451 2.241 15.505 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 15.451 2.529 15.505 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 15.451 2.817 15.505 ; + END + END w0_wmask_in[19] PIN w0_wd_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; + RECT 0.000 4.116 0.072 4.140 ; END END w0_wd_in[0] PIN w0_wd_in[1] @@ -20,7 +200,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.564 0.024 0.588 ; + RECT 0.000 4.884 0.072 4.908 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +209,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.852 0.024 0.876 ; + RECT 0.000 5.652 0.072 5.676 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +218,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.140 0.024 1.164 ; + RECT 0.000 6.420 0.072 6.444 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +227,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.428 0.024 1.452 ; + RECT 0.000 7.188 0.072 7.212 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +236,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 0.276 10.368 0.300 ; + RECT 11.997 4.116 12.069 4.140 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +245,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 0.564 10.368 0.588 ; + RECT 11.997 4.884 12.069 4.908 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +254,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 0.852 10.368 0.876 ; + RECT 11.997 5.652 12.069 5.676 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +263,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 1.140 10.368 1.164 ; + RECT 11.997 6.420 12.069 6.444 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,7 +272,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 1.428 10.368 1.452 ; + RECT 11.997 7.188 12.069 7.212 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,7 +281,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; + RECT 0.207 0.000 0.225 0.054 ; END END w0_wd_in[10] PIN w0_wd_in[11] @@ -110,7 +290,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.531 0.000 0.549 0.018 ; + RECT 0.567 0.000 0.585 0.054 ; END END w0_wd_in[11] PIN w0_wd_in[12] @@ -119,7 +299,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.855 0.000 0.873 0.018 ; + RECT 0.927 0.000 0.945 0.054 ; END END w0_wd_in[12] PIN w0_wd_in[13] @@ -128,7 +308,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.179 0.000 1.197 0.018 ; + RECT 1.287 0.000 1.305 0.054 ; END END w0_wd_in[13] PIN w0_wd_in[14] @@ -137,7 +317,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.503 0.000 1.521 0.018 ; + RECT 1.647 0.000 1.665 0.054 ; END END w0_wd_in[14] PIN w0_wd_in[15] @@ -146,7 +326,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.827 0.000 1.845 0.018 ; + RECT 2.007 0.000 2.025 0.054 ; END END w0_wd_in[15] PIN w0_wd_in[16] @@ -155,7 +335,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.151 0.000 2.169 0.018 ; + RECT 2.367 0.000 2.385 0.054 ; END END w0_wd_in[16] PIN w0_wd_in[17] @@ -164,7 +344,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.475 0.000 2.493 0.018 ; + RECT 2.727 0.000 2.745 0.054 ; END END w0_wd_in[17] PIN w0_wd_in[18] @@ -173,7 +353,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.799 0.000 2.817 0.018 ; + RECT 3.087 0.000 3.105 0.054 ; END END w0_wd_in[18] PIN w0_wd_in[19] @@ -182,7 +362,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.123 0.000 3.141 0.018 ; + RECT 3.447 0.000 3.465 0.054 ; END END w0_wd_in[19] PIN r0_rd_out[0] @@ -191,7 +371,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.447 0.000 3.465 0.018 ; + RECT 3.807 0.000 3.825 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -200,7 +380,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.771 0.000 3.789 0.018 ; + RECT 4.167 0.000 4.185 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -209,7 +389,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.095 0.000 4.113 0.018 ; + RECT 4.527 0.000 4.545 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -218,7 +398,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.419 0.000 4.437 0.018 ; + RECT 4.887 0.000 4.905 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -227,7 +407,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.743 0.000 4.761 0.018 ; + RECT 5.247 0.000 5.265 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -236,7 +416,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.067 0.000 5.085 0.018 ; + RECT 5.607 0.000 5.625 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -245,7 +425,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.391 0.000 5.409 0.018 ; + RECT 5.967 0.000 5.985 0.054 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -254,7 +434,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.715 0.000 5.733 0.018 ; + RECT 6.327 0.000 6.345 0.054 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -263,7 +443,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.039 0.000 6.057 0.018 ; + RECT 6.687 0.000 6.705 0.054 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -272,7 +452,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.363 0.000 6.381 0.018 ; + RECT 7.047 0.000 7.065 0.054 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -281,7 +461,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 5.166 0.225 5.184 ; + RECT 3.087 15.451 3.105 15.505 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -290,7 +470,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.567 5.166 0.585 5.184 ; + RECT 3.375 15.451 3.393 15.505 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -299,7 +479,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.927 5.166 0.945 5.184 ; + RECT 3.663 15.451 3.681 15.505 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -308,7 +488,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.287 5.166 1.305 5.184 ; + RECT 3.951 15.451 3.969 15.505 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -317,7 +497,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.647 5.166 1.665 5.184 ; + RECT 4.239 15.451 4.257 15.505 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -326,7 +506,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.007 5.166 2.025 5.184 ; + RECT 4.527 15.451 4.545 15.505 ; END END r0_rd_out[15] PIN r0_rd_out[16] @@ -335,7 +515,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.367 5.166 2.385 5.184 ; + RECT 4.815 15.451 4.833 15.505 ; END END r0_rd_out[16] PIN r0_rd_out[17] @@ -344,7 +524,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.727 5.166 2.745 5.184 ; + RECT 5.103 15.451 5.121 15.505 ; END END r0_rd_out[17] PIN r0_rd_out[18] @@ -353,7 +533,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.087 5.166 3.105 5.184 ; + RECT 5.391 15.451 5.409 15.505 ; END END r0_rd_out[18] PIN r0_rd_out[19] @@ -362,7 +542,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.447 5.166 3.465 5.184 ; + RECT 5.679 15.451 5.697 15.505 ; END END r0_rd_out[19] PIN r1_rd_out[0] @@ -371,7 +551,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.687 0.000 6.705 0.018 ; + RECT 7.407 0.000 7.425 0.054 ; END END r1_rd_out[0] PIN r1_rd_out[1] @@ -380,7 +560,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.011 0.000 7.029 0.018 ; + RECT 7.767 0.000 7.785 0.054 ; END END r1_rd_out[1] PIN r1_rd_out[2] @@ -389,7 +569,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.335 0.000 7.353 0.018 ; + RECT 8.127 0.000 8.145 0.054 ; END END r1_rd_out[2] PIN r1_rd_out[3] @@ -398,7 +578,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.659 0.000 7.677 0.018 ; + RECT 8.487 0.000 8.505 0.054 ; END END r1_rd_out[3] PIN r1_rd_out[4] @@ -407,7 +587,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.983 0.000 8.001 0.018 ; + RECT 8.847 0.000 8.865 0.054 ; END END r1_rd_out[4] PIN r1_rd_out[5] @@ -416,7 +596,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.307 0.000 8.325 0.018 ; + RECT 9.207 0.000 9.225 0.054 ; END END r1_rd_out[5] PIN r1_rd_out[6] @@ -425,7 +605,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.631 0.000 8.649 0.018 ; + RECT 9.567 0.000 9.585 0.054 ; END END r1_rd_out[6] PIN r1_rd_out[7] @@ -434,7 +614,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.955 0.000 8.973 0.018 ; + RECT 9.927 0.000 9.945 0.054 ; END END r1_rd_out[7] PIN r1_rd_out[8] @@ -443,7 +623,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.279 0.000 9.297 0.018 ; + RECT 10.287 0.000 10.305 0.054 ; END END r1_rd_out[8] PIN r1_rd_out[9] @@ -452,7 +632,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.603 0.000 9.621 0.018 ; + RECT 10.647 0.000 10.665 0.054 ; END END r1_rd_out[9] PIN r1_rd_out[10] @@ -461,7 +641,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.807 5.166 3.825 5.184 ; + RECT 5.967 15.451 5.985 15.505 ; END END r1_rd_out[10] PIN r1_rd_out[11] @@ -470,7 +650,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.167 5.166 4.185 5.184 ; + RECT 6.255 15.451 6.273 15.505 ; END END r1_rd_out[11] PIN r1_rd_out[12] @@ -479,7 +659,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.527 5.166 4.545 5.184 ; + RECT 6.543 15.451 6.561 15.505 ; END END r1_rd_out[12] PIN r1_rd_out[13] @@ -488,7 +668,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.887 5.166 4.905 5.184 ; + RECT 6.831 15.451 6.849 15.505 ; END END r1_rd_out[13] PIN r1_rd_out[14] @@ -497,7 +677,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.247 5.166 5.265 5.184 ; + RECT 7.119 15.451 7.137 15.505 ; END END r1_rd_out[14] PIN r1_rd_out[15] @@ -506,7 +686,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.607 5.166 5.625 5.184 ; + RECT 7.407 15.451 7.425 15.505 ; END END r1_rd_out[15] PIN r1_rd_out[16] @@ -515,7 +695,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.967 5.166 5.985 5.184 ; + RECT 7.695 15.451 7.713 15.505 ; END END r1_rd_out[16] PIN r1_rd_out[17] @@ -524,7 +704,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.327 5.166 6.345 5.184 ; + RECT 7.983 15.451 8.001 15.505 ; END END r1_rd_out[17] PIN r1_rd_out[18] @@ -533,7 +713,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.687 5.166 6.705 5.184 ; + RECT 8.271 15.451 8.289 15.505 ; END END r1_rd_out[18] PIN r1_rd_out[19] @@ -542,7 +722,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.047 5.166 7.065 5.184 ; + RECT 8.559 15.451 8.577 15.505 ; END END r1_rd_out[19] PIN w0_addr_in[0] @@ -551,7 +731,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.716 0.024 1.740 ; + RECT 0.000 7.956 0.072 7.980 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -560,7 +740,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.004 0.024 2.028 ; + RECT 0.000 8.724 0.072 8.748 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -569,7 +749,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.292 0.024 2.316 ; + RECT 0.000 9.492 0.072 9.516 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -578,7 +758,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 1.716 10.368 1.740 ; + RECT 11.997 7.956 12.069 7.980 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -587,7 +767,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 2.004 10.368 2.028 ; + RECT 11.997 8.724 12.069 8.748 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -596,7 +776,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 2.292 10.368 2.316 ; + RECT 11.997 9.492 12.069 9.516 ; END END w0_addr_in[5] PIN r0_addr_in[0] @@ -605,7 +785,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.580 0.024 2.604 ; + RECT 0.000 10.260 0.072 10.284 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -614,7 +794,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.868 0.024 2.892 ; + RECT 0.000 11.028 0.072 11.052 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -623,7 +803,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.156 0.024 3.180 ; + RECT 0.000 11.796 0.072 11.820 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -632,7 +812,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 2.580 10.368 2.604 ; + RECT 11.997 10.260 12.069 10.284 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -641,7 +821,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 2.868 10.368 2.892 ; + RECT 11.997 11.028 12.069 11.052 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -650,7 +830,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 3.156 10.368 3.180 ; + RECT 11.997 11.796 12.069 11.820 ; END END r0_addr_in[5] PIN r1_addr_in[0] @@ -659,7 +839,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.444 0.024 3.468 ; + RECT 0.000 12.564 0.072 12.588 ; END END r1_addr_in[0] PIN r1_addr_in[1] @@ -668,7 +848,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.732 0.024 3.756 ; + RECT 0.000 13.332 0.072 13.356 ; END END r1_addr_in[1] PIN r1_addr_in[2] @@ -677,7 +857,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.020 0.024 4.044 ; + RECT 0.000 14.100 0.072 14.124 ; END END r1_addr_in[2] PIN r1_addr_in[3] @@ -686,7 +866,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 3.444 10.368 3.468 ; + RECT 11.997 12.564 12.069 12.588 ; END END r1_addr_in[3] PIN r1_addr_in[4] @@ -695,7 +875,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 3.732 10.368 3.756 ; + RECT 11.997 13.332 12.069 13.356 ; END END r1_addr_in[4] PIN r1_addr_in[5] @@ -704,7 +884,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 4.020 10.368 4.044 ; + RECT 11.997 14.100 12.069 14.124 ; END END r1_addr_in[5] PIN w0_we_in @@ -713,7 +893,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.407 5.166 7.425 5.184 ; + RECT 8.847 15.451 8.865 15.505 ; END END w0_we_in PIN w0_ce_in @@ -722,7 +902,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.767 5.166 7.785 5.184 ; + RECT 9.135 15.451 9.153 15.505 ; END END w0_ce_in PIN w0_clk @@ -731,7 +911,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.127 5.166 8.145 5.184 ; + RECT 9.423 15.451 9.441 15.505 ; END END w0_clk PIN r0_ce_in @@ -740,7 +920,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.487 5.166 8.505 5.184 ; + RECT 9.711 15.451 9.729 15.505 ; END END r0_ce_in PIN r0_clk @@ -749,7 +929,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.847 5.166 8.865 5.184 ; + RECT 9.999 15.451 10.017 15.505 ; END END r0_clk PIN r1_ce_in @@ -758,7 +938,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.207 5.166 9.225 5.184 ; + RECT 10.287 15.451 10.305 15.505 ; END END r1_ce_in PIN r1_clk @@ -767,7 +947,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.567 5.166 9.585 5.184 ; + RECT 10.575 15.451 10.593 15.505 ; END END r1_clk PIN VSS @@ -775,13 +955,26 @@ MACRO fakeram_20x64_2r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.108 0.192 10.260 0.288 ; - RECT 0.108 0.960 10.260 1.056 ; - RECT 0.108 1.728 10.260 1.824 ; - RECT 0.108 2.496 10.260 2.592 ; - RECT 0.108 3.264 10.260 3.360 ; - RECT 0.108 4.032 10.260 4.128 ; - RECT 0.108 4.800 10.260 4.896 ; + RECT 0.216 0.240 11.853 0.336 ; + RECT 0.216 1.008 11.853 1.104 ; + RECT 0.216 1.776 11.853 1.872 ; + RECT 0.216 2.544 11.853 2.640 ; + RECT 0.216 3.312 11.853 3.408 ; + RECT 0.216 4.080 11.853 4.176 ; + RECT 0.216 4.848 11.853 4.944 ; + RECT 0.216 5.616 11.853 5.712 ; + RECT 0.216 6.384 11.853 6.480 ; + RECT 0.216 7.152 11.853 7.248 ; + RECT 0.216 7.920 11.853 8.016 ; + RECT 0.216 8.688 11.853 8.784 ; + RECT 0.216 9.456 11.853 9.552 ; + RECT 0.216 10.224 11.853 10.320 ; + RECT 0.216 10.992 11.853 11.088 ; + RECT 0.216 11.760 11.853 11.856 ; + RECT 0.216 12.528 11.853 12.624 ; + RECT 0.216 13.296 11.853 13.392 ; + RECT 0.216 14.064 11.853 14.160 ; + RECT 0.216 14.832 11.853 14.928 ; END END VSS PIN VDD @@ -789,24 +982,37 @@ MACRO fakeram_20x64_2r1w USE POWER ; PORT LAYER M4 ; - RECT 0.108 0.192 10.260 0.288 ; - RECT 0.108 0.960 10.260 1.056 ; - RECT 0.108 1.728 10.260 1.824 ; - RECT 0.108 2.496 10.260 2.592 ; - RECT 0.108 3.264 10.260 3.360 ; - RECT 0.108 4.032 10.260 4.128 ; - RECT 0.108 4.800 10.260 4.896 ; + RECT 0.216 0.240 11.853 0.336 ; + RECT 0.216 1.008 11.853 1.104 ; + RECT 0.216 1.776 11.853 1.872 ; + RECT 0.216 2.544 11.853 2.640 ; + RECT 0.216 3.312 11.853 3.408 ; + RECT 0.216 4.080 11.853 4.176 ; + RECT 0.216 4.848 11.853 4.944 ; + RECT 0.216 5.616 11.853 5.712 ; + RECT 0.216 6.384 11.853 6.480 ; + RECT 0.216 7.152 11.853 7.248 ; + RECT 0.216 7.920 11.853 8.016 ; + RECT 0.216 8.688 11.853 8.784 ; + RECT 0.216 9.456 11.853 9.552 ; + RECT 0.216 10.224 11.853 10.320 ; + RECT 0.216 10.992 11.853 11.088 ; + RECT 0.216 11.760 11.853 11.856 ; + RECT 0.216 12.528 11.853 12.624 ; + RECT 0.216 13.296 11.853 13.392 ; + RECT 0.216 14.064 11.853 14.160 ; + RECT 0.216 14.832 11.853 14.928 ; END END VDD OBS LAYER M1 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 12.069 15.505 ; LAYER M2 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 12.069 15.505 ; LAYER M3 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 12.069 15.505 ; LAYER M4 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 12.069 15.505 ; END END fakeram_20x64_2r1w diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_32x128_2r1w.lef b/designs/asap7/NyuziProcessor/sram/lef/fakeram_32x128_2r1w.lef index 9dd70c8..85a270b 100644 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_32x128_2r1w.lef +++ b/designs/asap7/NyuziProcessor/sram/lef/fakeram_32x128_2r1w.lef @@ -3,15 +3,303 @@ BUSBITCHARS "[]" ; MACRO fakeram_32x128_2r1w FOREIGN fakeram_32x128_2r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 16.589 BY 10.368 ; + SIZE 12.069 BY 30.171 ; CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.332 0.072 1.356 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.388 0.072 2.412 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.444 0.072 3.468 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.500 0.072 4.524 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.556 0.072 5.580 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.997 0.276 12.069 0.300 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.997 1.332 12.069 1.356 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.997 2.388 12.069 2.412 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.997 3.444 12.069 3.468 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.997 4.500 12.069 4.524 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.997 5.556 12.069 5.580 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.997 6.612 12.069 6.636 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.997 7.668 12.069 7.692 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 30.117 0.225 30.171 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.387 30.117 0.405 30.171 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.567 30.117 0.585 30.171 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 30.117 0.765 30.171 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 30.117 0.945 30.171 ; + END + END w0_wmask_in[20] + PIN w0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 30.117 1.125 30.171 ; + END + END w0_wmask_in[21] + PIN w0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 30.117 1.305 30.171 ; + END + END w0_wmask_in[22] + PIN w0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.467 30.117 1.485 30.171 ; + END + END w0_wmask_in[23] + PIN w0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 30.117 1.665 30.171 ; + END + END w0_wmask_in[24] + PIN w0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 30.117 1.845 30.171 ; + END + END w0_wmask_in[25] + PIN w0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 30.117 2.025 30.171 ; + END + END w0_wmask_in[26] + PIN w0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.187 30.117 2.205 30.171 ; + END + END w0_wmask_in[27] + PIN w0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 30.117 2.385 30.171 ; + END + END w0_wmask_in[28] + PIN w0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.547 30.117 2.565 30.171 ; + END + END w0_wmask_in[29] + PIN w0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 30.117 2.745 30.171 ; + END + END w0_wmask_in[30] + PIN w0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 30.117 2.925 30.171 ; + END + END w0_wmask_in[31] PIN w0_wd_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; + RECT 0.000 8.724 0.072 8.748 ; END END w0_wd_in[0] PIN w0_wd_in[1] @@ -20,7 +308,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.756 0.024 0.780 ; + RECT 0.000 9.780 0.072 9.804 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +317,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.236 0.024 1.260 ; + RECT 0.000 10.836 0.072 10.860 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +326,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.716 0.024 1.740 ; + RECT 0.000 11.892 0.072 11.916 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +335,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.196 0.024 2.220 ; + RECT 0.000 12.948 0.072 12.972 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +344,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.676 0.024 2.700 ; + RECT 0.000 14.004 0.072 14.028 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +353,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.156 0.024 3.180 ; + RECT 0.000 15.060 0.072 15.084 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +362,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.636 0.024 3.660 ; + RECT 0.000 16.116 0.072 16.140 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +371,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 0.276 16.589 0.300 ; + RECT 11.997 8.724 12.069 8.748 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,7 +380,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 0.756 16.589 0.780 ; + RECT 11.997 9.780 12.069 9.804 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,7 +389,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 1.236 16.589 1.260 ; + RECT 11.997 10.836 12.069 10.860 ; END END w0_wd_in[10] PIN w0_wd_in[11] @@ -110,7 +398,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 1.716 16.589 1.740 ; + RECT 11.997 11.892 12.069 11.916 ; END END w0_wd_in[11] PIN w0_wd_in[12] @@ -119,7 +407,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 2.196 16.589 2.220 ; + RECT 11.997 12.948 12.069 12.972 ; END END w0_wd_in[12] PIN w0_wd_in[13] @@ -128,7 +416,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 2.676 16.589 2.700 ; + RECT 11.997 14.004 12.069 14.028 ; END END w0_wd_in[13] PIN w0_wd_in[14] @@ -137,7 +425,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 3.156 16.589 3.180 ; + RECT 11.997 15.060 12.069 15.084 ; END END w0_wd_in[14] PIN w0_wd_in[15] @@ -146,7 +434,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 3.636 16.589 3.660 ; + RECT 11.997 16.116 12.069 16.140 ; END END w0_wd_in[15] PIN w0_wd_in[16] @@ -155,7 +443,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; + RECT 0.207 0.000 0.225 0.054 ; END END w0_wd_in[16] PIN w0_wd_in[17] @@ -164,7 +452,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.531 0.000 0.549 0.018 ; + RECT 0.423 0.000 0.441 0.054 ; END END w0_wd_in[17] PIN w0_wd_in[18] @@ -173,7 +461,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.855 0.000 0.873 0.018 ; + RECT 0.639 0.000 0.657 0.054 ; END END w0_wd_in[18] PIN w0_wd_in[19] @@ -182,7 +470,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.179 0.000 1.197 0.018 ; + RECT 0.855 0.000 0.873 0.054 ; END END w0_wd_in[19] PIN w0_wd_in[20] @@ -191,7 +479,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.503 0.000 1.521 0.018 ; + RECT 1.071 0.000 1.089 0.054 ; END END w0_wd_in[20] PIN w0_wd_in[21] @@ -200,7 +488,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.827 0.000 1.845 0.018 ; + RECT 1.287 0.000 1.305 0.054 ; END END w0_wd_in[21] PIN w0_wd_in[22] @@ -209,7 +497,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.151 0.000 2.169 0.018 ; + RECT 1.503 0.000 1.521 0.054 ; END END w0_wd_in[22] PIN w0_wd_in[23] @@ -218,7 +506,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.475 0.000 2.493 0.018 ; + RECT 1.719 0.000 1.737 0.054 ; END END w0_wd_in[23] PIN w0_wd_in[24] @@ -227,7 +515,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.799 0.000 2.817 0.018 ; + RECT 1.935 0.000 1.953 0.054 ; END END w0_wd_in[24] PIN w0_wd_in[25] @@ -236,7 +524,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.123 0.000 3.141 0.018 ; + RECT 2.151 0.000 2.169 0.054 ; END END w0_wd_in[25] PIN w0_wd_in[26] @@ -245,7 +533,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.447 0.000 3.465 0.018 ; + RECT 2.367 0.000 2.385 0.054 ; END END w0_wd_in[26] PIN w0_wd_in[27] @@ -254,7 +542,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.771 0.000 3.789 0.018 ; + RECT 2.583 0.000 2.601 0.054 ; END END w0_wd_in[27] PIN w0_wd_in[28] @@ -263,7 +551,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.095 0.000 4.113 0.018 ; + RECT 2.799 0.000 2.817 0.054 ; END END w0_wd_in[28] PIN w0_wd_in[29] @@ -272,7 +560,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.419 0.000 4.437 0.018 ; + RECT 3.015 0.000 3.033 0.054 ; END END w0_wd_in[29] PIN w0_wd_in[30] @@ -281,7 +569,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.743 0.000 4.761 0.018 ; + RECT 3.231 0.000 3.249 0.054 ; END END w0_wd_in[30] PIN w0_wd_in[31] @@ -290,7 +578,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.067 0.000 5.085 0.018 ; + RECT 3.447 0.000 3.465 0.054 ; END END w0_wd_in[31] PIN r0_rd_out[0] @@ -299,7 +587,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.391 0.000 5.409 0.018 ; + RECT 3.663 0.000 3.681 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -308,7 +596,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.715 0.000 5.733 0.018 ; + RECT 3.879 0.000 3.897 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -317,7 +605,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.039 0.000 6.057 0.018 ; + RECT 4.095 0.000 4.113 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -326,7 +614,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.363 0.000 6.381 0.018 ; + RECT 4.311 0.000 4.329 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -335,7 +623,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.687 0.000 6.705 0.018 ; + RECT 4.527 0.000 4.545 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -344,7 +632,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.011 0.000 7.029 0.018 ; + RECT 4.743 0.000 4.761 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -353,7 +641,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.335 0.000 7.353 0.018 ; + RECT 4.959 0.000 4.977 0.054 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -362,7 +650,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.659 0.000 7.677 0.018 ; + RECT 5.175 0.000 5.193 0.054 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -371,7 +659,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.983 0.000 8.001 0.018 ; + RECT 5.391 0.000 5.409 0.054 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -380,7 +668,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.307 0.000 8.325 0.018 ; + RECT 5.607 0.000 5.625 0.054 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -389,7 +677,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.631 0.000 8.649 0.018 ; + RECT 5.823 0.000 5.841 0.054 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -398,7 +686,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.955 0.000 8.973 0.018 ; + RECT 6.039 0.000 6.057 0.054 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -407,7 +695,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.279 0.000 9.297 0.018 ; + RECT 6.255 0.000 6.273 0.054 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -416,7 +704,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.603 0.000 9.621 0.018 ; + RECT 6.471 0.000 6.489 0.054 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -425,7 +713,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.927 0.000 9.945 0.018 ; + RECT 6.687 0.000 6.705 0.054 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -434,7 +722,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.251 0.000 10.269 0.018 ; + RECT 6.903 0.000 6.921 0.054 ; END END r0_rd_out[15] PIN r0_rd_out[16] @@ -443,7 +731,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 10.350 0.225 10.368 ; + RECT 3.087 30.117 3.105 30.171 ; END END r0_rd_out[16] PIN r0_rd_out[17] @@ -452,7 +740,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.603 10.350 0.621 10.368 ; + RECT 3.267 30.117 3.285 30.171 ; END END r0_rd_out[17] PIN r0_rd_out[18] @@ -461,7 +749,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.999 10.350 1.017 10.368 ; + RECT 3.447 30.117 3.465 30.171 ; END END r0_rd_out[18] PIN r0_rd_out[19] @@ -470,7 +758,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.395 10.350 1.413 10.368 ; + RECT 3.627 30.117 3.645 30.171 ; END END r0_rd_out[19] PIN r0_rd_out[20] @@ -479,7 +767,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.791 10.350 1.809 10.368 ; + RECT 3.807 30.117 3.825 30.171 ; END END r0_rd_out[20] PIN r0_rd_out[21] @@ -488,7 +776,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.187 10.350 2.205 10.368 ; + RECT 3.987 30.117 4.005 30.171 ; END END r0_rd_out[21] PIN r0_rd_out[22] @@ -497,7 +785,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.583 10.350 2.601 10.368 ; + RECT 4.167 30.117 4.185 30.171 ; END END r0_rd_out[22] PIN r0_rd_out[23] @@ -506,7 +794,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.979 10.350 2.997 10.368 ; + RECT 4.347 30.117 4.365 30.171 ; END END r0_rd_out[23] PIN r0_rd_out[24] @@ -515,7 +803,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.375 10.350 3.393 10.368 ; + RECT 4.527 30.117 4.545 30.171 ; END END r0_rd_out[24] PIN r0_rd_out[25] @@ -524,7 +812,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.771 10.350 3.789 10.368 ; + RECT 4.707 30.117 4.725 30.171 ; END END r0_rd_out[25] PIN r0_rd_out[26] @@ -533,7 +821,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.167 10.350 4.185 10.368 ; + RECT 4.887 30.117 4.905 30.171 ; END END r0_rd_out[26] PIN r0_rd_out[27] @@ -542,7 +830,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.563 10.350 4.581 10.368 ; + RECT 5.067 30.117 5.085 30.171 ; END END r0_rd_out[27] PIN r0_rd_out[28] @@ -551,7 +839,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.959 10.350 4.977 10.368 ; + RECT 5.247 30.117 5.265 30.171 ; END END r0_rd_out[28] PIN r0_rd_out[29] @@ -560,7 +848,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.355 10.350 5.373 10.368 ; + RECT 5.427 30.117 5.445 30.171 ; END END r0_rd_out[29] PIN r0_rd_out[30] @@ -569,7 +857,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.751 10.350 5.769 10.368 ; + RECT 5.607 30.117 5.625 30.171 ; END END r0_rd_out[30] PIN r0_rd_out[31] @@ -578,7 +866,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.147 10.350 6.165 10.368 ; + RECT 5.787 30.117 5.805 30.171 ; END END r0_rd_out[31] PIN r1_rd_out[0] @@ -587,7 +875,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.575 0.000 10.593 0.018 ; + RECT 7.119 0.000 7.137 0.054 ; END END r1_rd_out[0] PIN r1_rd_out[1] @@ -596,7 +884,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.899 0.000 10.917 0.018 ; + RECT 7.335 0.000 7.353 0.054 ; END END r1_rd_out[1] PIN r1_rd_out[2] @@ -605,7 +893,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.223 0.000 11.241 0.018 ; + RECT 7.551 0.000 7.569 0.054 ; END END r1_rd_out[2] PIN r1_rd_out[3] @@ -614,7 +902,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.547 0.000 11.565 0.018 ; + RECT 7.767 0.000 7.785 0.054 ; END END r1_rd_out[3] PIN r1_rd_out[4] @@ -623,7 +911,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.871 0.000 11.889 0.018 ; + RECT 7.983 0.000 8.001 0.054 ; END END r1_rd_out[4] PIN r1_rd_out[5] @@ -632,7 +920,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.195 0.000 12.213 0.018 ; + RECT 8.199 0.000 8.217 0.054 ; END END r1_rd_out[5] PIN r1_rd_out[6] @@ -641,7 +929,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.519 0.000 12.537 0.018 ; + RECT 8.415 0.000 8.433 0.054 ; END END r1_rd_out[6] PIN r1_rd_out[7] @@ -650,7 +938,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.843 0.000 12.861 0.018 ; + RECT 8.631 0.000 8.649 0.054 ; END END r1_rd_out[7] PIN r1_rd_out[8] @@ -659,7 +947,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.167 0.000 13.185 0.018 ; + RECT 8.847 0.000 8.865 0.054 ; END END r1_rd_out[8] PIN r1_rd_out[9] @@ -668,7 +956,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.491 0.000 13.509 0.018 ; + RECT 9.063 0.000 9.081 0.054 ; END END r1_rd_out[9] PIN r1_rd_out[10] @@ -677,7 +965,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.815 0.000 13.833 0.018 ; + RECT 9.279 0.000 9.297 0.054 ; END END r1_rd_out[10] PIN r1_rd_out[11] @@ -686,7 +974,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.139 0.000 14.157 0.018 ; + RECT 9.495 0.000 9.513 0.054 ; END END r1_rd_out[11] PIN r1_rd_out[12] @@ -695,7 +983,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.463 0.000 14.481 0.018 ; + RECT 9.711 0.000 9.729 0.054 ; END END r1_rd_out[12] PIN r1_rd_out[13] @@ -704,7 +992,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.787 0.000 14.805 0.018 ; + RECT 9.927 0.000 9.945 0.054 ; END END r1_rd_out[13] PIN r1_rd_out[14] @@ -713,7 +1001,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 15.111 0.000 15.129 0.018 ; + RECT 10.143 0.000 10.161 0.054 ; END END r1_rd_out[14] PIN r1_rd_out[15] @@ -722,7 +1010,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 15.435 0.000 15.453 0.018 ; + RECT 10.359 0.000 10.377 0.054 ; END END r1_rd_out[15] PIN r1_rd_out[16] @@ -731,7 +1019,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.543 10.350 6.561 10.368 ; + RECT 5.967 30.117 5.985 30.171 ; END END r1_rd_out[16] PIN r1_rd_out[17] @@ -740,7 +1028,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.939 10.350 6.957 10.368 ; + RECT 6.147 30.117 6.165 30.171 ; END END r1_rd_out[17] PIN r1_rd_out[18] @@ -749,7 +1037,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.335 10.350 7.353 10.368 ; + RECT 6.327 30.117 6.345 30.171 ; END END r1_rd_out[18] PIN r1_rd_out[19] @@ -758,7 +1046,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.731 10.350 7.749 10.368 ; + RECT 6.507 30.117 6.525 30.171 ; END END r1_rd_out[19] PIN r1_rd_out[20] @@ -767,7 +1055,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.127 10.350 8.145 10.368 ; + RECT 6.687 30.117 6.705 30.171 ; END END r1_rd_out[20] PIN r1_rd_out[21] @@ -776,7 +1064,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.523 10.350 8.541 10.368 ; + RECT 6.867 30.117 6.885 30.171 ; END END r1_rd_out[21] PIN r1_rd_out[22] @@ -785,7 +1073,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.919 10.350 8.937 10.368 ; + RECT 7.047 30.117 7.065 30.171 ; END END r1_rd_out[22] PIN r1_rd_out[23] @@ -794,7 +1082,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.315 10.350 9.333 10.368 ; + RECT 7.227 30.117 7.245 30.171 ; END END r1_rd_out[23] PIN r1_rd_out[24] @@ -803,7 +1091,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.711 10.350 9.729 10.368 ; + RECT 7.407 30.117 7.425 30.171 ; END END r1_rd_out[24] PIN r1_rd_out[25] @@ -812,7 +1100,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.107 10.350 10.125 10.368 ; + RECT 7.587 30.117 7.605 30.171 ; END END r1_rd_out[25] PIN r1_rd_out[26] @@ -821,7 +1109,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.503 10.350 10.521 10.368 ; + RECT 7.767 30.117 7.785 30.171 ; END END r1_rd_out[26] PIN r1_rd_out[27] @@ -830,7 +1118,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.899 10.350 10.917 10.368 ; + RECT 7.947 30.117 7.965 30.171 ; END END r1_rd_out[27] PIN r1_rd_out[28] @@ -839,7 +1127,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.295 10.350 11.313 10.368 ; + RECT 8.127 30.117 8.145 30.171 ; END END r1_rd_out[28] PIN r1_rd_out[29] @@ -848,7 +1136,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.691 10.350 11.709 10.368 ; + RECT 8.307 30.117 8.325 30.171 ; END END r1_rd_out[29] PIN r1_rd_out[30] @@ -857,7 +1145,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.087 10.350 12.105 10.368 ; + RECT 8.487 30.117 8.505 30.171 ; END END r1_rd_out[30] PIN r1_rd_out[31] @@ -866,7 +1154,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.483 10.350 12.501 10.368 ; + RECT 8.667 30.117 8.685 30.171 ; END END r1_rd_out[31] PIN w0_addr_in[0] @@ -875,7 +1163,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.116 0.024 4.140 ; + RECT 0.000 17.172 0.072 17.196 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -884,7 +1172,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.596 0.024 4.620 ; + RECT 0.000 18.228 0.072 18.252 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -893,7 +1181,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.076 0.024 5.100 ; + RECT 0.000 19.284 0.072 19.308 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -902,7 +1190,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.556 0.024 5.580 ; + RECT 0.000 20.340 0.072 20.364 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -911,7 +1199,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 4.116 16.589 4.140 ; + RECT 11.997 17.172 12.069 17.196 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -920,7 +1208,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 4.596 16.589 4.620 ; + RECT 11.997 18.228 12.069 18.252 ; END END w0_addr_in[5] PIN w0_addr_in[6] @@ -929,7 +1217,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 5.076 16.589 5.100 ; + RECT 11.997 19.284 12.069 19.308 ; END END w0_addr_in[6] PIN r0_addr_in[0] @@ -938,7 +1226,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.036 0.024 6.060 ; + RECT 0.000 21.396 0.072 21.420 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -947,7 +1235,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.516 0.024 6.540 ; + RECT 0.000 22.452 0.072 22.476 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -956,7 +1244,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.996 0.024 7.020 ; + RECT 0.000 23.508 0.072 23.532 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -965,7 +1253,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.476 0.024 7.500 ; + RECT 0.000 24.564 0.072 24.588 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -974,7 +1262,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 5.556 16.589 5.580 ; + RECT 11.997 20.340 12.069 20.364 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -983,7 +1271,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 6.036 16.589 6.060 ; + RECT 11.997 21.396 12.069 21.420 ; END END r0_addr_in[5] PIN r0_addr_in[6] @@ -992,7 +1280,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 6.516 16.589 6.540 ; + RECT 11.997 22.452 12.069 22.476 ; END END r0_addr_in[6] PIN r1_addr_in[0] @@ -1001,7 +1289,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.956 0.024 7.980 ; + RECT 0.000 25.620 0.072 25.644 ; END END r1_addr_in[0] PIN r1_addr_in[1] @@ -1010,7 +1298,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.436 0.024 8.460 ; + RECT 0.000 26.676 0.072 26.700 ; END END r1_addr_in[1] PIN r1_addr_in[2] @@ -1019,7 +1307,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.916 0.024 8.940 ; + RECT 0.000 27.732 0.072 27.756 ; END END r1_addr_in[2] PIN r1_addr_in[3] @@ -1028,7 +1316,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.396 0.024 9.420 ; + RECT 0.000 28.788 0.072 28.812 ; END END r1_addr_in[3] PIN r1_addr_in[4] @@ -1037,7 +1325,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 6.996 16.589 7.020 ; + RECT 11.997 23.508 12.069 23.532 ; END END r1_addr_in[4] PIN r1_addr_in[5] @@ -1046,7 +1334,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 7.476 16.589 7.500 ; + RECT 11.997 24.564 12.069 24.588 ; END END r1_addr_in[5] PIN r1_addr_in[6] @@ -1055,7 +1343,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 7.956 16.589 7.980 ; + RECT 11.997 25.620 12.069 25.644 ; END END r1_addr_in[6] PIN w0_we_in @@ -1064,7 +1352,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.879 10.350 12.897 10.368 ; + RECT 8.847 30.117 8.865 30.171 ; END END w0_we_in PIN w0_ce_in @@ -1073,7 +1361,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.275 10.350 13.293 10.368 ; + RECT 9.027 30.117 9.045 30.171 ; END END w0_ce_in PIN w0_clk @@ -1082,7 +1370,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.671 10.350 13.689 10.368 ; + RECT 9.207 30.117 9.225 30.171 ; END END w0_clk PIN r0_ce_in @@ -1091,7 +1379,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.067 10.350 14.085 10.368 ; + RECT 9.387 30.117 9.405 30.171 ; END END r0_ce_in PIN r0_clk @@ -1100,7 +1388,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.463 10.350 14.481 10.368 ; + RECT 9.567 30.117 9.585 30.171 ; END END r0_clk PIN r1_ce_in @@ -1109,7 +1397,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.859 10.350 14.877 10.368 ; + RECT 9.747 30.117 9.765 30.171 ; END END r1_ce_in PIN r1_clk @@ -1118,7 +1406,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 15.255 10.350 15.273 10.368 ; + RECT 9.927 30.117 9.945 30.171 ; END END r1_clk PIN VSS @@ -1126,19 +1414,45 @@ MACRO fakeram_32x128_2r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.108 0.192 16.481 0.288 ; - RECT 0.108 0.960 16.481 1.056 ; - RECT 0.108 1.728 16.481 1.824 ; - RECT 0.108 2.496 16.481 2.592 ; - RECT 0.108 3.264 16.481 3.360 ; - RECT 0.108 4.032 16.481 4.128 ; - RECT 0.108 4.800 16.481 4.896 ; - RECT 0.108 5.568 16.481 5.664 ; - RECT 0.108 6.336 16.481 6.432 ; - RECT 0.108 7.104 16.481 7.200 ; - RECT 0.108 7.872 16.481 7.968 ; - RECT 0.108 8.640 16.481 8.736 ; - RECT 0.108 9.408 16.481 9.504 ; + RECT 0.216 0.240 11.853 0.336 ; + RECT 0.216 1.008 11.853 1.104 ; + RECT 0.216 1.776 11.853 1.872 ; + RECT 0.216 2.544 11.853 2.640 ; + RECT 0.216 3.312 11.853 3.408 ; + RECT 0.216 4.080 11.853 4.176 ; + RECT 0.216 4.848 11.853 4.944 ; + RECT 0.216 5.616 11.853 5.712 ; + RECT 0.216 6.384 11.853 6.480 ; + RECT 0.216 7.152 11.853 7.248 ; + RECT 0.216 7.920 11.853 8.016 ; + RECT 0.216 8.688 11.853 8.784 ; + RECT 0.216 9.456 11.853 9.552 ; + RECT 0.216 10.224 11.853 10.320 ; + RECT 0.216 10.992 11.853 11.088 ; + RECT 0.216 11.760 11.853 11.856 ; + RECT 0.216 12.528 11.853 12.624 ; + RECT 0.216 13.296 11.853 13.392 ; + RECT 0.216 14.064 11.853 14.160 ; + RECT 0.216 14.832 11.853 14.928 ; + RECT 0.216 15.600 11.853 15.696 ; + RECT 0.216 16.368 11.853 16.464 ; + RECT 0.216 17.136 11.853 17.232 ; + RECT 0.216 17.904 11.853 18.000 ; + RECT 0.216 18.672 11.853 18.768 ; + RECT 0.216 19.440 11.853 19.536 ; + RECT 0.216 20.208 11.853 20.304 ; + RECT 0.216 20.976 11.853 21.072 ; + RECT 0.216 21.744 11.853 21.840 ; + RECT 0.216 22.512 11.853 22.608 ; + RECT 0.216 23.280 11.853 23.376 ; + RECT 0.216 24.048 11.853 24.144 ; + RECT 0.216 24.816 11.853 24.912 ; + RECT 0.216 25.584 11.853 25.680 ; + RECT 0.216 26.352 11.853 26.448 ; + RECT 0.216 27.120 11.853 27.216 ; + RECT 0.216 27.888 11.853 27.984 ; + RECT 0.216 28.656 11.853 28.752 ; + RECT 0.216 29.424 11.853 29.520 ; END END VSS PIN VDD @@ -1146,30 +1460,56 @@ MACRO fakeram_32x128_2r1w USE POWER ; PORT LAYER M4 ; - RECT 0.108 0.192 16.481 0.288 ; - RECT 0.108 0.960 16.481 1.056 ; - RECT 0.108 1.728 16.481 1.824 ; - RECT 0.108 2.496 16.481 2.592 ; - RECT 0.108 3.264 16.481 3.360 ; - RECT 0.108 4.032 16.481 4.128 ; - RECT 0.108 4.800 16.481 4.896 ; - RECT 0.108 5.568 16.481 5.664 ; - RECT 0.108 6.336 16.481 6.432 ; - RECT 0.108 7.104 16.481 7.200 ; - RECT 0.108 7.872 16.481 7.968 ; - RECT 0.108 8.640 16.481 8.736 ; - RECT 0.108 9.408 16.481 9.504 ; + RECT 0.216 0.240 11.853 0.336 ; + RECT 0.216 1.008 11.853 1.104 ; + RECT 0.216 1.776 11.853 1.872 ; + RECT 0.216 2.544 11.853 2.640 ; + RECT 0.216 3.312 11.853 3.408 ; + RECT 0.216 4.080 11.853 4.176 ; + RECT 0.216 4.848 11.853 4.944 ; + RECT 0.216 5.616 11.853 5.712 ; + RECT 0.216 6.384 11.853 6.480 ; + RECT 0.216 7.152 11.853 7.248 ; + RECT 0.216 7.920 11.853 8.016 ; + RECT 0.216 8.688 11.853 8.784 ; + RECT 0.216 9.456 11.853 9.552 ; + RECT 0.216 10.224 11.853 10.320 ; + RECT 0.216 10.992 11.853 11.088 ; + RECT 0.216 11.760 11.853 11.856 ; + RECT 0.216 12.528 11.853 12.624 ; + RECT 0.216 13.296 11.853 13.392 ; + RECT 0.216 14.064 11.853 14.160 ; + RECT 0.216 14.832 11.853 14.928 ; + RECT 0.216 15.600 11.853 15.696 ; + RECT 0.216 16.368 11.853 16.464 ; + RECT 0.216 17.136 11.853 17.232 ; + RECT 0.216 17.904 11.853 18.000 ; + RECT 0.216 18.672 11.853 18.768 ; + RECT 0.216 19.440 11.853 19.536 ; + RECT 0.216 20.208 11.853 20.304 ; + RECT 0.216 20.976 11.853 21.072 ; + RECT 0.216 21.744 11.853 21.840 ; + RECT 0.216 22.512 11.853 22.608 ; + RECT 0.216 23.280 11.853 23.376 ; + RECT 0.216 24.048 11.853 24.144 ; + RECT 0.216 24.816 11.853 24.912 ; + RECT 0.216 25.584 11.853 25.680 ; + RECT 0.216 26.352 11.853 26.448 ; + RECT 0.216 27.120 11.853 27.216 ; + RECT 0.216 27.888 11.853 27.984 ; + RECT 0.216 28.656 11.853 28.752 ; + RECT 0.216 29.424 11.853 29.520 ; END END VDD OBS LAYER M1 ; - RECT 0 0 16.589 10.368 ; + RECT 0 0 12.069 30.171 ; LAYER M2 ; - RECT 0 0 16.589 10.368 ; + RECT 0 0 12.069 30.171 ; LAYER M3 ; - RECT 0 0 16.589 10.368 ; + RECT 0 0 12.069 30.171 ; LAYER M4 ; - RECT 0 0 16.589 10.368 ; + RECT 0 0 12.069 30.171 ; END END fakeram_32x128_2r1w diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_3x64_1r1w.lef b/designs/asap7/NyuziProcessor/sram/lef/fakeram_3x64_1r1w.lef new file mode 100644 index 0000000..ffe1f03 --- /dev/null +++ b/designs/asap7/NyuziProcessor/sram/lef/fakeram_3x64_1r1w.lef @@ -0,0 +1,298 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_3x64_1r1w + FOREIGN fakeram_3x64_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 10.203 BY 11.602 ; + CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 0.276 10.203 0.300 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 11.548 0.225 11.602 ; + END + END w0_wmask_in[2] + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 1.620 10.203 1.644 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[2] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.619 0.000 2.637 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.031 0.000 5.049 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 11.548 1.305 11.602 ; + END + END r0_rd_out[2] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 2.964 10.203 2.988 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 4.308 10.203 4.332 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 5.652 10.203 5.676 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 6.996 10.203 7.020 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 8.340 10.203 8.364 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 9.684 10.203 9.708 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 11.548 2.385 11.602 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 11.548 3.465 11.602 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 11.548 4.545 11.602 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 11.548 5.625 11.602 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 11.548 6.705 11.602 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 10.203 11.602 ; + LAYER M2 ; + RECT 0 0 10.203 11.602 ; + LAYER M3 ; + RECT 0 0 10.203 11.602 ; + LAYER M4 ; + RECT 0 0 10.203 11.602 ; + END +END fakeram_3x64_1r1w + +END LIBRARY diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x2048_1r1w.lef b/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x2048_1r1w.lef index 1a00c4b..be3e13a 100644 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x2048_1r1w.lef +++ b/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x2048_1r1w.lef @@ -3,15 +3,4623 @@ BUSBITCHARS "[]" ; MACRO fakeram_512x2048_1r1w FOREIGN fakeram_512x2048_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 265.421 BY 165.888 ; + SIZE 163.234 BY 408.085 ; CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.764 0.072 1.788 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.252 0.072 3.276 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.740 0.072 4.764 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.228 0.072 6.252 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.716 0.072 7.740 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.204 0.072 9.228 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.692 0.072 10.716 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.180 0.072 12.204 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.668 0.072 13.692 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.156 0.072 15.180 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.644 0.072 16.668 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.132 0.072 18.156 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.620 0.072 19.644 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.108 0.072 21.132 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.596 0.072 22.620 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.084 0.072 24.108 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.572 0.072 25.596 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.060 0.072 27.084 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.548 0.072 28.572 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.036 0.072 30.060 ; + END + END w0_wmask_in[20] + PIN w0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.524 0.072 31.548 ; + END + END w0_wmask_in[21] + PIN w0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.012 0.072 33.036 ; + END + END w0_wmask_in[22] + PIN w0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.500 0.072 34.524 ; + END + END w0_wmask_in[23] + PIN w0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.988 0.072 36.012 ; + END + END w0_wmask_in[24] + PIN w0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.476 0.072 37.500 ; + END + END w0_wmask_in[25] + PIN w0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.964 0.072 38.988 ; + END + END w0_wmask_in[26] + PIN w0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.452 0.072 40.476 ; + END + END w0_wmask_in[27] + PIN w0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.940 0.072 41.964 ; + END + END w0_wmask_in[28] + PIN w0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.428 0.072 43.452 ; + END + END w0_wmask_in[29] + PIN w0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.916 0.072 44.940 ; + END + END w0_wmask_in[30] + PIN w0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.404 0.072 46.428 ; + END + END w0_wmask_in[31] + PIN w0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.892 0.072 47.916 ; + END + END w0_wmask_in[32] + PIN w0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.380 0.072 49.404 ; + END + END w0_wmask_in[33] + PIN w0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.868 0.072 50.892 ; + END + END w0_wmask_in[34] + PIN w0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.356 0.072 52.380 ; + END + END w0_wmask_in[35] + PIN w0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.844 0.072 53.868 ; + END + END w0_wmask_in[36] + PIN w0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.332 0.072 55.356 ; + END + END w0_wmask_in[37] + PIN w0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.820 0.072 56.844 ; + END + END w0_wmask_in[38] + PIN w0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.308 0.072 58.332 ; + END + END w0_wmask_in[39] + PIN w0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.796 0.072 59.820 ; + END + END w0_wmask_in[40] + PIN w0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.284 0.072 61.308 ; + END + END w0_wmask_in[41] + PIN w0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.772 0.072 62.796 ; + END + END w0_wmask_in[42] + PIN w0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.260 0.072 64.284 ; + END + END w0_wmask_in[43] + PIN w0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.748 0.072 65.772 ; + END + END w0_wmask_in[44] + PIN w0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.236 0.072 67.260 ; + END + END w0_wmask_in[45] + PIN w0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.724 0.072 68.748 ; + END + END w0_wmask_in[46] + PIN w0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.212 0.072 70.236 ; + END + END w0_wmask_in[47] + PIN w0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.700 0.072 71.724 ; + END + END w0_wmask_in[48] + PIN w0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.188 0.072 73.212 ; + END + END w0_wmask_in[49] + PIN w0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.676 0.072 74.700 ; + END + END w0_wmask_in[50] + PIN w0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.164 0.072 76.188 ; + END + END w0_wmask_in[51] + PIN w0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.652 0.072 77.676 ; + END + END w0_wmask_in[52] + PIN w0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.140 0.072 79.164 ; + END + END w0_wmask_in[53] + PIN w0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.628 0.072 80.652 ; + END + END w0_wmask_in[54] + PIN w0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.116 0.072 82.140 ; + END + END w0_wmask_in[55] + PIN w0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.604 0.072 83.628 ; + END + END w0_wmask_in[56] + PIN w0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.092 0.072 85.116 ; + END + END w0_wmask_in[57] + PIN w0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.580 0.072 86.604 ; + END + END w0_wmask_in[58] + PIN w0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.068 0.072 88.092 ; + END + END w0_wmask_in[59] + PIN w0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.556 0.072 89.580 ; + END + END w0_wmask_in[60] + PIN w0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.044 0.072 91.068 ; + END + END w0_wmask_in[61] + PIN w0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.532 0.072 92.556 ; + END + END w0_wmask_in[62] + PIN w0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.020 0.072 94.044 ; + END + END w0_wmask_in[63] + PIN w0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.508 0.072 95.532 ; + END + END w0_wmask_in[64] + PIN w0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 96.996 0.072 97.020 ; + END + END w0_wmask_in[65] + PIN w0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 98.484 0.072 98.508 ; + END + END w0_wmask_in[66] + PIN w0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 99.972 0.072 99.996 ; + END + END w0_wmask_in[67] + PIN w0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 101.460 0.072 101.484 ; + END + END w0_wmask_in[68] + PIN w0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 102.948 0.072 102.972 ; + END + END w0_wmask_in[69] + PIN w0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 104.436 0.072 104.460 ; + END + END w0_wmask_in[70] + PIN w0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 105.924 0.072 105.948 ; + END + END w0_wmask_in[71] + PIN w0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 107.412 0.072 107.436 ; + END + END w0_wmask_in[72] + PIN w0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 108.900 0.072 108.924 ; + END + END w0_wmask_in[73] + PIN w0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 110.388 0.072 110.412 ; + END + END w0_wmask_in[74] + PIN w0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 111.876 0.072 111.900 ; + END + END w0_wmask_in[75] + PIN w0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 113.364 0.072 113.388 ; + END + END w0_wmask_in[76] + PIN w0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 114.852 0.072 114.876 ; + END + END w0_wmask_in[77] + PIN w0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 116.340 0.072 116.364 ; + END + END w0_wmask_in[78] + PIN w0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 117.828 0.072 117.852 ; + END + END w0_wmask_in[79] + PIN w0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 119.316 0.072 119.340 ; + END + END w0_wmask_in[80] + PIN w0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 120.804 0.072 120.828 ; + END + END w0_wmask_in[81] + PIN w0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 122.292 0.072 122.316 ; + END + END w0_wmask_in[82] + PIN w0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 123.780 0.072 123.804 ; + END + END w0_wmask_in[83] + PIN w0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 125.268 0.072 125.292 ; + END + END w0_wmask_in[84] + PIN w0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 126.756 0.072 126.780 ; + END + END w0_wmask_in[85] + PIN w0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 128.244 0.072 128.268 ; + END + END w0_wmask_in[86] + PIN w0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 129.732 0.072 129.756 ; + END + END w0_wmask_in[87] + PIN w0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 131.220 0.072 131.244 ; + END + END w0_wmask_in[88] + PIN w0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 132.708 0.072 132.732 ; + END + END w0_wmask_in[89] + PIN w0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 134.196 0.072 134.220 ; + END + END w0_wmask_in[90] + PIN w0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 135.684 0.072 135.708 ; + END + END w0_wmask_in[91] + PIN w0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 137.172 0.072 137.196 ; + END + END w0_wmask_in[92] + PIN w0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 138.660 0.072 138.684 ; + END + END w0_wmask_in[93] + PIN w0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 140.148 0.072 140.172 ; + END + END w0_wmask_in[94] + PIN w0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 141.636 0.072 141.660 ; + END + END w0_wmask_in[95] + PIN w0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 143.124 0.072 143.148 ; + END + END w0_wmask_in[96] + PIN w0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 144.612 0.072 144.636 ; + END + END w0_wmask_in[97] + PIN w0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 146.100 0.072 146.124 ; + END + END w0_wmask_in[98] + PIN w0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 147.588 0.072 147.612 ; + END + END w0_wmask_in[99] + PIN w0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 149.076 0.072 149.100 ; + END + END w0_wmask_in[100] + PIN w0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 150.564 0.072 150.588 ; + END + END w0_wmask_in[101] + PIN w0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 152.052 0.072 152.076 ; + END + END w0_wmask_in[102] + PIN w0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 153.540 0.072 153.564 ; + END + END w0_wmask_in[103] + PIN w0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 155.028 0.072 155.052 ; + END + END w0_wmask_in[104] + PIN w0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 156.516 0.072 156.540 ; + END + END w0_wmask_in[105] + PIN w0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 158.004 0.072 158.028 ; + END + END w0_wmask_in[106] + PIN w0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 159.492 0.072 159.516 ; + END + END w0_wmask_in[107] + PIN w0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 160.980 0.072 161.004 ; + END + END w0_wmask_in[108] + PIN w0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 162.468 0.072 162.492 ; + END + END w0_wmask_in[109] + PIN w0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 163.956 0.072 163.980 ; + END + END w0_wmask_in[110] + PIN w0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 165.444 0.072 165.468 ; + END + END w0_wmask_in[111] + PIN w0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 166.932 0.072 166.956 ; + END + END w0_wmask_in[112] + PIN w0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 168.420 0.072 168.444 ; + END + END w0_wmask_in[113] + PIN w0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 169.908 0.072 169.932 ; + END + END w0_wmask_in[114] + PIN w0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 171.396 0.072 171.420 ; + END + END w0_wmask_in[115] + PIN w0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 172.884 0.072 172.908 ; + END + END w0_wmask_in[116] + PIN w0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 174.372 0.072 174.396 ; + END + END w0_wmask_in[117] + PIN w0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 175.860 0.072 175.884 ; + END + END w0_wmask_in[118] + PIN w0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 177.348 0.072 177.372 ; + END + END w0_wmask_in[119] + PIN w0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 178.836 0.072 178.860 ; + END + END w0_wmask_in[120] + PIN w0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 180.324 0.072 180.348 ; + END + END w0_wmask_in[121] + PIN w0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 181.812 0.072 181.836 ; + END + END w0_wmask_in[122] + PIN w0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 183.300 0.072 183.324 ; + END + END w0_wmask_in[123] + PIN w0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 184.788 0.072 184.812 ; + END + END w0_wmask_in[124] + PIN w0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 186.276 0.072 186.300 ; + END + END w0_wmask_in[125] + PIN w0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 187.764 0.072 187.788 ; + END + END w0_wmask_in[126] + PIN w0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 189.252 0.072 189.276 ; + END + END w0_wmask_in[127] + PIN w0_wmask_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 0.276 163.234 0.300 ; + END + END w0_wmask_in[128] + PIN w0_wmask_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 1.764 163.234 1.788 ; + END + END w0_wmask_in[129] + PIN w0_wmask_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 3.252 163.234 3.276 ; + END + END w0_wmask_in[130] + PIN w0_wmask_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 4.740 163.234 4.764 ; + END + END w0_wmask_in[131] + PIN w0_wmask_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 6.228 163.234 6.252 ; + END + END w0_wmask_in[132] + PIN w0_wmask_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 7.716 163.234 7.740 ; + END + END w0_wmask_in[133] + PIN w0_wmask_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 9.204 163.234 9.228 ; + END + END w0_wmask_in[134] + PIN w0_wmask_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 10.692 163.234 10.716 ; + END + END w0_wmask_in[135] + PIN w0_wmask_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 12.180 163.234 12.204 ; + END + END w0_wmask_in[136] + PIN w0_wmask_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 13.668 163.234 13.692 ; + END + END w0_wmask_in[137] + PIN w0_wmask_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 15.156 163.234 15.180 ; + END + END w0_wmask_in[138] + PIN w0_wmask_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 16.644 163.234 16.668 ; + END + END w0_wmask_in[139] + PIN w0_wmask_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 18.132 163.234 18.156 ; + END + END w0_wmask_in[140] + PIN w0_wmask_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 19.620 163.234 19.644 ; + END + END w0_wmask_in[141] + PIN w0_wmask_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 21.108 163.234 21.132 ; + END + END w0_wmask_in[142] + PIN w0_wmask_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 22.596 163.234 22.620 ; + END + END w0_wmask_in[143] + PIN w0_wmask_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 24.084 163.234 24.108 ; + END + END w0_wmask_in[144] + PIN w0_wmask_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 25.572 163.234 25.596 ; + END + END w0_wmask_in[145] + PIN w0_wmask_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 27.060 163.234 27.084 ; + END + END w0_wmask_in[146] + PIN w0_wmask_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 28.548 163.234 28.572 ; + END + END w0_wmask_in[147] + PIN w0_wmask_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 30.036 163.234 30.060 ; + END + END w0_wmask_in[148] + PIN w0_wmask_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 31.524 163.234 31.548 ; + END + END w0_wmask_in[149] + PIN w0_wmask_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 33.012 163.234 33.036 ; + END + END w0_wmask_in[150] + PIN w0_wmask_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 34.500 163.234 34.524 ; + END + END w0_wmask_in[151] + PIN w0_wmask_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 35.988 163.234 36.012 ; + END + END w0_wmask_in[152] + PIN w0_wmask_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 37.476 163.234 37.500 ; + END + END w0_wmask_in[153] + PIN w0_wmask_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 38.964 163.234 38.988 ; + END + END w0_wmask_in[154] + PIN w0_wmask_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 40.452 163.234 40.476 ; + END + END w0_wmask_in[155] + PIN w0_wmask_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 41.940 163.234 41.964 ; + END + END w0_wmask_in[156] + PIN w0_wmask_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 43.428 163.234 43.452 ; + END + END w0_wmask_in[157] + PIN w0_wmask_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 44.916 163.234 44.940 ; + END + END w0_wmask_in[158] + PIN w0_wmask_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 46.404 163.234 46.428 ; + END + END w0_wmask_in[159] + PIN w0_wmask_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 47.892 163.234 47.916 ; + END + END w0_wmask_in[160] + PIN w0_wmask_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 49.380 163.234 49.404 ; + END + END w0_wmask_in[161] + PIN w0_wmask_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 50.868 163.234 50.892 ; + END + END w0_wmask_in[162] + PIN w0_wmask_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 52.356 163.234 52.380 ; + END + END w0_wmask_in[163] + PIN w0_wmask_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 53.844 163.234 53.868 ; + END + END w0_wmask_in[164] + PIN w0_wmask_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 55.332 163.234 55.356 ; + END + END w0_wmask_in[165] + PIN w0_wmask_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 56.820 163.234 56.844 ; + END + END w0_wmask_in[166] + PIN w0_wmask_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 58.308 163.234 58.332 ; + END + END w0_wmask_in[167] + PIN w0_wmask_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 59.796 163.234 59.820 ; + END + END w0_wmask_in[168] + PIN w0_wmask_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 61.284 163.234 61.308 ; + END + END w0_wmask_in[169] + PIN w0_wmask_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 62.772 163.234 62.796 ; + END + END w0_wmask_in[170] + PIN w0_wmask_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 64.260 163.234 64.284 ; + END + END w0_wmask_in[171] + PIN w0_wmask_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 65.748 163.234 65.772 ; + END + END w0_wmask_in[172] + PIN w0_wmask_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 67.236 163.234 67.260 ; + END + END w0_wmask_in[173] + PIN w0_wmask_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 68.724 163.234 68.748 ; + END + END w0_wmask_in[174] + PIN w0_wmask_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 70.212 163.234 70.236 ; + END + END w0_wmask_in[175] + PIN w0_wmask_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 71.700 163.234 71.724 ; + END + END w0_wmask_in[176] + PIN w0_wmask_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 73.188 163.234 73.212 ; + END + END w0_wmask_in[177] + PIN w0_wmask_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 74.676 163.234 74.700 ; + END + END w0_wmask_in[178] + PIN w0_wmask_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 76.164 163.234 76.188 ; + END + END w0_wmask_in[179] + PIN w0_wmask_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 77.652 163.234 77.676 ; + END + END w0_wmask_in[180] + PIN w0_wmask_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 79.140 163.234 79.164 ; + END + END w0_wmask_in[181] + PIN w0_wmask_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 80.628 163.234 80.652 ; + END + END w0_wmask_in[182] + PIN w0_wmask_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 82.116 163.234 82.140 ; + END + END w0_wmask_in[183] + PIN w0_wmask_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 83.604 163.234 83.628 ; + END + END w0_wmask_in[184] + PIN w0_wmask_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 85.092 163.234 85.116 ; + END + END w0_wmask_in[185] + PIN w0_wmask_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 86.580 163.234 86.604 ; + END + END w0_wmask_in[186] + PIN w0_wmask_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 88.068 163.234 88.092 ; + END + END w0_wmask_in[187] + PIN w0_wmask_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 89.556 163.234 89.580 ; + END + END w0_wmask_in[188] + PIN w0_wmask_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 91.044 163.234 91.068 ; + END + END w0_wmask_in[189] + PIN w0_wmask_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 92.532 163.234 92.556 ; + END + END w0_wmask_in[190] + PIN w0_wmask_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 94.020 163.234 94.044 ; + END + END w0_wmask_in[191] + PIN w0_wmask_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 95.508 163.234 95.532 ; + END + END w0_wmask_in[192] + PIN w0_wmask_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 96.996 163.234 97.020 ; + END + END w0_wmask_in[193] + PIN w0_wmask_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 98.484 163.234 98.508 ; + END + END w0_wmask_in[194] + PIN w0_wmask_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 99.972 163.234 99.996 ; + END + END w0_wmask_in[195] + PIN w0_wmask_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 101.460 163.234 101.484 ; + END + END w0_wmask_in[196] + PIN w0_wmask_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 102.948 163.234 102.972 ; + END + END w0_wmask_in[197] + PIN w0_wmask_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 104.436 163.234 104.460 ; + END + END w0_wmask_in[198] + PIN w0_wmask_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 105.924 163.234 105.948 ; + END + END w0_wmask_in[199] + PIN w0_wmask_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 107.412 163.234 107.436 ; + END + END w0_wmask_in[200] + PIN w0_wmask_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 108.900 163.234 108.924 ; + END + END w0_wmask_in[201] + PIN w0_wmask_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 110.388 163.234 110.412 ; + END + END w0_wmask_in[202] + PIN w0_wmask_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 111.876 163.234 111.900 ; + END + END w0_wmask_in[203] + PIN w0_wmask_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 113.364 163.234 113.388 ; + END + END w0_wmask_in[204] + PIN w0_wmask_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 114.852 163.234 114.876 ; + END + END w0_wmask_in[205] + PIN w0_wmask_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 116.340 163.234 116.364 ; + END + END w0_wmask_in[206] + PIN w0_wmask_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 117.828 163.234 117.852 ; + END + END w0_wmask_in[207] + PIN w0_wmask_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 119.316 163.234 119.340 ; + END + END w0_wmask_in[208] + PIN w0_wmask_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 120.804 163.234 120.828 ; + END + END w0_wmask_in[209] + PIN w0_wmask_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 122.292 163.234 122.316 ; + END + END w0_wmask_in[210] + PIN w0_wmask_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 123.780 163.234 123.804 ; + END + END w0_wmask_in[211] + PIN w0_wmask_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 125.268 163.234 125.292 ; + END + END w0_wmask_in[212] + PIN w0_wmask_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 126.756 163.234 126.780 ; + END + END w0_wmask_in[213] + PIN w0_wmask_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 128.244 163.234 128.268 ; + END + END w0_wmask_in[214] + PIN w0_wmask_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 129.732 163.234 129.756 ; + END + END w0_wmask_in[215] + PIN w0_wmask_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 131.220 163.234 131.244 ; + END + END w0_wmask_in[216] + PIN w0_wmask_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 132.708 163.234 132.732 ; + END + END w0_wmask_in[217] + PIN w0_wmask_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 134.196 163.234 134.220 ; + END + END w0_wmask_in[218] + PIN w0_wmask_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 135.684 163.234 135.708 ; + END + END w0_wmask_in[219] + PIN w0_wmask_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 137.172 163.234 137.196 ; + END + END w0_wmask_in[220] + PIN w0_wmask_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 138.660 163.234 138.684 ; + END + END w0_wmask_in[221] + PIN w0_wmask_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 140.148 163.234 140.172 ; + END + END w0_wmask_in[222] + PIN w0_wmask_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 141.636 163.234 141.660 ; + END + END w0_wmask_in[223] + PIN w0_wmask_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 143.124 163.234 143.148 ; + END + END w0_wmask_in[224] + PIN w0_wmask_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 144.612 163.234 144.636 ; + END + END w0_wmask_in[225] + PIN w0_wmask_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 146.100 163.234 146.124 ; + END + END w0_wmask_in[226] + PIN w0_wmask_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 147.588 163.234 147.612 ; + END + END w0_wmask_in[227] + PIN w0_wmask_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 149.076 163.234 149.100 ; + END + END w0_wmask_in[228] + PIN w0_wmask_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 150.564 163.234 150.588 ; + END + END w0_wmask_in[229] + PIN w0_wmask_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 152.052 163.234 152.076 ; + END + END w0_wmask_in[230] + PIN w0_wmask_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 153.540 163.234 153.564 ; + END + END w0_wmask_in[231] + PIN w0_wmask_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 155.028 163.234 155.052 ; + END + END w0_wmask_in[232] + PIN w0_wmask_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 156.516 163.234 156.540 ; + END + END w0_wmask_in[233] + PIN w0_wmask_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 158.004 163.234 158.028 ; + END + END w0_wmask_in[234] + PIN w0_wmask_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 159.492 163.234 159.516 ; + END + END w0_wmask_in[235] + PIN w0_wmask_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 160.980 163.234 161.004 ; + END + END w0_wmask_in[236] + PIN w0_wmask_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 162.468 163.234 162.492 ; + END + END w0_wmask_in[237] + PIN w0_wmask_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 163.956 163.234 163.980 ; + END + END w0_wmask_in[238] + PIN w0_wmask_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 165.444 163.234 165.468 ; + END + END w0_wmask_in[239] + PIN w0_wmask_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 166.932 163.234 166.956 ; + END + END w0_wmask_in[240] + PIN w0_wmask_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 168.420 163.234 168.444 ; + END + END w0_wmask_in[241] + PIN w0_wmask_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 169.908 163.234 169.932 ; + END + END w0_wmask_in[242] + PIN w0_wmask_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 171.396 163.234 171.420 ; + END + END w0_wmask_in[243] + PIN w0_wmask_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 172.884 163.234 172.908 ; + END + END w0_wmask_in[244] + PIN w0_wmask_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 174.372 163.234 174.396 ; + END + END w0_wmask_in[245] + PIN w0_wmask_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 175.860 163.234 175.884 ; + END + END w0_wmask_in[246] + PIN w0_wmask_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 177.348 163.234 177.372 ; + END + END w0_wmask_in[247] + PIN w0_wmask_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 178.836 163.234 178.860 ; + END + END w0_wmask_in[248] + PIN w0_wmask_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 180.324 163.234 180.348 ; + END + END w0_wmask_in[249] + PIN w0_wmask_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 181.812 163.234 181.836 ; + END + END w0_wmask_in[250] + PIN w0_wmask_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 183.300 163.234 183.324 ; + END + END w0_wmask_in[251] + PIN w0_wmask_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 184.788 163.234 184.812 ; + END + END w0_wmask_in[252] + PIN w0_wmask_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 186.276 163.234 186.300 ; + END + END w0_wmask_in[253] + PIN w0_wmask_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 187.764 163.234 187.788 ; + END + END w0_wmask_in[254] + PIN w0_wmask_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 189.252 163.234 189.276 ; + END + END w0_wmask_in[255] + PIN w0_wmask_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 408.031 0.225 408.085 ; + END + END w0_wmask_in[256] + PIN w0_wmask_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 408.031 0.513 408.085 ; + END + END w0_wmask_in[257] + PIN w0_wmask_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 408.031 0.801 408.085 ; + END + END w0_wmask_in[258] + PIN w0_wmask_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 408.031 1.089 408.085 ; + END + END w0_wmask_in[259] + PIN w0_wmask_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 408.031 1.377 408.085 ; + END + END w0_wmask_in[260] + PIN w0_wmask_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 408.031 1.665 408.085 ; + END + END w0_wmask_in[261] + PIN w0_wmask_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 408.031 1.953 408.085 ; + END + END w0_wmask_in[262] + PIN w0_wmask_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 408.031 2.241 408.085 ; + END + END w0_wmask_in[263] + PIN w0_wmask_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 408.031 2.529 408.085 ; + END + END w0_wmask_in[264] + PIN w0_wmask_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 408.031 2.817 408.085 ; + END + END w0_wmask_in[265] + PIN w0_wmask_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 408.031 3.105 408.085 ; + END + END w0_wmask_in[266] + PIN w0_wmask_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 408.031 3.393 408.085 ; + END + END w0_wmask_in[267] + PIN w0_wmask_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 408.031 3.681 408.085 ; + END + END w0_wmask_in[268] + PIN w0_wmask_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 408.031 3.969 408.085 ; + END + END w0_wmask_in[269] + PIN w0_wmask_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 408.031 4.257 408.085 ; + END + END w0_wmask_in[270] + PIN w0_wmask_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 408.031 4.545 408.085 ; + END + END w0_wmask_in[271] + PIN w0_wmask_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 408.031 4.833 408.085 ; + END + END w0_wmask_in[272] + PIN w0_wmask_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 408.031 5.121 408.085 ; + END + END w0_wmask_in[273] + PIN w0_wmask_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 408.031 5.409 408.085 ; + END + END w0_wmask_in[274] + PIN w0_wmask_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 408.031 5.697 408.085 ; + END + END w0_wmask_in[275] + PIN w0_wmask_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 408.031 5.985 408.085 ; + END + END w0_wmask_in[276] + PIN w0_wmask_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 408.031 6.273 408.085 ; + END + END w0_wmask_in[277] + PIN w0_wmask_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 408.031 6.561 408.085 ; + END + END w0_wmask_in[278] + PIN w0_wmask_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 408.031 6.849 408.085 ; + END + END w0_wmask_in[279] + PIN w0_wmask_in[280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 408.031 7.137 408.085 ; + END + END w0_wmask_in[280] + PIN w0_wmask_in[281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 408.031 7.425 408.085 ; + END + END w0_wmask_in[281] + PIN w0_wmask_in[282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 408.031 7.713 408.085 ; + END + END w0_wmask_in[282] + PIN w0_wmask_in[283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 408.031 8.001 408.085 ; + END + END w0_wmask_in[283] + PIN w0_wmask_in[284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 408.031 8.289 408.085 ; + END + END w0_wmask_in[284] + PIN w0_wmask_in[285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 408.031 8.577 408.085 ; + END + END w0_wmask_in[285] + PIN w0_wmask_in[286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 408.031 8.865 408.085 ; + END + END w0_wmask_in[286] + PIN w0_wmask_in[287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 408.031 9.153 408.085 ; + END + END w0_wmask_in[287] + PIN w0_wmask_in[288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 408.031 9.441 408.085 ; + END + END w0_wmask_in[288] + PIN w0_wmask_in[289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 408.031 9.729 408.085 ; + END + END w0_wmask_in[289] + PIN w0_wmask_in[290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 408.031 10.017 408.085 ; + END + END w0_wmask_in[290] + PIN w0_wmask_in[291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 408.031 10.305 408.085 ; + END + END w0_wmask_in[291] + PIN w0_wmask_in[292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 408.031 10.593 408.085 ; + END + END w0_wmask_in[292] + PIN w0_wmask_in[293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 408.031 10.881 408.085 ; + END + END w0_wmask_in[293] + PIN w0_wmask_in[294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 408.031 11.169 408.085 ; + END + END w0_wmask_in[294] + PIN w0_wmask_in[295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 408.031 11.457 408.085 ; + END + END w0_wmask_in[295] + PIN w0_wmask_in[296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 408.031 11.745 408.085 ; + END + END w0_wmask_in[296] + PIN w0_wmask_in[297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 408.031 12.033 408.085 ; + END + END w0_wmask_in[297] + PIN w0_wmask_in[298] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 408.031 12.321 408.085 ; + END + END w0_wmask_in[298] + PIN w0_wmask_in[299] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 408.031 12.609 408.085 ; + END + END w0_wmask_in[299] + PIN w0_wmask_in[300] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 408.031 12.897 408.085 ; + END + END w0_wmask_in[300] + PIN w0_wmask_in[301] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 408.031 13.185 408.085 ; + END + END w0_wmask_in[301] + PIN w0_wmask_in[302] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 408.031 13.473 408.085 ; + END + END w0_wmask_in[302] + PIN w0_wmask_in[303] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 408.031 13.761 408.085 ; + END + END w0_wmask_in[303] + PIN w0_wmask_in[304] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 408.031 14.049 408.085 ; + END + END w0_wmask_in[304] + PIN w0_wmask_in[305] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 408.031 14.337 408.085 ; + END + END w0_wmask_in[305] + PIN w0_wmask_in[306] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 408.031 14.625 408.085 ; + END + END w0_wmask_in[306] + PIN w0_wmask_in[307] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 408.031 14.913 408.085 ; + END + END w0_wmask_in[307] + PIN w0_wmask_in[308] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 408.031 15.201 408.085 ; + END + END w0_wmask_in[308] + PIN w0_wmask_in[309] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 408.031 15.489 408.085 ; + END + END w0_wmask_in[309] + PIN w0_wmask_in[310] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 408.031 15.777 408.085 ; + END + END w0_wmask_in[310] + PIN w0_wmask_in[311] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 408.031 16.065 408.085 ; + END + END w0_wmask_in[311] + PIN w0_wmask_in[312] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 408.031 16.353 408.085 ; + END + END w0_wmask_in[312] + PIN w0_wmask_in[313] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 408.031 16.641 408.085 ; + END + END w0_wmask_in[313] + PIN w0_wmask_in[314] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 408.031 16.929 408.085 ; + END + END w0_wmask_in[314] + PIN w0_wmask_in[315] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 408.031 17.217 408.085 ; + END + END w0_wmask_in[315] + PIN w0_wmask_in[316] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 408.031 17.505 408.085 ; + END + END w0_wmask_in[316] + PIN w0_wmask_in[317] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 408.031 17.793 408.085 ; + END + END w0_wmask_in[317] + PIN w0_wmask_in[318] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 408.031 18.081 408.085 ; + END + END w0_wmask_in[318] + PIN w0_wmask_in[319] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 408.031 18.369 408.085 ; + END + END w0_wmask_in[319] + PIN w0_wmask_in[320] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 408.031 18.657 408.085 ; + END + END w0_wmask_in[320] + PIN w0_wmask_in[321] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 408.031 18.945 408.085 ; + END + END w0_wmask_in[321] + PIN w0_wmask_in[322] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 408.031 19.233 408.085 ; + END + END w0_wmask_in[322] + PIN w0_wmask_in[323] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 408.031 19.521 408.085 ; + END + END w0_wmask_in[323] + PIN w0_wmask_in[324] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 408.031 19.809 408.085 ; + END + END w0_wmask_in[324] + PIN w0_wmask_in[325] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 408.031 20.097 408.085 ; + END + END w0_wmask_in[325] + PIN w0_wmask_in[326] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 408.031 20.385 408.085 ; + END + END w0_wmask_in[326] + PIN w0_wmask_in[327] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 408.031 20.673 408.085 ; + END + END w0_wmask_in[327] + PIN w0_wmask_in[328] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 408.031 20.961 408.085 ; + END + END w0_wmask_in[328] + PIN w0_wmask_in[329] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 408.031 21.249 408.085 ; + END + END w0_wmask_in[329] + PIN w0_wmask_in[330] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 408.031 21.537 408.085 ; + END + END w0_wmask_in[330] + PIN w0_wmask_in[331] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 408.031 21.825 408.085 ; + END + END w0_wmask_in[331] + PIN w0_wmask_in[332] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 408.031 22.113 408.085 ; + END + END w0_wmask_in[332] + PIN w0_wmask_in[333] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 408.031 22.401 408.085 ; + END + END w0_wmask_in[333] + PIN w0_wmask_in[334] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 408.031 22.689 408.085 ; + END + END w0_wmask_in[334] + PIN w0_wmask_in[335] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 408.031 22.977 408.085 ; + END + END w0_wmask_in[335] + PIN w0_wmask_in[336] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 408.031 23.265 408.085 ; + END + END w0_wmask_in[336] + PIN w0_wmask_in[337] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 408.031 23.553 408.085 ; + END + END w0_wmask_in[337] + PIN w0_wmask_in[338] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 408.031 23.841 408.085 ; + END + END w0_wmask_in[338] + PIN w0_wmask_in[339] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 408.031 24.129 408.085 ; + END + END w0_wmask_in[339] + PIN w0_wmask_in[340] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 408.031 24.417 408.085 ; + END + END w0_wmask_in[340] + PIN w0_wmask_in[341] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 408.031 24.705 408.085 ; + END + END w0_wmask_in[341] + PIN w0_wmask_in[342] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 408.031 24.993 408.085 ; + END + END w0_wmask_in[342] + PIN w0_wmask_in[343] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 408.031 25.281 408.085 ; + END + END w0_wmask_in[343] + PIN w0_wmask_in[344] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 408.031 25.569 408.085 ; + END + END w0_wmask_in[344] + PIN w0_wmask_in[345] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 408.031 25.857 408.085 ; + END + END w0_wmask_in[345] + PIN w0_wmask_in[346] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 408.031 26.145 408.085 ; + END + END w0_wmask_in[346] + PIN w0_wmask_in[347] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 408.031 26.433 408.085 ; + END + END w0_wmask_in[347] + PIN w0_wmask_in[348] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 408.031 26.721 408.085 ; + END + END w0_wmask_in[348] + PIN w0_wmask_in[349] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 408.031 27.009 408.085 ; + END + END w0_wmask_in[349] + PIN w0_wmask_in[350] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 408.031 27.297 408.085 ; + END + END w0_wmask_in[350] + PIN w0_wmask_in[351] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 408.031 27.585 408.085 ; + END + END w0_wmask_in[351] + PIN w0_wmask_in[352] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 408.031 27.873 408.085 ; + END + END w0_wmask_in[352] + PIN w0_wmask_in[353] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 408.031 28.161 408.085 ; + END + END w0_wmask_in[353] + PIN w0_wmask_in[354] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 408.031 28.449 408.085 ; + END + END w0_wmask_in[354] + PIN w0_wmask_in[355] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 408.031 28.737 408.085 ; + END + END w0_wmask_in[355] + PIN w0_wmask_in[356] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 408.031 29.025 408.085 ; + END + END w0_wmask_in[356] + PIN w0_wmask_in[357] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 408.031 29.313 408.085 ; + END + END w0_wmask_in[357] + PIN w0_wmask_in[358] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 408.031 29.601 408.085 ; + END + END w0_wmask_in[358] + PIN w0_wmask_in[359] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 408.031 29.889 408.085 ; + END + END w0_wmask_in[359] + PIN w0_wmask_in[360] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 408.031 30.177 408.085 ; + END + END w0_wmask_in[360] + PIN w0_wmask_in[361] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 408.031 30.465 408.085 ; + END + END w0_wmask_in[361] + PIN w0_wmask_in[362] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 408.031 30.753 408.085 ; + END + END w0_wmask_in[362] + PIN w0_wmask_in[363] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 408.031 31.041 408.085 ; + END + END w0_wmask_in[363] + PIN w0_wmask_in[364] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 408.031 31.329 408.085 ; + END + END w0_wmask_in[364] + PIN w0_wmask_in[365] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 408.031 31.617 408.085 ; + END + END w0_wmask_in[365] + PIN w0_wmask_in[366] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 408.031 31.905 408.085 ; + END + END w0_wmask_in[366] + PIN w0_wmask_in[367] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 408.031 32.193 408.085 ; + END + END w0_wmask_in[367] + PIN w0_wmask_in[368] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 408.031 32.481 408.085 ; + END + END w0_wmask_in[368] + PIN w0_wmask_in[369] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 408.031 32.769 408.085 ; + END + END w0_wmask_in[369] + PIN w0_wmask_in[370] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 408.031 33.057 408.085 ; + END + END w0_wmask_in[370] + PIN w0_wmask_in[371] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 408.031 33.345 408.085 ; + END + END w0_wmask_in[371] + PIN w0_wmask_in[372] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 408.031 33.633 408.085 ; + END + END w0_wmask_in[372] + PIN w0_wmask_in[373] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 408.031 33.921 408.085 ; + END + END w0_wmask_in[373] + PIN w0_wmask_in[374] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 408.031 34.209 408.085 ; + END + END w0_wmask_in[374] + PIN w0_wmask_in[375] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 408.031 34.497 408.085 ; + END + END w0_wmask_in[375] + PIN w0_wmask_in[376] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 408.031 34.785 408.085 ; + END + END w0_wmask_in[376] + PIN w0_wmask_in[377] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 408.031 35.073 408.085 ; + END + END w0_wmask_in[377] + PIN w0_wmask_in[378] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 408.031 35.361 408.085 ; + END + END w0_wmask_in[378] + PIN w0_wmask_in[379] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 408.031 35.649 408.085 ; + END + END w0_wmask_in[379] + PIN w0_wmask_in[380] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 408.031 35.937 408.085 ; + END + END w0_wmask_in[380] + PIN w0_wmask_in[381] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 408.031 36.225 408.085 ; + END + END w0_wmask_in[381] + PIN w0_wmask_in[382] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 408.031 36.513 408.085 ; + END + END w0_wmask_in[382] + PIN w0_wmask_in[383] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 408.031 36.801 408.085 ; + END + END w0_wmask_in[383] + PIN w0_wmask_in[384] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 408.031 37.089 408.085 ; + END + END w0_wmask_in[384] + PIN w0_wmask_in[385] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 408.031 37.377 408.085 ; + END + END w0_wmask_in[385] + PIN w0_wmask_in[386] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 408.031 37.665 408.085 ; + END + END w0_wmask_in[386] + PIN w0_wmask_in[387] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 408.031 37.953 408.085 ; + END + END w0_wmask_in[387] + PIN w0_wmask_in[388] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 408.031 38.241 408.085 ; + END + END w0_wmask_in[388] + PIN w0_wmask_in[389] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 408.031 38.529 408.085 ; + END + END w0_wmask_in[389] + PIN w0_wmask_in[390] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 408.031 38.817 408.085 ; + END + END w0_wmask_in[390] + PIN w0_wmask_in[391] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 408.031 39.105 408.085 ; + END + END w0_wmask_in[391] + PIN w0_wmask_in[392] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 408.031 39.393 408.085 ; + END + END w0_wmask_in[392] + PIN w0_wmask_in[393] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 408.031 39.681 408.085 ; + END + END w0_wmask_in[393] + PIN w0_wmask_in[394] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 408.031 39.969 408.085 ; + END + END w0_wmask_in[394] + PIN w0_wmask_in[395] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 408.031 40.257 408.085 ; + END + END w0_wmask_in[395] + PIN w0_wmask_in[396] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 408.031 40.545 408.085 ; + END + END w0_wmask_in[396] + PIN w0_wmask_in[397] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 408.031 40.833 408.085 ; + END + END w0_wmask_in[397] + PIN w0_wmask_in[398] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 408.031 41.121 408.085 ; + END + END w0_wmask_in[398] + PIN w0_wmask_in[399] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 408.031 41.409 408.085 ; + END + END w0_wmask_in[399] + PIN w0_wmask_in[400] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 408.031 41.697 408.085 ; + END + END w0_wmask_in[400] + PIN w0_wmask_in[401] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 408.031 41.985 408.085 ; + END + END w0_wmask_in[401] + PIN w0_wmask_in[402] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 408.031 42.273 408.085 ; + END + END w0_wmask_in[402] + PIN w0_wmask_in[403] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 408.031 42.561 408.085 ; + END + END w0_wmask_in[403] + PIN w0_wmask_in[404] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 408.031 42.849 408.085 ; + END + END w0_wmask_in[404] + PIN w0_wmask_in[405] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 408.031 43.137 408.085 ; + END + END w0_wmask_in[405] + PIN w0_wmask_in[406] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 408.031 43.425 408.085 ; + END + END w0_wmask_in[406] + PIN w0_wmask_in[407] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 408.031 43.713 408.085 ; + END + END w0_wmask_in[407] + PIN w0_wmask_in[408] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 408.031 44.001 408.085 ; + END + END w0_wmask_in[408] + PIN w0_wmask_in[409] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 408.031 44.289 408.085 ; + END + END w0_wmask_in[409] + PIN w0_wmask_in[410] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 408.031 44.577 408.085 ; + END + END w0_wmask_in[410] + PIN w0_wmask_in[411] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 408.031 44.865 408.085 ; + END + END w0_wmask_in[411] + PIN w0_wmask_in[412] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 408.031 45.153 408.085 ; + END + END w0_wmask_in[412] + PIN w0_wmask_in[413] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 408.031 45.441 408.085 ; + END + END w0_wmask_in[413] + PIN w0_wmask_in[414] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 408.031 45.729 408.085 ; + END + END w0_wmask_in[414] + PIN w0_wmask_in[415] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 408.031 46.017 408.085 ; + END + END w0_wmask_in[415] + PIN w0_wmask_in[416] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 408.031 46.305 408.085 ; + END + END w0_wmask_in[416] + PIN w0_wmask_in[417] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 408.031 46.593 408.085 ; + END + END w0_wmask_in[417] + PIN w0_wmask_in[418] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 408.031 46.881 408.085 ; + END + END w0_wmask_in[418] + PIN w0_wmask_in[419] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 408.031 47.169 408.085 ; + END + END w0_wmask_in[419] + PIN w0_wmask_in[420] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 408.031 47.457 408.085 ; + END + END w0_wmask_in[420] + PIN w0_wmask_in[421] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 408.031 47.745 408.085 ; + END + END w0_wmask_in[421] + PIN w0_wmask_in[422] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 408.031 48.033 408.085 ; + END + END w0_wmask_in[422] + PIN w0_wmask_in[423] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 408.031 48.321 408.085 ; + END + END w0_wmask_in[423] + PIN w0_wmask_in[424] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 408.031 48.609 408.085 ; + END + END w0_wmask_in[424] + PIN w0_wmask_in[425] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 408.031 48.897 408.085 ; + END + END w0_wmask_in[425] + PIN w0_wmask_in[426] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 408.031 49.185 408.085 ; + END + END w0_wmask_in[426] + PIN w0_wmask_in[427] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 408.031 49.473 408.085 ; + END + END w0_wmask_in[427] + PIN w0_wmask_in[428] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 408.031 49.761 408.085 ; + END + END w0_wmask_in[428] + PIN w0_wmask_in[429] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 408.031 50.049 408.085 ; + END + END w0_wmask_in[429] + PIN w0_wmask_in[430] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 408.031 50.337 408.085 ; + END + END w0_wmask_in[430] + PIN w0_wmask_in[431] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 408.031 50.625 408.085 ; + END + END w0_wmask_in[431] + PIN w0_wmask_in[432] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 408.031 50.913 408.085 ; + END + END w0_wmask_in[432] + PIN w0_wmask_in[433] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 408.031 51.201 408.085 ; + END + END w0_wmask_in[433] + PIN w0_wmask_in[434] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 408.031 51.489 408.085 ; + END + END w0_wmask_in[434] + PIN w0_wmask_in[435] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 408.031 51.777 408.085 ; + END + END w0_wmask_in[435] + PIN w0_wmask_in[436] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 408.031 52.065 408.085 ; + END + END w0_wmask_in[436] + PIN w0_wmask_in[437] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 408.031 52.353 408.085 ; + END + END w0_wmask_in[437] + PIN w0_wmask_in[438] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 408.031 52.641 408.085 ; + END + END w0_wmask_in[438] + PIN w0_wmask_in[439] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 408.031 52.929 408.085 ; + END + END w0_wmask_in[439] + PIN w0_wmask_in[440] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 408.031 53.217 408.085 ; + END + END w0_wmask_in[440] + PIN w0_wmask_in[441] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 408.031 53.505 408.085 ; + END + END w0_wmask_in[441] + PIN w0_wmask_in[442] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 408.031 53.793 408.085 ; + END + END w0_wmask_in[442] + PIN w0_wmask_in[443] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 408.031 54.081 408.085 ; + END + END w0_wmask_in[443] + PIN w0_wmask_in[444] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 408.031 54.369 408.085 ; + END + END w0_wmask_in[444] + PIN w0_wmask_in[445] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 408.031 54.657 408.085 ; + END + END w0_wmask_in[445] + PIN w0_wmask_in[446] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 408.031 54.945 408.085 ; + END + END w0_wmask_in[446] + PIN w0_wmask_in[447] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 408.031 55.233 408.085 ; + END + END w0_wmask_in[447] + PIN w0_wmask_in[448] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 408.031 55.521 408.085 ; + END + END w0_wmask_in[448] + PIN w0_wmask_in[449] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 408.031 55.809 408.085 ; + END + END w0_wmask_in[449] + PIN w0_wmask_in[450] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 408.031 56.097 408.085 ; + END + END w0_wmask_in[450] + PIN w0_wmask_in[451] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 408.031 56.385 408.085 ; + END + END w0_wmask_in[451] + PIN w0_wmask_in[452] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 408.031 56.673 408.085 ; + END + END w0_wmask_in[452] + PIN w0_wmask_in[453] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 408.031 56.961 408.085 ; + END + END w0_wmask_in[453] + PIN w0_wmask_in[454] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 408.031 57.249 408.085 ; + END + END w0_wmask_in[454] + PIN w0_wmask_in[455] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 408.031 57.537 408.085 ; + END + END w0_wmask_in[455] + PIN w0_wmask_in[456] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 408.031 57.825 408.085 ; + END + END w0_wmask_in[456] + PIN w0_wmask_in[457] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 408.031 58.113 408.085 ; + END + END w0_wmask_in[457] + PIN w0_wmask_in[458] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 408.031 58.401 408.085 ; + END + END w0_wmask_in[458] + PIN w0_wmask_in[459] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 408.031 58.689 408.085 ; + END + END w0_wmask_in[459] + PIN w0_wmask_in[460] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 408.031 58.977 408.085 ; + END + END w0_wmask_in[460] + PIN w0_wmask_in[461] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 408.031 59.265 408.085 ; + END + END w0_wmask_in[461] + PIN w0_wmask_in[462] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 408.031 59.553 408.085 ; + END + END w0_wmask_in[462] + PIN w0_wmask_in[463] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 408.031 59.841 408.085 ; + END + END w0_wmask_in[463] + PIN w0_wmask_in[464] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 408.031 60.129 408.085 ; + END + END w0_wmask_in[464] + PIN w0_wmask_in[465] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 408.031 60.417 408.085 ; + END + END w0_wmask_in[465] + PIN w0_wmask_in[466] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 408.031 60.705 408.085 ; + END + END w0_wmask_in[466] + PIN w0_wmask_in[467] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 408.031 60.993 408.085 ; + END + END w0_wmask_in[467] + PIN w0_wmask_in[468] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 408.031 61.281 408.085 ; + END + END w0_wmask_in[468] + PIN w0_wmask_in[469] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 408.031 61.569 408.085 ; + END + END w0_wmask_in[469] + PIN w0_wmask_in[470] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 408.031 61.857 408.085 ; + END + END w0_wmask_in[470] + PIN w0_wmask_in[471] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 408.031 62.145 408.085 ; + END + END w0_wmask_in[471] + PIN w0_wmask_in[472] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 408.031 62.433 408.085 ; + END + END w0_wmask_in[472] + PIN w0_wmask_in[473] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 408.031 62.721 408.085 ; + END + END w0_wmask_in[473] + PIN w0_wmask_in[474] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 408.031 63.009 408.085 ; + END + END w0_wmask_in[474] + PIN w0_wmask_in[475] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 408.031 63.297 408.085 ; + END + END w0_wmask_in[475] + PIN w0_wmask_in[476] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 408.031 63.585 408.085 ; + END + END w0_wmask_in[476] + PIN w0_wmask_in[477] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 408.031 63.873 408.085 ; + END + END w0_wmask_in[477] + PIN w0_wmask_in[478] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 408.031 64.161 408.085 ; + END + END w0_wmask_in[478] + PIN w0_wmask_in[479] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 408.031 64.449 408.085 ; + END + END w0_wmask_in[479] + PIN w0_wmask_in[480] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 408.031 64.737 408.085 ; + END + END w0_wmask_in[480] + PIN w0_wmask_in[481] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 408.031 65.025 408.085 ; + END + END w0_wmask_in[481] + PIN w0_wmask_in[482] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 408.031 65.313 408.085 ; + END + END w0_wmask_in[482] + PIN w0_wmask_in[483] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 408.031 65.601 408.085 ; + END + END w0_wmask_in[483] + PIN w0_wmask_in[484] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 408.031 65.889 408.085 ; + END + END w0_wmask_in[484] + PIN w0_wmask_in[485] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 408.031 66.177 408.085 ; + END + END w0_wmask_in[485] + PIN w0_wmask_in[486] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 408.031 66.465 408.085 ; + END + END w0_wmask_in[486] + PIN w0_wmask_in[487] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 408.031 66.753 408.085 ; + END + END w0_wmask_in[487] + PIN w0_wmask_in[488] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 408.031 67.041 408.085 ; + END + END w0_wmask_in[488] + PIN w0_wmask_in[489] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 408.031 67.329 408.085 ; + END + END w0_wmask_in[489] + PIN w0_wmask_in[490] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 408.031 67.617 408.085 ; + END + END w0_wmask_in[490] + PIN w0_wmask_in[491] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 408.031 67.905 408.085 ; + END + END w0_wmask_in[491] + PIN w0_wmask_in[492] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 408.031 68.193 408.085 ; + END + END w0_wmask_in[492] + PIN w0_wmask_in[493] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 408.031 68.481 408.085 ; + END + END w0_wmask_in[493] + PIN w0_wmask_in[494] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 408.031 68.769 408.085 ; + END + END w0_wmask_in[494] + PIN w0_wmask_in[495] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 408.031 69.057 408.085 ; + END + END w0_wmask_in[495] + PIN w0_wmask_in[496] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 408.031 69.345 408.085 ; + END + END w0_wmask_in[496] + PIN w0_wmask_in[497] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 408.031 69.633 408.085 ; + END + END w0_wmask_in[497] + PIN w0_wmask_in[498] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 408.031 69.921 408.085 ; + END + END w0_wmask_in[498] + PIN w0_wmask_in[499] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 408.031 70.209 408.085 ; + END + END w0_wmask_in[499] + PIN w0_wmask_in[500] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 408.031 70.497 408.085 ; + END + END w0_wmask_in[500] + PIN w0_wmask_in[501] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 408.031 70.785 408.085 ; + END + END w0_wmask_in[501] + PIN w0_wmask_in[502] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 408.031 71.073 408.085 ; + END + END w0_wmask_in[502] + PIN w0_wmask_in[503] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 408.031 71.361 408.085 ; + END + END w0_wmask_in[503] + PIN w0_wmask_in[504] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 408.031 71.649 408.085 ; + END + END w0_wmask_in[504] + PIN w0_wmask_in[505] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 408.031 71.937 408.085 ; + END + END w0_wmask_in[505] + PIN w0_wmask_in[506] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 408.031 72.225 408.085 ; + END + END w0_wmask_in[506] + PIN w0_wmask_in[507] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 408.031 72.513 408.085 ; + END + END w0_wmask_in[507] + PIN w0_wmask_in[508] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 408.031 72.801 408.085 ; + END + END w0_wmask_in[508] + PIN w0_wmask_in[509] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 408.031 73.089 408.085 ; + END + END w0_wmask_in[509] + PIN w0_wmask_in[510] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 408.031 73.377 408.085 ; + END + END w0_wmask_in[510] + PIN w0_wmask_in[511] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 408.031 73.665 408.085 ; + END + END w0_wmask_in[511] PIN w0_wd_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; + RECT 0.000 190.740 0.072 190.764 ; END END w0_wd_in[0] PIN w0_wd_in[1] @@ -20,7 +4628,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.428 0.024 1.452 ; + RECT 0.000 192.228 0.072 192.252 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +4637,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.580 0.024 2.604 ; + RECT 0.000 193.716 0.072 193.740 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +4646,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.732 0.024 3.756 ; + RECT 0.000 195.204 0.072 195.228 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +4655,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.884 0.024 4.908 ; + RECT 0.000 196.692 0.072 196.716 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +4664,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.036 0.024 6.060 ; + RECT 0.000 198.180 0.072 198.204 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +4673,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.188 0.024 7.212 ; + RECT 0.000 199.668 0.072 199.692 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +4682,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.340 0.024 8.364 ; + RECT 0.000 201.156 0.072 201.180 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +4691,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.492 0.024 9.516 ; + RECT 0.000 202.644 0.072 202.668 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,7 +4700,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 10.644 0.024 10.668 ; + RECT 0.000 204.132 0.072 204.156 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,7 +4709,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 11.796 0.024 11.820 ; + RECT 0.000 205.620 0.072 205.644 ; END END w0_wd_in[10] PIN w0_wd_in[11] @@ -110,7 +4718,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 12.948 0.024 12.972 ; + RECT 0.000 207.108 0.072 207.132 ; END END w0_wd_in[11] PIN w0_wd_in[12] @@ -119,7 +4727,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 14.100 0.024 14.124 ; + RECT 0.000 208.596 0.072 208.620 ; END END w0_wd_in[12] PIN w0_wd_in[13] @@ -128,7 +4736,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 15.252 0.024 15.276 ; + RECT 0.000 210.084 0.072 210.108 ; END END w0_wd_in[13] PIN w0_wd_in[14] @@ -137,7 +4745,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 16.404 0.024 16.428 ; + RECT 0.000 211.572 0.072 211.596 ; END END w0_wd_in[14] PIN w0_wd_in[15] @@ -146,7 +4754,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 17.556 0.024 17.580 ; + RECT 0.000 213.060 0.072 213.084 ; END END w0_wd_in[15] PIN w0_wd_in[16] @@ -155,7 +4763,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 18.708 0.024 18.732 ; + RECT 0.000 214.548 0.072 214.572 ; END END w0_wd_in[16] PIN w0_wd_in[17] @@ -164,7 +4772,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 19.860 0.024 19.884 ; + RECT 0.000 216.036 0.072 216.060 ; END END w0_wd_in[17] PIN w0_wd_in[18] @@ -173,7 +4781,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 21.012 0.024 21.036 ; + RECT 0.000 217.524 0.072 217.548 ; END END w0_wd_in[18] PIN w0_wd_in[19] @@ -182,7 +4790,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 22.164 0.024 22.188 ; + RECT 0.000 219.012 0.072 219.036 ; END END w0_wd_in[19] PIN w0_wd_in[20] @@ -191,7 +4799,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 23.316 0.024 23.340 ; + RECT 0.000 220.500 0.072 220.524 ; END END w0_wd_in[20] PIN w0_wd_in[21] @@ -200,7 +4808,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 24.468 0.024 24.492 ; + RECT 0.000 221.988 0.072 222.012 ; END END w0_wd_in[21] PIN w0_wd_in[22] @@ -209,7 +4817,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 25.620 0.024 25.644 ; + RECT 0.000 223.476 0.072 223.500 ; END END w0_wd_in[22] PIN w0_wd_in[23] @@ -218,7 +4826,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 26.772 0.024 26.796 ; + RECT 0.000 224.964 0.072 224.988 ; END END w0_wd_in[23] PIN w0_wd_in[24] @@ -227,7 +4835,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 27.924 0.024 27.948 ; + RECT 0.000 226.452 0.072 226.476 ; END END w0_wd_in[24] PIN w0_wd_in[25] @@ -236,7 +4844,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 29.076 0.024 29.100 ; + RECT 0.000 227.940 0.072 227.964 ; END END w0_wd_in[25] PIN w0_wd_in[26] @@ -245,7 +4853,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 30.228 0.024 30.252 ; + RECT 0.000 229.428 0.072 229.452 ; END END w0_wd_in[26] PIN w0_wd_in[27] @@ -254,7 +4862,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 31.380 0.024 31.404 ; + RECT 0.000 230.916 0.072 230.940 ; END END w0_wd_in[27] PIN w0_wd_in[28] @@ -263,7 +4871,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 32.532 0.024 32.556 ; + RECT 0.000 232.404 0.072 232.428 ; END END w0_wd_in[28] PIN w0_wd_in[29] @@ -272,7 +4880,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 33.684 0.024 33.708 ; + RECT 0.000 233.892 0.072 233.916 ; END END w0_wd_in[29] PIN w0_wd_in[30] @@ -281,7 +4889,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 34.836 0.024 34.860 ; + RECT 0.000 235.380 0.072 235.404 ; END END w0_wd_in[30] PIN w0_wd_in[31] @@ -290,7 +4898,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 35.988 0.024 36.012 ; + RECT 0.000 236.868 0.072 236.892 ; END END w0_wd_in[31] PIN w0_wd_in[32] @@ -299,7 +4907,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 37.140 0.024 37.164 ; + RECT 0.000 238.356 0.072 238.380 ; END END w0_wd_in[32] PIN w0_wd_in[33] @@ -308,7 +4916,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 38.292 0.024 38.316 ; + RECT 0.000 239.844 0.072 239.868 ; END END w0_wd_in[33] PIN w0_wd_in[34] @@ -317,7 +4925,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 39.444 0.024 39.468 ; + RECT 0.000 241.332 0.072 241.356 ; END END w0_wd_in[34] PIN w0_wd_in[35] @@ -326,7 +4934,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 40.596 0.024 40.620 ; + RECT 0.000 242.820 0.072 242.844 ; END END w0_wd_in[35] PIN w0_wd_in[36] @@ -335,7 +4943,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 41.748 0.024 41.772 ; + RECT 0.000 244.308 0.072 244.332 ; END END w0_wd_in[36] PIN w0_wd_in[37] @@ -344,7 +4952,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 42.900 0.024 42.924 ; + RECT 0.000 245.796 0.072 245.820 ; END END w0_wd_in[37] PIN w0_wd_in[38] @@ -353,7 +4961,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 44.052 0.024 44.076 ; + RECT 0.000 247.284 0.072 247.308 ; END END w0_wd_in[38] PIN w0_wd_in[39] @@ -362,7 +4970,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 45.204 0.024 45.228 ; + RECT 0.000 248.772 0.072 248.796 ; END END w0_wd_in[39] PIN w0_wd_in[40] @@ -371,7 +4979,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 46.356 0.024 46.380 ; + RECT 0.000 250.260 0.072 250.284 ; END END w0_wd_in[40] PIN w0_wd_in[41] @@ -380,7 +4988,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 47.508 0.024 47.532 ; + RECT 0.000 251.748 0.072 251.772 ; END END w0_wd_in[41] PIN w0_wd_in[42] @@ -389,7 +4997,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 48.660 0.024 48.684 ; + RECT 0.000 253.236 0.072 253.260 ; END END w0_wd_in[42] PIN w0_wd_in[43] @@ -398,7 +5006,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 49.812 0.024 49.836 ; + RECT 0.000 254.724 0.072 254.748 ; END END w0_wd_in[43] PIN w0_wd_in[44] @@ -407,7 +5015,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 50.964 0.024 50.988 ; + RECT 0.000 256.212 0.072 256.236 ; END END w0_wd_in[44] PIN w0_wd_in[45] @@ -416,7 +5024,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 52.116 0.024 52.140 ; + RECT 0.000 257.700 0.072 257.724 ; END END w0_wd_in[45] PIN w0_wd_in[46] @@ -425,7 +5033,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 53.268 0.024 53.292 ; + RECT 0.000 259.188 0.072 259.212 ; END END w0_wd_in[46] PIN w0_wd_in[47] @@ -434,7 +5042,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 54.420 0.024 54.444 ; + RECT 0.000 260.676 0.072 260.700 ; END END w0_wd_in[47] PIN w0_wd_in[48] @@ -443,7 +5051,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 55.572 0.024 55.596 ; + RECT 0.000 262.164 0.072 262.188 ; END END w0_wd_in[48] PIN w0_wd_in[49] @@ -452,7 +5060,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 56.724 0.024 56.748 ; + RECT 0.000 263.652 0.072 263.676 ; END END w0_wd_in[49] PIN w0_wd_in[50] @@ -461,7 +5069,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 57.876 0.024 57.900 ; + RECT 0.000 265.140 0.072 265.164 ; END END w0_wd_in[50] PIN w0_wd_in[51] @@ -470,7 +5078,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 59.028 0.024 59.052 ; + RECT 0.000 266.628 0.072 266.652 ; END END w0_wd_in[51] PIN w0_wd_in[52] @@ -479,7 +5087,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 60.180 0.024 60.204 ; + RECT 0.000 268.116 0.072 268.140 ; END END w0_wd_in[52] PIN w0_wd_in[53] @@ -488,7 +5096,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 61.332 0.024 61.356 ; + RECT 0.000 269.604 0.072 269.628 ; END END w0_wd_in[53] PIN w0_wd_in[54] @@ -497,7 +5105,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 62.484 0.024 62.508 ; + RECT 0.000 271.092 0.072 271.116 ; END END w0_wd_in[54] PIN w0_wd_in[55] @@ -506,7 +5114,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 63.636 0.024 63.660 ; + RECT 0.000 272.580 0.072 272.604 ; END END w0_wd_in[55] PIN w0_wd_in[56] @@ -515,7 +5123,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 64.788 0.024 64.812 ; + RECT 0.000 274.068 0.072 274.092 ; END END w0_wd_in[56] PIN w0_wd_in[57] @@ -524,7 +5132,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 65.940 0.024 65.964 ; + RECT 0.000 275.556 0.072 275.580 ; END END w0_wd_in[57] PIN w0_wd_in[58] @@ -533,7 +5141,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 67.092 0.024 67.116 ; + RECT 0.000 277.044 0.072 277.068 ; END END w0_wd_in[58] PIN w0_wd_in[59] @@ -542,7 +5150,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 68.244 0.024 68.268 ; + RECT 0.000 278.532 0.072 278.556 ; END END w0_wd_in[59] PIN w0_wd_in[60] @@ -551,7 +5159,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 69.396 0.024 69.420 ; + RECT 0.000 280.020 0.072 280.044 ; END END w0_wd_in[60] PIN w0_wd_in[61] @@ -560,7 +5168,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 70.548 0.024 70.572 ; + RECT 0.000 281.508 0.072 281.532 ; END END w0_wd_in[61] PIN w0_wd_in[62] @@ -569,7 +5177,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 71.700 0.024 71.724 ; + RECT 0.000 282.996 0.072 283.020 ; END END w0_wd_in[62] PIN w0_wd_in[63] @@ -578,7 +5186,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 72.852 0.024 72.876 ; + RECT 0.000 284.484 0.072 284.508 ; END END w0_wd_in[63] PIN w0_wd_in[64] @@ -587,7 +5195,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 74.004 0.024 74.028 ; + RECT 0.000 285.972 0.072 285.996 ; END END w0_wd_in[64] PIN w0_wd_in[65] @@ -596,7 +5204,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 75.156 0.024 75.180 ; + RECT 0.000 287.460 0.072 287.484 ; END END w0_wd_in[65] PIN w0_wd_in[66] @@ -605,7 +5213,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 76.308 0.024 76.332 ; + RECT 0.000 288.948 0.072 288.972 ; END END w0_wd_in[66] PIN w0_wd_in[67] @@ -614,7 +5222,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 77.460 0.024 77.484 ; + RECT 0.000 290.436 0.072 290.460 ; END END w0_wd_in[67] PIN w0_wd_in[68] @@ -623,7 +5231,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 78.612 0.024 78.636 ; + RECT 0.000 291.924 0.072 291.948 ; END END w0_wd_in[68] PIN w0_wd_in[69] @@ -632,7 +5240,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 79.764 0.024 79.788 ; + RECT 0.000 293.412 0.072 293.436 ; END END w0_wd_in[69] PIN w0_wd_in[70] @@ -641,7 +5249,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 80.916 0.024 80.940 ; + RECT 0.000 294.900 0.072 294.924 ; END END w0_wd_in[70] PIN w0_wd_in[71] @@ -650,7 +5258,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 82.068 0.024 82.092 ; + RECT 0.000 296.388 0.072 296.412 ; END END w0_wd_in[71] PIN w0_wd_in[72] @@ -659,7 +5267,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 83.220 0.024 83.244 ; + RECT 0.000 297.876 0.072 297.900 ; END END w0_wd_in[72] PIN w0_wd_in[73] @@ -668,7 +5276,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 84.372 0.024 84.396 ; + RECT 0.000 299.364 0.072 299.388 ; END END w0_wd_in[73] PIN w0_wd_in[74] @@ -677,7 +5285,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 85.524 0.024 85.548 ; + RECT 0.000 300.852 0.072 300.876 ; END END w0_wd_in[74] PIN w0_wd_in[75] @@ -686,7 +5294,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 86.676 0.024 86.700 ; + RECT 0.000 302.340 0.072 302.364 ; END END w0_wd_in[75] PIN w0_wd_in[76] @@ -695,7 +5303,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 87.828 0.024 87.852 ; + RECT 0.000 303.828 0.072 303.852 ; END END w0_wd_in[76] PIN w0_wd_in[77] @@ -704,7 +5312,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 88.980 0.024 89.004 ; + RECT 0.000 305.316 0.072 305.340 ; END END w0_wd_in[77] PIN w0_wd_in[78] @@ -713,7 +5321,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 90.132 0.024 90.156 ; + RECT 0.000 306.804 0.072 306.828 ; END END w0_wd_in[78] PIN w0_wd_in[79] @@ -722,7 +5330,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 91.284 0.024 91.308 ; + RECT 0.000 308.292 0.072 308.316 ; END END w0_wd_in[79] PIN w0_wd_in[80] @@ -731,7 +5339,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 92.436 0.024 92.460 ; + RECT 0.000 309.780 0.072 309.804 ; END END w0_wd_in[80] PIN w0_wd_in[81] @@ -740,7 +5348,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 93.588 0.024 93.612 ; + RECT 0.000 311.268 0.072 311.292 ; END END w0_wd_in[81] PIN w0_wd_in[82] @@ -749,7 +5357,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 94.740 0.024 94.764 ; + RECT 0.000 312.756 0.072 312.780 ; END END w0_wd_in[82] PIN w0_wd_in[83] @@ -758,7 +5366,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 95.892 0.024 95.916 ; + RECT 0.000 314.244 0.072 314.268 ; END END w0_wd_in[83] PIN w0_wd_in[84] @@ -767,7 +5375,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 97.044 0.024 97.068 ; + RECT 0.000 315.732 0.072 315.756 ; END END w0_wd_in[84] PIN w0_wd_in[85] @@ -776,7 +5384,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 98.196 0.024 98.220 ; + RECT 0.000 317.220 0.072 317.244 ; END END w0_wd_in[85] PIN w0_wd_in[86] @@ -785,7 +5393,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 99.348 0.024 99.372 ; + RECT 0.000 318.708 0.072 318.732 ; END END w0_wd_in[86] PIN w0_wd_in[87] @@ -794,7 +5402,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 100.500 0.024 100.524 ; + RECT 0.000 320.196 0.072 320.220 ; END END w0_wd_in[87] PIN w0_wd_in[88] @@ -803,7 +5411,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 101.652 0.024 101.676 ; + RECT 0.000 321.684 0.072 321.708 ; END END w0_wd_in[88] PIN w0_wd_in[89] @@ -812,7 +5420,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 102.804 0.024 102.828 ; + RECT 0.000 323.172 0.072 323.196 ; END END w0_wd_in[89] PIN w0_wd_in[90] @@ -821,7 +5429,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 103.956 0.024 103.980 ; + RECT 0.000 324.660 0.072 324.684 ; END END w0_wd_in[90] PIN w0_wd_in[91] @@ -830,7 +5438,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 105.108 0.024 105.132 ; + RECT 0.000 326.148 0.072 326.172 ; END END w0_wd_in[91] PIN w0_wd_in[92] @@ -839,7 +5447,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 106.260 0.024 106.284 ; + RECT 0.000 327.636 0.072 327.660 ; END END w0_wd_in[92] PIN w0_wd_in[93] @@ -848,7 +5456,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 107.412 0.024 107.436 ; + RECT 0.000 329.124 0.072 329.148 ; END END w0_wd_in[93] PIN w0_wd_in[94] @@ -857,7 +5465,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 108.564 0.024 108.588 ; + RECT 0.000 330.612 0.072 330.636 ; END END w0_wd_in[94] PIN w0_wd_in[95] @@ -866,7 +5474,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 109.716 0.024 109.740 ; + RECT 0.000 332.100 0.072 332.124 ; END END w0_wd_in[95] PIN w0_wd_in[96] @@ -875,7 +5483,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 110.868 0.024 110.892 ; + RECT 0.000 333.588 0.072 333.612 ; END END w0_wd_in[96] PIN w0_wd_in[97] @@ -884,7 +5492,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 112.020 0.024 112.044 ; + RECT 0.000 335.076 0.072 335.100 ; END END w0_wd_in[97] PIN w0_wd_in[98] @@ -893,7 +5501,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 113.172 0.024 113.196 ; + RECT 0.000 336.564 0.072 336.588 ; END END w0_wd_in[98] PIN w0_wd_in[99] @@ -902,7 +5510,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 114.324 0.024 114.348 ; + RECT 0.000 338.052 0.072 338.076 ; END END w0_wd_in[99] PIN w0_wd_in[100] @@ -911,7 +5519,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 115.476 0.024 115.500 ; + RECT 0.000 339.540 0.072 339.564 ; END END w0_wd_in[100] PIN w0_wd_in[101] @@ -920,7 +5528,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 116.628 0.024 116.652 ; + RECT 0.000 341.028 0.072 341.052 ; END END w0_wd_in[101] PIN w0_wd_in[102] @@ -929,7 +5537,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 117.780 0.024 117.804 ; + RECT 0.000 342.516 0.072 342.540 ; END END w0_wd_in[102] PIN w0_wd_in[103] @@ -938,7 +5546,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 118.932 0.024 118.956 ; + RECT 0.000 344.004 0.072 344.028 ; END END w0_wd_in[103] PIN w0_wd_in[104] @@ -947,7 +5555,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 120.084 0.024 120.108 ; + RECT 0.000 345.492 0.072 345.516 ; END END w0_wd_in[104] PIN w0_wd_in[105] @@ -956,7 +5564,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 121.236 0.024 121.260 ; + RECT 0.000 346.980 0.072 347.004 ; END END w0_wd_in[105] PIN w0_wd_in[106] @@ -965,7 +5573,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 122.388 0.024 122.412 ; + RECT 0.000 348.468 0.072 348.492 ; END END w0_wd_in[106] PIN w0_wd_in[107] @@ -974,7 +5582,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 123.540 0.024 123.564 ; + RECT 0.000 349.956 0.072 349.980 ; END END w0_wd_in[107] PIN w0_wd_in[108] @@ -983,7 +5591,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 124.692 0.024 124.716 ; + RECT 0.000 351.444 0.072 351.468 ; END END w0_wd_in[108] PIN w0_wd_in[109] @@ -992,7 +5600,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 125.844 0.024 125.868 ; + RECT 0.000 352.932 0.072 352.956 ; END END w0_wd_in[109] PIN w0_wd_in[110] @@ -1001,7 +5609,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 126.996 0.024 127.020 ; + RECT 0.000 354.420 0.072 354.444 ; END END w0_wd_in[110] PIN w0_wd_in[111] @@ -1010,7 +5618,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 128.148 0.024 128.172 ; + RECT 0.000 355.908 0.072 355.932 ; END END w0_wd_in[111] PIN w0_wd_in[112] @@ -1019,7 +5627,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 129.300 0.024 129.324 ; + RECT 0.000 357.396 0.072 357.420 ; END END w0_wd_in[112] PIN w0_wd_in[113] @@ -1028,7 +5636,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 130.452 0.024 130.476 ; + RECT 0.000 358.884 0.072 358.908 ; END END w0_wd_in[113] PIN w0_wd_in[114] @@ -1037,7 +5645,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 131.604 0.024 131.628 ; + RECT 0.000 360.372 0.072 360.396 ; END END w0_wd_in[114] PIN w0_wd_in[115] @@ -1046,7 +5654,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 132.756 0.024 132.780 ; + RECT 0.000 361.860 0.072 361.884 ; END END w0_wd_in[115] PIN w0_wd_in[116] @@ -1055,7 +5663,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 133.908 0.024 133.932 ; + RECT 0.000 363.348 0.072 363.372 ; END END w0_wd_in[116] PIN w0_wd_in[117] @@ -1064,7 +5672,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 135.060 0.024 135.084 ; + RECT 0.000 364.836 0.072 364.860 ; END END w0_wd_in[117] PIN w0_wd_in[118] @@ -1073,7 +5681,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 136.212 0.024 136.236 ; + RECT 0.000 366.324 0.072 366.348 ; END END w0_wd_in[118] PIN w0_wd_in[119] @@ -1082,7 +5690,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 137.364 0.024 137.388 ; + RECT 0.000 367.812 0.072 367.836 ; END END w0_wd_in[119] PIN w0_wd_in[120] @@ -1091,7 +5699,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 138.516 0.024 138.540 ; + RECT 0.000 369.300 0.072 369.324 ; END END w0_wd_in[120] PIN w0_wd_in[121] @@ -1100,7 +5708,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 139.668 0.024 139.692 ; + RECT 0.000 370.788 0.072 370.812 ; END END w0_wd_in[121] PIN w0_wd_in[122] @@ -1109,7 +5717,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 140.820 0.024 140.844 ; + RECT 0.000 372.276 0.072 372.300 ; END END w0_wd_in[122] PIN w0_wd_in[123] @@ -1118,7 +5726,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 141.972 0.024 141.996 ; + RECT 0.000 373.764 0.072 373.788 ; END END w0_wd_in[123] PIN w0_wd_in[124] @@ -1127,7 +5735,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 143.124 0.024 143.148 ; + RECT 0.000 375.252 0.072 375.276 ; END END w0_wd_in[124] PIN w0_wd_in[125] @@ -1136,7 +5744,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 144.276 0.024 144.300 ; + RECT 0.000 376.740 0.072 376.764 ; END END w0_wd_in[125] PIN w0_wd_in[126] @@ -1145,7 +5753,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 145.428 0.024 145.452 ; + RECT 0.000 378.228 0.072 378.252 ; END END w0_wd_in[126] PIN w0_wd_in[127] @@ -1154,7 +5762,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 146.580 0.024 146.604 ; + RECT 0.000 379.716 0.072 379.740 ; END END w0_wd_in[127] PIN w0_wd_in[128] @@ -1163,7 +5771,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 0.276 265.421 0.300 ; + RECT 163.162 190.740 163.234 190.764 ; END END w0_wd_in[128] PIN w0_wd_in[129] @@ -1172,7 +5780,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 1.428 265.421 1.452 ; + RECT 163.162 192.228 163.234 192.252 ; END END w0_wd_in[129] PIN w0_wd_in[130] @@ -1181,7 +5789,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 2.580 265.421 2.604 ; + RECT 163.162 193.716 163.234 193.740 ; END END w0_wd_in[130] PIN w0_wd_in[131] @@ -1190,7 +5798,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 3.732 265.421 3.756 ; + RECT 163.162 195.204 163.234 195.228 ; END END w0_wd_in[131] PIN w0_wd_in[132] @@ -1199,7 +5807,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 4.884 265.421 4.908 ; + RECT 163.162 196.692 163.234 196.716 ; END END w0_wd_in[132] PIN w0_wd_in[133] @@ -1208,7 +5816,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 6.036 265.421 6.060 ; + RECT 163.162 198.180 163.234 198.204 ; END END w0_wd_in[133] PIN w0_wd_in[134] @@ -1217,7 +5825,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 7.188 265.421 7.212 ; + RECT 163.162 199.668 163.234 199.692 ; END END w0_wd_in[134] PIN w0_wd_in[135] @@ -1226,7 +5834,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 8.340 265.421 8.364 ; + RECT 163.162 201.156 163.234 201.180 ; END END w0_wd_in[135] PIN w0_wd_in[136] @@ -1235,7 +5843,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 9.492 265.421 9.516 ; + RECT 163.162 202.644 163.234 202.668 ; END END w0_wd_in[136] PIN w0_wd_in[137] @@ -1244,7 +5852,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 10.644 265.421 10.668 ; + RECT 163.162 204.132 163.234 204.156 ; END END w0_wd_in[137] PIN w0_wd_in[138] @@ -1253,7 +5861,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 11.796 265.421 11.820 ; + RECT 163.162 205.620 163.234 205.644 ; END END w0_wd_in[138] PIN w0_wd_in[139] @@ -1262,7 +5870,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 12.948 265.421 12.972 ; + RECT 163.162 207.108 163.234 207.132 ; END END w0_wd_in[139] PIN w0_wd_in[140] @@ -1271,7 +5879,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 14.100 265.421 14.124 ; + RECT 163.162 208.596 163.234 208.620 ; END END w0_wd_in[140] PIN w0_wd_in[141] @@ -1280,7 +5888,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 15.252 265.421 15.276 ; + RECT 163.162 210.084 163.234 210.108 ; END END w0_wd_in[141] PIN w0_wd_in[142] @@ -1289,7 +5897,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 16.404 265.421 16.428 ; + RECT 163.162 211.572 163.234 211.596 ; END END w0_wd_in[142] PIN w0_wd_in[143] @@ -1298,7 +5906,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 17.556 265.421 17.580 ; + RECT 163.162 213.060 163.234 213.084 ; END END w0_wd_in[143] PIN w0_wd_in[144] @@ -1307,7 +5915,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 18.708 265.421 18.732 ; + RECT 163.162 214.548 163.234 214.572 ; END END w0_wd_in[144] PIN w0_wd_in[145] @@ -1316,7 +5924,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 19.860 265.421 19.884 ; + RECT 163.162 216.036 163.234 216.060 ; END END w0_wd_in[145] PIN w0_wd_in[146] @@ -1325,7 +5933,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 21.012 265.421 21.036 ; + RECT 163.162 217.524 163.234 217.548 ; END END w0_wd_in[146] PIN w0_wd_in[147] @@ -1334,7 +5942,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 22.164 265.421 22.188 ; + RECT 163.162 219.012 163.234 219.036 ; END END w0_wd_in[147] PIN w0_wd_in[148] @@ -1343,7 +5951,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 23.316 265.421 23.340 ; + RECT 163.162 220.500 163.234 220.524 ; END END w0_wd_in[148] PIN w0_wd_in[149] @@ -1352,7 +5960,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 24.468 265.421 24.492 ; + RECT 163.162 221.988 163.234 222.012 ; END END w0_wd_in[149] PIN w0_wd_in[150] @@ -1361,7 +5969,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 25.620 265.421 25.644 ; + RECT 163.162 223.476 163.234 223.500 ; END END w0_wd_in[150] PIN w0_wd_in[151] @@ -1370,7 +5978,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 26.772 265.421 26.796 ; + RECT 163.162 224.964 163.234 224.988 ; END END w0_wd_in[151] PIN w0_wd_in[152] @@ -1379,7 +5987,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 27.924 265.421 27.948 ; + RECT 163.162 226.452 163.234 226.476 ; END END w0_wd_in[152] PIN w0_wd_in[153] @@ -1388,7 +5996,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 29.076 265.421 29.100 ; + RECT 163.162 227.940 163.234 227.964 ; END END w0_wd_in[153] PIN w0_wd_in[154] @@ -1397,7 +6005,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 30.228 265.421 30.252 ; + RECT 163.162 229.428 163.234 229.452 ; END END w0_wd_in[154] PIN w0_wd_in[155] @@ -1406,7 +6014,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 31.380 265.421 31.404 ; + RECT 163.162 230.916 163.234 230.940 ; END END w0_wd_in[155] PIN w0_wd_in[156] @@ -1415,7 +6023,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 32.532 265.421 32.556 ; + RECT 163.162 232.404 163.234 232.428 ; END END w0_wd_in[156] PIN w0_wd_in[157] @@ -1424,7 +6032,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 33.684 265.421 33.708 ; + RECT 163.162 233.892 163.234 233.916 ; END END w0_wd_in[157] PIN w0_wd_in[158] @@ -1433,7 +6041,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 34.836 265.421 34.860 ; + RECT 163.162 235.380 163.234 235.404 ; END END w0_wd_in[158] PIN w0_wd_in[159] @@ -1442,7 +6050,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 35.988 265.421 36.012 ; + RECT 163.162 236.868 163.234 236.892 ; END END w0_wd_in[159] PIN w0_wd_in[160] @@ -1451,7 +6059,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 37.140 265.421 37.164 ; + RECT 163.162 238.356 163.234 238.380 ; END END w0_wd_in[160] PIN w0_wd_in[161] @@ -1460,7 +6068,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 38.292 265.421 38.316 ; + RECT 163.162 239.844 163.234 239.868 ; END END w0_wd_in[161] PIN w0_wd_in[162] @@ -1469,7 +6077,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 39.444 265.421 39.468 ; + RECT 163.162 241.332 163.234 241.356 ; END END w0_wd_in[162] PIN w0_wd_in[163] @@ -1478,7 +6086,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 40.596 265.421 40.620 ; + RECT 163.162 242.820 163.234 242.844 ; END END w0_wd_in[163] PIN w0_wd_in[164] @@ -1487,7 +6095,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 41.748 265.421 41.772 ; + RECT 163.162 244.308 163.234 244.332 ; END END w0_wd_in[164] PIN w0_wd_in[165] @@ -1496,7 +6104,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 42.900 265.421 42.924 ; + RECT 163.162 245.796 163.234 245.820 ; END END w0_wd_in[165] PIN w0_wd_in[166] @@ -1505,7 +6113,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 44.052 265.421 44.076 ; + RECT 163.162 247.284 163.234 247.308 ; END END w0_wd_in[166] PIN w0_wd_in[167] @@ -1514,7 +6122,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 45.204 265.421 45.228 ; + RECT 163.162 248.772 163.234 248.796 ; END END w0_wd_in[167] PIN w0_wd_in[168] @@ -1523,7 +6131,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 46.356 265.421 46.380 ; + RECT 163.162 250.260 163.234 250.284 ; END END w0_wd_in[168] PIN w0_wd_in[169] @@ -1532,7 +6140,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 47.508 265.421 47.532 ; + RECT 163.162 251.748 163.234 251.772 ; END END w0_wd_in[169] PIN w0_wd_in[170] @@ -1541,7 +6149,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 48.660 265.421 48.684 ; + RECT 163.162 253.236 163.234 253.260 ; END END w0_wd_in[170] PIN w0_wd_in[171] @@ -1550,7 +6158,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 49.812 265.421 49.836 ; + RECT 163.162 254.724 163.234 254.748 ; END END w0_wd_in[171] PIN w0_wd_in[172] @@ -1559,7 +6167,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 50.964 265.421 50.988 ; + RECT 163.162 256.212 163.234 256.236 ; END END w0_wd_in[172] PIN w0_wd_in[173] @@ -1568,7 +6176,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 52.116 265.421 52.140 ; + RECT 163.162 257.700 163.234 257.724 ; END END w0_wd_in[173] PIN w0_wd_in[174] @@ -1577,7 +6185,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 53.268 265.421 53.292 ; + RECT 163.162 259.188 163.234 259.212 ; END END w0_wd_in[174] PIN w0_wd_in[175] @@ -1586,7 +6194,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 54.420 265.421 54.444 ; + RECT 163.162 260.676 163.234 260.700 ; END END w0_wd_in[175] PIN w0_wd_in[176] @@ -1595,7 +6203,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 55.572 265.421 55.596 ; + RECT 163.162 262.164 163.234 262.188 ; END END w0_wd_in[176] PIN w0_wd_in[177] @@ -1604,7 +6212,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 56.724 265.421 56.748 ; + RECT 163.162 263.652 163.234 263.676 ; END END w0_wd_in[177] PIN w0_wd_in[178] @@ -1613,7 +6221,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 57.876 265.421 57.900 ; + RECT 163.162 265.140 163.234 265.164 ; END END w0_wd_in[178] PIN w0_wd_in[179] @@ -1622,7 +6230,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 59.028 265.421 59.052 ; + RECT 163.162 266.628 163.234 266.652 ; END END w0_wd_in[179] PIN w0_wd_in[180] @@ -1631,7 +6239,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 60.180 265.421 60.204 ; + RECT 163.162 268.116 163.234 268.140 ; END END w0_wd_in[180] PIN w0_wd_in[181] @@ -1640,7 +6248,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 61.332 265.421 61.356 ; + RECT 163.162 269.604 163.234 269.628 ; END END w0_wd_in[181] PIN w0_wd_in[182] @@ -1649,7 +6257,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 62.484 265.421 62.508 ; + RECT 163.162 271.092 163.234 271.116 ; END END w0_wd_in[182] PIN w0_wd_in[183] @@ -1658,7 +6266,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 63.636 265.421 63.660 ; + RECT 163.162 272.580 163.234 272.604 ; END END w0_wd_in[183] PIN w0_wd_in[184] @@ -1667,7 +6275,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 64.788 265.421 64.812 ; + RECT 163.162 274.068 163.234 274.092 ; END END w0_wd_in[184] PIN w0_wd_in[185] @@ -1676,7 +6284,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 65.940 265.421 65.964 ; + RECT 163.162 275.556 163.234 275.580 ; END END w0_wd_in[185] PIN w0_wd_in[186] @@ -1685,7 +6293,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 67.092 265.421 67.116 ; + RECT 163.162 277.044 163.234 277.068 ; END END w0_wd_in[186] PIN w0_wd_in[187] @@ -1694,7 +6302,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 68.244 265.421 68.268 ; + RECT 163.162 278.532 163.234 278.556 ; END END w0_wd_in[187] PIN w0_wd_in[188] @@ -1703,7 +6311,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 69.396 265.421 69.420 ; + RECT 163.162 280.020 163.234 280.044 ; END END w0_wd_in[188] PIN w0_wd_in[189] @@ -1712,7 +6320,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 70.548 265.421 70.572 ; + RECT 163.162 281.508 163.234 281.532 ; END END w0_wd_in[189] PIN w0_wd_in[190] @@ -1721,7 +6329,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 71.700 265.421 71.724 ; + RECT 163.162 282.996 163.234 283.020 ; END END w0_wd_in[190] PIN w0_wd_in[191] @@ -1730,7 +6338,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 72.852 265.421 72.876 ; + RECT 163.162 284.484 163.234 284.508 ; END END w0_wd_in[191] PIN w0_wd_in[192] @@ -1739,7 +6347,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 74.004 265.421 74.028 ; + RECT 163.162 285.972 163.234 285.996 ; END END w0_wd_in[192] PIN w0_wd_in[193] @@ -1748,7 +6356,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 75.156 265.421 75.180 ; + RECT 163.162 287.460 163.234 287.484 ; END END w0_wd_in[193] PIN w0_wd_in[194] @@ -1757,7 +6365,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 76.308 265.421 76.332 ; + RECT 163.162 288.948 163.234 288.972 ; END END w0_wd_in[194] PIN w0_wd_in[195] @@ -1766,7 +6374,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 77.460 265.421 77.484 ; + RECT 163.162 290.436 163.234 290.460 ; END END w0_wd_in[195] PIN w0_wd_in[196] @@ -1775,7 +6383,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 78.612 265.421 78.636 ; + RECT 163.162 291.924 163.234 291.948 ; END END w0_wd_in[196] PIN w0_wd_in[197] @@ -1784,7 +6392,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 79.764 265.421 79.788 ; + RECT 163.162 293.412 163.234 293.436 ; END END w0_wd_in[197] PIN w0_wd_in[198] @@ -1793,7 +6401,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 80.916 265.421 80.940 ; + RECT 163.162 294.900 163.234 294.924 ; END END w0_wd_in[198] PIN w0_wd_in[199] @@ -1802,7 +6410,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 82.068 265.421 82.092 ; + RECT 163.162 296.388 163.234 296.412 ; END END w0_wd_in[199] PIN w0_wd_in[200] @@ -1811,7 +6419,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 83.220 265.421 83.244 ; + RECT 163.162 297.876 163.234 297.900 ; END END w0_wd_in[200] PIN w0_wd_in[201] @@ -1820,7 +6428,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 84.372 265.421 84.396 ; + RECT 163.162 299.364 163.234 299.388 ; END END w0_wd_in[201] PIN w0_wd_in[202] @@ -1829,7 +6437,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 85.524 265.421 85.548 ; + RECT 163.162 300.852 163.234 300.876 ; END END w0_wd_in[202] PIN w0_wd_in[203] @@ -1838,7 +6446,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 86.676 265.421 86.700 ; + RECT 163.162 302.340 163.234 302.364 ; END END w0_wd_in[203] PIN w0_wd_in[204] @@ -1847,7 +6455,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 87.828 265.421 87.852 ; + RECT 163.162 303.828 163.234 303.852 ; END END w0_wd_in[204] PIN w0_wd_in[205] @@ -1856,7 +6464,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 88.980 265.421 89.004 ; + RECT 163.162 305.316 163.234 305.340 ; END END w0_wd_in[205] PIN w0_wd_in[206] @@ -1865,7 +6473,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 90.132 265.421 90.156 ; + RECT 163.162 306.804 163.234 306.828 ; END END w0_wd_in[206] PIN w0_wd_in[207] @@ -1874,7 +6482,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 91.284 265.421 91.308 ; + RECT 163.162 308.292 163.234 308.316 ; END END w0_wd_in[207] PIN w0_wd_in[208] @@ -1883,7 +6491,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 92.436 265.421 92.460 ; + RECT 163.162 309.780 163.234 309.804 ; END END w0_wd_in[208] PIN w0_wd_in[209] @@ -1892,7 +6500,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 93.588 265.421 93.612 ; + RECT 163.162 311.268 163.234 311.292 ; END END w0_wd_in[209] PIN w0_wd_in[210] @@ -1901,7 +6509,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 94.740 265.421 94.764 ; + RECT 163.162 312.756 163.234 312.780 ; END END w0_wd_in[210] PIN w0_wd_in[211] @@ -1910,7 +6518,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 95.892 265.421 95.916 ; + RECT 163.162 314.244 163.234 314.268 ; END END w0_wd_in[211] PIN w0_wd_in[212] @@ -1919,7 +6527,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 97.044 265.421 97.068 ; + RECT 163.162 315.732 163.234 315.756 ; END END w0_wd_in[212] PIN w0_wd_in[213] @@ -1928,7 +6536,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 98.196 265.421 98.220 ; + RECT 163.162 317.220 163.234 317.244 ; END END w0_wd_in[213] PIN w0_wd_in[214] @@ -1937,7 +6545,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 99.348 265.421 99.372 ; + RECT 163.162 318.708 163.234 318.732 ; END END w0_wd_in[214] PIN w0_wd_in[215] @@ -1946,7 +6554,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 100.500 265.421 100.524 ; + RECT 163.162 320.196 163.234 320.220 ; END END w0_wd_in[215] PIN w0_wd_in[216] @@ -1955,7 +6563,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 101.652 265.421 101.676 ; + RECT 163.162 321.684 163.234 321.708 ; END END w0_wd_in[216] PIN w0_wd_in[217] @@ -1964,7 +6572,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 102.804 265.421 102.828 ; + RECT 163.162 323.172 163.234 323.196 ; END END w0_wd_in[217] PIN w0_wd_in[218] @@ -1973,7 +6581,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 103.956 265.421 103.980 ; + RECT 163.162 324.660 163.234 324.684 ; END END w0_wd_in[218] PIN w0_wd_in[219] @@ -1982,7 +6590,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 105.108 265.421 105.132 ; + RECT 163.162 326.148 163.234 326.172 ; END END w0_wd_in[219] PIN w0_wd_in[220] @@ -1991,7 +6599,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 106.260 265.421 106.284 ; + RECT 163.162 327.636 163.234 327.660 ; END END w0_wd_in[220] PIN w0_wd_in[221] @@ -2000,7 +6608,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 107.412 265.421 107.436 ; + RECT 163.162 329.124 163.234 329.148 ; END END w0_wd_in[221] PIN w0_wd_in[222] @@ -2009,7 +6617,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 108.564 265.421 108.588 ; + RECT 163.162 330.612 163.234 330.636 ; END END w0_wd_in[222] PIN w0_wd_in[223] @@ -2018,7 +6626,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 109.716 265.421 109.740 ; + RECT 163.162 332.100 163.234 332.124 ; END END w0_wd_in[223] PIN w0_wd_in[224] @@ -2027,7 +6635,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 110.868 265.421 110.892 ; + RECT 163.162 333.588 163.234 333.612 ; END END w0_wd_in[224] PIN w0_wd_in[225] @@ -2036,7 +6644,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 112.020 265.421 112.044 ; + RECT 163.162 335.076 163.234 335.100 ; END END w0_wd_in[225] PIN w0_wd_in[226] @@ -2045,7 +6653,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 113.172 265.421 113.196 ; + RECT 163.162 336.564 163.234 336.588 ; END END w0_wd_in[226] PIN w0_wd_in[227] @@ -2054,7 +6662,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 114.324 265.421 114.348 ; + RECT 163.162 338.052 163.234 338.076 ; END END w0_wd_in[227] PIN w0_wd_in[228] @@ -2063,7 +6671,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 115.476 265.421 115.500 ; + RECT 163.162 339.540 163.234 339.564 ; END END w0_wd_in[228] PIN w0_wd_in[229] @@ -2072,7 +6680,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 116.628 265.421 116.652 ; + RECT 163.162 341.028 163.234 341.052 ; END END w0_wd_in[229] PIN w0_wd_in[230] @@ -2081,7 +6689,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 117.780 265.421 117.804 ; + RECT 163.162 342.516 163.234 342.540 ; END END w0_wd_in[230] PIN w0_wd_in[231] @@ -2090,7 +6698,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 118.932 265.421 118.956 ; + RECT 163.162 344.004 163.234 344.028 ; END END w0_wd_in[231] PIN w0_wd_in[232] @@ -2099,7 +6707,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 120.084 265.421 120.108 ; + RECT 163.162 345.492 163.234 345.516 ; END END w0_wd_in[232] PIN w0_wd_in[233] @@ -2108,7 +6716,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 121.236 265.421 121.260 ; + RECT 163.162 346.980 163.234 347.004 ; END END w0_wd_in[233] PIN w0_wd_in[234] @@ -2117,7 +6725,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 122.388 265.421 122.412 ; + RECT 163.162 348.468 163.234 348.492 ; END END w0_wd_in[234] PIN w0_wd_in[235] @@ -2126,7 +6734,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 123.540 265.421 123.564 ; + RECT 163.162 349.956 163.234 349.980 ; END END w0_wd_in[235] PIN w0_wd_in[236] @@ -2135,7 +6743,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 124.692 265.421 124.716 ; + RECT 163.162 351.444 163.234 351.468 ; END END w0_wd_in[236] PIN w0_wd_in[237] @@ -2144,7 +6752,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 125.844 265.421 125.868 ; + RECT 163.162 352.932 163.234 352.956 ; END END w0_wd_in[237] PIN w0_wd_in[238] @@ -2153,7 +6761,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 126.996 265.421 127.020 ; + RECT 163.162 354.420 163.234 354.444 ; END END w0_wd_in[238] PIN w0_wd_in[239] @@ -2162,7 +6770,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 128.148 265.421 128.172 ; + RECT 163.162 355.908 163.234 355.932 ; END END w0_wd_in[239] PIN w0_wd_in[240] @@ -2171,7 +6779,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 129.300 265.421 129.324 ; + RECT 163.162 357.396 163.234 357.420 ; END END w0_wd_in[240] PIN w0_wd_in[241] @@ -2180,7 +6788,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 130.452 265.421 130.476 ; + RECT 163.162 358.884 163.234 358.908 ; END END w0_wd_in[241] PIN w0_wd_in[242] @@ -2189,7 +6797,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 131.604 265.421 131.628 ; + RECT 163.162 360.372 163.234 360.396 ; END END w0_wd_in[242] PIN w0_wd_in[243] @@ -2198,7 +6806,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 132.756 265.421 132.780 ; + RECT 163.162 361.860 163.234 361.884 ; END END w0_wd_in[243] PIN w0_wd_in[244] @@ -2207,7 +6815,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 133.908 265.421 133.932 ; + RECT 163.162 363.348 163.234 363.372 ; END END w0_wd_in[244] PIN w0_wd_in[245] @@ -2216,7 +6824,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 135.060 265.421 135.084 ; + RECT 163.162 364.836 163.234 364.860 ; END END w0_wd_in[245] PIN w0_wd_in[246] @@ -2225,7 +6833,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 136.212 265.421 136.236 ; + RECT 163.162 366.324 163.234 366.348 ; END END w0_wd_in[246] PIN w0_wd_in[247] @@ -2234,7 +6842,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 137.364 265.421 137.388 ; + RECT 163.162 367.812 163.234 367.836 ; END END w0_wd_in[247] PIN w0_wd_in[248] @@ -2243,7 +6851,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 138.516 265.421 138.540 ; + RECT 163.162 369.300 163.234 369.324 ; END END w0_wd_in[248] PIN w0_wd_in[249] @@ -2252,7 +6860,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 139.668 265.421 139.692 ; + RECT 163.162 370.788 163.234 370.812 ; END END w0_wd_in[249] PIN w0_wd_in[250] @@ -2261,7 +6869,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 140.820 265.421 140.844 ; + RECT 163.162 372.276 163.234 372.300 ; END END w0_wd_in[250] PIN w0_wd_in[251] @@ -2270,7 +6878,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 141.972 265.421 141.996 ; + RECT 163.162 373.764 163.234 373.788 ; END END w0_wd_in[251] PIN w0_wd_in[252] @@ -2279,7 +6887,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 143.124 265.421 143.148 ; + RECT 163.162 375.252 163.234 375.276 ; END END w0_wd_in[252] PIN w0_wd_in[253] @@ -2288,7 +6896,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 144.276 265.421 144.300 ; + RECT 163.162 376.740 163.234 376.764 ; END END w0_wd_in[253] PIN w0_wd_in[254] @@ -2297,7 +6905,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 145.428 265.421 145.452 ; + RECT 163.162 378.228 163.234 378.252 ; END END w0_wd_in[254] PIN w0_wd_in[255] @@ -2306,7 +6914,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 146.580 265.421 146.604 ; + RECT 163.162 379.716 163.234 379.740 ; END END w0_wd_in[255] PIN w0_wd_in[256] @@ -2315,7 +6923,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; + RECT 0.207 0.000 0.225 0.054 ; END END w0_wd_in[256] PIN w0_wd_in[257] @@ -2324,7 +6932,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.711 0.000 0.729 0.018 ; + RECT 0.495 0.000 0.513 0.054 ; END END w0_wd_in[257] PIN w0_wd_in[258] @@ -2333,7 +6941,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.215 0.000 1.233 0.018 ; + RECT 0.783 0.000 0.801 0.054 ; END END w0_wd_in[258] PIN w0_wd_in[259] @@ -2342,7 +6950,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.719 0.000 1.737 0.018 ; + RECT 1.071 0.000 1.089 0.054 ; END END w0_wd_in[259] PIN w0_wd_in[260] @@ -2351,7 +6959,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.223 0.000 2.241 0.018 ; + RECT 1.359 0.000 1.377 0.054 ; END END w0_wd_in[260] PIN w0_wd_in[261] @@ -2360,7 +6968,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.727 0.000 2.745 0.018 ; + RECT 1.647 0.000 1.665 0.054 ; END END w0_wd_in[261] PIN w0_wd_in[262] @@ -2369,7 +6977,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.231 0.000 3.249 0.018 ; + RECT 1.935 0.000 1.953 0.054 ; END END w0_wd_in[262] PIN w0_wd_in[263] @@ -2378,7 +6986,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.735 0.000 3.753 0.018 ; + RECT 2.223 0.000 2.241 0.054 ; END END w0_wd_in[263] PIN w0_wd_in[264] @@ -2387,7 +6995,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.239 0.000 4.257 0.018 ; + RECT 2.511 0.000 2.529 0.054 ; END END w0_wd_in[264] PIN w0_wd_in[265] @@ -2396,7 +7004,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.743 0.000 4.761 0.018 ; + RECT 2.799 0.000 2.817 0.054 ; END END w0_wd_in[265] PIN w0_wd_in[266] @@ -2405,7 +7013,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.247 0.000 5.265 0.018 ; + RECT 3.087 0.000 3.105 0.054 ; END END w0_wd_in[266] PIN w0_wd_in[267] @@ -2414,7 +7022,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.751 0.000 5.769 0.018 ; + RECT 3.375 0.000 3.393 0.054 ; END END w0_wd_in[267] PIN w0_wd_in[268] @@ -2423,7 +7031,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.255 0.000 6.273 0.018 ; + RECT 3.663 0.000 3.681 0.054 ; END END w0_wd_in[268] PIN w0_wd_in[269] @@ -2432,7 +7040,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.759 0.000 6.777 0.018 ; + RECT 3.951 0.000 3.969 0.054 ; END END w0_wd_in[269] PIN w0_wd_in[270] @@ -2441,7 +7049,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.263 0.000 7.281 0.018 ; + RECT 4.239 0.000 4.257 0.054 ; END END w0_wd_in[270] PIN w0_wd_in[271] @@ -2450,7 +7058,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.767 0.000 7.785 0.018 ; + RECT 4.527 0.000 4.545 0.054 ; END END w0_wd_in[271] PIN w0_wd_in[272] @@ -2459,7 +7067,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.271 0.000 8.289 0.018 ; + RECT 4.815 0.000 4.833 0.054 ; END END w0_wd_in[272] PIN w0_wd_in[273] @@ -2468,7 +7076,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.775 0.000 8.793 0.018 ; + RECT 5.103 0.000 5.121 0.054 ; END END w0_wd_in[273] PIN w0_wd_in[274] @@ -2477,7 +7085,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.279 0.000 9.297 0.018 ; + RECT 5.391 0.000 5.409 0.054 ; END END w0_wd_in[274] PIN w0_wd_in[275] @@ -2486,7 +7094,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.783 0.000 9.801 0.018 ; + RECT 5.679 0.000 5.697 0.054 ; END END w0_wd_in[275] PIN w0_wd_in[276] @@ -2495,7 +7103,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.287 0.000 10.305 0.018 ; + RECT 5.967 0.000 5.985 0.054 ; END END w0_wd_in[276] PIN w0_wd_in[277] @@ -2504,7 +7112,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.791 0.000 10.809 0.018 ; + RECT 6.255 0.000 6.273 0.054 ; END END w0_wd_in[277] PIN w0_wd_in[278] @@ -2513,7 +7121,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.295 0.000 11.313 0.018 ; + RECT 6.543 0.000 6.561 0.054 ; END END w0_wd_in[278] PIN w0_wd_in[279] @@ -2522,7 +7130,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.799 0.000 11.817 0.018 ; + RECT 6.831 0.000 6.849 0.054 ; END END w0_wd_in[279] PIN w0_wd_in[280] @@ -2531,7 +7139,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.303 0.000 12.321 0.018 ; + RECT 7.119 0.000 7.137 0.054 ; END END w0_wd_in[280] PIN w0_wd_in[281] @@ -2540,7 +7148,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.807 0.000 12.825 0.018 ; + RECT 7.407 0.000 7.425 0.054 ; END END w0_wd_in[281] PIN w0_wd_in[282] @@ -2549,7 +7157,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.311 0.000 13.329 0.018 ; + RECT 7.695 0.000 7.713 0.054 ; END END w0_wd_in[282] PIN w0_wd_in[283] @@ -2558,7 +7166,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.815 0.000 13.833 0.018 ; + RECT 7.983 0.000 8.001 0.054 ; END END w0_wd_in[283] PIN w0_wd_in[284] @@ -2567,7 +7175,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.319 0.000 14.337 0.018 ; + RECT 8.271 0.000 8.289 0.054 ; END END w0_wd_in[284] PIN w0_wd_in[285] @@ -2576,7 +7184,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.823 0.000 14.841 0.018 ; + RECT 8.559 0.000 8.577 0.054 ; END END w0_wd_in[285] PIN w0_wd_in[286] @@ -2585,7 +7193,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 15.327 0.000 15.345 0.018 ; + RECT 8.847 0.000 8.865 0.054 ; END END w0_wd_in[286] PIN w0_wd_in[287] @@ -2594,7 +7202,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 15.831 0.000 15.849 0.018 ; + RECT 9.135 0.000 9.153 0.054 ; END END w0_wd_in[287] PIN w0_wd_in[288] @@ -2603,7 +7211,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 16.335 0.000 16.353 0.018 ; + RECT 9.423 0.000 9.441 0.054 ; END END w0_wd_in[288] PIN w0_wd_in[289] @@ -2612,7 +7220,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 16.839 0.000 16.857 0.018 ; + RECT 9.711 0.000 9.729 0.054 ; END END w0_wd_in[289] PIN w0_wd_in[290] @@ -2621,7 +7229,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 17.343 0.000 17.361 0.018 ; + RECT 9.999 0.000 10.017 0.054 ; END END w0_wd_in[290] PIN w0_wd_in[291] @@ -2630,7 +7238,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 17.847 0.000 17.865 0.018 ; + RECT 10.287 0.000 10.305 0.054 ; END END w0_wd_in[291] PIN w0_wd_in[292] @@ -2639,7 +7247,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 18.351 0.000 18.369 0.018 ; + RECT 10.575 0.000 10.593 0.054 ; END END w0_wd_in[292] PIN w0_wd_in[293] @@ -2648,7 +7256,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 18.855 0.000 18.873 0.018 ; + RECT 10.863 0.000 10.881 0.054 ; END END w0_wd_in[293] PIN w0_wd_in[294] @@ -2657,7 +7265,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 19.359 0.000 19.377 0.018 ; + RECT 11.151 0.000 11.169 0.054 ; END END w0_wd_in[294] PIN w0_wd_in[295] @@ -2666,7 +7274,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 19.863 0.000 19.881 0.018 ; + RECT 11.439 0.000 11.457 0.054 ; END END w0_wd_in[295] PIN w0_wd_in[296] @@ -2675,7 +7283,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 20.367 0.000 20.385 0.018 ; + RECT 11.727 0.000 11.745 0.054 ; END END w0_wd_in[296] PIN w0_wd_in[297] @@ -2684,7 +7292,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 20.871 0.000 20.889 0.018 ; + RECT 12.015 0.000 12.033 0.054 ; END END w0_wd_in[297] PIN w0_wd_in[298] @@ -2693,7 +7301,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 21.375 0.000 21.393 0.018 ; + RECT 12.303 0.000 12.321 0.054 ; END END w0_wd_in[298] PIN w0_wd_in[299] @@ -2702,7 +7310,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 21.879 0.000 21.897 0.018 ; + RECT 12.591 0.000 12.609 0.054 ; END END w0_wd_in[299] PIN w0_wd_in[300] @@ -2711,7 +7319,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 22.383 0.000 22.401 0.018 ; + RECT 12.879 0.000 12.897 0.054 ; END END w0_wd_in[300] PIN w0_wd_in[301] @@ -2720,7 +7328,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 22.887 0.000 22.905 0.018 ; + RECT 13.167 0.000 13.185 0.054 ; END END w0_wd_in[301] PIN w0_wd_in[302] @@ -2729,7 +7337,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 23.391 0.000 23.409 0.018 ; + RECT 13.455 0.000 13.473 0.054 ; END END w0_wd_in[302] PIN w0_wd_in[303] @@ -2738,7 +7346,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 23.895 0.000 23.913 0.018 ; + RECT 13.743 0.000 13.761 0.054 ; END END w0_wd_in[303] PIN w0_wd_in[304] @@ -2747,7 +7355,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 24.399 0.000 24.417 0.018 ; + RECT 14.031 0.000 14.049 0.054 ; END END w0_wd_in[304] PIN w0_wd_in[305] @@ -2756,7 +7364,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 24.903 0.000 24.921 0.018 ; + RECT 14.319 0.000 14.337 0.054 ; END END w0_wd_in[305] PIN w0_wd_in[306] @@ -2765,7 +7373,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 25.407 0.000 25.425 0.018 ; + RECT 14.607 0.000 14.625 0.054 ; END END w0_wd_in[306] PIN w0_wd_in[307] @@ -2774,7 +7382,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 25.911 0.000 25.929 0.018 ; + RECT 14.895 0.000 14.913 0.054 ; END END w0_wd_in[307] PIN w0_wd_in[308] @@ -2783,7 +7391,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 26.415 0.000 26.433 0.018 ; + RECT 15.183 0.000 15.201 0.054 ; END END w0_wd_in[308] PIN w0_wd_in[309] @@ -2792,7 +7400,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 26.919 0.000 26.937 0.018 ; + RECT 15.471 0.000 15.489 0.054 ; END END w0_wd_in[309] PIN w0_wd_in[310] @@ -2801,7 +7409,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 27.423 0.000 27.441 0.018 ; + RECT 15.759 0.000 15.777 0.054 ; END END w0_wd_in[310] PIN w0_wd_in[311] @@ -2810,7 +7418,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 27.927 0.000 27.945 0.018 ; + RECT 16.047 0.000 16.065 0.054 ; END END w0_wd_in[311] PIN w0_wd_in[312] @@ -2819,7 +7427,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 28.431 0.000 28.449 0.018 ; + RECT 16.335 0.000 16.353 0.054 ; END END w0_wd_in[312] PIN w0_wd_in[313] @@ -2828,7 +7436,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 28.935 0.000 28.953 0.018 ; + RECT 16.623 0.000 16.641 0.054 ; END END w0_wd_in[313] PIN w0_wd_in[314] @@ -2837,7 +7445,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 29.439 0.000 29.457 0.018 ; + RECT 16.911 0.000 16.929 0.054 ; END END w0_wd_in[314] PIN w0_wd_in[315] @@ -2846,7 +7454,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 29.943 0.000 29.961 0.018 ; + RECT 17.199 0.000 17.217 0.054 ; END END w0_wd_in[315] PIN w0_wd_in[316] @@ -2855,7 +7463,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 30.447 0.000 30.465 0.018 ; + RECT 17.487 0.000 17.505 0.054 ; END END w0_wd_in[316] PIN w0_wd_in[317] @@ -2864,7 +7472,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 30.951 0.000 30.969 0.018 ; + RECT 17.775 0.000 17.793 0.054 ; END END w0_wd_in[317] PIN w0_wd_in[318] @@ -2873,7 +7481,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 31.455 0.000 31.473 0.018 ; + RECT 18.063 0.000 18.081 0.054 ; END END w0_wd_in[318] PIN w0_wd_in[319] @@ -2882,7 +7490,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 31.959 0.000 31.977 0.018 ; + RECT 18.351 0.000 18.369 0.054 ; END END w0_wd_in[319] PIN w0_wd_in[320] @@ -2891,7 +7499,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 32.463 0.000 32.481 0.018 ; + RECT 18.639 0.000 18.657 0.054 ; END END w0_wd_in[320] PIN w0_wd_in[321] @@ -2900,7 +7508,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 32.967 0.000 32.985 0.018 ; + RECT 18.927 0.000 18.945 0.054 ; END END w0_wd_in[321] PIN w0_wd_in[322] @@ -2909,7 +7517,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 33.471 0.000 33.489 0.018 ; + RECT 19.215 0.000 19.233 0.054 ; END END w0_wd_in[322] PIN w0_wd_in[323] @@ -2918,7 +7526,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 33.975 0.000 33.993 0.018 ; + RECT 19.503 0.000 19.521 0.054 ; END END w0_wd_in[323] PIN w0_wd_in[324] @@ -2927,7 +7535,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 34.479 0.000 34.497 0.018 ; + RECT 19.791 0.000 19.809 0.054 ; END END w0_wd_in[324] PIN w0_wd_in[325] @@ -2936,7 +7544,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 34.983 0.000 35.001 0.018 ; + RECT 20.079 0.000 20.097 0.054 ; END END w0_wd_in[325] PIN w0_wd_in[326] @@ -2945,7 +7553,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 35.487 0.000 35.505 0.018 ; + RECT 20.367 0.000 20.385 0.054 ; END END w0_wd_in[326] PIN w0_wd_in[327] @@ -2954,7 +7562,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 35.991 0.000 36.009 0.018 ; + RECT 20.655 0.000 20.673 0.054 ; END END w0_wd_in[327] PIN w0_wd_in[328] @@ -2963,7 +7571,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 36.495 0.000 36.513 0.018 ; + RECT 20.943 0.000 20.961 0.054 ; END END w0_wd_in[328] PIN w0_wd_in[329] @@ -2972,7 +7580,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 36.999 0.000 37.017 0.018 ; + RECT 21.231 0.000 21.249 0.054 ; END END w0_wd_in[329] PIN w0_wd_in[330] @@ -2981,7 +7589,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 37.503 0.000 37.521 0.018 ; + RECT 21.519 0.000 21.537 0.054 ; END END w0_wd_in[330] PIN w0_wd_in[331] @@ -2990,7 +7598,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 38.007 0.000 38.025 0.018 ; + RECT 21.807 0.000 21.825 0.054 ; END END w0_wd_in[331] PIN w0_wd_in[332] @@ -2999,7 +7607,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 38.511 0.000 38.529 0.018 ; + RECT 22.095 0.000 22.113 0.054 ; END END w0_wd_in[332] PIN w0_wd_in[333] @@ -3008,7 +7616,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 39.015 0.000 39.033 0.018 ; + RECT 22.383 0.000 22.401 0.054 ; END END w0_wd_in[333] PIN w0_wd_in[334] @@ -3017,7 +7625,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 39.519 0.000 39.537 0.018 ; + RECT 22.671 0.000 22.689 0.054 ; END END w0_wd_in[334] PIN w0_wd_in[335] @@ -3026,7 +7634,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 40.023 0.000 40.041 0.018 ; + RECT 22.959 0.000 22.977 0.054 ; END END w0_wd_in[335] PIN w0_wd_in[336] @@ -3035,7 +7643,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 40.527 0.000 40.545 0.018 ; + RECT 23.247 0.000 23.265 0.054 ; END END w0_wd_in[336] PIN w0_wd_in[337] @@ -3044,7 +7652,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 41.031 0.000 41.049 0.018 ; + RECT 23.535 0.000 23.553 0.054 ; END END w0_wd_in[337] PIN w0_wd_in[338] @@ -3053,7 +7661,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 41.535 0.000 41.553 0.018 ; + RECT 23.823 0.000 23.841 0.054 ; END END w0_wd_in[338] PIN w0_wd_in[339] @@ -3062,7 +7670,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 42.039 0.000 42.057 0.018 ; + RECT 24.111 0.000 24.129 0.054 ; END END w0_wd_in[339] PIN w0_wd_in[340] @@ -3071,7 +7679,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 42.543 0.000 42.561 0.018 ; + RECT 24.399 0.000 24.417 0.054 ; END END w0_wd_in[340] PIN w0_wd_in[341] @@ -3080,7 +7688,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 43.047 0.000 43.065 0.018 ; + RECT 24.687 0.000 24.705 0.054 ; END END w0_wd_in[341] PIN w0_wd_in[342] @@ -3089,7 +7697,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 43.551 0.000 43.569 0.018 ; + RECT 24.975 0.000 24.993 0.054 ; END END w0_wd_in[342] PIN w0_wd_in[343] @@ -3098,7 +7706,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 44.055 0.000 44.073 0.018 ; + RECT 25.263 0.000 25.281 0.054 ; END END w0_wd_in[343] PIN w0_wd_in[344] @@ -3107,7 +7715,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 44.559 0.000 44.577 0.018 ; + RECT 25.551 0.000 25.569 0.054 ; END END w0_wd_in[344] PIN w0_wd_in[345] @@ -3116,7 +7724,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 45.063 0.000 45.081 0.018 ; + RECT 25.839 0.000 25.857 0.054 ; END END w0_wd_in[345] PIN w0_wd_in[346] @@ -3125,7 +7733,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 45.567 0.000 45.585 0.018 ; + RECT 26.127 0.000 26.145 0.054 ; END END w0_wd_in[346] PIN w0_wd_in[347] @@ -3134,7 +7742,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 46.071 0.000 46.089 0.018 ; + RECT 26.415 0.000 26.433 0.054 ; END END w0_wd_in[347] PIN w0_wd_in[348] @@ -3143,7 +7751,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 46.575 0.000 46.593 0.018 ; + RECT 26.703 0.000 26.721 0.054 ; END END w0_wd_in[348] PIN w0_wd_in[349] @@ -3152,7 +7760,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 47.079 0.000 47.097 0.018 ; + RECT 26.991 0.000 27.009 0.054 ; END END w0_wd_in[349] PIN w0_wd_in[350] @@ -3161,7 +7769,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 47.583 0.000 47.601 0.018 ; + RECT 27.279 0.000 27.297 0.054 ; END END w0_wd_in[350] PIN w0_wd_in[351] @@ -3170,7 +7778,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 48.087 0.000 48.105 0.018 ; + RECT 27.567 0.000 27.585 0.054 ; END END w0_wd_in[351] PIN w0_wd_in[352] @@ -3179,7 +7787,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 48.591 0.000 48.609 0.018 ; + RECT 27.855 0.000 27.873 0.054 ; END END w0_wd_in[352] PIN w0_wd_in[353] @@ -3188,7 +7796,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 49.095 0.000 49.113 0.018 ; + RECT 28.143 0.000 28.161 0.054 ; END END w0_wd_in[353] PIN w0_wd_in[354] @@ -3197,7 +7805,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 49.599 0.000 49.617 0.018 ; + RECT 28.431 0.000 28.449 0.054 ; END END w0_wd_in[354] PIN w0_wd_in[355] @@ -3206,7 +7814,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 50.103 0.000 50.121 0.018 ; + RECT 28.719 0.000 28.737 0.054 ; END END w0_wd_in[355] PIN w0_wd_in[356] @@ -3215,7 +7823,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 50.607 0.000 50.625 0.018 ; + RECT 29.007 0.000 29.025 0.054 ; END END w0_wd_in[356] PIN w0_wd_in[357] @@ -3224,7 +7832,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 51.111 0.000 51.129 0.018 ; + RECT 29.295 0.000 29.313 0.054 ; END END w0_wd_in[357] PIN w0_wd_in[358] @@ -3233,7 +7841,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 51.615 0.000 51.633 0.018 ; + RECT 29.583 0.000 29.601 0.054 ; END END w0_wd_in[358] PIN w0_wd_in[359] @@ -3242,7 +7850,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 52.119 0.000 52.137 0.018 ; + RECT 29.871 0.000 29.889 0.054 ; END END w0_wd_in[359] PIN w0_wd_in[360] @@ -3251,7 +7859,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 52.623 0.000 52.641 0.018 ; + RECT 30.159 0.000 30.177 0.054 ; END END w0_wd_in[360] PIN w0_wd_in[361] @@ -3260,7 +7868,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 53.127 0.000 53.145 0.018 ; + RECT 30.447 0.000 30.465 0.054 ; END END w0_wd_in[361] PIN w0_wd_in[362] @@ -3269,7 +7877,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 53.631 0.000 53.649 0.018 ; + RECT 30.735 0.000 30.753 0.054 ; END END w0_wd_in[362] PIN w0_wd_in[363] @@ -3278,7 +7886,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 54.135 0.000 54.153 0.018 ; + RECT 31.023 0.000 31.041 0.054 ; END END w0_wd_in[363] PIN w0_wd_in[364] @@ -3287,7 +7895,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 54.639 0.000 54.657 0.018 ; + RECT 31.311 0.000 31.329 0.054 ; END END w0_wd_in[364] PIN w0_wd_in[365] @@ -3296,7 +7904,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 55.143 0.000 55.161 0.018 ; + RECT 31.599 0.000 31.617 0.054 ; END END w0_wd_in[365] PIN w0_wd_in[366] @@ -3305,7 +7913,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 55.647 0.000 55.665 0.018 ; + RECT 31.887 0.000 31.905 0.054 ; END END w0_wd_in[366] PIN w0_wd_in[367] @@ -3314,7 +7922,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 56.151 0.000 56.169 0.018 ; + RECT 32.175 0.000 32.193 0.054 ; END END w0_wd_in[367] PIN w0_wd_in[368] @@ -3323,7 +7931,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 56.655 0.000 56.673 0.018 ; + RECT 32.463 0.000 32.481 0.054 ; END END w0_wd_in[368] PIN w0_wd_in[369] @@ -3332,7 +7940,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 57.159 0.000 57.177 0.018 ; + RECT 32.751 0.000 32.769 0.054 ; END END w0_wd_in[369] PIN w0_wd_in[370] @@ -3341,7 +7949,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 57.663 0.000 57.681 0.018 ; + RECT 33.039 0.000 33.057 0.054 ; END END w0_wd_in[370] PIN w0_wd_in[371] @@ -3350,7 +7958,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 58.167 0.000 58.185 0.018 ; + RECT 33.327 0.000 33.345 0.054 ; END END w0_wd_in[371] PIN w0_wd_in[372] @@ -3359,7 +7967,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 58.671 0.000 58.689 0.018 ; + RECT 33.615 0.000 33.633 0.054 ; END END w0_wd_in[372] PIN w0_wd_in[373] @@ -3368,7 +7976,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 59.175 0.000 59.193 0.018 ; + RECT 33.903 0.000 33.921 0.054 ; END END w0_wd_in[373] PIN w0_wd_in[374] @@ -3377,7 +7985,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 59.679 0.000 59.697 0.018 ; + RECT 34.191 0.000 34.209 0.054 ; END END w0_wd_in[374] PIN w0_wd_in[375] @@ -3386,7 +7994,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 60.183 0.000 60.201 0.018 ; + RECT 34.479 0.000 34.497 0.054 ; END END w0_wd_in[375] PIN w0_wd_in[376] @@ -3395,7 +8003,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 60.687 0.000 60.705 0.018 ; + RECT 34.767 0.000 34.785 0.054 ; END END w0_wd_in[376] PIN w0_wd_in[377] @@ -3404,7 +8012,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 61.191 0.000 61.209 0.018 ; + RECT 35.055 0.000 35.073 0.054 ; END END w0_wd_in[377] PIN w0_wd_in[378] @@ -3413,7 +8021,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 61.695 0.000 61.713 0.018 ; + RECT 35.343 0.000 35.361 0.054 ; END END w0_wd_in[378] PIN w0_wd_in[379] @@ -3422,7 +8030,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 62.199 0.000 62.217 0.018 ; + RECT 35.631 0.000 35.649 0.054 ; END END w0_wd_in[379] PIN w0_wd_in[380] @@ -3431,7 +8039,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 62.703 0.000 62.721 0.018 ; + RECT 35.919 0.000 35.937 0.054 ; END END w0_wd_in[380] PIN w0_wd_in[381] @@ -3440,7 +8048,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 63.207 0.000 63.225 0.018 ; + RECT 36.207 0.000 36.225 0.054 ; END END w0_wd_in[381] PIN w0_wd_in[382] @@ -3449,7 +8057,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 63.711 0.000 63.729 0.018 ; + RECT 36.495 0.000 36.513 0.054 ; END END w0_wd_in[382] PIN w0_wd_in[383] @@ -3458,7 +8066,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 64.215 0.000 64.233 0.018 ; + RECT 36.783 0.000 36.801 0.054 ; END END w0_wd_in[383] PIN w0_wd_in[384] @@ -3467,7 +8075,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 64.719 0.000 64.737 0.018 ; + RECT 37.071 0.000 37.089 0.054 ; END END w0_wd_in[384] PIN w0_wd_in[385] @@ -3476,7 +8084,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 65.223 0.000 65.241 0.018 ; + RECT 37.359 0.000 37.377 0.054 ; END END w0_wd_in[385] PIN w0_wd_in[386] @@ -3485,7 +8093,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 65.727 0.000 65.745 0.018 ; + RECT 37.647 0.000 37.665 0.054 ; END END w0_wd_in[386] PIN w0_wd_in[387] @@ -3494,7 +8102,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 66.231 0.000 66.249 0.018 ; + RECT 37.935 0.000 37.953 0.054 ; END END w0_wd_in[387] PIN w0_wd_in[388] @@ -3503,7 +8111,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 66.735 0.000 66.753 0.018 ; + RECT 38.223 0.000 38.241 0.054 ; END END w0_wd_in[388] PIN w0_wd_in[389] @@ -3512,7 +8120,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 67.239 0.000 67.257 0.018 ; + RECT 38.511 0.000 38.529 0.054 ; END END w0_wd_in[389] PIN w0_wd_in[390] @@ -3521,7 +8129,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 67.743 0.000 67.761 0.018 ; + RECT 38.799 0.000 38.817 0.054 ; END END w0_wd_in[390] PIN w0_wd_in[391] @@ -3530,7 +8138,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 68.247 0.000 68.265 0.018 ; + RECT 39.087 0.000 39.105 0.054 ; END END w0_wd_in[391] PIN w0_wd_in[392] @@ -3539,7 +8147,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 68.751 0.000 68.769 0.018 ; + RECT 39.375 0.000 39.393 0.054 ; END END w0_wd_in[392] PIN w0_wd_in[393] @@ -3548,7 +8156,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 69.255 0.000 69.273 0.018 ; + RECT 39.663 0.000 39.681 0.054 ; END END w0_wd_in[393] PIN w0_wd_in[394] @@ -3557,7 +8165,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 69.759 0.000 69.777 0.018 ; + RECT 39.951 0.000 39.969 0.054 ; END END w0_wd_in[394] PIN w0_wd_in[395] @@ -3566,7 +8174,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 70.263 0.000 70.281 0.018 ; + RECT 40.239 0.000 40.257 0.054 ; END END w0_wd_in[395] PIN w0_wd_in[396] @@ -3575,7 +8183,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 70.767 0.000 70.785 0.018 ; + RECT 40.527 0.000 40.545 0.054 ; END END w0_wd_in[396] PIN w0_wd_in[397] @@ -3584,7 +8192,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 71.271 0.000 71.289 0.018 ; + RECT 40.815 0.000 40.833 0.054 ; END END w0_wd_in[397] PIN w0_wd_in[398] @@ -3593,7 +8201,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 71.775 0.000 71.793 0.018 ; + RECT 41.103 0.000 41.121 0.054 ; END END w0_wd_in[398] PIN w0_wd_in[399] @@ -3602,7 +8210,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 72.279 0.000 72.297 0.018 ; + RECT 41.391 0.000 41.409 0.054 ; END END w0_wd_in[399] PIN w0_wd_in[400] @@ -3611,7 +8219,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 72.783 0.000 72.801 0.018 ; + RECT 41.679 0.000 41.697 0.054 ; END END w0_wd_in[400] PIN w0_wd_in[401] @@ -3620,7 +8228,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 73.287 0.000 73.305 0.018 ; + RECT 41.967 0.000 41.985 0.054 ; END END w0_wd_in[401] PIN w0_wd_in[402] @@ -3629,7 +8237,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 73.791 0.000 73.809 0.018 ; + RECT 42.255 0.000 42.273 0.054 ; END END w0_wd_in[402] PIN w0_wd_in[403] @@ -3638,7 +8246,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 74.295 0.000 74.313 0.018 ; + RECT 42.543 0.000 42.561 0.054 ; END END w0_wd_in[403] PIN w0_wd_in[404] @@ -3647,7 +8255,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 74.799 0.000 74.817 0.018 ; + RECT 42.831 0.000 42.849 0.054 ; END END w0_wd_in[404] PIN w0_wd_in[405] @@ -3656,7 +8264,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 75.303 0.000 75.321 0.018 ; + RECT 43.119 0.000 43.137 0.054 ; END END w0_wd_in[405] PIN w0_wd_in[406] @@ -3665,7 +8273,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 75.807 0.000 75.825 0.018 ; + RECT 43.407 0.000 43.425 0.054 ; END END w0_wd_in[406] PIN w0_wd_in[407] @@ -3674,7 +8282,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 76.311 0.000 76.329 0.018 ; + RECT 43.695 0.000 43.713 0.054 ; END END w0_wd_in[407] PIN w0_wd_in[408] @@ -3683,7 +8291,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 76.815 0.000 76.833 0.018 ; + RECT 43.983 0.000 44.001 0.054 ; END END w0_wd_in[408] PIN w0_wd_in[409] @@ -3692,7 +8300,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 77.319 0.000 77.337 0.018 ; + RECT 44.271 0.000 44.289 0.054 ; END END w0_wd_in[409] PIN w0_wd_in[410] @@ -3701,7 +8309,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 77.823 0.000 77.841 0.018 ; + RECT 44.559 0.000 44.577 0.054 ; END END w0_wd_in[410] PIN w0_wd_in[411] @@ -3710,7 +8318,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 78.327 0.000 78.345 0.018 ; + RECT 44.847 0.000 44.865 0.054 ; END END w0_wd_in[411] PIN w0_wd_in[412] @@ -3719,7 +8327,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 78.831 0.000 78.849 0.018 ; + RECT 45.135 0.000 45.153 0.054 ; END END w0_wd_in[412] PIN w0_wd_in[413] @@ -3728,7 +8336,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 79.335 0.000 79.353 0.018 ; + RECT 45.423 0.000 45.441 0.054 ; END END w0_wd_in[413] PIN w0_wd_in[414] @@ -3737,7 +8345,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 79.839 0.000 79.857 0.018 ; + RECT 45.711 0.000 45.729 0.054 ; END END w0_wd_in[414] PIN w0_wd_in[415] @@ -3746,7 +8354,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 80.343 0.000 80.361 0.018 ; + RECT 45.999 0.000 46.017 0.054 ; END END w0_wd_in[415] PIN w0_wd_in[416] @@ -3755,7 +8363,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 80.847 0.000 80.865 0.018 ; + RECT 46.287 0.000 46.305 0.054 ; END END w0_wd_in[416] PIN w0_wd_in[417] @@ -3764,7 +8372,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 81.351 0.000 81.369 0.018 ; + RECT 46.575 0.000 46.593 0.054 ; END END w0_wd_in[417] PIN w0_wd_in[418] @@ -3773,7 +8381,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 81.855 0.000 81.873 0.018 ; + RECT 46.863 0.000 46.881 0.054 ; END END w0_wd_in[418] PIN w0_wd_in[419] @@ -3782,7 +8390,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 82.359 0.000 82.377 0.018 ; + RECT 47.151 0.000 47.169 0.054 ; END END w0_wd_in[419] PIN w0_wd_in[420] @@ -3791,7 +8399,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 82.863 0.000 82.881 0.018 ; + RECT 47.439 0.000 47.457 0.054 ; END END w0_wd_in[420] PIN w0_wd_in[421] @@ -3800,7 +8408,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 83.367 0.000 83.385 0.018 ; + RECT 47.727 0.000 47.745 0.054 ; END END w0_wd_in[421] PIN w0_wd_in[422] @@ -3809,7 +8417,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 83.871 0.000 83.889 0.018 ; + RECT 48.015 0.000 48.033 0.054 ; END END w0_wd_in[422] PIN w0_wd_in[423] @@ -3818,7 +8426,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 84.375 0.000 84.393 0.018 ; + RECT 48.303 0.000 48.321 0.054 ; END END w0_wd_in[423] PIN w0_wd_in[424] @@ -3827,7 +8435,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 84.879 0.000 84.897 0.018 ; + RECT 48.591 0.000 48.609 0.054 ; END END w0_wd_in[424] PIN w0_wd_in[425] @@ -3836,7 +8444,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 85.383 0.000 85.401 0.018 ; + RECT 48.879 0.000 48.897 0.054 ; END END w0_wd_in[425] PIN w0_wd_in[426] @@ -3845,7 +8453,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 85.887 0.000 85.905 0.018 ; + RECT 49.167 0.000 49.185 0.054 ; END END w0_wd_in[426] PIN w0_wd_in[427] @@ -3854,7 +8462,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 86.391 0.000 86.409 0.018 ; + RECT 49.455 0.000 49.473 0.054 ; END END w0_wd_in[427] PIN w0_wd_in[428] @@ -3863,7 +8471,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 86.895 0.000 86.913 0.018 ; + RECT 49.743 0.000 49.761 0.054 ; END END w0_wd_in[428] PIN w0_wd_in[429] @@ -3872,7 +8480,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 87.399 0.000 87.417 0.018 ; + RECT 50.031 0.000 50.049 0.054 ; END END w0_wd_in[429] PIN w0_wd_in[430] @@ -3881,7 +8489,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 87.903 0.000 87.921 0.018 ; + RECT 50.319 0.000 50.337 0.054 ; END END w0_wd_in[430] PIN w0_wd_in[431] @@ -3890,7 +8498,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 88.407 0.000 88.425 0.018 ; + RECT 50.607 0.000 50.625 0.054 ; END END w0_wd_in[431] PIN w0_wd_in[432] @@ -3899,7 +8507,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 88.911 0.000 88.929 0.018 ; + RECT 50.895 0.000 50.913 0.054 ; END END w0_wd_in[432] PIN w0_wd_in[433] @@ -3908,7 +8516,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 89.415 0.000 89.433 0.018 ; + RECT 51.183 0.000 51.201 0.054 ; END END w0_wd_in[433] PIN w0_wd_in[434] @@ -3917,7 +8525,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 89.919 0.000 89.937 0.018 ; + RECT 51.471 0.000 51.489 0.054 ; END END w0_wd_in[434] PIN w0_wd_in[435] @@ -3926,7 +8534,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 90.423 0.000 90.441 0.018 ; + RECT 51.759 0.000 51.777 0.054 ; END END w0_wd_in[435] PIN w0_wd_in[436] @@ -3935,7 +8543,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 90.927 0.000 90.945 0.018 ; + RECT 52.047 0.000 52.065 0.054 ; END END w0_wd_in[436] PIN w0_wd_in[437] @@ -3944,7 +8552,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 91.431 0.000 91.449 0.018 ; + RECT 52.335 0.000 52.353 0.054 ; END END w0_wd_in[437] PIN w0_wd_in[438] @@ -3953,7 +8561,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 91.935 0.000 91.953 0.018 ; + RECT 52.623 0.000 52.641 0.054 ; END END w0_wd_in[438] PIN w0_wd_in[439] @@ -3962,7 +8570,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 92.439 0.000 92.457 0.018 ; + RECT 52.911 0.000 52.929 0.054 ; END END w0_wd_in[439] PIN w0_wd_in[440] @@ -3971,7 +8579,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 92.943 0.000 92.961 0.018 ; + RECT 53.199 0.000 53.217 0.054 ; END END w0_wd_in[440] PIN w0_wd_in[441] @@ -3980,7 +8588,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 93.447 0.000 93.465 0.018 ; + RECT 53.487 0.000 53.505 0.054 ; END END w0_wd_in[441] PIN w0_wd_in[442] @@ -3989,7 +8597,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 93.951 0.000 93.969 0.018 ; + RECT 53.775 0.000 53.793 0.054 ; END END w0_wd_in[442] PIN w0_wd_in[443] @@ -3998,7 +8606,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 94.455 0.000 94.473 0.018 ; + RECT 54.063 0.000 54.081 0.054 ; END END w0_wd_in[443] PIN w0_wd_in[444] @@ -4007,7 +8615,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 94.959 0.000 94.977 0.018 ; + RECT 54.351 0.000 54.369 0.054 ; END END w0_wd_in[444] PIN w0_wd_in[445] @@ -4016,7 +8624,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 95.463 0.000 95.481 0.018 ; + RECT 54.639 0.000 54.657 0.054 ; END END w0_wd_in[445] PIN w0_wd_in[446] @@ -4025,7 +8633,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 95.967 0.000 95.985 0.018 ; + RECT 54.927 0.000 54.945 0.054 ; END END w0_wd_in[446] PIN w0_wd_in[447] @@ -4034,7 +8642,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 96.471 0.000 96.489 0.018 ; + RECT 55.215 0.000 55.233 0.054 ; END END w0_wd_in[447] PIN w0_wd_in[448] @@ -4043,7 +8651,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 96.975 0.000 96.993 0.018 ; + RECT 55.503 0.000 55.521 0.054 ; END END w0_wd_in[448] PIN w0_wd_in[449] @@ -4052,7 +8660,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 97.479 0.000 97.497 0.018 ; + RECT 55.791 0.000 55.809 0.054 ; END END w0_wd_in[449] PIN w0_wd_in[450] @@ -4061,7 +8669,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 97.983 0.000 98.001 0.018 ; + RECT 56.079 0.000 56.097 0.054 ; END END w0_wd_in[450] PIN w0_wd_in[451] @@ -4070,7 +8678,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 98.487 0.000 98.505 0.018 ; + RECT 56.367 0.000 56.385 0.054 ; END END w0_wd_in[451] PIN w0_wd_in[452] @@ -4079,7 +8687,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 98.991 0.000 99.009 0.018 ; + RECT 56.655 0.000 56.673 0.054 ; END END w0_wd_in[452] PIN w0_wd_in[453] @@ -4088,7 +8696,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 99.495 0.000 99.513 0.018 ; + RECT 56.943 0.000 56.961 0.054 ; END END w0_wd_in[453] PIN w0_wd_in[454] @@ -4097,7 +8705,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 99.999 0.000 100.017 0.018 ; + RECT 57.231 0.000 57.249 0.054 ; END END w0_wd_in[454] PIN w0_wd_in[455] @@ -4106,7 +8714,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 100.503 0.000 100.521 0.018 ; + RECT 57.519 0.000 57.537 0.054 ; END END w0_wd_in[455] PIN w0_wd_in[456] @@ -4115,7 +8723,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 101.007 0.000 101.025 0.018 ; + RECT 57.807 0.000 57.825 0.054 ; END END w0_wd_in[456] PIN w0_wd_in[457] @@ -4124,7 +8732,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 101.511 0.000 101.529 0.018 ; + RECT 58.095 0.000 58.113 0.054 ; END END w0_wd_in[457] PIN w0_wd_in[458] @@ -4133,7 +8741,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 102.015 0.000 102.033 0.018 ; + RECT 58.383 0.000 58.401 0.054 ; END END w0_wd_in[458] PIN w0_wd_in[459] @@ -4142,7 +8750,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 102.519 0.000 102.537 0.018 ; + RECT 58.671 0.000 58.689 0.054 ; END END w0_wd_in[459] PIN w0_wd_in[460] @@ -4151,7 +8759,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 103.023 0.000 103.041 0.018 ; + RECT 58.959 0.000 58.977 0.054 ; END END w0_wd_in[460] PIN w0_wd_in[461] @@ -4160,7 +8768,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 103.527 0.000 103.545 0.018 ; + RECT 59.247 0.000 59.265 0.054 ; END END w0_wd_in[461] PIN w0_wd_in[462] @@ -4169,7 +8777,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 104.031 0.000 104.049 0.018 ; + RECT 59.535 0.000 59.553 0.054 ; END END w0_wd_in[462] PIN w0_wd_in[463] @@ -4178,7 +8786,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 104.535 0.000 104.553 0.018 ; + RECT 59.823 0.000 59.841 0.054 ; END END w0_wd_in[463] PIN w0_wd_in[464] @@ -4187,7 +8795,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 105.039 0.000 105.057 0.018 ; + RECT 60.111 0.000 60.129 0.054 ; END END w0_wd_in[464] PIN w0_wd_in[465] @@ -4196,7 +8804,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 105.543 0.000 105.561 0.018 ; + RECT 60.399 0.000 60.417 0.054 ; END END w0_wd_in[465] PIN w0_wd_in[466] @@ -4205,7 +8813,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 106.047 0.000 106.065 0.018 ; + RECT 60.687 0.000 60.705 0.054 ; END END w0_wd_in[466] PIN w0_wd_in[467] @@ -4214,7 +8822,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 106.551 0.000 106.569 0.018 ; + RECT 60.975 0.000 60.993 0.054 ; END END w0_wd_in[467] PIN w0_wd_in[468] @@ -4223,7 +8831,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 107.055 0.000 107.073 0.018 ; + RECT 61.263 0.000 61.281 0.054 ; END END w0_wd_in[468] PIN w0_wd_in[469] @@ -4232,7 +8840,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 107.559 0.000 107.577 0.018 ; + RECT 61.551 0.000 61.569 0.054 ; END END w0_wd_in[469] PIN w0_wd_in[470] @@ -4241,7 +8849,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 108.063 0.000 108.081 0.018 ; + RECT 61.839 0.000 61.857 0.054 ; END END w0_wd_in[470] PIN w0_wd_in[471] @@ -4250,7 +8858,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 108.567 0.000 108.585 0.018 ; + RECT 62.127 0.000 62.145 0.054 ; END END w0_wd_in[471] PIN w0_wd_in[472] @@ -4259,7 +8867,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 109.071 0.000 109.089 0.018 ; + RECT 62.415 0.000 62.433 0.054 ; END END w0_wd_in[472] PIN w0_wd_in[473] @@ -4268,7 +8876,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 109.575 0.000 109.593 0.018 ; + RECT 62.703 0.000 62.721 0.054 ; END END w0_wd_in[473] PIN w0_wd_in[474] @@ -4277,7 +8885,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 110.079 0.000 110.097 0.018 ; + RECT 62.991 0.000 63.009 0.054 ; END END w0_wd_in[474] PIN w0_wd_in[475] @@ -4286,7 +8894,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 110.583 0.000 110.601 0.018 ; + RECT 63.279 0.000 63.297 0.054 ; END END w0_wd_in[475] PIN w0_wd_in[476] @@ -4295,7 +8903,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 111.087 0.000 111.105 0.018 ; + RECT 63.567 0.000 63.585 0.054 ; END END w0_wd_in[476] PIN w0_wd_in[477] @@ -4304,7 +8912,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 111.591 0.000 111.609 0.018 ; + RECT 63.855 0.000 63.873 0.054 ; END END w0_wd_in[477] PIN w0_wd_in[478] @@ -4313,7 +8921,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 112.095 0.000 112.113 0.018 ; + RECT 64.143 0.000 64.161 0.054 ; END END w0_wd_in[478] PIN w0_wd_in[479] @@ -4322,7 +8930,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 112.599 0.000 112.617 0.018 ; + RECT 64.431 0.000 64.449 0.054 ; END END w0_wd_in[479] PIN w0_wd_in[480] @@ -4331,7 +8939,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 113.103 0.000 113.121 0.018 ; + RECT 64.719 0.000 64.737 0.054 ; END END w0_wd_in[480] PIN w0_wd_in[481] @@ -4340,7 +8948,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 113.607 0.000 113.625 0.018 ; + RECT 65.007 0.000 65.025 0.054 ; END END w0_wd_in[481] PIN w0_wd_in[482] @@ -4349,7 +8957,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 114.111 0.000 114.129 0.018 ; + RECT 65.295 0.000 65.313 0.054 ; END END w0_wd_in[482] PIN w0_wd_in[483] @@ -4358,7 +8966,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 114.615 0.000 114.633 0.018 ; + RECT 65.583 0.000 65.601 0.054 ; END END w0_wd_in[483] PIN w0_wd_in[484] @@ -4367,7 +8975,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 115.119 0.000 115.137 0.018 ; + RECT 65.871 0.000 65.889 0.054 ; END END w0_wd_in[484] PIN w0_wd_in[485] @@ -4376,7 +8984,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 115.623 0.000 115.641 0.018 ; + RECT 66.159 0.000 66.177 0.054 ; END END w0_wd_in[485] PIN w0_wd_in[486] @@ -4385,7 +8993,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 116.127 0.000 116.145 0.018 ; + RECT 66.447 0.000 66.465 0.054 ; END END w0_wd_in[486] PIN w0_wd_in[487] @@ -4394,7 +9002,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 116.631 0.000 116.649 0.018 ; + RECT 66.735 0.000 66.753 0.054 ; END END w0_wd_in[487] PIN w0_wd_in[488] @@ -4403,7 +9011,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 117.135 0.000 117.153 0.018 ; + RECT 67.023 0.000 67.041 0.054 ; END END w0_wd_in[488] PIN w0_wd_in[489] @@ -4412,7 +9020,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 117.639 0.000 117.657 0.018 ; + RECT 67.311 0.000 67.329 0.054 ; END END w0_wd_in[489] PIN w0_wd_in[490] @@ -4421,7 +9029,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 118.143 0.000 118.161 0.018 ; + RECT 67.599 0.000 67.617 0.054 ; END END w0_wd_in[490] PIN w0_wd_in[491] @@ -4430,7 +9038,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 118.647 0.000 118.665 0.018 ; + RECT 67.887 0.000 67.905 0.054 ; END END w0_wd_in[491] PIN w0_wd_in[492] @@ -4439,7 +9047,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 119.151 0.000 119.169 0.018 ; + RECT 68.175 0.000 68.193 0.054 ; END END w0_wd_in[492] PIN w0_wd_in[493] @@ -4448,7 +9056,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 119.655 0.000 119.673 0.018 ; + RECT 68.463 0.000 68.481 0.054 ; END END w0_wd_in[493] PIN w0_wd_in[494] @@ -4457,7 +9065,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 120.159 0.000 120.177 0.018 ; + RECT 68.751 0.000 68.769 0.054 ; END END w0_wd_in[494] PIN w0_wd_in[495] @@ -4466,7 +9074,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 120.663 0.000 120.681 0.018 ; + RECT 69.039 0.000 69.057 0.054 ; END END w0_wd_in[495] PIN w0_wd_in[496] @@ -4475,7 +9083,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 121.167 0.000 121.185 0.018 ; + RECT 69.327 0.000 69.345 0.054 ; END END w0_wd_in[496] PIN w0_wd_in[497] @@ -4484,7 +9092,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 121.671 0.000 121.689 0.018 ; + RECT 69.615 0.000 69.633 0.054 ; END END w0_wd_in[497] PIN w0_wd_in[498] @@ -4493,7 +9101,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 122.175 0.000 122.193 0.018 ; + RECT 69.903 0.000 69.921 0.054 ; END END w0_wd_in[498] PIN w0_wd_in[499] @@ -4502,7 +9110,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 122.679 0.000 122.697 0.018 ; + RECT 70.191 0.000 70.209 0.054 ; END END w0_wd_in[499] PIN w0_wd_in[500] @@ -4511,7 +9119,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 123.183 0.000 123.201 0.018 ; + RECT 70.479 0.000 70.497 0.054 ; END END w0_wd_in[500] PIN w0_wd_in[501] @@ -4520,7 +9128,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 123.687 0.000 123.705 0.018 ; + RECT 70.767 0.000 70.785 0.054 ; END END w0_wd_in[501] PIN w0_wd_in[502] @@ -4529,7 +9137,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 124.191 0.000 124.209 0.018 ; + RECT 71.055 0.000 71.073 0.054 ; END END w0_wd_in[502] PIN w0_wd_in[503] @@ -4538,7 +9146,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 124.695 0.000 124.713 0.018 ; + RECT 71.343 0.000 71.361 0.054 ; END END w0_wd_in[503] PIN w0_wd_in[504] @@ -4547,7 +9155,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 125.199 0.000 125.217 0.018 ; + RECT 71.631 0.000 71.649 0.054 ; END END w0_wd_in[504] PIN w0_wd_in[505] @@ -4556,7 +9164,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 125.703 0.000 125.721 0.018 ; + RECT 71.919 0.000 71.937 0.054 ; END END w0_wd_in[505] PIN w0_wd_in[506] @@ -4565,7 +9173,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 126.207 0.000 126.225 0.018 ; + RECT 72.207 0.000 72.225 0.054 ; END END w0_wd_in[506] PIN w0_wd_in[507] @@ -4574,7 +9182,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 126.711 0.000 126.729 0.018 ; + RECT 72.495 0.000 72.513 0.054 ; END END w0_wd_in[507] PIN w0_wd_in[508] @@ -4583,7 +9191,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 127.215 0.000 127.233 0.018 ; + RECT 72.783 0.000 72.801 0.054 ; END END w0_wd_in[508] PIN w0_wd_in[509] @@ -4592,7 +9200,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 127.719 0.000 127.737 0.018 ; + RECT 73.071 0.000 73.089 0.054 ; END END w0_wd_in[509] PIN w0_wd_in[510] @@ -4601,7 +9209,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 128.223 0.000 128.241 0.018 ; + RECT 73.359 0.000 73.377 0.054 ; END END w0_wd_in[510] PIN w0_wd_in[511] @@ -4610,7 +9218,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 128.727 0.000 128.745 0.018 ; + RECT 73.647 0.000 73.665 0.054 ; END END w0_wd_in[511] PIN r0_rd_out[0] @@ -4619,7 +9227,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 129.231 0.000 129.249 0.018 ; + RECT 73.935 0.000 73.953 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -4628,7 +9236,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 129.735 0.000 129.753 0.018 ; + RECT 74.223 0.000 74.241 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -4637,7 +9245,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 130.239 0.000 130.257 0.018 ; + RECT 74.511 0.000 74.529 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -4646,7 +9254,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 130.743 0.000 130.761 0.018 ; + RECT 74.799 0.000 74.817 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -4655,7 +9263,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 131.247 0.000 131.265 0.018 ; + RECT 75.087 0.000 75.105 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -4664,7 +9272,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 131.751 0.000 131.769 0.018 ; + RECT 75.375 0.000 75.393 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -4673,7 +9281,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 132.255 0.000 132.273 0.018 ; + RECT 75.663 0.000 75.681 0.054 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -4682,7 +9290,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 132.759 0.000 132.777 0.018 ; + RECT 75.951 0.000 75.969 0.054 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -4691,7 +9299,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 133.263 0.000 133.281 0.018 ; + RECT 76.239 0.000 76.257 0.054 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -4700,7 +9308,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 133.767 0.000 133.785 0.018 ; + RECT 76.527 0.000 76.545 0.054 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -4709,7 +9317,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 134.271 0.000 134.289 0.018 ; + RECT 76.815 0.000 76.833 0.054 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -4718,7 +9326,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 134.775 0.000 134.793 0.018 ; + RECT 77.103 0.000 77.121 0.054 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -4727,7 +9335,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 135.279 0.000 135.297 0.018 ; + RECT 77.391 0.000 77.409 0.054 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -4736,7 +9344,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 135.783 0.000 135.801 0.018 ; + RECT 77.679 0.000 77.697 0.054 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -4745,7 +9353,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 136.287 0.000 136.305 0.018 ; + RECT 77.967 0.000 77.985 0.054 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -4754,7 +9362,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 136.791 0.000 136.809 0.018 ; + RECT 78.255 0.000 78.273 0.054 ; END END r0_rd_out[15] PIN r0_rd_out[16] @@ -4763,7 +9371,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 137.295 0.000 137.313 0.018 ; + RECT 78.543 0.000 78.561 0.054 ; END END r0_rd_out[16] PIN r0_rd_out[17] @@ -4772,7 +9380,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 137.799 0.000 137.817 0.018 ; + RECT 78.831 0.000 78.849 0.054 ; END END r0_rd_out[17] PIN r0_rd_out[18] @@ -4781,7 +9389,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 138.303 0.000 138.321 0.018 ; + RECT 79.119 0.000 79.137 0.054 ; END END r0_rd_out[18] PIN r0_rd_out[19] @@ -4790,7 +9398,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 138.807 0.000 138.825 0.018 ; + RECT 79.407 0.000 79.425 0.054 ; END END r0_rd_out[19] PIN r0_rd_out[20] @@ -4799,7 +9407,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 139.311 0.000 139.329 0.018 ; + RECT 79.695 0.000 79.713 0.054 ; END END r0_rd_out[20] PIN r0_rd_out[21] @@ -4808,7 +9416,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 139.815 0.000 139.833 0.018 ; + RECT 79.983 0.000 80.001 0.054 ; END END r0_rd_out[21] PIN r0_rd_out[22] @@ -4817,7 +9425,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 140.319 0.000 140.337 0.018 ; + RECT 80.271 0.000 80.289 0.054 ; END END r0_rd_out[22] PIN r0_rd_out[23] @@ -4826,7 +9434,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 140.823 0.000 140.841 0.018 ; + RECT 80.559 0.000 80.577 0.054 ; END END r0_rd_out[23] PIN r0_rd_out[24] @@ -4835,7 +9443,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 141.327 0.000 141.345 0.018 ; + RECT 80.847 0.000 80.865 0.054 ; END END r0_rd_out[24] PIN r0_rd_out[25] @@ -4844,7 +9452,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 141.831 0.000 141.849 0.018 ; + RECT 81.135 0.000 81.153 0.054 ; END END r0_rd_out[25] PIN r0_rd_out[26] @@ -4853,7 +9461,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 142.335 0.000 142.353 0.018 ; + RECT 81.423 0.000 81.441 0.054 ; END END r0_rd_out[26] PIN r0_rd_out[27] @@ -4862,7 +9470,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 142.839 0.000 142.857 0.018 ; + RECT 81.711 0.000 81.729 0.054 ; END END r0_rd_out[27] PIN r0_rd_out[28] @@ -4871,7 +9479,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 143.343 0.000 143.361 0.018 ; + RECT 81.999 0.000 82.017 0.054 ; END END r0_rd_out[28] PIN r0_rd_out[29] @@ -4880,7 +9488,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 143.847 0.000 143.865 0.018 ; + RECT 82.287 0.000 82.305 0.054 ; END END r0_rd_out[29] PIN r0_rd_out[30] @@ -4889,7 +9497,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 144.351 0.000 144.369 0.018 ; + RECT 82.575 0.000 82.593 0.054 ; END END r0_rd_out[30] PIN r0_rd_out[31] @@ -4898,7 +9506,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 144.855 0.000 144.873 0.018 ; + RECT 82.863 0.000 82.881 0.054 ; END END r0_rd_out[31] PIN r0_rd_out[32] @@ -4907,7 +9515,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 145.359 0.000 145.377 0.018 ; + RECT 83.151 0.000 83.169 0.054 ; END END r0_rd_out[32] PIN r0_rd_out[33] @@ -4916,7 +9524,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 145.863 0.000 145.881 0.018 ; + RECT 83.439 0.000 83.457 0.054 ; END END r0_rd_out[33] PIN r0_rd_out[34] @@ -4925,7 +9533,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 146.367 0.000 146.385 0.018 ; + RECT 83.727 0.000 83.745 0.054 ; END END r0_rd_out[34] PIN r0_rd_out[35] @@ -4934,7 +9542,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 146.871 0.000 146.889 0.018 ; + RECT 84.015 0.000 84.033 0.054 ; END END r0_rd_out[35] PIN r0_rd_out[36] @@ -4943,7 +9551,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 147.375 0.000 147.393 0.018 ; + RECT 84.303 0.000 84.321 0.054 ; END END r0_rd_out[36] PIN r0_rd_out[37] @@ -4952,7 +9560,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 147.879 0.000 147.897 0.018 ; + RECT 84.591 0.000 84.609 0.054 ; END END r0_rd_out[37] PIN r0_rd_out[38] @@ -4961,7 +9569,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 148.383 0.000 148.401 0.018 ; + RECT 84.879 0.000 84.897 0.054 ; END END r0_rd_out[38] PIN r0_rd_out[39] @@ -4970,7 +9578,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 148.887 0.000 148.905 0.018 ; + RECT 85.167 0.000 85.185 0.054 ; END END r0_rd_out[39] PIN r0_rd_out[40] @@ -4979,7 +9587,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 149.391 0.000 149.409 0.018 ; + RECT 85.455 0.000 85.473 0.054 ; END END r0_rd_out[40] PIN r0_rd_out[41] @@ -4988,7 +9596,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 149.895 0.000 149.913 0.018 ; + RECT 85.743 0.000 85.761 0.054 ; END END r0_rd_out[41] PIN r0_rd_out[42] @@ -4997,7 +9605,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 150.399 0.000 150.417 0.018 ; + RECT 86.031 0.000 86.049 0.054 ; END END r0_rd_out[42] PIN r0_rd_out[43] @@ -5006,7 +9614,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 150.903 0.000 150.921 0.018 ; + RECT 86.319 0.000 86.337 0.054 ; END END r0_rd_out[43] PIN r0_rd_out[44] @@ -5015,7 +9623,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 151.407 0.000 151.425 0.018 ; + RECT 86.607 0.000 86.625 0.054 ; END END r0_rd_out[44] PIN r0_rd_out[45] @@ -5024,7 +9632,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 151.911 0.000 151.929 0.018 ; + RECT 86.895 0.000 86.913 0.054 ; END END r0_rd_out[45] PIN r0_rd_out[46] @@ -5033,7 +9641,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 152.415 0.000 152.433 0.018 ; + RECT 87.183 0.000 87.201 0.054 ; END END r0_rd_out[46] PIN r0_rd_out[47] @@ -5042,7 +9650,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 152.919 0.000 152.937 0.018 ; + RECT 87.471 0.000 87.489 0.054 ; END END r0_rd_out[47] PIN r0_rd_out[48] @@ -5051,7 +9659,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 153.423 0.000 153.441 0.018 ; + RECT 87.759 0.000 87.777 0.054 ; END END r0_rd_out[48] PIN r0_rd_out[49] @@ -5060,7 +9668,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 153.927 0.000 153.945 0.018 ; + RECT 88.047 0.000 88.065 0.054 ; END END r0_rd_out[49] PIN r0_rd_out[50] @@ -5069,7 +9677,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 154.431 0.000 154.449 0.018 ; + RECT 88.335 0.000 88.353 0.054 ; END END r0_rd_out[50] PIN r0_rd_out[51] @@ -5078,7 +9686,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 154.935 0.000 154.953 0.018 ; + RECT 88.623 0.000 88.641 0.054 ; END END r0_rd_out[51] PIN r0_rd_out[52] @@ -5087,7 +9695,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 155.439 0.000 155.457 0.018 ; + RECT 88.911 0.000 88.929 0.054 ; END END r0_rd_out[52] PIN r0_rd_out[53] @@ -5096,7 +9704,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 155.943 0.000 155.961 0.018 ; + RECT 89.199 0.000 89.217 0.054 ; END END r0_rd_out[53] PIN r0_rd_out[54] @@ -5105,7 +9713,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 156.447 0.000 156.465 0.018 ; + RECT 89.487 0.000 89.505 0.054 ; END END r0_rd_out[54] PIN r0_rd_out[55] @@ -5114,7 +9722,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 156.951 0.000 156.969 0.018 ; + RECT 89.775 0.000 89.793 0.054 ; END END r0_rd_out[55] PIN r0_rd_out[56] @@ -5123,7 +9731,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 157.455 0.000 157.473 0.018 ; + RECT 90.063 0.000 90.081 0.054 ; END END r0_rd_out[56] PIN r0_rd_out[57] @@ -5132,7 +9740,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 157.959 0.000 157.977 0.018 ; + RECT 90.351 0.000 90.369 0.054 ; END END r0_rd_out[57] PIN r0_rd_out[58] @@ -5141,7 +9749,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 158.463 0.000 158.481 0.018 ; + RECT 90.639 0.000 90.657 0.054 ; END END r0_rd_out[58] PIN r0_rd_out[59] @@ -5150,7 +9758,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 158.967 0.000 158.985 0.018 ; + RECT 90.927 0.000 90.945 0.054 ; END END r0_rd_out[59] PIN r0_rd_out[60] @@ -5159,7 +9767,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 159.471 0.000 159.489 0.018 ; + RECT 91.215 0.000 91.233 0.054 ; END END r0_rd_out[60] PIN r0_rd_out[61] @@ -5168,7 +9776,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 159.975 0.000 159.993 0.018 ; + RECT 91.503 0.000 91.521 0.054 ; END END r0_rd_out[61] PIN r0_rd_out[62] @@ -5177,7 +9785,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 160.479 0.000 160.497 0.018 ; + RECT 91.791 0.000 91.809 0.054 ; END END r0_rd_out[62] PIN r0_rd_out[63] @@ -5186,7 +9794,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 160.983 0.000 161.001 0.018 ; + RECT 92.079 0.000 92.097 0.054 ; END END r0_rd_out[63] PIN r0_rd_out[64] @@ -5195,7 +9803,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 161.487 0.000 161.505 0.018 ; + RECT 92.367 0.000 92.385 0.054 ; END END r0_rd_out[64] PIN r0_rd_out[65] @@ -5204,7 +9812,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 161.991 0.000 162.009 0.018 ; + RECT 92.655 0.000 92.673 0.054 ; END END r0_rd_out[65] PIN r0_rd_out[66] @@ -5213,7 +9821,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 162.495 0.000 162.513 0.018 ; + RECT 92.943 0.000 92.961 0.054 ; END END r0_rd_out[66] PIN r0_rd_out[67] @@ -5222,7 +9830,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 162.999 0.000 163.017 0.018 ; + RECT 93.231 0.000 93.249 0.054 ; END END r0_rd_out[67] PIN r0_rd_out[68] @@ -5231,7 +9839,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 163.503 0.000 163.521 0.018 ; + RECT 93.519 0.000 93.537 0.054 ; END END r0_rd_out[68] PIN r0_rd_out[69] @@ -5240,7 +9848,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 164.007 0.000 164.025 0.018 ; + RECT 93.807 0.000 93.825 0.054 ; END END r0_rd_out[69] PIN r0_rd_out[70] @@ -5249,7 +9857,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 164.511 0.000 164.529 0.018 ; + RECT 94.095 0.000 94.113 0.054 ; END END r0_rd_out[70] PIN r0_rd_out[71] @@ -5258,7 +9866,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 165.015 0.000 165.033 0.018 ; + RECT 94.383 0.000 94.401 0.054 ; END END r0_rd_out[71] PIN r0_rd_out[72] @@ -5267,7 +9875,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 165.519 0.000 165.537 0.018 ; + RECT 94.671 0.000 94.689 0.054 ; END END r0_rd_out[72] PIN r0_rd_out[73] @@ -5276,7 +9884,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 166.023 0.000 166.041 0.018 ; + RECT 94.959 0.000 94.977 0.054 ; END END r0_rd_out[73] PIN r0_rd_out[74] @@ -5285,7 +9893,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 166.527 0.000 166.545 0.018 ; + RECT 95.247 0.000 95.265 0.054 ; END END r0_rd_out[74] PIN r0_rd_out[75] @@ -5294,7 +9902,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 167.031 0.000 167.049 0.018 ; + RECT 95.535 0.000 95.553 0.054 ; END END r0_rd_out[75] PIN r0_rd_out[76] @@ -5303,7 +9911,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 167.535 0.000 167.553 0.018 ; + RECT 95.823 0.000 95.841 0.054 ; END END r0_rd_out[76] PIN r0_rd_out[77] @@ -5312,7 +9920,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 168.039 0.000 168.057 0.018 ; + RECT 96.111 0.000 96.129 0.054 ; END END r0_rd_out[77] PIN r0_rd_out[78] @@ -5321,7 +9929,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 168.543 0.000 168.561 0.018 ; + RECT 96.399 0.000 96.417 0.054 ; END END r0_rd_out[78] PIN r0_rd_out[79] @@ -5330,7 +9938,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 169.047 0.000 169.065 0.018 ; + RECT 96.687 0.000 96.705 0.054 ; END END r0_rd_out[79] PIN r0_rd_out[80] @@ -5339,7 +9947,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 169.551 0.000 169.569 0.018 ; + RECT 96.975 0.000 96.993 0.054 ; END END r0_rd_out[80] PIN r0_rd_out[81] @@ -5348,7 +9956,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 170.055 0.000 170.073 0.018 ; + RECT 97.263 0.000 97.281 0.054 ; END END r0_rd_out[81] PIN r0_rd_out[82] @@ -5357,7 +9965,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 170.559 0.000 170.577 0.018 ; + RECT 97.551 0.000 97.569 0.054 ; END END r0_rd_out[82] PIN r0_rd_out[83] @@ -5366,7 +9974,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 171.063 0.000 171.081 0.018 ; + RECT 97.839 0.000 97.857 0.054 ; END END r0_rd_out[83] PIN r0_rd_out[84] @@ -5375,7 +9983,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 171.567 0.000 171.585 0.018 ; + RECT 98.127 0.000 98.145 0.054 ; END END r0_rd_out[84] PIN r0_rd_out[85] @@ -5384,7 +9992,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 172.071 0.000 172.089 0.018 ; + RECT 98.415 0.000 98.433 0.054 ; END END r0_rd_out[85] PIN r0_rd_out[86] @@ -5393,7 +10001,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 172.575 0.000 172.593 0.018 ; + RECT 98.703 0.000 98.721 0.054 ; END END r0_rd_out[86] PIN r0_rd_out[87] @@ -5402,7 +10010,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 173.079 0.000 173.097 0.018 ; + RECT 98.991 0.000 99.009 0.054 ; END END r0_rd_out[87] PIN r0_rd_out[88] @@ -5411,7 +10019,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 173.583 0.000 173.601 0.018 ; + RECT 99.279 0.000 99.297 0.054 ; END END r0_rd_out[88] PIN r0_rd_out[89] @@ -5420,7 +10028,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 174.087 0.000 174.105 0.018 ; + RECT 99.567 0.000 99.585 0.054 ; END END r0_rd_out[89] PIN r0_rd_out[90] @@ -5429,7 +10037,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 174.591 0.000 174.609 0.018 ; + RECT 99.855 0.000 99.873 0.054 ; END END r0_rd_out[90] PIN r0_rd_out[91] @@ -5438,7 +10046,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 175.095 0.000 175.113 0.018 ; + RECT 100.143 0.000 100.161 0.054 ; END END r0_rd_out[91] PIN r0_rd_out[92] @@ -5447,7 +10055,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 175.599 0.000 175.617 0.018 ; + RECT 100.431 0.000 100.449 0.054 ; END END r0_rd_out[92] PIN r0_rd_out[93] @@ -5456,7 +10064,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 176.103 0.000 176.121 0.018 ; + RECT 100.719 0.000 100.737 0.054 ; END END r0_rd_out[93] PIN r0_rd_out[94] @@ -5465,7 +10073,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 176.607 0.000 176.625 0.018 ; + RECT 101.007 0.000 101.025 0.054 ; END END r0_rd_out[94] PIN r0_rd_out[95] @@ -5474,7 +10082,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 177.111 0.000 177.129 0.018 ; + RECT 101.295 0.000 101.313 0.054 ; END END r0_rd_out[95] PIN r0_rd_out[96] @@ -5483,7 +10091,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 177.615 0.000 177.633 0.018 ; + RECT 101.583 0.000 101.601 0.054 ; END END r0_rd_out[96] PIN r0_rd_out[97] @@ -5492,7 +10100,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 178.119 0.000 178.137 0.018 ; + RECT 101.871 0.000 101.889 0.054 ; END END r0_rd_out[97] PIN r0_rd_out[98] @@ -5501,7 +10109,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 178.623 0.000 178.641 0.018 ; + RECT 102.159 0.000 102.177 0.054 ; END END r0_rd_out[98] PIN r0_rd_out[99] @@ -5510,7 +10118,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 179.127 0.000 179.145 0.018 ; + RECT 102.447 0.000 102.465 0.054 ; END END r0_rd_out[99] PIN r0_rd_out[100] @@ -5519,7 +10127,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 179.631 0.000 179.649 0.018 ; + RECT 102.735 0.000 102.753 0.054 ; END END r0_rd_out[100] PIN r0_rd_out[101] @@ -5528,7 +10136,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 180.135 0.000 180.153 0.018 ; + RECT 103.023 0.000 103.041 0.054 ; END END r0_rd_out[101] PIN r0_rd_out[102] @@ -5537,7 +10145,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 180.639 0.000 180.657 0.018 ; + RECT 103.311 0.000 103.329 0.054 ; END END r0_rd_out[102] PIN r0_rd_out[103] @@ -5546,7 +10154,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 181.143 0.000 181.161 0.018 ; + RECT 103.599 0.000 103.617 0.054 ; END END r0_rd_out[103] PIN r0_rd_out[104] @@ -5555,7 +10163,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 181.647 0.000 181.665 0.018 ; + RECT 103.887 0.000 103.905 0.054 ; END END r0_rd_out[104] PIN r0_rd_out[105] @@ -5564,7 +10172,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 182.151 0.000 182.169 0.018 ; + RECT 104.175 0.000 104.193 0.054 ; END END r0_rd_out[105] PIN r0_rd_out[106] @@ -5573,7 +10181,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 182.655 0.000 182.673 0.018 ; + RECT 104.463 0.000 104.481 0.054 ; END END r0_rd_out[106] PIN r0_rd_out[107] @@ -5582,7 +10190,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 183.159 0.000 183.177 0.018 ; + RECT 104.751 0.000 104.769 0.054 ; END END r0_rd_out[107] PIN r0_rd_out[108] @@ -5591,7 +10199,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 183.663 0.000 183.681 0.018 ; + RECT 105.039 0.000 105.057 0.054 ; END END r0_rd_out[108] PIN r0_rd_out[109] @@ -5600,7 +10208,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 184.167 0.000 184.185 0.018 ; + RECT 105.327 0.000 105.345 0.054 ; END END r0_rd_out[109] PIN r0_rd_out[110] @@ -5609,7 +10217,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 184.671 0.000 184.689 0.018 ; + RECT 105.615 0.000 105.633 0.054 ; END END r0_rd_out[110] PIN r0_rd_out[111] @@ -5618,7 +10226,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 185.175 0.000 185.193 0.018 ; + RECT 105.903 0.000 105.921 0.054 ; END END r0_rd_out[111] PIN r0_rd_out[112] @@ -5627,7 +10235,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 185.679 0.000 185.697 0.018 ; + RECT 106.191 0.000 106.209 0.054 ; END END r0_rd_out[112] PIN r0_rd_out[113] @@ -5636,7 +10244,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 186.183 0.000 186.201 0.018 ; + RECT 106.479 0.000 106.497 0.054 ; END END r0_rd_out[113] PIN r0_rd_out[114] @@ -5645,7 +10253,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 186.687 0.000 186.705 0.018 ; + RECT 106.767 0.000 106.785 0.054 ; END END r0_rd_out[114] PIN r0_rd_out[115] @@ -5654,7 +10262,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 187.191 0.000 187.209 0.018 ; + RECT 107.055 0.000 107.073 0.054 ; END END r0_rd_out[115] PIN r0_rd_out[116] @@ -5663,7 +10271,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 187.695 0.000 187.713 0.018 ; + RECT 107.343 0.000 107.361 0.054 ; END END r0_rd_out[116] PIN r0_rd_out[117] @@ -5672,7 +10280,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 188.199 0.000 188.217 0.018 ; + RECT 107.631 0.000 107.649 0.054 ; END END r0_rd_out[117] PIN r0_rd_out[118] @@ -5681,7 +10289,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 188.703 0.000 188.721 0.018 ; + RECT 107.919 0.000 107.937 0.054 ; END END r0_rd_out[118] PIN r0_rd_out[119] @@ -5690,7 +10298,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 189.207 0.000 189.225 0.018 ; + RECT 108.207 0.000 108.225 0.054 ; END END r0_rd_out[119] PIN r0_rd_out[120] @@ -5699,7 +10307,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 189.711 0.000 189.729 0.018 ; + RECT 108.495 0.000 108.513 0.054 ; END END r0_rd_out[120] PIN r0_rd_out[121] @@ -5708,7 +10316,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 190.215 0.000 190.233 0.018 ; + RECT 108.783 0.000 108.801 0.054 ; END END r0_rd_out[121] PIN r0_rd_out[122] @@ -5717,7 +10325,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 190.719 0.000 190.737 0.018 ; + RECT 109.071 0.000 109.089 0.054 ; END END r0_rd_out[122] PIN r0_rd_out[123] @@ -5726,7 +10334,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 191.223 0.000 191.241 0.018 ; + RECT 109.359 0.000 109.377 0.054 ; END END r0_rd_out[123] PIN r0_rd_out[124] @@ -5735,7 +10343,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 191.727 0.000 191.745 0.018 ; + RECT 109.647 0.000 109.665 0.054 ; END END r0_rd_out[124] PIN r0_rd_out[125] @@ -5744,7 +10352,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 192.231 0.000 192.249 0.018 ; + RECT 109.935 0.000 109.953 0.054 ; END END r0_rd_out[125] PIN r0_rd_out[126] @@ -5753,7 +10361,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 192.735 0.000 192.753 0.018 ; + RECT 110.223 0.000 110.241 0.054 ; END END r0_rd_out[126] PIN r0_rd_out[127] @@ -5762,7 +10370,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 193.239 0.000 193.257 0.018 ; + RECT 110.511 0.000 110.529 0.054 ; END END r0_rd_out[127] PIN r0_rd_out[128] @@ -5771,7 +10379,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 193.743 0.000 193.761 0.018 ; + RECT 110.799 0.000 110.817 0.054 ; END END r0_rd_out[128] PIN r0_rd_out[129] @@ -5780,7 +10388,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 194.247 0.000 194.265 0.018 ; + RECT 111.087 0.000 111.105 0.054 ; END END r0_rd_out[129] PIN r0_rd_out[130] @@ -5789,7 +10397,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 194.751 0.000 194.769 0.018 ; + RECT 111.375 0.000 111.393 0.054 ; END END r0_rd_out[130] PIN r0_rd_out[131] @@ -5798,7 +10406,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 195.255 0.000 195.273 0.018 ; + RECT 111.663 0.000 111.681 0.054 ; END END r0_rd_out[131] PIN r0_rd_out[132] @@ -5807,7 +10415,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 195.759 0.000 195.777 0.018 ; + RECT 111.951 0.000 111.969 0.054 ; END END r0_rd_out[132] PIN r0_rd_out[133] @@ -5816,7 +10424,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 196.263 0.000 196.281 0.018 ; + RECT 112.239 0.000 112.257 0.054 ; END END r0_rd_out[133] PIN r0_rd_out[134] @@ -5825,7 +10433,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 196.767 0.000 196.785 0.018 ; + RECT 112.527 0.000 112.545 0.054 ; END END r0_rd_out[134] PIN r0_rd_out[135] @@ -5834,7 +10442,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 197.271 0.000 197.289 0.018 ; + RECT 112.815 0.000 112.833 0.054 ; END END r0_rd_out[135] PIN r0_rd_out[136] @@ -5843,7 +10451,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 197.775 0.000 197.793 0.018 ; + RECT 113.103 0.000 113.121 0.054 ; END END r0_rd_out[136] PIN r0_rd_out[137] @@ -5852,7 +10460,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 198.279 0.000 198.297 0.018 ; + RECT 113.391 0.000 113.409 0.054 ; END END r0_rd_out[137] PIN r0_rd_out[138] @@ -5861,7 +10469,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 198.783 0.000 198.801 0.018 ; + RECT 113.679 0.000 113.697 0.054 ; END END r0_rd_out[138] PIN r0_rd_out[139] @@ -5870,7 +10478,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 199.287 0.000 199.305 0.018 ; + RECT 113.967 0.000 113.985 0.054 ; END END r0_rd_out[139] PIN r0_rd_out[140] @@ -5879,7 +10487,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 199.791 0.000 199.809 0.018 ; + RECT 114.255 0.000 114.273 0.054 ; END END r0_rd_out[140] PIN r0_rd_out[141] @@ -5888,7 +10496,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 200.295 0.000 200.313 0.018 ; + RECT 114.543 0.000 114.561 0.054 ; END END r0_rd_out[141] PIN r0_rd_out[142] @@ -5897,7 +10505,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 200.799 0.000 200.817 0.018 ; + RECT 114.831 0.000 114.849 0.054 ; END END r0_rd_out[142] PIN r0_rd_out[143] @@ -5906,7 +10514,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 201.303 0.000 201.321 0.018 ; + RECT 115.119 0.000 115.137 0.054 ; END END r0_rd_out[143] PIN r0_rd_out[144] @@ -5915,7 +10523,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 201.807 0.000 201.825 0.018 ; + RECT 115.407 0.000 115.425 0.054 ; END END r0_rd_out[144] PIN r0_rd_out[145] @@ -5924,7 +10532,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 202.311 0.000 202.329 0.018 ; + RECT 115.695 0.000 115.713 0.054 ; END END r0_rd_out[145] PIN r0_rd_out[146] @@ -5933,7 +10541,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 202.815 0.000 202.833 0.018 ; + RECT 115.983 0.000 116.001 0.054 ; END END r0_rd_out[146] PIN r0_rd_out[147] @@ -5942,7 +10550,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 203.319 0.000 203.337 0.018 ; + RECT 116.271 0.000 116.289 0.054 ; END END r0_rd_out[147] PIN r0_rd_out[148] @@ -5951,7 +10559,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 203.823 0.000 203.841 0.018 ; + RECT 116.559 0.000 116.577 0.054 ; END END r0_rd_out[148] PIN r0_rd_out[149] @@ -5960,7 +10568,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 204.327 0.000 204.345 0.018 ; + RECT 116.847 0.000 116.865 0.054 ; END END r0_rd_out[149] PIN r0_rd_out[150] @@ -5969,7 +10577,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 204.831 0.000 204.849 0.018 ; + RECT 117.135 0.000 117.153 0.054 ; END END r0_rd_out[150] PIN r0_rd_out[151] @@ -5978,7 +10586,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 205.335 0.000 205.353 0.018 ; + RECT 117.423 0.000 117.441 0.054 ; END END r0_rd_out[151] PIN r0_rd_out[152] @@ -5987,7 +10595,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 205.839 0.000 205.857 0.018 ; + RECT 117.711 0.000 117.729 0.054 ; END END r0_rd_out[152] PIN r0_rd_out[153] @@ -5996,7 +10604,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 206.343 0.000 206.361 0.018 ; + RECT 117.999 0.000 118.017 0.054 ; END END r0_rd_out[153] PIN r0_rd_out[154] @@ -6005,7 +10613,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 206.847 0.000 206.865 0.018 ; + RECT 118.287 0.000 118.305 0.054 ; END END r0_rd_out[154] PIN r0_rd_out[155] @@ -6014,7 +10622,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 207.351 0.000 207.369 0.018 ; + RECT 118.575 0.000 118.593 0.054 ; END END r0_rd_out[155] PIN r0_rd_out[156] @@ -6023,7 +10631,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 207.855 0.000 207.873 0.018 ; + RECT 118.863 0.000 118.881 0.054 ; END END r0_rd_out[156] PIN r0_rd_out[157] @@ -6032,7 +10640,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 208.359 0.000 208.377 0.018 ; + RECT 119.151 0.000 119.169 0.054 ; END END r0_rd_out[157] PIN r0_rd_out[158] @@ -6041,7 +10649,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 208.863 0.000 208.881 0.018 ; + RECT 119.439 0.000 119.457 0.054 ; END END r0_rd_out[158] PIN r0_rd_out[159] @@ -6050,7 +10658,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 209.367 0.000 209.385 0.018 ; + RECT 119.727 0.000 119.745 0.054 ; END END r0_rd_out[159] PIN r0_rd_out[160] @@ -6059,7 +10667,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 209.871 0.000 209.889 0.018 ; + RECT 120.015 0.000 120.033 0.054 ; END END r0_rd_out[160] PIN r0_rd_out[161] @@ -6068,7 +10676,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 210.375 0.000 210.393 0.018 ; + RECT 120.303 0.000 120.321 0.054 ; END END r0_rd_out[161] PIN r0_rd_out[162] @@ -6077,7 +10685,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 210.879 0.000 210.897 0.018 ; + RECT 120.591 0.000 120.609 0.054 ; END END r0_rd_out[162] PIN r0_rd_out[163] @@ -6086,7 +10694,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 211.383 0.000 211.401 0.018 ; + RECT 120.879 0.000 120.897 0.054 ; END END r0_rd_out[163] PIN r0_rd_out[164] @@ -6095,7 +10703,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 211.887 0.000 211.905 0.018 ; + RECT 121.167 0.000 121.185 0.054 ; END END r0_rd_out[164] PIN r0_rd_out[165] @@ -6104,7 +10712,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 212.391 0.000 212.409 0.018 ; + RECT 121.455 0.000 121.473 0.054 ; END END r0_rd_out[165] PIN r0_rd_out[166] @@ -6113,7 +10721,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 212.895 0.000 212.913 0.018 ; + RECT 121.743 0.000 121.761 0.054 ; END END r0_rd_out[166] PIN r0_rd_out[167] @@ -6122,7 +10730,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 213.399 0.000 213.417 0.018 ; + RECT 122.031 0.000 122.049 0.054 ; END END r0_rd_out[167] PIN r0_rd_out[168] @@ -6131,7 +10739,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 213.903 0.000 213.921 0.018 ; + RECT 122.319 0.000 122.337 0.054 ; END END r0_rd_out[168] PIN r0_rd_out[169] @@ -6140,7 +10748,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 214.407 0.000 214.425 0.018 ; + RECT 122.607 0.000 122.625 0.054 ; END END r0_rd_out[169] PIN r0_rd_out[170] @@ -6149,7 +10757,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 214.911 0.000 214.929 0.018 ; + RECT 122.895 0.000 122.913 0.054 ; END END r0_rd_out[170] PIN r0_rd_out[171] @@ -6158,7 +10766,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 215.415 0.000 215.433 0.018 ; + RECT 123.183 0.000 123.201 0.054 ; END END r0_rd_out[171] PIN r0_rd_out[172] @@ -6167,7 +10775,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 215.919 0.000 215.937 0.018 ; + RECT 123.471 0.000 123.489 0.054 ; END END r0_rd_out[172] PIN r0_rd_out[173] @@ -6176,7 +10784,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 216.423 0.000 216.441 0.018 ; + RECT 123.759 0.000 123.777 0.054 ; END END r0_rd_out[173] PIN r0_rd_out[174] @@ -6185,7 +10793,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 216.927 0.000 216.945 0.018 ; + RECT 124.047 0.000 124.065 0.054 ; END END r0_rd_out[174] PIN r0_rd_out[175] @@ -6194,7 +10802,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 217.431 0.000 217.449 0.018 ; + RECT 124.335 0.000 124.353 0.054 ; END END r0_rd_out[175] PIN r0_rd_out[176] @@ -6203,7 +10811,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 217.935 0.000 217.953 0.018 ; + RECT 124.623 0.000 124.641 0.054 ; END END r0_rd_out[176] PIN r0_rd_out[177] @@ -6212,7 +10820,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 218.439 0.000 218.457 0.018 ; + RECT 124.911 0.000 124.929 0.054 ; END END r0_rd_out[177] PIN r0_rd_out[178] @@ -6221,7 +10829,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 218.943 0.000 218.961 0.018 ; + RECT 125.199 0.000 125.217 0.054 ; END END r0_rd_out[178] PIN r0_rd_out[179] @@ -6230,7 +10838,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 219.447 0.000 219.465 0.018 ; + RECT 125.487 0.000 125.505 0.054 ; END END r0_rd_out[179] PIN r0_rd_out[180] @@ -6239,7 +10847,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 219.951 0.000 219.969 0.018 ; + RECT 125.775 0.000 125.793 0.054 ; END END r0_rd_out[180] PIN r0_rd_out[181] @@ -6248,7 +10856,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 220.455 0.000 220.473 0.018 ; + RECT 126.063 0.000 126.081 0.054 ; END END r0_rd_out[181] PIN r0_rd_out[182] @@ -6257,7 +10865,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 220.959 0.000 220.977 0.018 ; + RECT 126.351 0.000 126.369 0.054 ; END END r0_rd_out[182] PIN r0_rd_out[183] @@ -6266,7 +10874,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 221.463 0.000 221.481 0.018 ; + RECT 126.639 0.000 126.657 0.054 ; END END r0_rd_out[183] PIN r0_rd_out[184] @@ -6275,7 +10883,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 221.967 0.000 221.985 0.018 ; + RECT 126.927 0.000 126.945 0.054 ; END END r0_rd_out[184] PIN r0_rd_out[185] @@ -6284,7 +10892,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 222.471 0.000 222.489 0.018 ; + RECT 127.215 0.000 127.233 0.054 ; END END r0_rd_out[185] PIN r0_rd_out[186] @@ -6293,7 +10901,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 222.975 0.000 222.993 0.018 ; + RECT 127.503 0.000 127.521 0.054 ; END END r0_rd_out[186] PIN r0_rd_out[187] @@ -6302,7 +10910,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 223.479 0.000 223.497 0.018 ; + RECT 127.791 0.000 127.809 0.054 ; END END r0_rd_out[187] PIN r0_rd_out[188] @@ -6311,7 +10919,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 223.983 0.000 224.001 0.018 ; + RECT 128.079 0.000 128.097 0.054 ; END END r0_rd_out[188] PIN r0_rd_out[189] @@ -6320,7 +10928,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 224.487 0.000 224.505 0.018 ; + RECT 128.367 0.000 128.385 0.054 ; END END r0_rd_out[189] PIN r0_rd_out[190] @@ -6329,7 +10937,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 224.991 0.000 225.009 0.018 ; + RECT 128.655 0.000 128.673 0.054 ; END END r0_rd_out[190] PIN r0_rd_out[191] @@ -6338,7 +10946,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 225.495 0.000 225.513 0.018 ; + RECT 128.943 0.000 128.961 0.054 ; END END r0_rd_out[191] PIN r0_rd_out[192] @@ -6347,7 +10955,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 225.999 0.000 226.017 0.018 ; + RECT 129.231 0.000 129.249 0.054 ; END END r0_rd_out[192] PIN r0_rd_out[193] @@ -6356,7 +10964,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 226.503 0.000 226.521 0.018 ; + RECT 129.519 0.000 129.537 0.054 ; END END r0_rd_out[193] PIN r0_rd_out[194] @@ -6365,7 +10973,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 227.007 0.000 227.025 0.018 ; + RECT 129.807 0.000 129.825 0.054 ; END END r0_rd_out[194] PIN r0_rd_out[195] @@ -6374,7 +10982,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 227.511 0.000 227.529 0.018 ; + RECT 130.095 0.000 130.113 0.054 ; END END r0_rd_out[195] PIN r0_rd_out[196] @@ -6383,7 +10991,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 228.015 0.000 228.033 0.018 ; + RECT 130.383 0.000 130.401 0.054 ; END END r0_rd_out[196] PIN r0_rd_out[197] @@ -6392,7 +11000,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 228.519 0.000 228.537 0.018 ; + RECT 130.671 0.000 130.689 0.054 ; END END r0_rd_out[197] PIN r0_rd_out[198] @@ -6401,7 +11009,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 229.023 0.000 229.041 0.018 ; + RECT 130.959 0.000 130.977 0.054 ; END END r0_rd_out[198] PIN r0_rd_out[199] @@ -6410,7 +11018,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 229.527 0.000 229.545 0.018 ; + RECT 131.247 0.000 131.265 0.054 ; END END r0_rd_out[199] PIN r0_rd_out[200] @@ -6419,7 +11027,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 230.031 0.000 230.049 0.018 ; + RECT 131.535 0.000 131.553 0.054 ; END END r0_rd_out[200] PIN r0_rd_out[201] @@ -6428,7 +11036,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 230.535 0.000 230.553 0.018 ; + RECT 131.823 0.000 131.841 0.054 ; END END r0_rd_out[201] PIN r0_rd_out[202] @@ -6437,7 +11045,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 231.039 0.000 231.057 0.018 ; + RECT 132.111 0.000 132.129 0.054 ; END END r0_rd_out[202] PIN r0_rd_out[203] @@ -6446,7 +11054,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 231.543 0.000 231.561 0.018 ; + RECT 132.399 0.000 132.417 0.054 ; END END r0_rd_out[203] PIN r0_rd_out[204] @@ -6455,7 +11063,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 232.047 0.000 232.065 0.018 ; + RECT 132.687 0.000 132.705 0.054 ; END END r0_rd_out[204] PIN r0_rd_out[205] @@ -6464,7 +11072,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 232.551 0.000 232.569 0.018 ; + RECT 132.975 0.000 132.993 0.054 ; END END r0_rd_out[205] PIN r0_rd_out[206] @@ -6473,7 +11081,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 233.055 0.000 233.073 0.018 ; + RECT 133.263 0.000 133.281 0.054 ; END END r0_rd_out[206] PIN r0_rd_out[207] @@ -6482,7 +11090,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 233.559 0.000 233.577 0.018 ; + RECT 133.551 0.000 133.569 0.054 ; END END r0_rd_out[207] PIN r0_rd_out[208] @@ -6491,7 +11099,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 234.063 0.000 234.081 0.018 ; + RECT 133.839 0.000 133.857 0.054 ; END END r0_rd_out[208] PIN r0_rd_out[209] @@ -6500,7 +11108,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 234.567 0.000 234.585 0.018 ; + RECT 134.127 0.000 134.145 0.054 ; END END r0_rd_out[209] PIN r0_rd_out[210] @@ -6509,7 +11117,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 235.071 0.000 235.089 0.018 ; + RECT 134.415 0.000 134.433 0.054 ; END END r0_rd_out[210] PIN r0_rd_out[211] @@ -6518,7 +11126,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 235.575 0.000 235.593 0.018 ; + RECT 134.703 0.000 134.721 0.054 ; END END r0_rd_out[211] PIN r0_rd_out[212] @@ -6527,7 +11135,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 236.079 0.000 236.097 0.018 ; + RECT 134.991 0.000 135.009 0.054 ; END END r0_rd_out[212] PIN r0_rd_out[213] @@ -6536,7 +11144,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 236.583 0.000 236.601 0.018 ; + RECT 135.279 0.000 135.297 0.054 ; END END r0_rd_out[213] PIN r0_rd_out[214] @@ -6545,7 +11153,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 237.087 0.000 237.105 0.018 ; + RECT 135.567 0.000 135.585 0.054 ; END END r0_rd_out[214] PIN r0_rd_out[215] @@ -6554,7 +11162,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 237.591 0.000 237.609 0.018 ; + RECT 135.855 0.000 135.873 0.054 ; END END r0_rd_out[215] PIN r0_rd_out[216] @@ -6563,7 +11171,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 238.095 0.000 238.113 0.018 ; + RECT 136.143 0.000 136.161 0.054 ; END END r0_rd_out[216] PIN r0_rd_out[217] @@ -6572,7 +11180,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 238.599 0.000 238.617 0.018 ; + RECT 136.431 0.000 136.449 0.054 ; END END r0_rd_out[217] PIN r0_rd_out[218] @@ -6581,7 +11189,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 239.103 0.000 239.121 0.018 ; + RECT 136.719 0.000 136.737 0.054 ; END END r0_rd_out[218] PIN r0_rd_out[219] @@ -6590,7 +11198,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 239.607 0.000 239.625 0.018 ; + RECT 137.007 0.000 137.025 0.054 ; END END r0_rd_out[219] PIN r0_rd_out[220] @@ -6599,7 +11207,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 240.111 0.000 240.129 0.018 ; + RECT 137.295 0.000 137.313 0.054 ; END END r0_rd_out[220] PIN r0_rd_out[221] @@ -6608,7 +11216,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 240.615 0.000 240.633 0.018 ; + RECT 137.583 0.000 137.601 0.054 ; END END r0_rd_out[221] PIN r0_rd_out[222] @@ -6617,7 +11225,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 241.119 0.000 241.137 0.018 ; + RECT 137.871 0.000 137.889 0.054 ; END END r0_rd_out[222] PIN r0_rd_out[223] @@ -6626,7 +11234,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 241.623 0.000 241.641 0.018 ; + RECT 138.159 0.000 138.177 0.054 ; END END r0_rd_out[223] PIN r0_rd_out[224] @@ -6635,7 +11243,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 242.127 0.000 242.145 0.018 ; + RECT 138.447 0.000 138.465 0.054 ; END END r0_rd_out[224] PIN r0_rd_out[225] @@ -6644,7 +11252,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 242.631 0.000 242.649 0.018 ; + RECT 138.735 0.000 138.753 0.054 ; END END r0_rd_out[225] PIN r0_rd_out[226] @@ -6653,7 +11261,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 243.135 0.000 243.153 0.018 ; + RECT 139.023 0.000 139.041 0.054 ; END END r0_rd_out[226] PIN r0_rd_out[227] @@ -6662,7 +11270,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 243.639 0.000 243.657 0.018 ; + RECT 139.311 0.000 139.329 0.054 ; END END r0_rd_out[227] PIN r0_rd_out[228] @@ -6671,7 +11279,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 244.143 0.000 244.161 0.018 ; + RECT 139.599 0.000 139.617 0.054 ; END END r0_rd_out[228] PIN r0_rd_out[229] @@ -6680,7 +11288,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 244.647 0.000 244.665 0.018 ; + RECT 139.887 0.000 139.905 0.054 ; END END r0_rd_out[229] PIN r0_rd_out[230] @@ -6689,7 +11297,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 245.151 0.000 245.169 0.018 ; + RECT 140.175 0.000 140.193 0.054 ; END END r0_rd_out[230] PIN r0_rd_out[231] @@ -6698,7 +11306,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 245.655 0.000 245.673 0.018 ; + RECT 140.463 0.000 140.481 0.054 ; END END r0_rd_out[231] PIN r0_rd_out[232] @@ -6707,7 +11315,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 246.159 0.000 246.177 0.018 ; + RECT 140.751 0.000 140.769 0.054 ; END END r0_rd_out[232] PIN r0_rd_out[233] @@ -6716,7 +11324,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 246.663 0.000 246.681 0.018 ; + RECT 141.039 0.000 141.057 0.054 ; END END r0_rd_out[233] PIN r0_rd_out[234] @@ -6725,7 +11333,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 247.167 0.000 247.185 0.018 ; + RECT 141.327 0.000 141.345 0.054 ; END END r0_rd_out[234] PIN r0_rd_out[235] @@ -6734,7 +11342,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 247.671 0.000 247.689 0.018 ; + RECT 141.615 0.000 141.633 0.054 ; END END r0_rd_out[235] PIN r0_rd_out[236] @@ -6743,7 +11351,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 248.175 0.000 248.193 0.018 ; + RECT 141.903 0.000 141.921 0.054 ; END END r0_rd_out[236] PIN r0_rd_out[237] @@ -6752,7 +11360,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 248.679 0.000 248.697 0.018 ; + RECT 142.191 0.000 142.209 0.054 ; END END r0_rd_out[237] PIN r0_rd_out[238] @@ -6761,7 +11369,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 249.183 0.000 249.201 0.018 ; + RECT 142.479 0.000 142.497 0.054 ; END END r0_rd_out[238] PIN r0_rd_out[239] @@ -6770,7 +11378,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 249.687 0.000 249.705 0.018 ; + RECT 142.767 0.000 142.785 0.054 ; END END r0_rd_out[239] PIN r0_rd_out[240] @@ -6779,7 +11387,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 250.191 0.000 250.209 0.018 ; + RECT 143.055 0.000 143.073 0.054 ; END END r0_rd_out[240] PIN r0_rd_out[241] @@ -6788,7 +11396,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 250.695 0.000 250.713 0.018 ; + RECT 143.343 0.000 143.361 0.054 ; END END r0_rd_out[241] PIN r0_rd_out[242] @@ -6797,7 +11405,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 251.199 0.000 251.217 0.018 ; + RECT 143.631 0.000 143.649 0.054 ; END END r0_rd_out[242] PIN r0_rd_out[243] @@ -6806,7 +11414,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 251.703 0.000 251.721 0.018 ; + RECT 143.919 0.000 143.937 0.054 ; END END r0_rd_out[243] PIN r0_rd_out[244] @@ -6815,7 +11423,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 252.207 0.000 252.225 0.018 ; + RECT 144.207 0.000 144.225 0.054 ; END END r0_rd_out[244] PIN r0_rd_out[245] @@ -6824,7 +11432,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 252.711 0.000 252.729 0.018 ; + RECT 144.495 0.000 144.513 0.054 ; END END r0_rd_out[245] PIN r0_rd_out[246] @@ -6833,7 +11441,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 253.215 0.000 253.233 0.018 ; + RECT 144.783 0.000 144.801 0.054 ; END END r0_rd_out[246] PIN r0_rd_out[247] @@ -6842,7 +11450,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 253.719 0.000 253.737 0.018 ; + RECT 145.071 0.000 145.089 0.054 ; END END r0_rd_out[247] PIN r0_rd_out[248] @@ -6851,7 +11459,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 254.223 0.000 254.241 0.018 ; + RECT 145.359 0.000 145.377 0.054 ; END END r0_rd_out[248] PIN r0_rd_out[249] @@ -6860,7 +11468,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 254.727 0.000 254.745 0.018 ; + RECT 145.647 0.000 145.665 0.054 ; END END r0_rd_out[249] PIN r0_rd_out[250] @@ -6869,7 +11477,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 255.231 0.000 255.249 0.018 ; + RECT 145.935 0.000 145.953 0.054 ; END END r0_rd_out[250] PIN r0_rd_out[251] @@ -6878,7 +11486,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 255.735 0.000 255.753 0.018 ; + RECT 146.223 0.000 146.241 0.054 ; END END r0_rd_out[251] PIN r0_rd_out[252] @@ -6887,7 +11495,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 256.239 0.000 256.257 0.018 ; + RECT 146.511 0.000 146.529 0.054 ; END END r0_rd_out[252] PIN r0_rd_out[253] @@ -6896,7 +11504,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 256.743 0.000 256.761 0.018 ; + RECT 146.799 0.000 146.817 0.054 ; END END r0_rd_out[253] PIN r0_rd_out[254] @@ -6905,7 +11513,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 257.247 0.000 257.265 0.018 ; + RECT 147.087 0.000 147.105 0.054 ; END END r0_rd_out[254] PIN r0_rd_out[255] @@ -6914,7 +11522,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 257.751 0.000 257.769 0.018 ; + RECT 147.375 0.000 147.393 0.054 ; END END r0_rd_out[255] PIN r0_rd_out[256] @@ -6923,7 +11531,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 165.870 0.225 165.888 ; + RECT 73.935 408.031 73.953 408.085 ; END END r0_rd_out[256] PIN r0_rd_out[257] @@ -6932,7 +11540,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.215 165.870 1.233 165.888 ; + RECT 74.223 408.031 74.241 408.085 ; END END r0_rd_out[257] PIN r0_rd_out[258] @@ -6941,7 +11549,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.223 165.870 2.241 165.888 ; + RECT 74.511 408.031 74.529 408.085 ; END END r0_rd_out[258] PIN r0_rd_out[259] @@ -6950,7 +11558,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.231 165.870 3.249 165.888 ; + RECT 74.799 408.031 74.817 408.085 ; END END r0_rd_out[259] PIN r0_rd_out[260] @@ -6959,7 +11567,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.239 165.870 4.257 165.888 ; + RECT 75.087 408.031 75.105 408.085 ; END END r0_rd_out[260] PIN r0_rd_out[261] @@ -6968,7 +11576,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.247 165.870 5.265 165.888 ; + RECT 75.375 408.031 75.393 408.085 ; END END r0_rd_out[261] PIN r0_rd_out[262] @@ -6977,7 +11585,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.255 165.870 6.273 165.888 ; + RECT 75.663 408.031 75.681 408.085 ; END END r0_rd_out[262] PIN r0_rd_out[263] @@ -6986,7 +11594,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.263 165.870 7.281 165.888 ; + RECT 75.951 408.031 75.969 408.085 ; END END r0_rd_out[263] PIN r0_rd_out[264] @@ -6995,7 +11603,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.271 165.870 8.289 165.888 ; + RECT 76.239 408.031 76.257 408.085 ; END END r0_rd_out[264] PIN r0_rd_out[265] @@ -7004,7 +11612,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.279 165.870 9.297 165.888 ; + RECT 76.527 408.031 76.545 408.085 ; END END r0_rd_out[265] PIN r0_rd_out[266] @@ -7013,7 +11621,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.287 165.870 10.305 165.888 ; + RECT 76.815 408.031 76.833 408.085 ; END END r0_rd_out[266] PIN r0_rd_out[267] @@ -7022,7 +11630,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.295 165.870 11.313 165.888 ; + RECT 77.103 408.031 77.121 408.085 ; END END r0_rd_out[267] PIN r0_rd_out[268] @@ -7031,7 +11639,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.303 165.870 12.321 165.888 ; + RECT 77.391 408.031 77.409 408.085 ; END END r0_rd_out[268] PIN r0_rd_out[269] @@ -7040,7 +11648,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.311 165.870 13.329 165.888 ; + RECT 77.679 408.031 77.697 408.085 ; END END r0_rd_out[269] PIN r0_rd_out[270] @@ -7049,7 +11657,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.319 165.870 14.337 165.888 ; + RECT 77.967 408.031 77.985 408.085 ; END END r0_rd_out[270] PIN r0_rd_out[271] @@ -7058,7 +11666,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 15.327 165.870 15.345 165.888 ; + RECT 78.255 408.031 78.273 408.085 ; END END r0_rd_out[271] PIN r0_rd_out[272] @@ -7067,7 +11675,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 16.335 165.870 16.353 165.888 ; + RECT 78.543 408.031 78.561 408.085 ; END END r0_rd_out[272] PIN r0_rd_out[273] @@ -7076,7 +11684,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 17.343 165.870 17.361 165.888 ; + RECT 78.831 408.031 78.849 408.085 ; END END r0_rd_out[273] PIN r0_rd_out[274] @@ -7085,7 +11693,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 18.351 165.870 18.369 165.888 ; + RECT 79.119 408.031 79.137 408.085 ; END END r0_rd_out[274] PIN r0_rd_out[275] @@ -7094,7 +11702,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 19.359 165.870 19.377 165.888 ; + RECT 79.407 408.031 79.425 408.085 ; END END r0_rd_out[275] PIN r0_rd_out[276] @@ -7103,7 +11711,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 20.367 165.870 20.385 165.888 ; + RECT 79.695 408.031 79.713 408.085 ; END END r0_rd_out[276] PIN r0_rd_out[277] @@ -7112,7 +11720,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 21.375 165.870 21.393 165.888 ; + RECT 79.983 408.031 80.001 408.085 ; END END r0_rd_out[277] PIN r0_rd_out[278] @@ -7121,7 +11729,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 22.383 165.870 22.401 165.888 ; + RECT 80.271 408.031 80.289 408.085 ; END END r0_rd_out[278] PIN r0_rd_out[279] @@ -7130,7 +11738,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 23.391 165.870 23.409 165.888 ; + RECT 80.559 408.031 80.577 408.085 ; END END r0_rd_out[279] PIN r0_rd_out[280] @@ -7139,7 +11747,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 24.399 165.870 24.417 165.888 ; + RECT 80.847 408.031 80.865 408.085 ; END END r0_rd_out[280] PIN r0_rd_out[281] @@ -7148,7 +11756,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 25.407 165.870 25.425 165.888 ; + RECT 81.135 408.031 81.153 408.085 ; END END r0_rd_out[281] PIN r0_rd_out[282] @@ -7157,7 +11765,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 26.415 165.870 26.433 165.888 ; + RECT 81.423 408.031 81.441 408.085 ; END END r0_rd_out[282] PIN r0_rd_out[283] @@ -7166,7 +11774,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 27.423 165.870 27.441 165.888 ; + RECT 81.711 408.031 81.729 408.085 ; END END r0_rd_out[283] PIN r0_rd_out[284] @@ -7175,7 +11783,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 28.431 165.870 28.449 165.888 ; + RECT 81.999 408.031 82.017 408.085 ; END END r0_rd_out[284] PIN r0_rd_out[285] @@ -7184,7 +11792,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 29.439 165.870 29.457 165.888 ; + RECT 82.287 408.031 82.305 408.085 ; END END r0_rd_out[285] PIN r0_rd_out[286] @@ -7193,7 +11801,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 30.447 165.870 30.465 165.888 ; + RECT 82.575 408.031 82.593 408.085 ; END END r0_rd_out[286] PIN r0_rd_out[287] @@ -7202,7 +11810,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 31.455 165.870 31.473 165.888 ; + RECT 82.863 408.031 82.881 408.085 ; END END r0_rd_out[287] PIN r0_rd_out[288] @@ -7211,7 +11819,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 32.463 165.870 32.481 165.888 ; + RECT 83.151 408.031 83.169 408.085 ; END END r0_rd_out[288] PIN r0_rd_out[289] @@ -7220,7 +11828,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 33.471 165.870 33.489 165.888 ; + RECT 83.439 408.031 83.457 408.085 ; END END r0_rd_out[289] PIN r0_rd_out[290] @@ -7229,7 +11837,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 34.479 165.870 34.497 165.888 ; + RECT 83.727 408.031 83.745 408.085 ; END END r0_rd_out[290] PIN r0_rd_out[291] @@ -7238,7 +11846,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 35.487 165.870 35.505 165.888 ; + RECT 84.015 408.031 84.033 408.085 ; END END r0_rd_out[291] PIN r0_rd_out[292] @@ -7247,7 +11855,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 36.495 165.870 36.513 165.888 ; + RECT 84.303 408.031 84.321 408.085 ; END END r0_rd_out[292] PIN r0_rd_out[293] @@ -7256,7 +11864,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 37.503 165.870 37.521 165.888 ; + RECT 84.591 408.031 84.609 408.085 ; END END r0_rd_out[293] PIN r0_rd_out[294] @@ -7265,7 +11873,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 38.511 165.870 38.529 165.888 ; + RECT 84.879 408.031 84.897 408.085 ; END END r0_rd_out[294] PIN r0_rd_out[295] @@ -7274,7 +11882,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 39.519 165.870 39.537 165.888 ; + RECT 85.167 408.031 85.185 408.085 ; END END r0_rd_out[295] PIN r0_rd_out[296] @@ -7283,7 +11891,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 40.527 165.870 40.545 165.888 ; + RECT 85.455 408.031 85.473 408.085 ; END END r0_rd_out[296] PIN r0_rd_out[297] @@ -7292,7 +11900,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 41.535 165.870 41.553 165.888 ; + RECT 85.743 408.031 85.761 408.085 ; END END r0_rd_out[297] PIN r0_rd_out[298] @@ -7301,7 +11909,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 42.543 165.870 42.561 165.888 ; + RECT 86.031 408.031 86.049 408.085 ; END END r0_rd_out[298] PIN r0_rd_out[299] @@ -7310,7 +11918,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 43.551 165.870 43.569 165.888 ; + RECT 86.319 408.031 86.337 408.085 ; END END r0_rd_out[299] PIN r0_rd_out[300] @@ -7319,7 +11927,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 44.559 165.870 44.577 165.888 ; + RECT 86.607 408.031 86.625 408.085 ; END END r0_rd_out[300] PIN r0_rd_out[301] @@ -7328,7 +11936,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 45.567 165.870 45.585 165.888 ; + RECT 86.895 408.031 86.913 408.085 ; END END r0_rd_out[301] PIN r0_rd_out[302] @@ -7337,7 +11945,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 46.575 165.870 46.593 165.888 ; + RECT 87.183 408.031 87.201 408.085 ; END END r0_rd_out[302] PIN r0_rd_out[303] @@ -7346,7 +11954,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 47.583 165.870 47.601 165.888 ; + RECT 87.471 408.031 87.489 408.085 ; END END r0_rd_out[303] PIN r0_rd_out[304] @@ -7355,7 +11963,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 48.591 165.870 48.609 165.888 ; + RECT 87.759 408.031 87.777 408.085 ; END END r0_rd_out[304] PIN r0_rd_out[305] @@ -7364,7 +11972,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 49.599 165.870 49.617 165.888 ; + RECT 88.047 408.031 88.065 408.085 ; END END r0_rd_out[305] PIN r0_rd_out[306] @@ -7373,7 +11981,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 50.607 165.870 50.625 165.888 ; + RECT 88.335 408.031 88.353 408.085 ; END END r0_rd_out[306] PIN r0_rd_out[307] @@ -7382,7 +11990,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 51.615 165.870 51.633 165.888 ; + RECT 88.623 408.031 88.641 408.085 ; END END r0_rd_out[307] PIN r0_rd_out[308] @@ -7391,7 +11999,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 52.623 165.870 52.641 165.888 ; + RECT 88.911 408.031 88.929 408.085 ; END END r0_rd_out[308] PIN r0_rd_out[309] @@ -7400,7 +12008,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 53.631 165.870 53.649 165.888 ; + RECT 89.199 408.031 89.217 408.085 ; END END r0_rd_out[309] PIN r0_rd_out[310] @@ -7409,7 +12017,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 54.639 165.870 54.657 165.888 ; + RECT 89.487 408.031 89.505 408.085 ; END END r0_rd_out[310] PIN r0_rd_out[311] @@ -7418,7 +12026,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 55.647 165.870 55.665 165.888 ; + RECT 89.775 408.031 89.793 408.085 ; END END r0_rd_out[311] PIN r0_rd_out[312] @@ -7427,7 +12035,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 56.655 165.870 56.673 165.888 ; + RECT 90.063 408.031 90.081 408.085 ; END END r0_rd_out[312] PIN r0_rd_out[313] @@ -7436,7 +12044,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 57.663 165.870 57.681 165.888 ; + RECT 90.351 408.031 90.369 408.085 ; END END r0_rd_out[313] PIN r0_rd_out[314] @@ -7445,7 +12053,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 58.671 165.870 58.689 165.888 ; + RECT 90.639 408.031 90.657 408.085 ; END END r0_rd_out[314] PIN r0_rd_out[315] @@ -7454,7 +12062,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 59.679 165.870 59.697 165.888 ; + RECT 90.927 408.031 90.945 408.085 ; END END r0_rd_out[315] PIN r0_rd_out[316] @@ -7463,7 +12071,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 60.687 165.870 60.705 165.888 ; + RECT 91.215 408.031 91.233 408.085 ; END END r0_rd_out[316] PIN r0_rd_out[317] @@ -7472,7 +12080,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 61.695 165.870 61.713 165.888 ; + RECT 91.503 408.031 91.521 408.085 ; END END r0_rd_out[317] PIN r0_rd_out[318] @@ -7481,7 +12089,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 62.703 165.870 62.721 165.888 ; + RECT 91.791 408.031 91.809 408.085 ; END END r0_rd_out[318] PIN r0_rd_out[319] @@ -7490,7 +12098,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 63.711 165.870 63.729 165.888 ; + RECT 92.079 408.031 92.097 408.085 ; END END r0_rd_out[319] PIN r0_rd_out[320] @@ -7499,7 +12107,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 64.719 165.870 64.737 165.888 ; + RECT 92.367 408.031 92.385 408.085 ; END END r0_rd_out[320] PIN r0_rd_out[321] @@ -7508,7 +12116,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 65.727 165.870 65.745 165.888 ; + RECT 92.655 408.031 92.673 408.085 ; END END r0_rd_out[321] PIN r0_rd_out[322] @@ -7517,7 +12125,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 66.735 165.870 66.753 165.888 ; + RECT 92.943 408.031 92.961 408.085 ; END END r0_rd_out[322] PIN r0_rd_out[323] @@ -7526,7 +12134,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 67.743 165.870 67.761 165.888 ; + RECT 93.231 408.031 93.249 408.085 ; END END r0_rd_out[323] PIN r0_rd_out[324] @@ -7535,7 +12143,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 68.751 165.870 68.769 165.888 ; + RECT 93.519 408.031 93.537 408.085 ; END END r0_rd_out[324] PIN r0_rd_out[325] @@ -7544,7 +12152,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 69.759 165.870 69.777 165.888 ; + RECT 93.807 408.031 93.825 408.085 ; END END r0_rd_out[325] PIN r0_rd_out[326] @@ -7553,7 +12161,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 70.767 165.870 70.785 165.888 ; + RECT 94.095 408.031 94.113 408.085 ; END END r0_rd_out[326] PIN r0_rd_out[327] @@ -7562,7 +12170,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 71.775 165.870 71.793 165.888 ; + RECT 94.383 408.031 94.401 408.085 ; END END r0_rd_out[327] PIN r0_rd_out[328] @@ -7571,7 +12179,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 72.783 165.870 72.801 165.888 ; + RECT 94.671 408.031 94.689 408.085 ; END END r0_rd_out[328] PIN r0_rd_out[329] @@ -7580,7 +12188,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 73.791 165.870 73.809 165.888 ; + RECT 94.959 408.031 94.977 408.085 ; END END r0_rd_out[329] PIN r0_rd_out[330] @@ -7589,7 +12197,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 74.799 165.870 74.817 165.888 ; + RECT 95.247 408.031 95.265 408.085 ; END END r0_rd_out[330] PIN r0_rd_out[331] @@ -7598,7 +12206,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 75.807 165.870 75.825 165.888 ; + RECT 95.535 408.031 95.553 408.085 ; END END r0_rd_out[331] PIN r0_rd_out[332] @@ -7607,7 +12215,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 76.815 165.870 76.833 165.888 ; + RECT 95.823 408.031 95.841 408.085 ; END END r0_rd_out[332] PIN r0_rd_out[333] @@ -7616,7 +12224,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 77.823 165.870 77.841 165.888 ; + RECT 96.111 408.031 96.129 408.085 ; END END r0_rd_out[333] PIN r0_rd_out[334] @@ -7625,7 +12233,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 78.831 165.870 78.849 165.888 ; + RECT 96.399 408.031 96.417 408.085 ; END END r0_rd_out[334] PIN r0_rd_out[335] @@ -7634,7 +12242,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 79.839 165.870 79.857 165.888 ; + RECT 96.687 408.031 96.705 408.085 ; END END r0_rd_out[335] PIN r0_rd_out[336] @@ -7643,7 +12251,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 80.847 165.870 80.865 165.888 ; + RECT 96.975 408.031 96.993 408.085 ; END END r0_rd_out[336] PIN r0_rd_out[337] @@ -7652,7 +12260,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 81.855 165.870 81.873 165.888 ; + RECT 97.263 408.031 97.281 408.085 ; END END r0_rd_out[337] PIN r0_rd_out[338] @@ -7661,7 +12269,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 82.863 165.870 82.881 165.888 ; + RECT 97.551 408.031 97.569 408.085 ; END END r0_rd_out[338] PIN r0_rd_out[339] @@ -7670,7 +12278,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 83.871 165.870 83.889 165.888 ; + RECT 97.839 408.031 97.857 408.085 ; END END r0_rd_out[339] PIN r0_rd_out[340] @@ -7679,7 +12287,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 84.879 165.870 84.897 165.888 ; + RECT 98.127 408.031 98.145 408.085 ; END END r0_rd_out[340] PIN r0_rd_out[341] @@ -7688,7 +12296,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 85.887 165.870 85.905 165.888 ; + RECT 98.415 408.031 98.433 408.085 ; END END r0_rd_out[341] PIN r0_rd_out[342] @@ -7697,7 +12305,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 86.895 165.870 86.913 165.888 ; + RECT 98.703 408.031 98.721 408.085 ; END END r0_rd_out[342] PIN r0_rd_out[343] @@ -7706,7 +12314,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 87.903 165.870 87.921 165.888 ; + RECT 98.991 408.031 99.009 408.085 ; END END r0_rd_out[343] PIN r0_rd_out[344] @@ -7715,7 +12323,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 88.911 165.870 88.929 165.888 ; + RECT 99.279 408.031 99.297 408.085 ; END END r0_rd_out[344] PIN r0_rd_out[345] @@ -7724,7 +12332,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 89.919 165.870 89.937 165.888 ; + RECT 99.567 408.031 99.585 408.085 ; END END r0_rd_out[345] PIN r0_rd_out[346] @@ -7733,7 +12341,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 90.927 165.870 90.945 165.888 ; + RECT 99.855 408.031 99.873 408.085 ; END END r0_rd_out[346] PIN r0_rd_out[347] @@ -7742,7 +12350,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 91.935 165.870 91.953 165.888 ; + RECT 100.143 408.031 100.161 408.085 ; END END r0_rd_out[347] PIN r0_rd_out[348] @@ -7751,7 +12359,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 92.943 165.870 92.961 165.888 ; + RECT 100.431 408.031 100.449 408.085 ; END END r0_rd_out[348] PIN r0_rd_out[349] @@ -7760,7 +12368,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 93.951 165.870 93.969 165.888 ; + RECT 100.719 408.031 100.737 408.085 ; END END r0_rd_out[349] PIN r0_rd_out[350] @@ -7769,7 +12377,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 94.959 165.870 94.977 165.888 ; + RECT 101.007 408.031 101.025 408.085 ; END END r0_rd_out[350] PIN r0_rd_out[351] @@ -7778,7 +12386,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 95.967 165.870 95.985 165.888 ; + RECT 101.295 408.031 101.313 408.085 ; END END r0_rd_out[351] PIN r0_rd_out[352] @@ -7787,7 +12395,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 96.975 165.870 96.993 165.888 ; + RECT 101.583 408.031 101.601 408.085 ; END END r0_rd_out[352] PIN r0_rd_out[353] @@ -7796,7 +12404,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 97.983 165.870 98.001 165.888 ; + RECT 101.871 408.031 101.889 408.085 ; END END r0_rd_out[353] PIN r0_rd_out[354] @@ -7805,7 +12413,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 98.991 165.870 99.009 165.888 ; + RECT 102.159 408.031 102.177 408.085 ; END END r0_rd_out[354] PIN r0_rd_out[355] @@ -7814,7 +12422,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 99.999 165.870 100.017 165.888 ; + RECT 102.447 408.031 102.465 408.085 ; END END r0_rd_out[355] PIN r0_rd_out[356] @@ -7823,7 +12431,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 101.007 165.870 101.025 165.888 ; + RECT 102.735 408.031 102.753 408.085 ; END END r0_rd_out[356] PIN r0_rd_out[357] @@ -7832,7 +12440,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 102.015 165.870 102.033 165.888 ; + RECT 103.023 408.031 103.041 408.085 ; END END r0_rd_out[357] PIN r0_rd_out[358] @@ -7841,7 +12449,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 103.023 165.870 103.041 165.888 ; + RECT 103.311 408.031 103.329 408.085 ; END END r0_rd_out[358] PIN r0_rd_out[359] @@ -7850,7 +12458,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 104.031 165.870 104.049 165.888 ; + RECT 103.599 408.031 103.617 408.085 ; END END r0_rd_out[359] PIN r0_rd_out[360] @@ -7859,7 +12467,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 105.039 165.870 105.057 165.888 ; + RECT 103.887 408.031 103.905 408.085 ; END END r0_rd_out[360] PIN r0_rd_out[361] @@ -7868,7 +12476,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 106.047 165.870 106.065 165.888 ; + RECT 104.175 408.031 104.193 408.085 ; END END r0_rd_out[361] PIN r0_rd_out[362] @@ -7877,7 +12485,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 107.055 165.870 107.073 165.888 ; + RECT 104.463 408.031 104.481 408.085 ; END END r0_rd_out[362] PIN r0_rd_out[363] @@ -7886,7 +12494,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 108.063 165.870 108.081 165.888 ; + RECT 104.751 408.031 104.769 408.085 ; END END r0_rd_out[363] PIN r0_rd_out[364] @@ -7895,7 +12503,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 109.071 165.870 109.089 165.888 ; + RECT 105.039 408.031 105.057 408.085 ; END END r0_rd_out[364] PIN r0_rd_out[365] @@ -7904,7 +12512,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 110.079 165.870 110.097 165.888 ; + RECT 105.327 408.031 105.345 408.085 ; END END r0_rd_out[365] PIN r0_rd_out[366] @@ -7913,7 +12521,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 111.087 165.870 111.105 165.888 ; + RECT 105.615 408.031 105.633 408.085 ; END END r0_rd_out[366] PIN r0_rd_out[367] @@ -7922,7 +12530,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 112.095 165.870 112.113 165.888 ; + RECT 105.903 408.031 105.921 408.085 ; END END r0_rd_out[367] PIN r0_rd_out[368] @@ -7931,7 +12539,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 113.103 165.870 113.121 165.888 ; + RECT 106.191 408.031 106.209 408.085 ; END END r0_rd_out[368] PIN r0_rd_out[369] @@ -7940,7 +12548,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 114.111 165.870 114.129 165.888 ; + RECT 106.479 408.031 106.497 408.085 ; END END r0_rd_out[369] PIN r0_rd_out[370] @@ -7949,7 +12557,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 115.119 165.870 115.137 165.888 ; + RECT 106.767 408.031 106.785 408.085 ; END END r0_rd_out[370] PIN r0_rd_out[371] @@ -7958,7 +12566,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 116.127 165.870 116.145 165.888 ; + RECT 107.055 408.031 107.073 408.085 ; END END r0_rd_out[371] PIN r0_rd_out[372] @@ -7967,7 +12575,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 117.135 165.870 117.153 165.888 ; + RECT 107.343 408.031 107.361 408.085 ; END END r0_rd_out[372] PIN r0_rd_out[373] @@ -7976,7 +12584,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 118.143 165.870 118.161 165.888 ; + RECT 107.631 408.031 107.649 408.085 ; END END r0_rd_out[373] PIN r0_rd_out[374] @@ -7985,7 +12593,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 119.151 165.870 119.169 165.888 ; + RECT 107.919 408.031 107.937 408.085 ; END END r0_rd_out[374] PIN r0_rd_out[375] @@ -7994,7 +12602,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 120.159 165.870 120.177 165.888 ; + RECT 108.207 408.031 108.225 408.085 ; END END r0_rd_out[375] PIN r0_rd_out[376] @@ -8003,7 +12611,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 121.167 165.870 121.185 165.888 ; + RECT 108.495 408.031 108.513 408.085 ; END END r0_rd_out[376] PIN r0_rd_out[377] @@ -8012,7 +12620,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 122.175 165.870 122.193 165.888 ; + RECT 108.783 408.031 108.801 408.085 ; END END r0_rd_out[377] PIN r0_rd_out[378] @@ -8021,7 +12629,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 123.183 165.870 123.201 165.888 ; + RECT 109.071 408.031 109.089 408.085 ; END END r0_rd_out[378] PIN r0_rd_out[379] @@ -8030,7 +12638,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 124.191 165.870 124.209 165.888 ; + RECT 109.359 408.031 109.377 408.085 ; END END r0_rd_out[379] PIN r0_rd_out[380] @@ -8039,7 +12647,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 125.199 165.870 125.217 165.888 ; + RECT 109.647 408.031 109.665 408.085 ; END END r0_rd_out[380] PIN r0_rd_out[381] @@ -8048,7 +12656,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 126.207 165.870 126.225 165.888 ; + RECT 109.935 408.031 109.953 408.085 ; END END r0_rd_out[381] PIN r0_rd_out[382] @@ -8057,7 +12665,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 127.215 165.870 127.233 165.888 ; + RECT 110.223 408.031 110.241 408.085 ; END END r0_rd_out[382] PIN r0_rd_out[383] @@ -8066,7 +12674,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 128.223 165.870 128.241 165.888 ; + RECT 110.511 408.031 110.529 408.085 ; END END r0_rd_out[383] PIN r0_rd_out[384] @@ -8075,7 +12683,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 129.231 165.870 129.249 165.888 ; + RECT 110.799 408.031 110.817 408.085 ; END END r0_rd_out[384] PIN r0_rd_out[385] @@ -8084,7 +12692,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 130.239 165.870 130.257 165.888 ; + RECT 111.087 408.031 111.105 408.085 ; END END r0_rd_out[385] PIN r0_rd_out[386] @@ -8093,7 +12701,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 131.247 165.870 131.265 165.888 ; + RECT 111.375 408.031 111.393 408.085 ; END END r0_rd_out[386] PIN r0_rd_out[387] @@ -8102,7 +12710,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 132.255 165.870 132.273 165.888 ; + RECT 111.663 408.031 111.681 408.085 ; END END r0_rd_out[387] PIN r0_rd_out[388] @@ -8111,7 +12719,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 133.263 165.870 133.281 165.888 ; + RECT 111.951 408.031 111.969 408.085 ; END END r0_rd_out[388] PIN r0_rd_out[389] @@ -8120,7 +12728,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 134.271 165.870 134.289 165.888 ; + RECT 112.239 408.031 112.257 408.085 ; END END r0_rd_out[389] PIN r0_rd_out[390] @@ -8129,7 +12737,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 135.279 165.870 135.297 165.888 ; + RECT 112.527 408.031 112.545 408.085 ; END END r0_rd_out[390] PIN r0_rd_out[391] @@ -8138,7 +12746,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 136.287 165.870 136.305 165.888 ; + RECT 112.815 408.031 112.833 408.085 ; END END r0_rd_out[391] PIN r0_rd_out[392] @@ -8147,7 +12755,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 137.295 165.870 137.313 165.888 ; + RECT 113.103 408.031 113.121 408.085 ; END END r0_rd_out[392] PIN r0_rd_out[393] @@ -8156,7 +12764,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 138.303 165.870 138.321 165.888 ; + RECT 113.391 408.031 113.409 408.085 ; END END r0_rd_out[393] PIN r0_rd_out[394] @@ -8165,7 +12773,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 139.311 165.870 139.329 165.888 ; + RECT 113.679 408.031 113.697 408.085 ; END END r0_rd_out[394] PIN r0_rd_out[395] @@ -8174,7 +12782,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 140.319 165.870 140.337 165.888 ; + RECT 113.967 408.031 113.985 408.085 ; END END r0_rd_out[395] PIN r0_rd_out[396] @@ -8183,7 +12791,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 141.327 165.870 141.345 165.888 ; + RECT 114.255 408.031 114.273 408.085 ; END END r0_rd_out[396] PIN r0_rd_out[397] @@ -8192,7 +12800,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 142.335 165.870 142.353 165.888 ; + RECT 114.543 408.031 114.561 408.085 ; END END r0_rd_out[397] PIN r0_rd_out[398] @@ -8201,7 +12809,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 143.343 165.870 143.361 165.888 ; + RECT 114.831 408.031 114.849 408.085 ; END END r0_rd_out[398] PIN r0_rd_out[399] @@ -8210,7 +12818,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 144.351 165.870 144.369 165.888 ; + RECT 115.119 408.031 115.137 408.085 ; END END r0_rd_out[399] PIN r0_rd_out[400] @@ -8219,7 +12827,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 145.359 165.870 145.377 165.888 ; + RECT 115.407 408.031 115.425 408.085 ; END END r0_rd_out[400] PIN r0_rd_out[401] @@ -8228,7 +12836,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 146.367 165.870 146.385 165.888 ; + RECT 115.695 408.031 115.713 408.085 ; END END r0_rd_out[401] PIN r0_rd_out[402] @@ -8237,7 +12845,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 147.375 165.870 147.393 165.888 ; + RECT 115.983 408.031 116.001 408.085 ; END END r0_rd_out[402] PIN r0_rd_out[403] @@ -8246,7 +12854,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 148.383 165.870 148.401 165.888 ; + RECT 116.271 408.031 116.289 408.085 ; END END r0_rd_out[403] PIN r0_rd_out[404] @@ -8255,7 +12863,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 149.391 165.870 149.409 165.888 ; + RECT 116.559 408.031 116.577 408.085 ; END END r0_rd_out[404] PIN r0_rd_out[405] @@ -8264,7 +12872,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 150.399 165.870 150.417 165.888 ; + RECT 116.847 408.031 116.865 408.085 ; END END r0_rd_out[405] PIN r0_rd_out[406] @@ -8273,7 +12881,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 151.407 165.870 151.425 165.888 ; + RECT 117.135 408.031 117.153 408.085 ; END END r0_rd_out[406] PIN r0_rd_out[407] @@ -8282,7 +12890,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 152.415 165.870 152.433 165.888 ; + RECT 117.423 408.031 117.441 408.085 ; END END r0_rd_out[407] PIN r0_rd_out[408] @@ -8291,7 +12899,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 153.423 165.870 153.441 165.888 ; + RECT 117.711 408.031 117.729 408.085 ; END END r0_rd_out[408] PIN r0_rd_out[409] @@ -8300,7 +12908,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 154.431 165.870 154.449 165.888 ; + RECT 117.999 408.031 118.017 408.085 ; END END r0_rd_out[409] PIN r0_rd_out[410] @@ -8309,7 +12917,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 155.439 165.870 155.457 165.888 ; + RECT 118.287 408.031 118.305 408.085 ; END END r0_rd_out[410] PIN r0_rd_out[411] @@ -8318,7 +12926,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 156.447 165.870 156.465 165.888 ; + RECT 118.575 408.031 118.593 408.085 ; END END r0_rd_out[411] PIN r0_rd_out[412] @@ -8327,7 +12935,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 157.455 165.870 157.473 165.888 ; + RECT 118.863 408.031 118.881 408.085 ; END END r0_rd_out[412] PIN r0_rd_out[413] @@ -8336,7 +12944,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 158.463 165.870 158.481 165.888 ; + RECT 119.151 408.031 119.169 408.085 ; END END r0_rd_out[413] PIN r0_rd_out[414] @@ -8345,7 +12953,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 159.471 165.870 159.489 165.888 ; + RECT 119.439 408.031 119.457 408.085 ; END END r0_rd_out[414] PIN r0_rd_out[415] @@ -8354,7 +12962,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 160.479 165.870 160.497 165.888 ; + RECT 119.727 408.031 119.745 408.085 ; END END r0_rd_out[415] PIN r0_rd_out[416] @@ -8363,7 +12971,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 161.487 165.870 161.505 165.888 ; + RECT 120.015 408.031 120.033 408.085 ; END END r0_rd_out[416] PIN r0_rd_out[417] @@ -8372,7 +12980,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 162.495 165.870 162.513 165.888 ; + RECT 120.303 408.031 120.321 408.085 ; END END r0_rd_out[417] PIN r0_rd_out[418] @@ -8381,7 +12989,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 163.503 165.870 163.521 165.888 ; + RECT 120.591 408.031 120.609 408.085 ; END END r0_rd_out[418] PIN r0_rd_out[419] @@ -8390,7 +12998,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 164.511 165.870 164.529 165.888 ; + RECT 120.879 408.031 120.897 408.085 ; END END r0_rd_out[419] PIN r0_rd_out[420] @@ -8399,7 +13007,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 165.519 165.870 165.537 165.888 ; + RECT 121.167 408.031 121.185 408.085 ; END END r0_rd_out[420] PIN r0_rd_out[421] @@ -8408,7 +13016,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 166.527 165.870 166.545 165.888 ; + RECT 121.455 408.031 121.473 408.085 ; END END r0_rd_out[421] PIN r0_rd_out[422] @@ -8417,7 +13025,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 167.535 165.870 167.553 165.888 ; + RECT 121.743 408.031 121.761 408.085 ; END END r0_rd_out[422] PIN r0_rd_out[423] @@ -8426,7 +13034,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 168.543 165.870 168.561 165.888 ; + RECT 122.031 408.031 122.049 408.085 ; END END r0_rd_out[423] PIN r0_rd_out[424] @@ -8435,7 +13043,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 169.551 165.870 169.569 165.888 ; + RECT 122.319 408.031 122.337 408.085 ; END END r0_rd_out[424] PIN r0_rd_out[425] @@ -8444,7 +13052,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 170.559 165.870 170.577 165.888 ; + RECT 122.607 408.031 122.625 408.085 ; END END r0_rd_out[425] PIN r0_rd_out[426] @@ -8453,7 +13061,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 171.567 165.870 171.585 165.888 ; + RECT 122.895 408.031 122.913 408.085 ; END END r0_rd_out[426] PIN r0_rd_out[427] @@ -8462,7 +13070,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 172.575 165.870 172.593 165.888 ; + RECT 123.183 408.031 123.201 408.085 ; END END r0_rd_out[427] PIN r0_rd_out[428] @@ -8471,7 +13079,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 173.583 165.870 173.601 165.888 ; + RECT 123.471 408.031 123.489 408.085 ; END END r0_rd_out[428] PIN r0_rd_out[429] @@ -8480,7 +13088,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 174.591 165.870 174.609 165.888 ; + RECT 123.759 408.031 123.777 408.085 ; END END r0_rd_out[429] PIN r0_rd_out[430] @@ -8489,7 +13097,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 175.599 165.870 175.617 165.888 ; + RECT 124.047 408.031 124.065 408.085 ; END END r0_rd_out[430] PIN r0_rd_out[431] @@ -8498,7 +13106,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 176.607 165.870 176.625 165.888 ; + RECT 124.335 408.031 124.353 408.085 ; END END r0_rd_out[431] PIN r0_rd_out[432] @@ -8507,7 +13115,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 177.615 165.870 177.633 165.888 ; + RECT 124.623 408.031 124.641 408.085 ; END END r0_rd_out[432] PIN r0_rd_out[433] @@ -8516,7 +13124,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 178.623 165.870 178.641 165.888 ; + RECT 124.911 408.031 124.929 408.085 ; END END r0_rd_out[433] PIN r0_rd_out[434] @@ -8525,7 +13133,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 179.631 165.870 179.649 165.888 ; + RECT 125.199 408.031 125.217 408.085 ; END END r0_rd_out[434] PIN r0_rd_out[435] @@ -8534,7 +13142,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 180.639 165.870 180.657 165.888 ; + RECT 125.487 408.031 125.505 408.085 ; END END r0_rd_out[435] PIN r0_rd_out[436] @@ -8543,7 +13151,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 181.647 165.870 181.665 165.888 ; + RECT 125.775 408.031 125.793 408.085 ; END END r0_rd_out[436] PIN r0_rd_out[437] @@ -8552,7 +13160,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 182.655 165.870 182.673 165.888 ; + RECT 126.063 408.031 126.081 408.085 ; END END r0_rd_out[437] PIN r0_rd_out[438] @@ -8561,7 +13169,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 183.663 165.870 183.681 165.888 ; + RECT 126.351 408.031 126.369 408.085 ; END END r0_rd_out[438] PIN r0_rd_out[439] @@ -8570,7 +13178,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 184.671 165.870 184.689 165.888 ; + RECT 126.639 408.031 126.657 408.085 ; END END r0_rd_out[439] PIN r0_rd_out[440] @@ -8579,7 +13187,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 185.679 165.870 185.697 165.888 ; + RECT 126.927 408.031 126.945 408.085 ; END END r0_rd_out[440] PIN r0_rd_out[441] @@ -8588,7 +13196,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 186.687 165.870 186.705 165.888 ; + RECT 127.215 408.031 127.233 408.085 ; END END r0_rd_out[441] PIN r0_rd_out[442] @@ -8597,7 +13205,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 187.695 165.870 187.713 165.888 ; + RECT 127.503 408.031 127.521 408.085 ; END END r0_rd_out[442] PIN r0_rd_out[443] @@ -8606,7 +13214,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 188.703 165.870 188.721 165.888 ; + RECT 127.791 408.031 127.809 408.085 ; END END r0_rd_out[443] PIN r0_rd_out[444] @@ -8615,7 +13223,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 189.711 165.870 189.729 165.888 ; + RECT 128.079 408.031 128.097 408.085 ; END END r0_rd_out[444] PIN r0_rd_out[445] @@ -8624,7 +13232,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 190.719 165.870 190.737 165.888 ; + RECT 128.367 408.031 128.385 408.085 ; END END r0_rd_out[445] PIN r0_rd_out[446] @@ -8633,7 +13241,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 191.727 165.870 191.745 165.888 ; + RECT 128.655 408.031 128.673 408.085 ; END END r0_rd_out[446] PIN r0_rd_out[447] @@ -8642,7 +13250,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 192.735 165.870 192.753 165.888 ; + RECT 128.943 408.031 128.961 408.085 ; END END r0_rd_out[447] PIN r0_rd_out[448] @@ -8651,7 +13259,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 193.743 165.870 193.761 165.888 ; + RECT 129.231 408.031 129.249 408.085 ; END END r0_rd_out[448] PIN r0_rd_out[449] @@ -8660,7 +13268,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 194.751 165.870 194.769 165.888 ; + RECT 129.519 408.031 129.537 408.085 ; END END r0_rd_out[449] PIN r0_rd_out[450] @@ -8669,7 +13277,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 195.759 165.870 195.777 165.888 ; + RECT 129.807 408.031 129.825 408.085 ; END END r0_rd_out[450] PIN r0_rd_out[451] @@ -8678,7 +13286,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 196.767 165.870 196.785 165.888 ; + RECT 130.095 408.031 130.113 408.085 ; END END r0_rd_out[451] PIN r0_rd_out[452] @@ -8687,7 +13295,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 197.775 165.870 197.793 165.888 ; + RECT 130.383 408.031 130.401 408.085 ; END END r0_rd_out[452] PIN r0_rd_out[453] @@ -8696,7 +13304,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 198.783 165.870 198.801 165.888 ; + RECT 130.671 408.031 130.689 408.085 ; END END r0_rd_out[453] PIN r0_rd_out[454] @@ -8705,7 +13313,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 199.791 165.870 199.809 165.888 ; + RECT 130.959 408.031 130.977 408.085 ; END END r0_rd_out[454] PIN r0_rd_out[455] @@ -8714,7 +13322,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 200.799 165.870 200.817 165.888 ; + RECT 131.247 408.031 131.265 408.085 ; END END r0_rd_out[455] PIN r0_rd_out[456] @@ -8723,7 +13331,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 201.807 165.870 201.825 165.888 ; + RECT 131.535 408.031 131.553 408.085 ; END END r0_rd_out[456] PIN r0_rd_out[457] @@ -8732,7 +13340,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 202.815 165.870 202.833 165.888 ; + RECT 131.823 408.031 131.841 408.085 ; END END r0_rd_out[457] PIN r0_rd_out[458] @@ -8741,7 +13349,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 203.823 165.870 203.841 165.888 ; + RECT 132.111 408.031 132.129 408.085 ; END END r0_rd_out[458] PIN r0_rd_out[459] @@ -8750,7 +13358,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 204.831 165.870 204.849 165.888 ; + RECT 132.399 408.031 132.417 408.085 ; END END r0_rd_out[459] PIN r0_rd_out[460] @@ -8759,7 +13367,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 205.839 165.870 205.857 165.888 ; + RECT 132.687 408.031 132.705 408.085 ; END END r0_rd_out[460] PIN r0_rd_out[461] @@ -8768,7 +13376,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 206.847 165.870 206.865 165.888 ; + RECT 132.975 408.031 132.993 408.085 ; END END r0_rd_out[461] PIN r0_rd_out[462] @@ -8777,7 +13385,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 207.855 165.870 207.873 165.888 ; + RECT 133.263 408.031 133.281 408.085 ; END END r0_rd_out[462] PIN r0_rd_out[463] @@ -8786,7 +13394,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 208.863 165.870 208.881 165.888 ; + RECT 133.551 408.031 133.569 408.085 ; END END r0_rd_out[463] PIN r0_rd_out[464] @@ -8795,7 +13403,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 209.871 165.870 209.889 165.888 ; + RECT 133.839 408.031 133.857 408.085 ; END END r0_rd_out[464] PIN r0_rd_out[465] @@ -8804,7 +13412,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 210.879 165.870 210.897 165.888 ; + RECT 134.127 408.031 134.145 408.085 ; END END r0_rd_out[465] PIN r0_rd_out[466] @@ -8813,7 +13421,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 211.887 165.870 211.905 165.888 ; + RECT 134.415 408.031 134.433 408.085 ; END END r0_rd_out[466] PIN r0_rd_out[467] @@ -8822,7 +13430,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 212.895 165.870 212.913 165.888 ; + RECT 134.703 408.031 134.721 408.085 ; END END r0_rd_out[467] PIN r0_rd_out[468] @@ -8831,7 +13439,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 213.903 165.870 213.921 165.888 ; + RECT 134.991 408.031 135.009 408.085 ; END END r0_rd_out[468] PIN r0_rd_out[469] @@ -8840,7 +13448,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 214.911 165.870 214.929 165.888 ; + RECT 135.279 408.031 135.297 408.085 ; END END r0_rd_out[469] PIN r0_rd_out[470] @@ -8849,7 +13457,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 215.919 165.870 215.937 165.888 ; + RECT 135.567 408.031 135.585 408.085 ; END END r0_rd_out[470] PIN r0_rd_out[471] @@ -8858,7 +13466,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 216.927 165.870 216.945 165.888 ; + RECT 135.855 408.031 135.873 408.085 ; END END r0_rd_out[471] PIN r0_rd_out[472] @@ -8867,7 +13475,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 217.935 165.870 217.953 165.888 ; + RECT 136.143 408.031 136.161 408.085 ; END END r0_rd_out[472] PIN r0_rd_out[473] @@ -8876,7 +13484,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 218.943 165.870 218.961 165.888 ; + RECT 136.431 408.031 136.449 408.085 ; END END r0_rd_out[473] PIN r0_rd_out[474] @@ -8885,7 +13493,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 219.951 165.870 219.969 165.888 ; + RECT 136.719 408.031 136.737 408.085 ; END END r0_rd_out[474] PIN r0_rd_out[475] @@ -8894,7 +13502,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 220.959 165.870 220.977 165.888 ; + RECT 137.007 408.031 137.025 408.085 ; END END r0_rd_out[475] PIN r0_rd_out[476] @@ -8903,7 +13511,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 221.967 165.870 221.985 165.888 ; + RECT 137.295 408.031 137.313 408.085 ; END END r0_rd_out[476] PIN r0_rd_out[477] @@ -8912,7 +13520,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 222.975 165.870 222.993 165.888 ; + RECT 137.583 408.031 137.601 408.085 ; END END r0_rd_out[477] PIN r0_rd_out[478] @@ -8921,7 +13529,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 223.983 165.870 224.001 165.888 ; + RECT 137.871 408.031 137.889 408.085 ; END END r0_rd_out[478] PIN r0_rd_out[479] @@ -8930,7 +13538,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 224.991 165.870 225.009 165.888 ; + RECT 138.159 408.031 138.177 408.085 ; END END r0_rd_out[479] PIN r0_rd_out[480] @@ -8939,7 +13547,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 225.999 165.870 226.017 165.888 ; + RECT 138.447 408.031 138.465 408.085 ; END END r0_rd_out[480] PIN r0_rd_out[481] @@ -8948,7 +13556,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 227.007 165.870 227.025 165.888 ; + RECT 138.735 408.031 138.753 408.085 ; END END r0_rd_out[481] PIN r0_rd_out[482] @@ -8957,7 +13565,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 228.015 165.870 228.033 165.888 ; + RECT 139.023 408.031 139.041 408.085 ; END END r0_rd_out[482] PIN r0_rd_out[483] @@ -8966,7 +13574,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 229.023 165.870 229.041 165.888 ; + RECT 139.311 408.031 139.329 408.085 ; END END r0_rd_out[483] PIN r0_rd_out[484] @@ -8975,7 +13583,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 230.031 165.870 230.049 165.888 ; + RECT 139.599 408.031 139.617 408.085 ; END END r0_rd_out[484] PIN r0_rd_out[485] @@ -8984,7 +13592,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 231.039 165.870 231.057 165.888 ; + RECT 139.887 408.031 139.905 408.085 ; END END r0_rd_out[485] PIN r0_rd_out[486] @@ -8993,7 +13601,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 232.047 165.870 232.065 165.888 ; + RECT 140.175 408.031 140.193 408.085 ; END END r0_rd_out[486] PIN r0_rd_out[487] @@ -9002,7 +13610,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 233.055 165.870 233.073 165.888 ; + RECT 140.463 408.031 140.481 408.085 ; END END r0_rd_out[487] PIN r0_rd_out[488] @@ -9011,7 +13619,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 234.063 165.870 234.081 165.888 ; + RECT 140.751 408.031 140.769 408.085 ; END END r0_rd_out[488] PIN r0_rd_out[489] @@ -9020,7 +13628,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 235.071 165.870 235.089 165.888 ; + RECT 141.039 408.031 141.057 408.085 ; END END r0_rd_out[489] PIN r0_rd_out[490] @@ -9029,7 +13637,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 236.079 165.870 236.097 165.888 ; + RECT 141.327 408.031 141.345 408.085 ; END END r0_rd_out[490] PIN r0_rd_out[491] @@ -9038,7 +13646,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 237.087 165.870 237.105 165.888 ; + RECT 141.615 408.031 141.633 408.085 ; END END r0_rd_out[491] PIN r0_rd_out[492] @@ -9047,7 +13655,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 238.095 165.870 238.113 165.888 ; + RECT 141.903 408.031 141.921 408.085 ; END END r0_rd_out[492] PIN r0_rd_out[493] @@ -9056,7 +13664,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 239.103 165.870 239.121 165.888 ; + RECT 142.191 408.031 142.209 408.085 ; END END r0_rd_out[493] PIN r0_rd_out[494] @@ -9065,7 +13673,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 240.111 165.870 240.129 165.888 ; + RECT 142.479 408.031 142.497 408.085 ; END END r0_rd_out[494] PIN r0_rd_out[495] @@ -9074,7 +13682,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 241.119 165.870 241.137 165.888 ; + RECT 142.767 408.031 142.785 408.085 ; END END r0_rd_out[495] PIN r0_rd_out[496] @@ -9083,7 +13691,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 242.127 165.870 242.145 165.888 ; + RECT 143.055 408.031 143.073 408.085 ; END END r0_rd_out[496] PIN r0_rd_out[497] @@ -9092,7 +13700,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 243.135 165.870 243.153 165.888 ; + RECT 143.343 408.031 143.361 408.085 ; END END r0_rd_out[497] PIN r0_rd_out[498] @@ -9101,7 +13709,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 244.143 165.870 244.161 165.888 ; + RECT 143.631 408.031 143.649 408.085 ; END END r0_rd_out[498] PIN r0_rd_out[499] @@ -9110,7 +13718,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 245.151 165.870 245.169 165.888 ; + RECT 143.919 408.031 143.937 408.085 ; END END r0_rd_out[499] PIN r0_rd_out[500] @@ -9119,7 +13727,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 246.159 165.870 246.177 165.888 ; + RECT 144.207 408.031 144.225 408.085 ; END END r0_rd_out[500] PIN r0_rd_out[501] @@ -9128,7 +13736,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 247.167 165.870 247.185 165.888 ; + RECT 144.495 408.031 144.513 408.085 ; END END r0_rd_out[501] PIN r0_rd_out[502] @@ -9137,7 +13745,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 248.175 165.870 248.193 165.888 ; + RECT 144.783 408.031 144.801 408.085 ; END END r0_rd_out[502] PIN r0_rd_out[503] @@ -9146,7 +13754,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 249.183 165.870 249.201 165.888 ; + RECT 145.071 408.031 145.089 408.085 ; END END r0_rd_out[503] PIN r0_rd_out[504] @@ -9155,7 +13763,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 250.191 165.870 250.209 165.888 ; + RECT 145.359 408.031 145.377 408.085 ; END END r0_rd_out[504] PIN r0_rd_out[505] @@ -9164,7 +13772,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 251.199 165.870 251.217 165.888 ; + RECT 145.647 408.031 145.665 408.085 ; END END r0_rd_out[505] PIN r0_rd_out[506] @@ -9173,7 +13781,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 252.207 165.870 252.225 165.888 ; + RECT 145.935 408.031 145.953 408.085 ; END END r0_rd_out[506] PIN r0_rd_out[507] @@ -9182,7 +13790,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 253.215 165.870 253.233 165.888 ; + RECT 146.223 408.031 146.241 408.085 ; END END r0_rd_out[507] PIN r0_rd_out[508] @@ -9191,7 +13799,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 254.223 165.870 254.241 165.888 ; + RECT 146.511 408.031 146.529 408.085 ; END END r0_rd_out[508] PIN r0_rd_out[509] @@ -9200,7 +13808,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 255.231 165.870 255.249 165.888 ; + RECT 146.799 408.031 146.817 408.085 ; END END r0_rd_out[509] PIN r0_rd_out[510] @@ -9209,7 +13817,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 256.239 165.870 256.257 165.888 ; + RECT 147.087 408.031 147.105 408.085 ; END END r0_rd_out[510] PIN r0_rd_out[511] @@ -9218,7 +13826,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 257.247 165.870 257.265 165.888 ; + RECT 147.375 408.031 147.393 408.085 ; END END r0_rd_out[511] PIN w0_addr_in[0] @@ -9227,7 +13835,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 147.732 0.024 147.756 ; + RECT 0.000 381.204 0.072 381.228 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -9236,7 +13844,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 148.884 0.024 148.908 ; + RECT 0.000 382.692 0.072 382.716 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -9245,7 +13853,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 150.036 0.024 150.060 ; + RECT 0.000 384.180 0.072 384.204 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -9254,7 +13862,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 151.188 0.024 151.212 ; + RECT 0.000 385.668 0.072 385.692 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -9263,7 +13871,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 152.340 0.024 152.364 ; + RECT 0.000 387.156 0.072 387.180 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -9272,7 +13880,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 153.492 0.024 153.516 ; + RECT 0.000 388.644 0.072 388.668 ; END END w0_addr_in[5] PIN w0_addr_in[6] @@ -9281,7 +13889,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 147.732 265.421 147.756 ; + RECT 163.162 381.204 163.234 381.228 ; END END w0_addr_in[6] PIN w0_addr_in[7] @@ -9290,7 +13898,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 148.884 265.421 148.908 ; + RECT 163.162 382.692 163.234 382.716 ; END END w0_addr_in[7] PIN w0_addr_in[8] @@ -9299,7 +13907,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 150.036 265.421 150.060 ; + RECT 163.162 384.180 163.234 384.204 ; END END w0_addr_in[8] PIN w0_addr_in[9] @@ -9308,7 +13916,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 151.188 265.421 151.212 ; + RECT 163.162 385.668 163.234 385.692 ; END END w0_addr_in[9] PIN w0_addr_in[10] @@ -9317,7 +13925,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 152.340 265.421 152.364 ; + RECT 163.162 387.156 163.234 387.180 ; END END w0_addr_in[10] PIN r0_addr_in[0] @@ -9326,7 +13934,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 154.644 0.024 154.668 ; + RECT 0.000 390.132 0.072 390.156 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -9335,7 +13943,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 155.796 0.024 155.820 ; + RECT 0.000 391.620 0.072 391.644 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -9344,7 +13952,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 156.948 0.024 156.972 ; + RECT 0.000 393.108 0.072 393.132 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -9353,7 +13961,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 158.100 0.024 158.124 ; + RECT 0.000 394.596 0.072 394.620 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -9362,7 +13970,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 159.252 0.024 159.276 ; + RECT 0.000 396.084 0.072 396.108 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -9371,7 +13979,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 160.404 0.024 160.428 ; + RECT 0.000 397.572 0.072 397.596 ; END END r0_addr_in[5] PIN r0_addr_in[6] @@ -9380,7 +13988,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 153.492 265.421 153.516 ; + RECT 163.162 388.644 163.234 388.668 ; END END r0_addr_in[6] PIN r0_addr_in[7] @@ -9389,7 +13997,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 154.644 265.421 154.668 ; + RECT 163.162 390.132 163.234 390.156 ; END END r0_addr_in[7] PIN r0_addr_in[8] @@ -9398,7 +14006,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 155.796 265.421 155.820 ; + RECT 163.162 391.620 163.234 391.644 ; END END r0_addr_in[8] PIN r0_addr_in[9] @@ -9407,7 +14015,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 156.948 265.421 156.972 ; + RECT 163.162 393.108 163.234 393.132 ; END END r0_addr_in[9] PIN r0_addr_in[10] @@ -9416,7 +14024,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 158.100 265.421 158.124 ; + RECT 163.162 394.596 163.234 394.620 ; END END r0_addr_in[10] PIN w0_we_in @@ -9425,7 +14033,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 258.255 165.870 258.273 165.888 ; + RECT 147.663 408.031 147.681 408.085 ; END END w0_we_in PIN w0_ce_in @@ -9434,7 +14042,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 259.263 165.870 259.281 165.888 ; + RECT 147.951 408.031 147.969 408.085 ; END END w0_ce_in PIN w0_clk @@ -9443,7 +14051,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 260.271 165.870 260.289 165.888 ; + RECT 148.239 408.031 148.257 408.085 ; END END w0_clk PIN r0_ce_in @@ -9452,7 +14060,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 261.279 165.870 261.297 165.888 ; + RECT 148.527 408.031 148.545 408.085 ; END END r0_ce_in PIN r0_clk @@ -9461,7 +14069,7 @@ MACRO fakeram_512x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 262.287 165.870 262.305 165.888 ; + RECT 148.815 408.031 148.833 408.085 ; END END r0_clk PIN VSS @@ -9469,222 +14077,537 @@ MACRO fakeram_512x2048_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.108 0.192 265.313 0.288 ; - RECT 0.108 0.960 265.313 1.056 ; - RECT 0.108 1.728 265.313 1.824 ; - RECT 0.108 2.496 265.313 2.592 ; - RECT 0.108 3.264 265.313 3.360 ; - RECT 0.108 4.032 265.313 4.128 ; - RECT 0.108 4.800 265.313 4.896 ; - RECT 0.108 5.568 265.313 5.664 ; - RECT 0.108 6.336 265.313 6.432 ; - RECT 0.108 7.104 265.313 7.200 ; - RECT 0.108 7.872 265.313 7.968 ; - RECT 0.108 8.640 265.313 8.736 ; - RECT 0.108 9.408 265.313 9.504 ; - RECT 0.108 10.176 265.313 10.272 ; - RECT 0.108 10.944 265.313 11.040 ; - RECT 0.108 11.712 265.313 11.808 ; - RECT 0.108 12.480 265.313 12.576 ; - RECT 0.108 13.248 265.313 13.344 ; - RECT 0.108 14.016 265.313 14.112 ; - RECT 0.108 14.784 265.313 14.880 ; - RECT 0.108 15.552 265.313 15.648 ; - RECT 0.108 16.320 265.313 16.416 ; - RECT 0.108 17.088 265.313 17.184 ; - RECT 0.108 17.856 265.313 17.952 ; - RECT 0.108 18.624 265.313 18.720 ; - RECT 0.108 19.392 265.313 19.488 ; - RECT 0.108 20.160 265.313 20.256 ; - RECT 0.108 20.928 265.313 21.024 ; - RECT 0.108 21.696 265.313 21.792 ; - RECT 0.108 22.464 265.313 22.560 ; - RECT 0.108 23.232 265.313 23.328 ; - RECT 0.108 24.000 265.313 24.096 ; - RECT 0.108 24.768 265.313 24.864 ; - RECT 0.108 25.536 265.313 25.632 ; - RECT 0.108 26.304 265.313 26.400 ; - RECT 0.108 27.072 265.313 27.168 ; - RECT 0.108 27.840 265.313 27.936 ; - RECT 0.108 28.608 265.313 28.704 ; - RECT 0.108 29.376 265.313 29.472 ; - RECT 0.108 30.144 265.313 30.240 ; - RECT 0.108 30.912 265.313 31.008 ; - RECT 0.108 31.680 265.313 31.776 ; - RECT 0.108 32.448 265.313 32.544 ; - RECT 0.108 33.216 265.313 33.312 ; - RECT 0.108 33.984 265.313 34.080 ; - RECT 0.108 34.752 265.313 34.848 ; - RECT 0.108 35.520 265.313 35.616 ; - RECT 0.108 36.288 265.313 36.384 ; - RECT 0.108 37.056 265.313 37.152 ; - RECT 0.108 37.824 265.313 37.920 ; - RECT 0.108 38.592 265.313 38.688 ; - RECT 0.108 39.360 265.313 39.456 ; - RECT 0.108 40.128 265.313 40.224 ; - RECT 0.108 40.896 265.313 40.992 ; - RECT 0.108 41.664 265.313 41.760 ; - RECT 0.108 42.432 265.313 42.528 ; - RECT 0.108 43.200 265.313 43.296 ; - RECT 0.108 43.968 265.313 44.064 ; - RECT 0.108 44.736 265.313 44.832 ; - RECT 0.108 45.504 265.313 45.600 ; - RECT 0.108 46.272 265.313 46.368 ; - RECT 0.108 47.040 265.313 47.136 ; - RECT 0.108 47.808 265.313 47.904 ; - RECT 0.108 48.576 265.313 48.672 ; - RECT 0.108 49.344 265.313 49.440 ; - RECT 0.108 50.112 265.313 50.208 ; - RECT 0.108 50.880 265.313 50.976 ; - RECT 0.108 51.648 265.313 51.744 ; - RECT 0.108 52.416 265.313 52.512 ; - RECT 0.108 53.184 265.313 53.280 ; - RECT 0.108 53.952 265.313 54.048 ; - RECT 0.108 54.720 265.313 54.816 ; - RECT 0.108 55.488 265.313 55.584 ; - RECT 0.108 56.256 265.313 56.352 ; - RECT 0.108 57.024 265.313 57.120 ; - RECT 0.108 57.792 265.313 57.888 ; - RECT 0.108 58.560 265.313 58.656 ; - RECT 0.108 59.328 265.313 59.424 ; - RECT 0.108 60.096 265.313 60.192 ; - RECT 0.108 60.864 265.313 60.960 ; - RECT 0.108 61.632 265.313 61.728 ; - RECT 0.108 62.400 265.313 62.496 ; - RECT 0.108 63.168 265.313 63.264 ; - RECT 0.108 63.936 265.313 64.032 ; - RECT 0.108 64.704 265.313 64.800 ; - RECT 0.108 65.472 265.313 65.568 ; - RECT 0.108 66.240 265.313 66.336 ; - RECT 0.108 67.008 265.313 67.104 ; - RECT 0.108 67.776 265.313 67.872 ; - RECT 0.108 68.544 265.313 68.640 ; - RECT 0.108 69.312 265.313 69.408 ; - RECT 0.108 70.080 265.313 70.176 ; - RECT 0.108 70.848 265.313 70.944 ; - RECT 0.108 71.616 265.313 71.712 ; - RECT 0.108 72.384 265.313 72.480 ; - RECT 0.108 73.152 265.313 73.248 ; - RECT 0.108 73.920 265.313 74.016 ; - RECT 0.108 74.688 265.313 74.784 ; - RECT 0.108 75.456 265.313 75.552 ; - RECT 0.108 76.224 265.313 76.320 ; - RECT 0.108 76.992 265.313 77.088 ; - RECT 0.108 77.760 265.313 77.856 ; - RECT 0.108 78.528 265.313 78.624 ; - RECT 0.108 79.296 265.313 79.392 ; - RECT 0.108 80.064 265.313 80.160 ; - RECT 0.108 80.832 265.313 80.928 ; - RECT 0.108 81.600 265.313 81.696 ; - RECT 0.108 82.368 265.313 82.464 ; - RECT 0.108 83.136 265.313 83.232 ; - RECT 0.108 83.904 265.313 84.000 ; - RECT 0.108 84.672 265.313 84.768 ; - RECT 0.108 85.440 265.313 85.536 ; - RECT 0.108 86.208 265.313 86.304 ; - RECT 0.108 86.976 265.313 87.072 ; - RECT 0.108 87.744 265.313 87.840 ; - RECT 0.108 88.512 265.313 88.608 ; - RECT 0.108 89.280 265.313 89.376 ; - RECT 0.108 90.048 265.313 90.144 ; - RECT 0.108 90.816 265.313 90.912 ; - RECT 0.108 91.584 265.313 91.680 ; - RECT 0.108 92.352 265.313 92.448 ; - RECT 0.108 93.120 265.313 93.216 ; - RECT 0.108 93.888 265.313 93.984 ; - RECT 0.108 94.656 265.313 94.752 ; - RECT 0.108 95.424 265.313 95.520 ; - RECT 0.108 96.192 265.313 96.288 ; - RECT 0.108 96.960 265.313 97.056 ; - RECT 0.108 97.728 265.313 97.824 ; - RECT 0.108 98.496 265.313 98.592 ; - RECT 0.108 99.264 265.313 99.360 ; - RECT 0.108 100.032 265.313 100.128 ; - RECT 0.108 100.800 265.313 100.896 ; - RECT 0.108 101.568 265.313 101.664 ; - RECT 0.108 102.336 265.313 102.432 ; - RECT 0.108 103.104 265.313 103.200 ; - RECT 0.108 103.872 265.313 103.968 ; - RECT 0.108 104.640 265.313 104.736 ; - RECT 0.108 105.408 265.313 105.504 ; - RECT 0.108 106.176 265.313 106.272 ; - RECT 0.108 106.944 265.313 107.040 ; - RECT 0.108 107.712 265.313 107.808 ; - RECT 0.108 108.480 265.313 108.576 ; - RECT 0.108 109.248 265.313 109.344 ; - RECT 0.108 110.016 265.313 110.112 ; - RECT 0.108 110.784 265.313 110.880 ; - RECT 0.108 111.552 265.313 111.648 ; - RECT 0.108 112.320 265.313 112.416 ; - RECT 0.108 113.088 265.313 113.184 ; - RECT 0.108 113.856 265.313 113.952 ; - RECT 0.108 114.624 265.313 114.720 ; - RECT 0.108 115.392 265.313 115.488 ; - RECT 0.108 116.160 265.313 116.256 ; - RECT 0.108 116.928 265.313 117.024 ; - RECT 0.108 117.696 265.313 117.792 ; - RECT 0.108 118.464 265.313 118.560 ; - RECT 0.108 119.232 265.313 119.328 ; - RECT 0.108 120.000 265.313 120.096 ; - RECT 0.108 120.768 265.313 120.864 ; - RECT 0.108 121.536 265.313 121.632 ; - RECT 0.108 122.304 265.313 122.400 ; - RECT 0.108 123.072 265.313 123.168 ; - RECT 0.108 123.840 265.313 123.936 ; - RECT 0.108 124.608 265.313 124.704 ; - RECT 0.108 125.376 265.313 125.472 ; - RECT 0.108 126.144 265.313 126.240 ; - RECT 0.108 126.912 265.313 127.008 ; - RECT 0.108 127.680 265.313 127.776 ; - RECT 0.108 128.448 265.313 128.544 ; - RECT 0.108 129.216 265.313 129.312 ; - RECT 0.108 129.984 265.313 130.080 ; - RECT 0.108 130.752 265.313 130.848 ; - RECT 0.108 131.520 265.313 131.616 ; - RECT 0.108 132.288 265.313 132.384 ; - RECT 0.108 133.056 265.313 133.152 ; - RECT 0.108 133.824 265.313 133.920 ; - RECT 0.108 134.592 265.313 134.688 ; - RECT 0.108 135.360 265.313 135.456 ; - RECT 0.108 136.128 265.313 136.224 ; - RECT 0.108 136.896 265.313 136.992 ; - RECT 0.108 137.664 265.313 137.760 ; - RECT 0.108 138.432 265.313 138.528 ; - RECT 0.108 139.200 265.313 139.296 ; - RECT 0.108 139.968 265.313 140.064 ; - RECT 0.108 140.736 265.313 140.832 ; - RECT 0.108 141.504 265.313 141.600 ; - RECT 0.108 142.272 265.313 142.368 ; - RECT 0.108 143.040 265.313 143.136 ; - RECT 0.108 143.808 265.313 143.904 ; - RECT 0.108 144.576 265.313 144.672 ; - RECT 0.108 145.344 265.313 145.440 ; - RECT 0.108 146.112 265.313 146.208 ; - RECT 0.108 146.880 265.313 146.976 ; - RECT 0.108 147.648 265.313 147.744 ; - RECT 0.108 148.416 265.313 148.512 ; - RECT 0.108 149.184 265.313 149.280 ; - RECT 0.108 149.952 265.313 150.048 ; - RECT 0.108 150.720 265.313 150.816 ; - RECT 0.108 151.488 265.313 151.584 ; - RECT 0.108 152.256 265.313 152.352 ; - RECT 0.108 153.024 265.313 153.120 ; - RECT 0.108 153.792 265.313 153.888 ; - RECT 0.108 154.560 265.313 154.656 ; - RECT 0.108 155.328 265.313 155.424 ; - RECT 0.108 156.096 265.313 156.192 ; - RECT 0.108 156.864 265.313 156.960 ; - RECT 0.108 157.632 265.313 157.728 ; - RECT 0.108 158.400 265.313 158.496 ; - RECT 0.108 159.168 265.313 159.264 ; - RECT 0.108 159.936 265.313 160.032 ; - RECT 0.108 160.704 265.313 160.800 ; - RECT 0.108 161.472 265.313 161.568 ; - RECT 0.108 162.240 265.313 162.336 ; - RECT 0.108 163.008 265.313 163.104 ; - RECT 0.108 163.776 265.313 163.872 ; - RECT 0.108 164.544 265.313 164.640 ; - RECT 0.108 165.312 265.313 165.408 ; + RECT 0.216 0.240 163.018 0.336 ; + RECT 0.216 1.008 163.018 1.104 ; + RECT 0.216 1.776 163.018 1.872 ; + RECT 0.216 2.544 163.018 2.640 ; + RECT 0.216 3.312 163.018 3.408 ; + RECT 0.216 4.080 163.018 4.176 ; + RECT 0.216 4.848 163.018 4.944 ; + RECT 0.216 5.616 163.018 5.712 ; + RECT 0.216 6.384 163.018 6.480 ; + RECT 0.216 7.152 163.018 7.248 ; + RECT 0.216 7.920 163.018 8.016 ; + RECT 0.216 8.688 163.018 8.784 ; + RECT 0.216 9.456 163.018 9.552 ; + RECT 0.216 10.224 163.018 10.320 ; + RECT 0.216 10.992 163.018 11.088 ; + RECT 0.216 11.760 163.018 11.856 ; + RECT 0.216 12.528 163.018 12.624 ; + RECT 0.216 13.296 163.018 13.392 ; + RECT 0.216 14.064 163.018 14.160 ; + RECT 0.216 14.832 163.018 14.928 ; + RECT 0.216 15.600 163.018 15.696 ; + RECT 0.216 16.368 163.018 16.464 ; + RECT 0.216 17.136 163.018 17.232 ; + RECT 0.216 17.904 163.018 18.000 ; + RECT 0.216 18.672 163.018 18.768 ; + RECT 0.216 19.440 163.018 19.536 ; + RECT 0.216 20.208 163.018 20.304 ; + RECT 0.216 20.976 163.018 21.072 ; + RECT 0.216 21.744 163.018 21.840 ; + RECT 0.216 22.512 163.018 22.608 ; + RECT 0.216 23.280 163.018 23.376 ; + RECT 0.216 24.048 163.018 24.144 ; + RECT 0.216 24.816 163.018 24.912 ; + RECT 0.216 25.584 163.018 25.680 ; + RECT 0.216 26.352 163.018 26.448 ; + RECT 0.216 27.120 163.018 27.216 ; + RECT 0.216 27.888 163.018 27.984 ; + RECT 0.216 28.656 163.018 28.752 ; + RECT 0.216 29.424 163.018 29.520 ; + RECT 0.216 30.192 163.018 30.288 ; + RECT 0.216 30.960 163.018 31.056 ; + RECT 0.216 31.728 163.018 31.824 ; + RECT 0.216 32.496 163.018 32.592 ; + RECT 0.216 33.264 163.018 33.360 ; + RECT 0.216 34.032 163.018 34.128 ; + RECT 0.216 34.800 163.018 34.896 ; + RECT 0.216 35.568 163.018 35.664 ; + RECT 0.216 36.336 163.018 36.432 ; + RECT 0.216 37.104 163.018 37.200 ; + RECT 0.216 37.872 163.018 37.968 ; + RECT 0.216 38.640 163.018 38.736 ; + RECT 0.216 39.408 163.018 39.504 ; + RECT 0.216 40.176 163.018 40.272 ; + RECT 0.216 40.944 163.018 41.040 ; + RECT 0.216 41.712 163.018 41.808 ; + RECT 0.216 42.480 163.018 42.576 ; + RECT 0.216 43.248 163.018 43.344 ; + RECT 0.216 44.016 163.018 44.112 ; + RECT 0.216 44.784 163.018 44.880 ; + RECT 0.216 45.552 163.018 45.648 ; + RECT 0.216 46.320 163.018 46.416 ; + RECT 0.216 47.088 163.018 47.184 ; + RECT 0.216 47.856 163.018 47.952 ; + RECT 0.216 48.624 163.018 48.720 ; + RECT 0.216 49.392 163.018 49.488 ; + RECT 0.216 50.160 163.018 50.256 ; + RECT 0.216 50.928 163.018 51.024 ; + RECT 0.216 51.696 163.018 51.792 ; + RECT 0.216 52.464 163.018 52.560 ; + RECT 0.216 53.232 163.018 53.328 ; + RECT 0.216 54.000 163.018 54.096 ; + RECT 0.216 54.768 163.018 54.864 ; + RECT 0.216 55.536 163.018 55.632 ; + RECT 0.216 56.304 163.018 56.400 ; + RECT 0.216 57.072 163.018 57.168 ; + RECT 0.216 57.840 163.018 57.936 ; + RECT 0.216 58.608 163.018 58.704 ; + RECT 0.216 59.376 163.018 59.472 ; + RECT 0.216 60.144 163.018 60.240 ; + RECT 0.216 60.912 163.018 61.008 ; + RECT 0.216 61.680 163.018 61.776 ; + RECT 0.216 62.448 163.018 62.544 ; + RECT 0.216 63.216 163.018 63.312 ; + RECT 0.216 63.984 163.018 64.080 ; + RECT 0.216 64.752 163.018 64.848 ; + RECT 0.216 65.520 163.018 65.616 ; + RECT 0.216 66.288 163.018 66.384 ; + RECT 0.216 67.056 163.018 67.152 ; + RECT 0.216 67.824 163.018 67.920 ; + RECT 0.216 68.592 163.018 68.688 ; + RECT 0.216 69.360 163.018 69.456 ; + RECT 0.216 70.128 163.018 70.224 ; + RECT 0.216 70.896 163.018 70.992 ; + RECT 0.216 71.664 163.018 71.760 ; + RECT 0.216 72.432 163.018 72.528 ; + RECT 0.216 73.200 163.018 73.296 ; + RECT 0.216 73.968 163.018 74.064 ; + RECT 0.216 74.736 163.018 74.832 ; + RECT 0.216 75.504 163.018 75.600 ; + RECT 0.216 76.272 163.018 76.368 ; + RECT 0.216 77.040 163.018 77.136 ; + RECT 0.216 77.808 163.018 77.904 ; + RECT 0.216 78.576 163.018 78.672 ; + RECT 0.216 79.344 163.018 79.440 ; + RECT 0.216 80.112 163.018 80.208 ; + RECT 0.216 80.880 163.018 80.976 ; + RECT 0.216 81.648 163.018 81.744 ; + RECT 0.216 82.416 163.018 82.512 ; + RECT 0.216 83.184 163.018 83.280 ; + RECT 0.216 83.952 163.018 84.048 ; + RECT 0.216 84.720 163.018 84.816 ; + RECT 0.216 85.488 163.018 85.584 ; + RECT 0.216 86.256 163.018 86.352 ; + RECT 0.216 87.024 163.018 87.120 ; + RECT 0.216 87.792 163.018 87.888 ; + RECT 0.216 88.560 163.018 88.656 ; + RECT 0.216 89.328 163.018 89.424 ; + RECT 0.216 90.096 163.018 90.192 ; + RECT 0.216 90.864 163.018 90.960 ; + RECT 0.216 91.632 163.018 91.728 ; + RECT 0.216 92.400 163.018 92.496 ; + RECT 0.216 93.168 163.018 93.264 ; + RECT 0.216 93.936 163.018 94.032 ; + RECT 0.216 94.704 163.018 94.800 ; + RECT 0.216 95.472 163.018 95.568 ; + RECT 0.216 96.240 163.018 96.336 ; + RECT 0.216 97.008 163.018 97.104 ; + RECT 0.216 97.776 163.018 97.872 ; + RECT 0.216 98.544 163.018 98.640 ; + RECT 0.216 99.312 163.018 99.408 ; + RECT 0.216 100.080 163.018 100.176 ; + RECT 0.216 100.848 163.018 100.944 ; + RECT 0.216 101.616 163.018 101.712 ; + RECT 0.216 102.384 163.018 102.480 ; + RECT 0.216 103.152 163.018 103.248 ; + RECT 0.216 103.920 163.018 104.016 ; + RECT 0.216 104.688 163.018 104.784 ; + RECT 0.216 105.456 163.018 105.552 ; + RECT 0.216 106.224 163.018 106.320 ; + RECT 0.216 106.992 163.018 107.088 ; + RECT 0.216 107.760 163.018 107.856 ; + RECT 0.216 108.528 163.018 108.624 ; + RECT 0.216 109.296 163.018 109.392 ; + RECT 0.216 110.064 163.018 110.160 ; + RECT 0.216 110.832 163.018 110.928 ; + RECT 0.216 111.600 163.018 111.696 ; + RECT 0.216 112.368 163.018 112.464 ; + RECT 0.216 113.136 163.018 113.232 ; + RECT 0.216 113.904 163.018 114.000 ; + RECT 0.216 114.672 163.018 114.768 ; + RECT 0.216 115.440 163.018 115.536 ; + RECT 0.216 116.208 163.018 116.304 ; + RECT 0.216 116.976 163.018 117.072 ; + RECT 0.216 117.744 163.018 117.840 ; + RECT 0.216 118.512 163.018 118.608 ; + RECT 0.216 119.280 163.018 119.376 ; + RECT 0.216 120.048 163.018 120.144 ; + RECT 0.216 120.816 163.018 120.912 ; + RECT 0.216 121.584 163.018 121.680 ; + RECT 0.216 122.352 163.018 122.448 ; + RECT 0.216 123.120 163.018 123.216 ; + RECT 0.216 123.888 163.018 123.984 ; + RECT 0.216 124.656 163.018 124.752 ; + RECT 0.216 125.424 163.018 125.520 ; + RECT 0.216 126.192 163.018 126.288 ; + RECT 0.216 126.960 163.018 127.056 ; + RECT 0.216 127.728 163.018 127.824 ; + RECT 0.216 128.496 163.018 128.592 ; + RECT 0.216 129.264 163.018 129.360 ; + RECT 0.216 130.032 163.018 130.128 ; + RECT 0.216 130.800 163.018 130.896 ; + RECT 0.216 131.568 163.018 131.664 ; + RECT 0.216 132.336 163.018 132.432 ; + RECT 0.216 133.104 163.018 133.200 ; + RECT 0.216 133.872 163.018 133.968 ; + RECT 0.216 134.640 163.018 134.736 ; + RECT 0.216 135.408 163.018 135.504 ; + RECT 0.216 136.176 163.018 136.272 ; + RECT 0.216 136.944 163.018 137.040 ; + RECT 0.216 137.712 163.018 137.808 ; + RECT 0.216 138.480 163.018 138.576 ; + RECT 0.216 139.248 163.018 139.344 ; + RECT 0.216 140.016 163.018 140.112 ; + RECT 0.216 140.784 163.018 140.880 ; + RECT 0.216 141.552 163.018 141.648 ; + RECT 0.216 142.320 163.018 142.416 ; + RECT 0.216 143.088 163.018 143.184 ; + RECT 0.216 143.856 163.018 143.952 ; + RECT 0.216 144.624 163.018 144.720 ; + RECT 0.216 145.392 163.018 145.488 ; + RECT 0.216 146.160 163.018 146.256 ; + RECT 0.216 146.928 163.018 147.024 ; + RECT 0.216 147.696 163.018 147.792 ; + RECT 0.216 148.464 163.018 148.560 ; + RECT 0.216 149.232 163.018 149.328 ; + RECT 0.216 150.000 163.018 150.096 ; + RECT 0.216 150.768 163.018 150.864 ; + RECT 0.216 151.536 163.018 151.632 ; + RECT 0.216 152.304 163.018 152.400 ; + RECT 0.216 153.072 163.018 153.168 ; + RECT 0.216 153.840 163.018 153.936 ; + RECT 0.216 154.608 163.018 154.704 ; + RECT 0.216 155.376 163.018 155.472 ; + RECT 0.216 156.144 163.018 156.240 ; + RECT 0.216 156.912 163.018 157.008 ; + RECT 0.216 157.680 163.018 157.776 ; + RECT 0.216 158.448 163.018 158.544 ; + RECT 0.216 159.216 163.018 159.312 ; + RECT 0.216 159.984 163.018 160.080 ; + RECT 0.216 160.752 163.018 160.848 ; + RECT 0.216 161.520 163.018 161.616 ; + RECT 0.216 162.288 163.018 162.384 ; + RECT 0.216 163.056 163.018 163.152 ; + RECT 0.216 163.824 163.018 163.920 ; + RECT 0.216 164.592 163.018 164.688 ; + RECT 0.216 165.360 163.018 165.456 ; + RECT 0.216 166.128 163.018 166.224 ; + RECT 0.216 166.896 163.018 166.992 ; + RECT 0.216 167.664 163.018 167.760 ; + RECT 0.216 168.432 163.018 168.528 ; + RECT 0.216 169.200 163.018 169.296 ; + RECT 0.216 169.968 163.018 170.064 ; + RECT 0.216 170.736 163.018 170.832 ; + RECT 0.216 171.504 163.018 171.600 ; + RECT 0.216 172.272 163.018 172.368 ; + RECT 0.216 173.040 163.018 173.136 ; + RECT 0.216 173.808 163.018 173.904 ; + RECT 0.216 174.576 163.018 174.672 ; + RECT 0.216 175.344 163.018 175.440 ; + RECT 0.216 176.112 163.018 176.208 ; + RECT 0.216 176.880 163.018 176.976 ; + RECT 0.216 177.648 163.018 177.744 ; + RECT 0.216 178.416 163.018 178.512 ; + RECT 0.216 179.184 163.018 179.280 ; + RECT 0.216 179.952 163.018 180.048 ; + RECT 0.216 180.720 163.018 180.816 ; + RECT 0.216 181.488 163.018 181.584 ; + RECT 0.216 182.256 163.018 182.352 ; + RECT 0.216 183.024 163.018 183.120 ; + RECT 0.216 183.792 163.018 183.888 ; + RECT 0.216 184.560 163.018 184.656 ; + RECT 0.216 185.328 163.018 185.424 ; + RECT 0.216 186.096 163.018 186.192 ; + RECT 0.216 186.864 163.018 186.960 ; + RECT 0.216 187.632 163.018 187.728 ; + RECT 0.216 188.400 163.018 188.496 ; + RECT 0.216 189.168 163.018 189.264 ; + RECT 0.216 189.936 163.018 190.032 ; + RECT 0.216 190.704 163.018 190.800 ; + RECT 0.216 191.472 163.018 191.568 ; + RECT 0.216 192.240 163.018 192.336 ; + RECT 0.216 193.008 163.018 193.104 ; + RECT 0.216 193.776 163.018 193.872 ; + RECT 0.216 194.544 163.018 194.640 ; + RECT 0.216 195.312 163.018 195.408 ; + RECT 0.216 196.080 163.018 196.176 ; + RECT 0.216 196.848 163.018 196.944 ; + RECT 0.216 197.616 163.018 197.712 ; + RECT 0.216 198.384 163.018 198.480 ; + RECT 0.216 199.152 163.018 199.248 ; + RECT 0.216 199.920 163.018 200.016 ; + RECT 0.216 200.688 163.018 200.784 ; + RECT 0.216 201.456 163.018 201.552 ; + RECT 0.216 202.224 163.018 202.320 ; + RECT 0.216 202.992 163.018 203.088 ; + RECT 0.216 203.760 163.018 203.856 ; + RECT 0.216 204.528 163.018 204.624 ; + RECT 0.216 205.296 163.018 205.392 ; + RECT 0.216 206.064 163.018 206.160 ; + RECT 0.216 206.832 163.018 206.928 ; + RECT 0.216 207.600 163.018 207.696 ; + RECT 0.216 208.368 163.018 208.464 ; + RECT 0.216 209.136 163.018 209.232 ; + RECT 0.216 209.904 163.018 210.000 ; + RECT 0.216 210.672 163.018 210.768 ; + RECT 0.216 211.440 163.018 211.536 ; + RECT 0.216 212.208 163.018 212.304 ; + RECT 0.216 212.976 163.018 213.072 ; + RECT 0.216 213.744 163.018 213.840 ; + RECT 0.216 214.512 163.018 214.608 ; + RECT 0.216 215.280 163.018 215.376 ; + RECT 0.216 216.048 163.018 216.144 ; + RECT 0.216 216.816 163.018 216.912 ; + RECT 0.216 217.584 163.018 217.680 ; + RECT 0.216 218.352 163.018 218.448 ; + RECT 0.216 219.120 163.018 219.216 ; + RECT 0.216 219.888 163.018 219.984 ; + RECT 0.216 220.656 163.018 220.752 ; + RECT 0.216 221.424 163.018 221.520 ; + RECT 0.216 222.192 163.018 222.288 ; + RECT 0.216 222.960 163.018 223.056 ; + RECT 0.216 223.728 163.018 223.824 ; + RECT 0.216 224.496 163.018 224.592 ; + RECT 0.216 225.264 163.018 225.360 ; + RECT 0.216 226.032 163.018 226.128 ; + RECT 0.216 226.800 163.018 226.896 ; + RECT 0.216 227.568 163.018 227.664 ; + RECT 0.216 228.336 163.018 228.432 ; + RECT 0.216 229.104 163.018 229.200 ; + RECT 0.216 229.872 163.018 229.968 ; + RECT 0.216 230.640 163.018 230.736 ; + RECT 0.216 231.408 163.018 231.504 ; + RECT 0.216 232.176 163.018 232.272 ; + RECT 0.216 232.944 163.018 233.040 ; + RECT 0.216 233.712 163.018 233.808 ; + RECT 0.216 234.480 163.018 234.576 ; + RECT 0.216 235.248 163.018 235.344 ; + RECT 0.216 236.016 163.018 236.112 ; + RECT 0.216 236.784 163.018 236.880 ; + RECT 0.216 237.552 163.018 237.648 ; + RECT 0.216 238.320 163.018 238.416 ; + RECT 0.216 239.088 163.018 239.184 ; + RECT 0.216 239.856 163.018 239.952 ; + RECT 0.216 240.624 163.018 240.720 ; + RECT 0.216 241.392 163.018 241.488 ; + RECT 0.216 242.160 163.018 242.256 ; + RECT 0.216 242.928 163.018 243.024 ; + RECT 0.216 243.696 163.018 243.792 ; + RECT 0.216 244.464 163.018 244.560 ; + RECT 0.216 245.232 163.018 245.328 ; + RECT 0.216 246.000 163.018 246.096 ; + RECT 0.216 246.768 163.018 246.864 ; + RECT 0.216 247.536 163.018 247.632 ; + RECT 0.216 248.304 163.018 248.400 ; + RECT 0.216 249.072 163.018 249.168 ; + RECT 0.216 249.840 163.018 249.936 ; + RECT 0.216 250.608 163.018 250.704 ; + RECT 0.216 251.376 163.018 251.472 ; + RECT 0.216 252.144 163.018 252.240 ; + RECT 0.216 252.912 163.018 253.008 ; + RECT 0.216 253.680 163.018 253.776 ; + RECT 0.216 254.448 163.018 254.544 ; + RECT 0.216 255.216 163.018 255.312 ; + RECT 0.216 255.984 163.018 256.080 ; + RECT 0.216 256.752 163.018 256.848 ; + RECT 0.216 257.520 163.018 257.616 ; + RECT 0.216 258.288 163.018 258.384 ; + RECT 0.216 259.056 163.018 259.152 ; + RECT 0.216 259.824 163.018 259.920 ; + RECT 0.216 260.592 163.018 260.688 ; + RECT 0.216 261.360 163.018 261.456 ; + RECT 0.216 262.128 163.018 262.224 ; + RECT 0.216 262.896 163.018 262.992 ; + RECT 0.216 263.664 163.018 263.760 ; + RECT 0.216 264.432 163.018 264.528 ; + RECT 0.216 265.200 163.018 265.296 ; + RECT 0.216 265.968 163.018 266.064 ; + RECT 0.216 266.736 163.018 266.832 ; + RECT 0.216 267.504 163.018 267.600 ; + RECT 0.216 268.272 163.018 268.368 ; + RECT 0.216 269.040 163.018 269.136 ; + RECT 0.216 269.808 163.018 269.904 ; + RECT 0.216 270.576 163.018 270.672 ; + RECT 0.216 271.344 163.018 271.440 ; + RECT 0.216 272.112 163.018 272.208 ; + RECT 0.216 272.880 163.018 272.976 ; + RECT 0.216 273.648 163.018 273.744 ; + RECT 0.216 274.416 163.018 274.512 ; + RECT 0.216 275.184 163.018 275.280 ; + RECT 0.216 275.952 163.018 276.048 ; + RECT 0.216 276.720 163.018 276.816 ; + RECT 0.216 277.488 163.018 277.584 ; + RECT 0.216 278.256 163.018 278.352 ; + RECT 0.216 279.024 163.018 279.120 ; + RECT 0.216 279.792 163.018 279.888 ; + RECT 0.216 280.560 163.018 280.656 ; + RECT 0.216 281.328 163.018 281.424 ; + RECT 0.216 282.096 163.018 282.192 ; + RECT 0.216 282.864 163.018 282.960 ; + RECT 0.216 283.632 163.018 283.728 ; + RECT 0.216 284.400 163.018 284.496 ; + RECT 0.216 285.168 163.018 285.264 ; + RECT 0.216 285.936 163.018 286.032 ; + RECT 0.216 286.704 163.018 286.800 ; + RECT 0.216 287.472 163.018 287.568 ; + RECT 0.216 288.240 163.018 288.336 ; + RECT 0.216 289.008 163.018 289.104 ; + RECT 0.216 289.776 163.018 289.872 ; + RECT 0.216 290.544 163.018 290.640 ; + RECT 0.216 291.312 163.018 291.408 ; + RECT 0.216 292.080 163.018 292.176 ; + RECT 0.216 292.848 163.018 292.944 ; + RECT 0.216 293.616 163.018 293.712 ; + RECT 0.216 294.384 163.018 294.480 ; + RECT 0.216 295.152 163.018 295.248 ; + RECT 0.216 295.920 163.018 296.016 ; + RECT 0.216 296.688 163.018 296.784 ; + RECT 0.216 297.456 163.018 297.552 ; + RECT 0.216 298.224 163.018 298.320 ; + RECT 0.216 298.992 163.018 299.088 ; + RECT 0.216 299.760 163.018 299.856 ; + RECT 0.216 300.528 163.018 300.624 ; + RECT 0.216 301.296 163.018 301.392 ; + RECT 0.216 302.064 163.018 302.160 ; + RECT 0.216 302.832 163.018 302.928 ; + RECT 0.216 303.600 163.018 303.696 ; + RECT 0.216 304.368 163.018 304.464 ; + RECT 0.216 305.136 163.018 305.232 ; + RECT 0.216 305.904 163.018 306.000 ; + RECT 0.216 306.672 163.018 306.768 ; + RECT 0.216 307.440 163.018 307.536 ; + RECT 0.216 308.208 163.018 308.304 ; + RECT 0.216 308.976 163.018 309.072 ; + RECT 0.216 309.744 163.018 309.840 ; + RECT 0.216 310.512 163.018 310.608 ; + RECT 0.216 311.280 163.018 311.376 ; + RECT 0.216 312.048 163.018 312.144 ; + RECT 0.216 312.816 163.018 312.912 ; + RECT 0.216 313.584 163.018 313.680 ; + RECT 0.216 314.352 163.018 314.448 ; + RECT 0.216 315.120 163.018 315.216 ; + RECT 0.216 315.888 163.018 315.984 ; + RECT 0.216 316.656 163.018 316.752 ; + RECT 0.216 317.424 163.018 317.520 ; + RECT 0.216 318.192 163.018 318.288 ; + RECT 0.216 318.960 163.018 319.056 ; + RECT 0.216 319.728 163.018 319.824 ; + RECT 0.216 320.496 163.018 320.592 ; + RECT 0.216 321.264 163.018 321.360 ; + RECT 0.216 322.032 163.018 322.128 ; + RECT 0.216 322.800 163.018 322.896 ; + RECT 0.216 323.568 163.018 323.664 ; + RECT 0.216 324.336 163.018 324.432 ; + RECT 0.216 325.104 163.018 325.200 ; + RECT 0.216 325.872 163.018 325.968 ; + RECT 0.216 326.640 163.018 326.736 ; + RECT 0.216 327.408 163.018 327.504 ; + RECT 0.216 328.176 163.018 328.272 ; + RECT 0.216 328.944 163.018 329.040 ; + RECT 0.216 329.712 163.018 329.808 ; + RECT 0.216 330.480 163.018 330.576 ; + RECT 0.216 331.248 163.018 331.344 ; + RECT 0.216 332.016 163.018 332.112 ; + RECT 0.216 332.784 163.018 332.880 ; + RECT 0.216 333.552 163.018 333.648 ; + RECT 0.216 334.320 163.018 334.416 ; + RECT 0.216 335.088 163.018 335.184 ; + RECT 0.216 335.856 163.018 335.952 ; + RECT 0.216 336.624 163.018 336.720 ; + RECT 0.216 337.392 163.018 337.488 ; + RECT 0.216 338.160 163.018 338.256 ; + RECT 0.216 338.928 163.018 339.024 ; + RECT 0.216 339.696 163.018 339.792 ; + RECT 0.216 340.464 163.018 340.560 ; + RECT 0.216 341.232 163.018 341.328 ; + RECT 0.216 342.000 163.018 342.096 ; + RECT 0.216 342.768 163.018 342.864 ; + RECT 0.216 343.536 163.018 343.632 ; + RECT 0.216 344.304 163.018 344.400 ; + RECT 0.216 345.072 163.018 345.168 ; + RECT 0.216 345.840 163.018 345.936 ; + RECT 0.216 346.608 163.018 346.704 ; + RECT 0.216 347.376 163.018 347.472 ; + RECT 0.216 348.144 163.018 348.240 ; + RECT 0.216 348.912 163.018 349.008 ; + RECT 0.216 349.680 163.018 349.776 ; + RECT 0.216 350.448 163.018 350.544 ; + RECT 0.216 351.216 163.018 351.312 ; + RECT 0.216 351.984 163.018 352.080 ; + RECT 0.216 352.752 163.018 352.848 ; + RECT 0.216 353.520 163.018 353.616 ; + RECT 0.216 354.288 163.018 354.384 ; + RECT 0.216 355.056 163.018 355.152 ; + RECT 0.216 355.824 163.018 355.920 ; + RECT 0.216 356.592 163.018 356.688 ; + RECT 0.216 357.360 163.018 357.456 ; + RECT 0.216 358.128 163.018 358.224 ; + RECT 0.216 358.896 163.018 358.992 ; + RECT 0.216 359.664 163.018 359.760 ; + RECT 0.216 360.432 163.018 360.528 ; + RECT 0.216 361.200 163.018 361.296 ; + RECT 0.216 361.968 163.018 362.064 ; + RECT 0.216 362.736 163.018 362.832 ; + RECT 0.216 363.504 163.018 363.600 ; + RECT 0.216 364.272 163.018 364.368 ; + RECT 0.216 365.040 163.018 365.136 ; + RECT 0.216 365.808 163.018 365.904 ; + RECT 0.216 366.576 163.018 366.672 ; + RECT 0.216 367.344 163.018 367.440 ; + RECT 0.216 368.112 163.018 368.208 ; + RECT 0.216 368.880 163.018 368.976 ; + RECT 0.216 369.648 163.018 369.744 ; + RECT 0.216 370.416 163.018 370.512 ; + RECT 0.216 371.184 163.018 371.280 ; + RECT 0.216 371.952 163.018 372.048 ; + RECT 0.216 372.720 163.018 372.816 ; + RECT 0.216 373.488 163.018 373.584 ; + RECT 0.216 374.256 163.018 374.352 ; + RECT 0.216 375.024 163.018 375.120 ; + RECT 0.216 375.792 163.018 375.888 ; + RECT 0.216 376.560 163.018 376.656 ; + RECT 0.216 377.328 163.018 377.424 ; + RECT 0.216 378.096 163.018 378.192 ; + RECT 0.216 378.864 163.018 378.960 ; + RECT 0.216 379.632 163.018 379.728 ; + RECT 0.216 380.400 163.018 380.496 ; + RECT 0.216 381.168 163.018 381.264 ; + RECT 0.216 381.936 163.018 382.032 ; + RECT 0.216 382.704 163.018 382.800 ; + RECT 0.216 383.472 163.018 383.568 ; + RECT 0.216 384.240 163.018 384.336 ; + RECT 0.216 385.008 163.018 385.104 ; + RECT 0.216 385.776 163.018 385.872 ; + RECT 0.216 386.544 163.018 386.640 ; + RECT 0.216 387.312 163.018 387.408 ; + RECT 0.216 388.080 163.018 388.176 ; + RECT 0.216 388.848 163.018 388.944 ; + RECT 0.216 389.616 163.018 389.712 ; + RECT 0.216 390.384 163.018 390.480 ; + RECT 0.216 391.152 163.018 391.248 ; + RECT 0.216 391.920 163.018 392.016 ; + RECT 0.216 392.688 163.018 392.784 ; + RECT 0.216 393.456 163.018 393.552 ; + RECT 0.216 394.224 163.018 394.320 ; + RECT 0.216 394.992 163.018 395.088 ; + RECT 0.216 395.760 163.018 395.856 ; + RECT 0.216 396.528 163.018 396.624 ; + RECT 0.216 397.296 163.018 397.392 ; + RECT 0.216 398.064 163.018 398.160 ; + RECT 0.216 398.832 163.018 398.928 ; + RECT 0.216 399.600 163.018 399.696 ; + RECT 0.216 400.368 163.018 400.464 ; + RECT 0.216 401.136 163.018 401.232 ; + RECT 0.216 401.904 163.018 402.000 ; + RECT 0.216 402.672 163.018 402.768 ; + RECT 0.216 403.440 163.018 403.536 ; + RECT 0.216 404.208 163.018 404.304 ; + RECT 0.216 404.976 163.018 405.072 ; + RECT 0.216 405.744 163.018 405.840 ; + RECT 0.216 406.512 163.018 406.608 ; + RECT 0.216 407.280 163.018 407.376 ; END END VSS PIN VDD @@ -9692,233 +14615,548 @@ MACRO fakeram_512x2048_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.108 0.192 265.313 0.288 ; - RECT 0.108 0.960 265.313 1.056 ; - RECT 0.108 1.728 265.313 1.824 ; - RECT 0.108 2.496 265.313 2.592 ; - RECT 0.108 3.264 265.313 3.360 ; - RECT 0.108 4.032 265.313 4.128 ; - RECT 0.108 4.800 265.313 4.896 ; - RECT 0.108 5.568 265.313 5.664 ; - RECT 0.108 6.336 265.313 6.432 ; - RECT 0.108 7.104 265.313 7.200 ; - RECT 0.108 7.872 265.313 7.968 ; - RECT 0.108 8.640 265.313 8.736 ; - RECT 0.108 9.408 265.313 9.504 ; - RECT 0.108 10.176 265.313 10.272 ; - RECT 0.108 10.944 265.313 11.040 ; - RECT 0.108 11.712 265.313 11.808 ; - RECT 0.108 12.480 265.313 12.576 ; - RECT 0.108 13.248 265.313 13.344 ; - RECT 0.108 14.016 265.313 14.112 ; - RECT 0.108 14.784 265.313 14.880 ; - RECT 0.108 15.552 265.313 15.648 ; - RECT 0.108 16.320 265.313 16.416 ; - RECT 0.108 17.088 265.313 17.184 ; - RECT 0.108 17.856 265.313 17.952 ; - RECT 0.108 18.624 265.313 18.720 ; - RECT 0.108 19.392 265.313 19.488 ; - RECT 0.108 20.160 265.313 20.256 ; - RECT 0.108 20.928 265.313 21.024 ; - RECT 0.108 21.696 265.313 21.792 ; - RECT 0.108 22.464 265.313 22.560 ; - RECT 0.108 23.232 265.313 23.328 ; - RECT 0.108 24.000 265.313 24.096 ; - RECT 0.108 24.768 265.313 24.864 ; - RECT 0.108 25.536 265.313 25.632 ; - RECT 0.108 26.304 265.313 26.400 ; - RECT 0.108 27.072 265.313 27.168 ; - RECT 0.108 27.840 265.313 27.936 ; - RECT 0.108 28.608 265.313 28.704 ; - RECT 0.108 29.376 265.313 29.472 ; - RECT 0.108 30.144 265.313 30.240 ; - RECT 0.108 30.912 265.313 31.008 ; - RECT 0.108 31.680 265.313 31.776 ; - RECT 0.108 32.448 265.313 32.544 ; - RECT 0.108 33.216 265.313 33.312 ; - RECT 0.108 33.984 265.313 34.080 ; - RECT 0.108 34.752 265.313 34.848 ; - RECT 0.108 35.520 265.313 35.616 ; - RECT 0.108 36.288 265.313 36.384 ; - RECT 0.108 37.056 265.313 37.152 ; - RECT 0.108 37.824 265.313 37.920 ; - RECT 0.108 38.592 265.313 38.688 ; - RECT 0.108 39.360 265.313 39.456 ; - RECT 0.108 40.128 265.313 40.224 ; - RECT 0.108 40.896 265.313 40.992 ; - RECT 0.108 41.664 265.313 41.760 ; - RECT 0.108 42.432 265.313 42.528 ; - RECT 0.108 43.200 265.313 43.296 ; - RECT 0.108 43.968 265.313 44.064 ; - RECT 0.108 44.736 265.313 44.832 ; - RECT 0.108 45.504 265.313 45.600 ; - RECT 0.108 46.272 265.313 46.368 ; - RECT 0.108 47.040 265.313 47.136 ; - RECT 0.108 47.808 265.313 47.904 ; - RECT 0.108 48.576 265.313 48.672 ; - RECT 0.108 49.344 265.313 49.440 ; - RECT 0.108 50.112 265.313 50.208 ; - RECT 0.108 50.880 265.313 50.976 ; - RECT 0.108 51.648 265.313 51.744 ; - RECT 0.108 52.416 265.313 52.512 ; - RECT 0.108 53.184 265.313 53.280 ; - RECT 0.108 53.952 265.313 54.048 ; - RECT 0.108 54.720 265.313 54.816 ; - RECT 0.108 55.488 265.313 55.584 ; - RECT 0.108 56.256 265.313 56.352 ; - RECT 0.108 57.024 265.313 57.120 ; - RECT 0.108 57.792 265.313 57.888 ; - RECT 0.108 58.560 265.313 58.656 ; - RECT 0.108 59.328 265.313 59.424 ; - RECT 0.108 60.096 265.313 60.192 ; - RECT 0.108 60.864 265.313 60.960 ; - RECT 0.108 61.632 265.313 61.728 ; - RECT 0.108 62.400 265.313 62.496 ; - RECT 0.108 63.168 265.313 63.264 ; - RECT 0.108 63.936 265.313 64.032 ; - RECT 0.108 64.704 265.313 64.800 ; - RECT 0.108 65.472 265.313 65.568 ; - RECT 0.108 66.240 265.313 66.336 ; - RECT 0.108 67.008 265.313 67.104 ; - RECT 0.108 67.776 265.313 67.872 ; - RECT 0.108 68.544 265.313 68.640 ; - RECT 0.108 69.312 265.313 69.408 ; - RECT 0.108 70.080 265.313 70.176 ; - RECT 0.108 70.848 265.313 70.944 ; - RECT 0.108 71.616 265.313 71.712 ; - RECT 0.108 72.384 265.313 72.480 ; - RECT 0.108 73.152 265.313 73.248 ; - RECT 0.108 73.920 265.313 74.016 ; - RECT 0.108 74.688 265.313 74.784 ; - RECT 0.108 75.456 265.313 75.552 ; - RECT 0.108 76.224 265.313 76.320 ; - RECT 0.108 76.992 265.313 77.088 ; - RECT 0.108 77.760 265.313 77.856 ; - RECT 0.108 78.528 265.313 78.624 ; - RECT 0.108 79.296 265.313 79.392 ; - RECT 0.108 80.064 265.313 80.160 ; - RECT 0.108 80.832 265.313 80.928 ; - RECT 0.108 81.600 265.313 81.696 ; - RECT 0.108 82.368 265.313 82.464 ; - RECT 0.108 83.136 265.313 83.232 ; - RECT 0.108 83.904 265.313 84.000 ; - RECT 0.108 84.672 265.313 84.768 ; - RECT 0.108 85.440 265.313 85.536 ; - RECT 0.108 86.208 265.313 86.304 ; - RECT 0.108 86.976 265.313 87.072 ; - RECT 0.108 87.744 265.313 87.840 ; - RECT 0.108 88.512 265.313 88.608 ; - RECT 0.108 89.280 265.313 89.376 ; - RECT 0.108 90.048 265.313 90.144 ; - RECT 0.108 90.816 265.313 90.912 ; - RECT 0.108 91.584 265.313 91.680 ; - RECT 0.108 92.352 265.313 92.448 ; - RECT 0.108 93.120 265.313 93.216 ; - RECT 0.108 93.888 265.313 93.984 ; - RECT 0.108 94.656 265.313 94.752 ; - RECT 0.108 95.424 265.313 95.520 ; - RECT 0.108 96.192 265.313 96.288 ; - RECT 0.108 96.960 265.313 97.056 ; - RECT 0.108 97.728 265.313 97.824 ; - RECT 0.108 98.496 265.313 98.592 ; - RECT 0.108 99.264 265.313 99.360 ; - RECT 0.108 100.032 265.313 100.128 ; - RECT 0.108 100.800 265.313 100.896 ; - RECT 0.108 101.568 265.313 101.664 ; - RECT 0.108 102.336 265.313 102.432 ; - RECT 0.108 103.104 265.313 103.200 ; - RECT 0.108 103.872 265.313 103.968 ; - RECT 0.108 104.640 265.313 104.736 ; - RECT 0.108 105.408 265.313 105.504 ; - RECT 0.108 106.176 265.313 106.272 ; - RECT 0.108 106.944 265.313 107.040 ; - RECT 0.108 107.712 265.313 107.808 ; - RECT 0.108 108.480 265.313 108.576 ; - RECT 0.108 109.248 265.313 109.344 ; - RECT 0.108 110.016 265.313 110.112 ; - RECT 0.108 110.784 265.313 110.880 ; - RECT 0.108 111.552 265.313 111.648 ; - RECT 0.108 112.320 265.313 112.416 ; - RECT 0.108 113.088 265.313 113.184 ; - RECT 0.108 113.856 265.313 113.952 ; - RECT 0.108 114.624 265.313 114.720 ; - RECT 0.108 115.392 265.313 115.488 ; - RECT 0.108 116.160 265.313 116.256 ; - RECT 0.108 116.928 265.313 117.024 ; - RECT 0.108 117.696 265.313 117.792 ; - RECT 0.108 118.464 265.313 118.560 ; - RECT 0.108 119.232 265.313 119.328 ; - RECT 0.108 120.000 265.313 120.096 ; - RECT 0.108 120.768 265.313 120.864 ; - RECT 0.108 121.536 265.313 121.632 ; - RECT 0.108 122.304 265.313 122.400 ; - RECT 0.108 123.072 265.313 123.168 ; - RECT 0.108 123.840 265.313 123.936 ; - RECT 0.108 124.608 265.313 124.704 ; - RECT 0.108 125.376 265.313 125.472 ; - RECT 0.108 126.144 265.313 126.240 ; - RECT 0.108 126.912 265.313 127.008 ; - RECT 0.108 127.680 265.313 127.776 ; - RECT 0.108 128.448 265.313 128.544 ; - RECT 0.108 129.216 265.313 129.312 ; - RECT 0.108 129.984 265.313 130.080 ; - RECT 0.108 130.752 265.313 130.848 ; - RECT 0.108 131.520 265.313 131.616 ; - RECT 0.108 132.288 265.313 132.384 ; - RECT 0.108 133.056 265.313 133.152 ; - RECT 0.108 133.824 265.313 133.920 ; - RECT 0.108 134.592 265.313 134.688 ; - RECT 0.108 135.360 265.313 135.456 ; - RECT 0.108 136.128 265.313 136.224 ; - RECT 0.108 136.896 265.313 136.992 ; - RECT 0.108 137.664 265.313 137.760 ; - RECT 0.108 138.432 265.313 138.528 ; - RECT 0.108 139.200 265.313 139.296 ; - RECT 0.108 139.968 265.313 140.064 ; - RECT 0.108 140.736 265.313 140.832 ; - RECT 0.108 141.504 265.313 141.600 ; - RECT 0.108 142.272 265.313 142.368 ; - RECT 0.108 143.040 265.313 143.136 ; - RECT 0.108 143.808 265.313 143.904 ; - RECT 0.108 144.576 265.313 144.672 ; - RECT 0.108 145.344 265.313 145.440 ; - RECT 0.108 146.112 265.313 146.208 ; - RECT 0.108 146.880 265.313 146.976 ; - RECT 0.108 147.648 265.313 147.744 ; - RECT 0.108 148.416 265.313 148.512 ; - RECT 0.108 149.184 265.313 149.280 ; - RECT 0.108 149.952 265.313 150.048 ; - RECT 0.108 150.720 265.313 150.816 ; - RECT 0.108 151.488 265.313 151.584 ; - RECT 0.108 152.256 265.313 152.352 ; - RECT 0.108 153.024 265.313 153.120 ; - RECT 0.108 153.792 265.313 153.888 ; - RECT 0.108 154.560 265.313 154.656 ; - RECT 0.108 155.328 265.313 155.424 ; - RECT 0.108 156.096 265.313 156.192 ; - RECT 0.108 156.864 265.313 156.960 ; - RECT 0.108 157.632 265.313 157.728 ; - RECT 0.108 158.400 265.313 158.496 ; - RECT 0.108 159.168 265.313 159.264 ; - RECT 0.108 159.936 265.313 160.032 ; - RECT 0.108 160.704 265.313 160.800 ; - RECT 0.108 161.472 265.313 161.568 ; - RECT 0.108 162.240 265.313 162.336 ; - RECT 0.108 163.008 265.313 163.104 ; - RECT 0.108 163.776 265.313 163.872 ; - RECT 0.108 164.544 265.313 164.640 ; - RECT 0.108 165.312 265.313 165.408 ; + RECT 0.216 0.240 163.018 0.336 ; + RECT 0.216 1.008 163.018 1.104 ; + RECT 0.216 1.776 163.018 1.872 ; + RECT 0.216 2.544 163.018 2.640 ; + RECT 0.216 3.312 163.018 3.408 ; + RECT 0.216 4.080 163.018 4.176 ; + RECT 0.216 4.848 163.018 4.944 ; + RECT 0.216 5.616 163.018 5.712 ; + RECT 0.216 6.384 163.018 6.480 ; + RECT 0.216 7.152 163.018 7.248 ; + RECT 0.216 7.920 163.018 8.016 ; + RECT 0.216 8.688 163.018 8.784 ; + RECT 0.216 9.456 163.018 9.552 ; + RECT 0.216 10.224 163.018 10.320 ; + RECT 0.216 10.992 163.018 11.088 ; + RECT 0.216 11.760 163.018 11.856 ; + RECT 0.216 12.528 163.018 12.624 ; + RECT 0.216 13.296 163.018 13.392 ; + RECT 0.216 14.064 163.018 14.160 ; + RECT 0.216 14.832 163.018 14.928 ; + RECT 0.216 15.600 163.018 15.696 ; + RECT 0.216 16.368 163.018 16.464 ; + RECT 0.216 17.136 163.018 17.232 ; + RECT 0.216 17.904 163.018 18.000 ; + RECT 0.216 18.672 163.018 18.768 ; + RECT 0.216 19.440 163.018 19.536 ; + RECT 0.216 20.208 163.018 20.304 ; + RECT 0.216 20.976 163.018 21.072 ; + RECT 0.216 21.744 163.018 21.840 ; + RECT 0.216 22.512 163.018 22.608 ; + RECT 0.216 23.280 163.018 23.376 ; + RECT 0.216 24.048 163.018 24.144 ; + RECT 0.216 24.816 163.018 24.912 ; + RECT 0.216 25.584 163.018 25.680 ; + RECT 0.216 26.352 163.018 26.448 ; + RECT 0.216 27.120 163.018 27.216 ; + RECT 0.216 27.888 163.018 27.984 ; + RECT 0.216 28.656 163.018 28.752 ; + RECT 0.216 29.424 163.018 29.520 ; + RECT 0.216 30.192 163.018 30.288 ; + RECT 0.216 30.960 163.018 31.056 ; + RECT 0.216 31.728 163.018 31.824 ; + RECT 0.216 32.496 163.018 32.592 ; + RECT 0.216 33.264 163.018 33.360 ; + RECT 0.216 34.032 163.018 34.128 ; + RECT 0.216 34.800 163.018 34.896 ; + RECT 0.216 35.568 163.018 35.664 ; + RECT 0.216 36.336 163.018 36.432 ; + RECT 0.216 37.104 163.018 37.200 ; + RECT 0.216 37.872 163.018 37.968 ; + RECT 0.216 38.640 163.018 38.736 ; + RECT 0.216 39.408 163.018 39.504 ; + RECT 0.216 40.176 163.018 40.272 ; + RECT 0.216 40.944 163.018 41.040 ; + RECT 0.216 41.712 163.018 41.808 ; + RECT 0.216 42.480 163.018 42.576 ; + RECT 0.216 43.248 163.018 43.344 ; + RECT 0.216 44.016 163.018 44.112 ; + RECT 0.216 44.784 163.018 44.880 ; + RECT 0.216 45.552 163.018 45.648 ; + RECT 0.216 46.320 163.018 46.416 ; + RECT 0.216 47.088 163.018 47.184 ; + RECT 0.216 47.856 163.018 47.952 ; + RECT 0.216 48.624 163.018 48.720 ; + RECT 0.216 49.392 163.018 49.488 ; + RECT 0.216 50.160 163.018 50.256 ; + RECT 0.216 50.928 163.018 51.024 ; + RECT 0.216 51.696 163.018 51.792 ; + RECT 0.216 52.464 163.018 52.560 ; + RECT 0.216 53.232 163.018 53.328 ; + RECT 0.216 54.000 163.018 54.096 ; + RECT 0.216 54.768 163.018 54.864 ; + RECT 0.216 55.536 163.018 55.632 ; + RECT 0.216 56.304 163.018 56.400 ; + RECT 0.216 57.072 163.018 57.168 ; + RECT 0.216 57.840 163.018 57.936 ; + RECT 0.216 58.608 163.018 58.704 ; + RECT 0.216 59.376 163.018 59.472 ; + RECT 0.216 60.144 163.018 60.240 ; + RECT 0.216 60.912 163.018 61.008 ; + RECT 0.216 61.680 163.018 61.776 ; + RECT 0.216 62.448 163.018 62.544 ; + RECT 0.216 63.216 163.018 63.312 ; + RECT 0.216 63.984 163.018 64.080 ; + RECT 0.216 64.752 163.018 64.848 ; + RECT 0.216 65.520 163.018 65.616 ; + RECT 0.216 66.288 163.018 66.384 ; + RECT 0.216 67.056 163.018 67.152 ; + RECT 0.216 67.824 163.018 67.920 ; + RECT 0.216 68.592 163.018 68.688 ; + RECT 0.216 69.360 163.018 69.456 ; + RECT 0.216 70.128 163.018 70.224 ; + RECT 0.216 70.896 163.018 70.992 ; + RECT 0.216 71.664 163.018 71.760 ; + RECT 0.216 72.432 163.018 72.528 ; + RECT 0.216 73.200 163.018 73.296 ; + RECT 0.216 73.968 163.018 74.064 ; + RECT 0.216 74.736 163.018 74.832 ; + RECT 0.216 75.504 163.018 75.600 ; + RECT 0.216 76.272 163.018 76.368 ; + RECT 0.216 77.040 163.018 77.136 ; + RECT 0.216 77.808 163.018 77.904 ; + RECT 0.216 78.576 163.018 78.672 ; + RECT 0.216 79.344 163.018 79.440 ; + RECT 0.216 80.112 163.018 80.208 ; + RECT 0.216 80.880 163.018 80.976 ; + RECT 0.216 81.648 163.018 81.744 ; + RECT 0.216 82.416 163.018 82.512 ; + RECT 0.216 83.184 163.018 83.280 ; + RECT 0.216 83.952 163.018 84.048 ; + RECT 0.216 84.720 163.018 84.816 ; + RECT 0.216 85.488 163.018 85.584 ; + RECT 0.216 86.256 163.018 86.352 ; + RECT 0.216 87.024 163.018 87.120 ; + RECT 0.216 87.792 163.018 87.888 ; + RECT 0.216 88.560 163.018 88.656 ; + RECT 0.216 89.328 163.018 89.424 ; + RECT 0.216 90.096 163.018 90.192 ; + RECT 0.216 90.864 163.018 90.960 ; + RECT 0.216 91.632 163.018 91.728 ; + RECT 0.216 92.400 163.018 92.496 ; + RECT 0.216 93.168 163.018 93.264 ; + RECT 0.216 93.936 163.018 94.032 ; + RECT 0.216 94.704 163.018 94.800 ; + RECT 0.216 95.472 163.018 95.568 ; + RECT 0.216 96.240 163.018 96.336 ; + RECT 0.216 97.008 163.018 97.104 ; + RECT 0.216 97.776 163.018 97.872 ; + RECT 0.216 98.544 163.018 98.640 ; + RECT 0.216 99.312 163.018 99.408 ; + RECT 0.216 100.080 163.018 100.176 ; + RECT 0.216 100.848 163.018 100.944 ; + RECT 0.216 101.616 163.018 101.712 ; + RECT 0.216 102.384 163.018 102.480 ; + RECT 0.216 103.152 163.018 103.248 ; + RECT 0.216 103.920 163.018 104.016 ; + RECT 0.216 104.688 163.018 104.784 ; + RECT 0.216 105.456 163.018 105.552 ; + RECT 0.216 106.224 163.018 106.320 ; + RECT 0.216 106.992 163.018 107.088 ; + RECT 0.216 107.760 163.018 107.856 ; + RECT 0.216 108.528 163.018 108.624 ; + RECT 0.216 109.296 163.018 109.392 ; + RECT 0.216 110.064 163.018 110.160 ; + RECT 0.216 110.832 163.018 110.928 ; + RECT 0.216 111.600 163.018 111.696 ; + RECT 0.216 112.368 163.018 112.464 ; + RECT 0.216 113.136 163.018 113.232 ; + RECT 0.216 113.904 163.018 114.000 ; + RECT 0.216 114.672 163.018 114.768 ; + RECT 0.216 115.440 163.018 115.536 ; + RECT 0.216 116.208 163.018 116.304 ; + RECT 0.216 116.976 163.018 117.072 ; + RECT 0.216 117.744 163.018 117.840 ; + RECT 0.216 118.512 163.018 118.608 ; + RECT 0.216 119.280 163.018 119.376 ; + RECT 0.216 120.048 163.018 120.144 ; + RECT 0.216 120.816 163.018 120.912 ; + RECT 0.216 121.584 163.018 121.680 ; + RECT 0.216 122.352 163.018 122.448 ; + RECT 0.216 123.120 163.018 123.216 ; + RECT 0.216 123.888 163.018 123.984 ; + RECT 0.216 124.656 163.018 124.752 ; + RECT 0.216 125.424 163.018 125.520 ; + RECT 0.216 126.192 163.018 126.288 ; + RECT 0.216 126.960 163.018 127.056 ; + RECT 0.216 127.728 163.018 127.824 ; + RECT 0.216 128.496 163.018 128.592 ; + RECT 0.216 129.264 163.018 129.360 ; + RECT 0.216 130.032 163.018 130.128 ; + RECT 0.216 130.800 163.018 130.896 ; + RECT 0.216 131.568 163.018 131.664 ; + RECT 0.216 132.336 163.018 132.432 ; + RECT 0.216 133.104 163.018 133.200 ; + RECT 0.216 133.872 163.018 133.968 ; + RECT 0.216 134.640 163.018 134.736 ; + RECT 0.216 135.408 163.018 135.504 ; + RECT 0.216 136.176 163.018 136.272 ; + RECT 0.216 136.944 163.018 137.040 ; + RECT 0.216 137.712 163.018 137.808 ; + RECT 0.216 138.480 163.018 138.576 ; + RECT 0.216 139.248 163.018 139.344 ; + RECT 0.216 140.016 163.018 140.112 ; + RECT 0.216 140.784 163.018 140.880 ; + RECT 0.216 141.552 163.018 141.648 ; + RECT 0.216 142.320 163.018 142.416 ; + RECT 0.216 143.088 163.018 143.184 ; + RECT 0.216 143.856 163.018 143.952 ; + RECT 0.216 144.624 163.018 144.720 ; + RECT 0.216 145.392 163.018 145.488 ; + RECT 0.216 146.160 163.018 146.256 ; + RECT 0.216 146.928 163.018 147.024 ; + RECT 0.216 147.696 163.018 147.792 ; + RECT 0.216 148.464 163.018 148.560 ; + RECT 0.216 149.232 163.018 149.328 ; + RECT 0.216 150.000 163.018 150.096 ; + RECT 0.216 150.768 163.018 150.864 ; + RECT 0.216 151.536 163.018 151.632 ; + RECT 0.216 152.304 163.018 152.400 ; + RECT 0.216 153.072 163.018 153.168 ; + RECT 0.216 153.840 163.018 153.936 ; + RECT 0.216 154.608 163.018 154.704 ; + RECT 0.216 155.376 163.018 155.472 ; + RECT 0.216 156.144 163.018 156.240 ; + RECT 0.216 156.912 163.018 157.008 ; + RECT 0.216 157.680 163.018 157.776 ; + RECT 0.216 158.448 163.018 158.544 ; + RECT 0.216 159.216 163.018 159.312 ; + RECT 0.216 159.984 163.018 160.080 ; + RECT 0.216 160.752 163.018 160.848 ; + RECT 0.216 161.520 163.018 161.616 ; + RECT 0.216 162.288 163.018 162.384 ; + RECT 0.216 163.056 163.018 163.152 ; + RECT 0.216 163.824 163.018 163.920 ; + RECT 0.216 164.592 163.018 164.688 ; + RECT 0.216 165.360 163.018 165.456 ; + RECT 0.216 166.128 163.018 166.224 ; + RECT 0.216 166.896 163.018 166.992 ; + RECT 0.216 167.664 163.018 167.760 ; + RECT 0.216 168.432 163.018 168.528 ; + RECT 0.216 169.200 163.018 169.296 ; + RECT 0.216 169.968 163.018 170.064 ; + RECT 0.216 170.736 163.018 170.832 ; + RECT 0.216 171.504 163.018 171.600 ; + RECT 0.216 172.272 163.018 172.368 ; + RECT 0.216 173.040 163.018 173.136 ; + RECT 0.216 173.808 163.018 173.904 ; + RECT 0.216 174.576 163.018 174.672 ; + RECT 0.216 175.344 163.018 175.440 ; + RECT 0.216 176.112 163.018 176.208 ; + RECT 0.216 176.880 163.018 176.976 ; + RECT 0.216 177.648 163.018 177.744 ; + RECT 0.216 178.416 163.018 178.512 ; + RECT 0.216 179.184 163.018 179.280 ; + RECT 0.216 179.952 163.018 180.048 ; + RECT 0.216 180.720 163.018 180.816 ; + RECT 0.216 181.488 163.018 181.584 ; + RECT 0.216 182.256 163.018 182.352 ; + RECT 0.216 183.024 163.018 183.120 ; + RECT 0.216 183.792 163.018 183.888 ; + RECT 0.216 184.560 163.018 184.656 ; + RECT 0.216 185.328 163.018 185.424 ; + RECT 0.216 186.096 163.018 186.192 ; + RECT 0.216 186.864 163.018 186.960 ; + RECT 0.216 187.632 163.018 187.728 ; + RECT 0.216 188.400 163.018 188.496 ; + RECT 0.216 189.168 163.018 189.264 ; + RECT 0.216 189.936 163.018 190.032 ; + RECT 0.216 190.704 163.018 190.800 ; + RECT 0.216 191.472 163.018 191.568 ; + RECT 0.216 192.240 163.018 192.336 ; + RECT 0.216 193.008 163.018 193.104 ; + RECT 0.216 193.776 163.018 193.872 ; + RECT 0.216 194.544 163.018 194.640 ; + RECT 0.216 195.312 163.018 195.408 ; + RECT 0.216 196.080 163.018 196.176 ; + RECT 0.216 196.848 163.018 196.944 ; + RECT 0.216 197.616 163.018 197.712 ; + RECT 0.216 198.384 163.018 198.480 ; + RECT 0.216 199.152 163.018 199.248 ; + RECT 0.216 199.920 163.018 200.016 ; + RECT 0.216 200.688 163.018 200.784 ; + RECT 0.216 201.456 163.018 201.552 ; + RECT 0.216 202.224 163.018 202.320 ; + RECT 0.216 202.992 163.018 203.088 ; + RECT 0.216 203.760 163.018 203.856 ; + RECT 0.216 204.528 163.018 204.624 ; + RECT 0.216 205.296 163.018 205.392 ; + RECT 0.216 206.064 163.018 206.160 ; + RECT 0.216 206.832 163.018 206.928 ; + RECT 0.216 207.600 163.018 207.696 ; + RECT 0.216 208.368 163.018 208.464 ; + RECT 0.216 209.136 163.018 209.232 ; + RECT 0.216 209.904 163.018 210.000 ; + RECT 0.216 210.672 163.018 210.768 ; + RECT 0.216 211.440 163.018 211.536 ; + RECT 0.216 212.208 163.018 212.304 ; + RECT 0.216 212.976 163.018 213.072 ; + RECT 0.216 213.744 163.018 213.840 ; + RECT 0.216 214.512 163.018 214.608 ; + RECT 0.216 215.280 163.018 215.376 ; + RECT 0.216 216.048 163.018 216.144 ; + RECT 0.216 216.816 163.018 216.912 ; + RECT 0.216 217.584 163.018 217.680 ; + RECT 0.216 218.352 163.018 218.448 ; + RECT 0.216 219.120 163.018 219.216 ; + RECT 0.216 219.888 163.018 219.984 ; + RECT 0.216 220.656 163.018 220.752 ; + RECT 0.216 221.424 163.018 221.520 ; + RECT 0.216 222.192 163.018 222.288 ; + RECT 0.216 222.960 163.018 223.056 ; + RECT 0.216 223.728 163.018 223.824 ; + RECT 0.216 224.496 163.018 224.592 ; + RECT 0.216 225.264 163.018 225.360 ; + RECT 0.216 226.032 163.018 226.128 ; + RECT 0.216 226.800 163.018 226.896 ; + RECT 0.216 227.568 163.018 227.664 ; + RECT 0.216 228.336 163.018 228.432 ; + RECT 0.216 229.104 163.018 229.200 ; + RECT 0.216 229.872 163.018 229.968 ; + RECT 0.216 230.640 163.018 230.736 ; + RECT 0.216 231.408 163.018 231.504 ; + RECT 0.216 232.176 163.018 232.272 ; + RECT 0.216 232.944 163.018 233.040 ; + RECT 0.216 233.712 163.018 233.808 ; + RECT 0.216 234.480 163.018 234.576 ; + RECT 0.216 235.248 163.018 235.344 ; + RECT 0.216 236.016 163.018 236.112 ; + RECT 0.216 236.784 163.018 236.880 ; + RECT 0.216 237.552 163.018 237.648 ; + RECT 0.216 238.320 163.018 238.416 ; + RECT 0.216 239.088 163.018 239.184 ; + RECT 0.216 239.856 163.018 239.952 ; + RECT 0.216 240.624 163.018 240.720 ; + RECT 0.216 241.392 163.018 241.488 ; + RECT 0.216 242.160 163.018 242.256 ; + RECT 0.216 242.928 163.018 243.024 ; + RECT 0.216 243.696 163.018 243.792 ; + RECT 0.216 244.464 163.018 244.560 ; + RECT 0.216 245.232 163.018 245.328 ; + RECT 0.216 246.000 163.018 246.096 ; + RECT 0.216 246.768 163.018 246.864 ; + RECT 0.216 247.536 163.018 247.632 ; + RECT 0.216 248.304 163.018 248.400 ; + RECT 0.216 249.072 163.018 249.168 ; + RECT 0.216 249.840 163.018 249.936 ; + RECT 0.216 250.608 163.018 250.704 ; + RECT 0.216 251.376 163.018 251.472 ; + RECT 0.216 252.144 163.018 252.240 ; + RECT 0.216 252.912 163.018 253.008 ; + RECT 0.216 253.680 163.018 253.776 ; + RECT 0.216 254.448 163.018 254.544 ; + RECT 0.216 255.216 163.018 255.312 ; + RECT 0.216 255.984 163.018 256.080 ; + RECT 0.216 256.752 163.018 256.848 ; + RECT 0.216 257.520 163.018 257.616 ; + RECT 0.216 258.288 163.018 258.384 ; + RECT 0.216 259.056 163.018 259.152 ; + RECT 0.216 259.824 163.018 259.920 ; + RECT 0.216 260.592 163.018 260.688 ; + RECT 0.216 261.360 163.018 261.456 ; + RECT 0.216 262.128 163.018 262.224 ; + RECT 0.216 262.896 163.018 262.992 ; + RECT 0.216 263.664 163.018 263.760 ; + RECT 0.216 264.432 163.018 264.528 ; + RECT 0.216 265.200 163.018 265.296 ; + RECT 0.216 265.968 163.018 266.064 ; + RECT 0.216 266.736 163.018 266.832 ; + RECT 0.216 267.504 163.018 267.600 ; + RECT 0.216 268.272 163.018 268.368 ; + RECT 0.216 269.040 163.018 269.136 ; + RECT 0.216 269.808 163.018 269.904 ; + RECT 0.216 270.576 163.018 270.672 ; + RECT 0.216 271.344 163.018 271.440 ; + RECT 0.216 272.112 163.018 272.208 ; + RECT 0.216 272.880 163.018 272.976 ; + RECT 0.216 273.648 163.018 273.744 ; + RECT 0.216 274.416 163.018 274.512 ; + RECT 0.216 275.184 163.018 275.280 ; + RECT 0.216 275.952 163.018 276.048 ; + RECT 0.216 276.720 163.018 276.816 ; + RECT 0.216 277.488 163.018 277.584 ; + RECT 0.216 278.256 163.018 278.352 ; + RECT 0.216 279.024 163.018 279.120 ; + RECT 0.216 279.792 163.018 279.888 ; + RECT 0.216 280.560 163.018 280.656 ; + RECT 0.216 281.328 163.018 281.424 ; + RECT 0.216 282.096 163.018 282.192 ; + RECT 0.216 282.864 163.018 282.960 ; + RECT 0.216 283.632 163.018 283.728 ; + RECT 0.216 284.400 163.018 284.496 ; + RECT 0.216 285.168 163.018 285.264 ; + RECT 0.216 285.936 163.018 286.032 ; + RECT 0.216 286.704 163.018 286.800 ; + RECT 0.216 287.472 163.018 287.568 ; + RECT 0.216 288.240 163.018 288.336 ; + RECT 0.216 289.008 163.018 289.104 ; + RECT 0.216 289.776 163.018 289.872 ; + RECT 0.216 290.544 163.018 290.640 ; + RECT 0.216 291.312 163.018 291.408 ; + RECT 0.216 292.080 163.018 292.176 ; + RECT 0.216 292.848 163.018 292.944 ; + RECT 0.216 293.616 163.018 293.712 ; + RECT 0.216 294.384 163.018 294.480 ; + RECT 0.216 295.152 163.018 295.248 ; + RECT 0.216 295.920 163.018 296.016 ; + RECT 0.216 296.688 163.018 296.784 ; + RECT 0.216 297.456 163.018 297.552 ; + RECT 0.216 298.224 163.018 298.320 ; + RECT 0.216 298.992 163.018 299.088 ; + RECT 0.216 299.760 163.018 299.856 ; + RECT 0.216 300.528 163.018 300.624 ; + RECT 0.216 301.296 163.018 301.392 ; + RECT 0.216 302.064 163.018 302.160 ; + RECT 0.216 302.832 163.018 302.928 ; + RECT 0.216 303.600 163.018 303.696 ; + RECT 0.216 304.368 163.018 304.464 ; + RECT 0.216 305.136 163.018 305.232 ; + RECT 0.216 305.904 163.018 306.000 ; + RECT 0.216 306.672 163.018 306.768 ; + RECT 0.216 307.440 163.018 307.536 ; + RECT 0.216 308.208 163.018 308.304 ; + RECT 0.216 308.976 163.018 309.072 ; + RECT 0.216 309.744 163.018 309.840 ; + RECT 0.216 310.512 163.018 310.608 ; + RECT 0.216 311.280 163.018 311.376 ; + RECT 0.216 312.048 163.018 312.144 ; + RECT 0.216 312.816 163.018 312.912 ; + RECT 0.216 313.584 163.018 313.680 ; + RECT 0.216 314.352 163.018 314.448 ; + RECT 0.216 315.120 163.018 315.216 ; + RECT 0.216 315.888 163.018 315.984 ; + RECT 0.216 316.656 163.018 316.752 ; + RECT 0.216 317.424 163.018 317.520 ; + RECT 0.216 318.192 163.018 318.288 ; + RECT 0.216 318.960 163.018 319.056 ; + RECT 0.216 319.728 163.018 319.824 ; + RECT 0.216 320.496 163.018 320.592 ; + RECT 0.216 321.264 163.018 321.360 ; + RECT 0.216 322.032 163.018 322.128 ; + RECT 0.216 322.800 163.018 322.896 ; + RECT 0.216 323.568 163.018 323.664 ; + RECT 0.216 324.336 163.018 324.432 ; + RECT 0.216 325.104 163.018 325.200 ; + RECT 0.216 325.872 163.018 325.968 ; + RECT 0.216 326.640 163.018 326.736 ; + RECT 0.216 327.408 163.018 327.504 ; + RECT 0.216 328.176 163.018 328.272 ; + RECT 0.216 328.944 163.018 329.040 ; + RECT 0.216 329.712 163.018 329.808 ; + RECT 0.216 330.480 163.018 330.576 ; + RECT 0.216 331.248 163.018 331.344 ; + RECT 0.216 332.016 163.018 332.112 ; + RECT 0.216 332.784 163.018 332.880 ; + RECT 0.216 333.552 163.018 333.648 ; + RECT 0.216 334.320 163.018 334.416 ; + RECT 0.216 335.088 163.018 335.184 ; + RECT 0.216 335.856 163.018 335.952 ; + RECT 0.216 336.624 163.018 336.720 ; + RECT 0.216 337.392 163.018 337.488 ; + RECT 0.216 338.160 163.018 338.256 ; + RECT 0.216 338.928 163.018 339.024 ; + RECT 0.216 339.696 163.018 339.792 ; + RECT 0.216 340.464 163.018 340.560 ; + RECT 0.216 341.232 163.018 341.328 ; + RECT 0.216 342.000 163.018 342.096 ; + RECT 0.216 342.768 163.018 342.864 ; + RECT 0.216 343.536 163.018 343.632 ; + RECT 0.216 344.304 163.018 344.400 ; + RECT 0.216 345.072 163.018 345.168 ; + RECT 0.216 345.840 163.018 345.936 ; + RECT 0.216 346.608 163.018 346.704 ; + RECT 0.216 347.376 163.018 347.472 ; + RECT 0.216 348.144 163.018 348.240 ; + RECT 0.216 348.912 163.018 349.008 ; + RECT 0.216 349.680 163.018 349.776 ; + RECT 0.216 350.448 163.018 350.544 ; + RECT 0.216 351.216 163.018 351.312 ; + RECT 0.216 351.984 163.018 352.080 ; + RECT 0.216 352.752 163.018 352.848 ; + RECT 0.216 353.520 163.018 353.616 ; + RECT 0.216 354.288 163.018 354.384 ; + RECT 0.216 355.056 163.018 355.152 ; + RECT 0.216 355.824 163.018 355.920 ; + RECT 0.216 356.592 163.018 356.688 ; + RECT 0.216 357.360 163.018 357.456 ; + RECT 0.216 358.128 163.018 358.224 ; + RECT 0.216 358.896 163.018 358.992 ; + RECT 0.216 359.664 163.018 359.760 ; + RECT 0.216 360.432 163.018 360.528 ; + RECT 0.216 361.200 163.018 361.296 ; + RECT 0.216 361.968 163.018 362.064 ; + RECT 0.216 362.736 163.018 362.832 ; + RECT 0.216 363.504 163.018 363.600 ; + RECT 0.216 364.272 163.018 364.368 ; + RECT 0.216 365.040 163.018 365.136 ; + RECT 0.216 365.808 163.018 365.904 ; + RECT 0.216 366.576 163.018 366.672 ; + RECT 0.216 367.344 163.018 367.440 ; + RECT 0.216 368.112 163.018 368.208 ; + RECT 0.216 368.880 163.018 368.976 ; + RECT 0.216 369.648 163.018 369.744 ; + RECT 0.216 370.416 163.018 370.512 ; + RECT 0.216 371.184 163.018 371.280 ; + RECT 0.216 371.952 163.018 372.048 ; + RECT 0.216 372.720 163.018 372.816 ; + RECT 0.216 373.488 163.018 373.584 ; + RECT 0.216 374.256 163.018 374.352 ; + RECT 0.216 375.024 163.018 375.120 ; + RECT 0.216 375.792 163.018 375.888 ; + RECT 0.216 376.560 163.018 376.656 ; + RECT 0.216 377.328 163.018 377.424 ; + RECT 0.216 378.096 163.018 378.192 ; + RECT 0.216 378.864 163.018 378.960 ; + RECT 0.216 379.632 163.018 379.728 ; + RECT 0.216 380.400 163.018 380.496 ; + RECT 0.216 381.168 163.018 381.264 ; + RECT 0.216 381.936 163.018 382.032 ; + RECT 0.216 382.704 163.018 382.800 ; + RECT 0.216 383.472 163.018 383.568 ; + RECT 0.216 384.240 163.018 384.336 ; + RECT 0.216 385.008 163.018 385.104 ; + RECT 0.216 385.776 163.018 385.872 ; + RECT 0.216 386.544 163.018 386.640 ; + RECT 0.216 387.312 163.018 387.408 ; + RECT 0.216 388.080 163.018 388.176 ; + RECT 0.216 388.848 163.018 388.944 ; + RECT 0.216 389.616 163.018 389.712 ; + RECT 0.216 390.384 163.018 390.480 ; + RECT 0.216 391.152 163.018 391.248 ; + RECT 0.216 391.920 163.018 392.016 ; + RECT 0.216 392.688 163.018 392.784 ; + RECT 0.216 393.456 163.018 393.552 ; + RECT 0.216 394.224 163.018 394.320 ; + RECT 0.216 394.992 163.018 395.088 ; + RECT 0.216 395.760 163.018 395.856 ; + RECT 0.216 396.528 163.018 396.624 ; + RECT 0.216 397.296 163.018 397.392 ; + RECT 0.216 398.064 163.018 398.160 ; + RECT 0.216 398.832 163.018 398.928 ; + RECT 0.216 399.600 163.018 399.696 ; + RECT 0.216 400.368 163.018 400.464 ; + RECT 0.216 401.136 163.018 401.232 ; + RECT 0.216 401.904 163.018 402.000 ; + RECT 0.216 402.672 163.018 402.768 ; + RECT 0.216 403.440 163.018 403.536 ; + RECT 0.216 404.208 163.018 404.304 ; + RECT 0.216 404.976 163.018 405.072 ; + RECT 0.216 405.744 163.018 405.840 ; + RECT 0.216 406.512 163.018 406.608 ; + RECT 0.216 407.280 163.018 407.376 ; END END VDD OBS LAYER M1 ; - RECT 0 0 265.421 165.888 ; + RECT 0 0 163.234 408.085 ; LAYER M2 ; - RECT 0 0 265.421 165.888 ; + RECT 0 0 163.234 408.085 ; LAYER M3 ; - RECT 0 0 265.421 165.888 ; + RECT 0 0 163.234 408.085 ; LAYER M4 ; - RECT 0 0 265.421 165.888 ; + RECT 0 0 163.234 408.085 ; END END fakeram_512x2048_1r1w diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x256_1r1w.lef b/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x256_1r1w.lef index 93f4233..1cad111 100644 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x256_1r1w.lef +++ b/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x256_1r1w.lef @@ -3,15 +3,4623 @@ BUSBITCHARS "[]" ; MACRO fakeram_512x256_1r1w FOREIGN fakeram_512x256_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 265.421 BY 20.736 ; + SIZE 163.234 BY 90.686 ; CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.612 0.072 0.636 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.948 0.072 0.972 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.956 0.072 1.980 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.628 0.072 2.652 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.972 0.072 3.996 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.644 0.072 4.668 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.988 0.072 6.012 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.660 0.072 6.684 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wmask_in[20] + PIN w0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_wmask_in[21] + PIN w0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END w0_wmask_in[22] + PIN w0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.004 0.072 8.028 ; + END + END w0_wmask_in[23] + PIN w0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wmask_in[24] + PIN w0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.676 0.072 8.700 ; + END + END w0_wmask_in[25] + PIN w0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END w0_wmask_in[26] + PIN w0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wmask_in[27] + PIN w0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END w0_wmask_in[28] + PIN w0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.020 0.072 10.044 ; + END + END w0_wmask_in[29] + PIN w0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wmask_in[30] + PIN w0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.692 0.072 10.716 ; + END + END w0_wmask_in[31] + PIN w0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_wmask_in[32] + PIN w0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END w0_wmask_in[33] + PIN w0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.700 0.072 11.724 ; + END + END w0_wmask_in[34] + PIN w0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.036 0.072 12.060 ; + END + END w0_wmask_in[35] + PIN w0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wmask_in[36] + PIN w0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.708 0.072 12.732 ; + END + END w0_wmask_in[37] + PIN w0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.044 0.072 13.068 ; + END + END w0_wmask_in[38] + PIN w0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.380 0.072 13.404 ; + END + END w0_wmask_in[39] + PIN w0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wmask_in[40] + PIN w0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.052 0.072 14.076 ; + END + END w0_wmask_in[41] + PIN w0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_wmask_in[42] + PIN w0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.724 0.072 14.748 ; + END + END w0_wmask_in[43] + PIN w0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.060 0.072 15.084 ; + END + END w0_wmask_in[44] + PIN w0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wmask_in[45] + PIN w0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.732 0.072 15.756 ; + END + END w0_wmask_in[46] + PIN w0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.068 0.072 16.092 ; + END + END w0_wmask_in[47] + PIN w0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wmask_in[48] + PIN w0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.740 0.072 16.764 ; + END + END w0_wmask_in[49] + PIN w0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END w0_wmask_in[50] + PIN w0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.412 0.072 17.436 ; + END + END w0_wmask_in[51] + PIN w0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.748 0.072 17.772 ; + END + END w0_wmask_in[52] + PIN w0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.084 0.072 18.108 ; + END + END w0_wmask_in[53] + PIN w0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wmask_in[54] + PIN w0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.756 0.072 18.780 ; + END + END w0_wmask_in[55] + PIN w0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END w0_wmask_in[56] + PIN w0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.428 0.072 19.452 ; + END + END w0_wmask_in[57] + PIN w0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.764 0.072 19.788 ; + END + END w0_wmask_in[58] + PIN w0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.100 0.072 20.124 ; + END + END w0_wmask_in[59] + PIN w0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wmask_in[60] + PIN w0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.772 0.072 20.796 ; + END + END w0_wmask_in[61] + PIN w0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.108 0.072 21.132 ; + END + END w0_wmask_in[62] + PIN w0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wmask_in[63] + PIN w0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.780 0.072 21.804 ; + END + END w0_wmask_in[64] + PIN w0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.116 0.072 22.140 ; + END + END w0_wmask_in[65] + PIN w0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END w0_wmask_in[66] + PIN w0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.788 0.072 22.812 ; + END + END w0_wmask_in[67] + PIN w0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.124 0.072 23.148 ; + END + END w0_wmask_in[68] + PIN w0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.460 0.072 23.484 ; + END + END w0_wmask_in[69] + PIN w0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.796 0.072 23.820 ; + END + END w0_wmask_in[70] + PIN w0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.132 0.072 24.156 ; + END + END w0_wmask_in[71] + PIN w0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_wmask_in[72] + PIN w0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.804 0.072 24.828 ; + END + END w0_wmask_in[73] + PIN w0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.140 0.072 25.164 ; + END + END w0_wmask_in[74] + PIN w0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.476 0.072 25.500 ; + END + END w0_wmask_in[75] + PIN w0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.812 0.072 25.836 ; + END + END w0_wmask_in[76] + PIN w0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.148 0.072 26.172 ; + END + END w0_wmask_in[77] + PIN w0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.484 0.072 26.508 ; + END + END w0_wmask_in[78] + PIN w0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.820 0.072 26.844 ; + END + END w0_wmask_in[79] + PIN w0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.156 0.072 27.180 ; + END + END w0_wmask_in[80] + PIN w0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.492 0.072 27.516 ; + END + END w0_wmask_in[81] + PIN w0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.828 0.072 27.852 ; + END + END w0_wmask_in[82] + PIN w0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.164 0.072 28.188 ; + END + END w0_wmask_in[83] + PIN w0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.500 0.072 28.524 ; + END + END w0_wmask_in[84] + PIN w0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.836 0.072 28.860 ; + END + END w0_wmask_in[85] + PIN w0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.172 0.072 29.196 ; + END + END w0_wmask_in[86] + PIN w0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.508 0.072 29.532 ; + END + END w0_wmask_in[87] + PIN w0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.844 0.072 29.868 ; + END + END w0_wmask_in[88] + PIN w0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.180 0.072 30.204 ; + END + END w0_wmask_in[89] + PIN w0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.516 0.072 30.540 ; + END + END w0_wmask_in[90] + PIN w0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.852 0.072 30.876 ; + END + END w0_wmask_in[91] + PIN w0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.188 0.072 31.212 ; + END + END w0_wmask_in[92] + PIN w0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.524 0.072 31.548 ; + END + END w0_wmask_in[93] + PIN w0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.860 0.072 31.884 ; + END + END w0_wmask_in[94] + PIN w0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.196 0.072 32.220 ; + END + END w0_wmask_in[95] + PIN w0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.532 0.072 32.556 ; + END + END w0_wmask_in[96] + PIN w0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.868 0.072 32.892 ; + END + END w0_wmask_in[97] + PIN w0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.204 0.072 33.228 ; + END + END w0_wmask_in[98] + PIN w0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.540 0.072 33.564 ; + END + END w0_wmask_in[99] + PIN w0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.876 0.072 33.900 ; + END + END w0_wmask_in[100] + PIN w0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.212 0.072 34.236 ; + END + END w0_wmask_in[101] + PIN w0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.548 0.072 34.572 ; + END + END w0_wmask_in[102] + PIN w0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.884 0.072 34.908 ; + END + END w0_wmask_in[103] + PIN w0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.220 0.072 35.244 ; + END + END w0_wmask_in[104] + PIN w0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.556 0.072 35.580 ; + END + END w0_wmask_in[105] + PIN w0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.892 0.072 35.916 ; + END + END w0_wmask_in[106] + PIN w0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.228 0.072 36.252 ; + END + END w0_wmask_in[107] + PIN w0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.564 0.072 36.588 ; + END + END w0_wmask_in[108] + PIN w0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.900 0.072 36.924 ; + END + END w0_wmask_in[109] + PIN w0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.236 0.072 37.260 ; + END + END w0_wmask_in[110] + PIN w0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.572 0.072 37.596 ; + END + END w0_wmask_in[111] + PIN w0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.908 0.072 37.932 ; + END + END w0_wmask_in[112] + PIN w0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.244 0.072 38.268 ; + END + END w0_wmask_in[113] + PIN w0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.580 0.072 38.604 ; + END + END w0_wmask_in[114] + PIN w0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.916 0.072 38.940 ; + END + END w0_wmask_in[115] + PIN w0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.252 0.072 39.276 ; + END + END w0_wmask_in[116] + PIN w0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.588 0.072 39.612 ; + END + END w0_wmask_in[117] + PIN w0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.924 0.072 39.948 ; + END + END w0_wmask_in[118] + PIN w0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.260 0.072 40.284 ; + END + END w0_wmask_in[119] + PIN w0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.596 0.072 40.620 ; + END + END w0_wmask_in[120] + PIN w0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.932 0.072 40.956 ; + END + END w0_wmask_in[121] + PIN w0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.268 0.072 41.292 ; + END + END w0_wmask_in[122] + PIN w0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.604 0.072 41.628 ; + END + END w0_wmask_in[123] + PIN w0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.940 0.072 41.964 ; + END + END w0_wmask_in[124] + PIN w0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.276 0.072 42.300 ; + END + END w0_wmask_in[125] + PIN w0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.612 0.072 42.636 ; + END + END w0_wmask_in[126] + PIN w0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.948 0.072 42.972 ; + END + END w0_wmask_in[127] + PIN w0_wmask_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 0.276 163.234 0.300 ; + END + END w0_wmask_in[128] + PIN w0_wmask_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 0.612 163.234 0.636 ; + END + END w0_wmask_in[129] + PIN w0_wmask_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 0.948 163.234 0.972 ; + END + END w0_wmask_in[130] + PIN w0_wmask_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 1.284 163.234 1.308 ; + END + END w0_wmask_in[131] + PIN w0_wmask_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 1.620 163.234 1.644 ; + END + END w0_wmask_in[132] + PIN w0_wmask_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 1.956 163.234 1.980 ; + END + END w0_wmask_in[133] + PIN w0_wmask_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 2.292 163.234 2.316 ; + END + END w0_wmask_in[134] + PIN w0_wmask_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 2.628 163.234 2.652 ; + END + END w0_wmask_in[135] + PIN w0_wmask_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 2.964 163.234 2.988 ; + END + END w0_wmask_in[136] + PIN w0_wmask_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 3.300 163.234 3.324 ; + END + END w0_wmask_in[137] + PIN w0_wmask_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 3.636 163.234 3.660 ; + END + END w0_wmask_in[138] + PIN w0_wmask_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 3.972 163.234 3.996 ; + END + END w0_wmask_in[139] + PIN w0_wmask_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 4.308 163.234 4.332 ; + END + END w0_wmask_in[140] + PIN w0_wmask_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 4.644 163.234 4.668 ; + END + END w0_wmask_in[141] + PIN w0_wmask_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 4.980 163.234 5.004 ; + END + END w0_wmask_in[142] + PIN w0_wmask_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 5.316 163.234 5.340 ; + END + END w0_wmask_in[143] + PIN w0_wmask_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 5.652 163.234 5.676 ; + END + END w0_wmask_in[144] + PIN w0_wmask_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 5.988 163.234 6.012 ; + END + END w0_wmask_in[145] + PIN w0_wmask_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 6.324 163.234 6.348 ; + END + END w0_wmask_in[146] + PIN w0_wmask_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 6.660 163.234 6.684 ; + END + END w0_wmask_in[147] + PIN w0_wmask_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 6.996 163.234 7.020 ; + END + END w0_wmask_in[148] + PIN w0_wmask_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 7.332 163.234 7.356 ; + END + END w0_wmask_in[149] + PIN w0_wmask_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 7.668 163.234 7.692 ; + END + END w0_wmask_in[150] + PIN w0_wmask_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 8.004 163.234 8.028 ; + END + END w0_wmask_in[151] + PIN w0_wmask_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 8.340 163.234 8.364 ; + END + END w0_wmask_in[152] + PIN w0_wmask_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 8.676 163.234 8.700 ; + END + END w0_wmask_in[153] + PIN w0_wmask_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 9.012 163.234 9.036 ; + END + END w0_wmask_in[154] + PIN w0_wmask_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 9.348 163.234 9.372 ; + END + END w0_wmask_in[155] + PIN w0_wmask_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 9.684 163.234 9.708 ; + END + END w0_wmask_in[156] + PIN w0_wmask_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 10.020 163.234 10.044 ; + END + END w0_wmask_in[157] + PIN w0_wmask_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 10.356 163.234 10.380 ; + END + END w0_wmask_in[158] + PIN w0_wmask_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 10.692 163.234 10.716 ; + END + END w0_wmask_in[159] + PIN w0_wmask_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 11.028 163.234 11.052 ; + END + END w0_wmask_in[160] + PIN w0_wmask_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 11.364 163.234 11.388 ; + END + END w0_wmask_in[161] + PIN w0_wmask_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 11.700 163.234 11.724 ; + END + END w0_wmask_in[162] + PIN w0_wmask_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 12.036 163.234 12.060 ; + END + END w0_wmask_in[163] + PIN w0_wmask_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 12.372 163.234 12.396 ; + END + END w0_wmask_in[164] + PIN w0_wmask_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 12.708 163.234 12.732 ; + END + END w0_wmask_in[165] + PIN w0_wmask_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 13.044 163.234 13.068 ; + END + END w0_wmask_in[166] + PIN w0_wmask_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 13.380 163.234 13.404 ; + END + END w0_wmask_in[167] + PIN w0_wmask_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 13.716 163.234 13.740 ; + END + END w0_wmask_in[168] + PIN w0_wmask_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 14.052 163.234 14.076 ; + END + END w0_wmask_in[169] + PIN w0_wmask_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 14.388 163.234 14.412 ; + END + END w0_wmask_in[170] + PIN w0_wmask_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 14.724 163.234 14.748 ; + END + END w0_wmask_in[171] + PIN w0_wmask_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 15.060 163.234 15.084 ; + END + END w0_wmask_in[172] + PIN w0_wmask_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 15.396 163.234 15.420 ; + END + END w0_wmask_in[173] + PIN w0_wmask_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 15.732 163.234 15.756 ; + END + END w0_wmask_in[174] + PIN w0_wmask_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 16.068 163.234 16.092 ; + END + END w0_wmask_in[175] + PIN w0_wmask_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 16.404 163.234 16.428 ; + END + END w0_wmask_in[176] + PIN w0_wmask_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 16.740 163.234 16.764 ; + END + END w0_wmask_in[177] + PIN w0_wmask_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 17.076 163.234 17.100 ; + END + END w0_wmask_in[178] + PIN w0_wmask_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 17.412 163.234 17.436 ; + END + END w0_wmask_in[179] + PIN w0_wmask_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 17.748 163.234 17.772 ; + END + END w0_wmask_in[180] + PIN w0_wmask_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 18.084 163.234 18.108 ; + END + END w0_wmask_in[181] + PIN w0_wmask_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 18.420 163.234 18.444 ; + END + END w0_wmask_in[182] + PIN w0_wmask_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 18.756 163.234 18.780 ; + END + END w0_wmask_in[183] + PIN w0_wmask_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 19.092 163.234 19.116 ; + END + END w0_wmask_in[184] + PIN w0_wmask_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 19.428 163.234 19.452 ; + END + END w0_wmask_in[185] + PIN w0_wmask_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 19.764 163.234 19.788 ; + END + END w0_wmask_in[186] + PIN w0_wmask_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 20.100 163.234 20.124 ; + END + END w0_wmask_in[187] + PIN w0_wmask_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 20.436 163.234 20.460 ; + END + END w0_wmask_in[188] + PIN w0_wmask_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 20.772 163.234 20.796 ; + END + END w0_wmask_in[189] + PIN w0_wmask_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 21.108 163.234 21.132 ; + END + END w0_wmask_in[190] + PIN w0_wmask_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 21.444 163.234 21.468 ; + END + END w0_wmask_in[191] + PIN w0_wmask_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 21.780 163.234 21.804 ; + END + END w0_wmask_in[192] + PIN w0_wmask_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 22.116 163.234 22.140 ; + END + END w0_wmask_in[193] + PIN w0_wmask_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 22.452 163.234 22.476 ; + END + END w0_wmask_in[194] + PIN w0_wmask_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 22.788 163.234 22.812 ; + END + END w0_wmask_in[195] + PIN w0_wmask_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 23.124 163.234 23.148 ; + END + END w0_wmask_in[196] + PIN w0_wmask_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 23.460 163.234 23.484 ; + END + END w0_wmask_in[197] + PIN w0_wmask_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 23.796 163.234 23.820 ; + END + END w0_wmask_in[198] + PIN w0_wmask_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 24.132 163.234 24.156 ; + END + END w0_wmask_in[199] + PIN w0_wmask_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 24.468 163.234 24.492 ; + END + END w0_wmask_in[200] + PIN w0_wmask_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 24.804 163.234 24.828 ; + END + END w0_wmask_in[201] + PIN w0_wmask_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 25.140 163.234 25.164 ; + END + END w0_wmask_in[202] + PIN w0_wmask_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 25.476 163.234 25.500 ; + END + END w0_wmask_in[203] + PIN w0_wmask_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 25.812 163.234 25.836 ; + END + END w0_wmask_in[204] + PIN w0_wmask_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 26.148 163.234 26.172 ; + END + END w0_wmask_in[205] + PIN w0_wmask_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 26.484 163.234 26.508 ; + END + END w0_wmask_in[206] + PIN w0_wmask_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 26.820 163.234 26.844 ; + END + END w0_wmask_in[207] + PIN w0_wmask_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 27.156 163.234 27.180 ; + END + END w0_wmask_in[208] + PIN w0_wmask_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 27.492 163.234 27.516 ; + END + END w0_wmask_in[209] + PIN w0_wmask_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 27.828 163.234 27.852 ; + END + END w0_wmask_in[210] + PIN w0_wmask_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 28.164 163.234 28.188 ; + END + END w0_wmask_in[211] + PIN w0_wmask_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 28.500 163.234 28.524 ; + END + END w0_wmask_in[212] + PIN w0_wmask_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 28.836 163.234 28.860 ; + END + END w0_wmask_in[213] + PIN w0_wmask_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 29.172 163.234 29.196 ; + END + END w0_wmask_in[214] + PIN w0_wmask_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 29.508 163.234 29.532 ; + END + END w0_wmask_in[215] + PIN w0_wmask_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 29.844 163.234 29.868 ; + END + END w0_wmask_in[216] + PIN w0_wmask_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 30.180 163.234 30.204 ; + END + END w0_wmask_in[217] + PIN w0_wmask_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 30.516 163.234 30.540 ; + END + END w0_wmask_in[218] + PIN w0_wmask_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 30.852 163.234 30.876 ; + END + END w0_wmask_in[219] + PIN w0_wmask_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 31.188 163.234 31.212 ; + END + END w0_wmask_in[220] + PIN w0_wmask_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 31.524 163.234 31.548 ; + END + END w0_wmask_in[221] + PIN w0_wmask_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 31.860 163.234 31.884 ; + END + END w0_wmask_in[222] + PIN w0_wmask_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 32.196 163.234 32.220 ; + END + END w0_wmask_in[223] + PIN w0_wmask_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 32.532 163.234 32.556 ; + END + END w0_wmask_in[224] + PIN w0_wmask_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 32.868 163.234 32.892 ; + END + END w0_wmask_in[225] + PIN w0_wmask_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 33.204 163.234 33.228 ; + END + END w0_wmask_in[226] + PIN w0_wmask_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 33.540 163.234 33.564 ; + END + END w0_wmask_in[227] + PIN w0_wmask_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 33.876 163.234 33.900 ; + END + END w0_wmask_in[228] + PIN w0_wmask_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 34.212 163.234 34.236 ; + END + END w0_wmask_in[229] + PIN w0_wmask_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 34.548 163.234 34.572 ; + END + END w0_wmask_in[230] + PIN w0_wmask_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 34.884 163.234 34.908 ; + END + END w0_wmask_in[231] + PIN w0_wmask_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 35.220 163.234 35.244 ; + END + END w0_wmask_in[232] + PIN w0_wmask_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 35.556 163.234 35.580 ; + END + END w0_wmask_in[233] + PIN w0_wmask_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 35.892 163.234 35.916 ; + END + END w0_wmask_in[234] + PIN w0_wmask_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 36.228 163.234 36.252 ; + END + END w0_wmask_in[235] + PIN w0_wmask_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 36.564 163.234 36.588 ; + END + END w0_wmask_in[236] + PIN w0_wmask_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 36.900 163.234 36.924 ; + END + END w0_wmask_in[237] + PIN w0_wmask_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 37.236 163.234 37.260 ; + END + END w0_wmask_in[238] + PIN w0_wmask_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 37.572 163.234 37.596 ; + END + END w0_wmask_in[239] + PIN w0_wmask_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 37.908 163.234 37.932 ; + END + END w0_wmask_in[240] + PIN w0_wmask_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 38.244 163.234 38.268 ; + END + END w0_wmask_in[241] + PIN w0_wmask_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 38.580 163.234 38.604 ; + END + END w0_wmask_in[242] + PIN w0_wmask_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 38.916 163.234 38.940 ; + END + END w0_wmask_in[243] + PIN w0_wmask_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 39.252 163.234 39.276 ; + END + END w0_wmask_in[244] + PIN w0_wmask_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 39.588 163.234 39.612 ; + END + END w0_wmask_in[245] + PIN w0_wmask_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 39.924 163.234 39.948 ; + END + END w0_wmask_in[246] + PIN w0_wmask_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 40.260 163.234 40.284 ; + END + END w0_wmask_in[247] + PIN w0_wmask_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 40.596 163.234 40.620 ; + END + END w0_wmask_in[248] + PIN w0_wmask_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 40.932 163.234 40.956 ; + END + END w0_wmask_in[249] + PIN w0_wmask_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 41.268 163.234 41.292 ; + END + END w0_wmask_in[250] + PIN w0_wmask_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 41.604 163.234 41.628 ; + END + END w0_wmask_in[251] + PIN w0_wmask_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 41.940 163.234 41.964 ; + END + END w0_wmask_in[252] + PIN w0_wmask_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 42.276 163.234 42.300 ; + END + END w0_wmask_in[253] + PIN w0_wmask_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 42.612 163.234 42.636 ; + END + END w0_wmask_in[254] + PIN w0_wmask_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 163.162 42.948 163.234 42.972 ; + END + END w0_wmask_in[255] + PIN w0_wmask_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 90.632 0.225 90.686 ; + END + END w0_wmask_in[256] + PIN w0_wmask_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 90.632 0.513 90.686 ; + END + END w0_wmask_in[257] + PIN w0_wmask_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 90.632 0.801 90.686 ; + END + END w0_wmask_in[258] + PIN w0_wmask_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 90.632 1.089 90.686 ; + END + END w0_wmask_in[259] + PIN w0_wmask_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 90.632 1.377 90.686 ; + END + END w0_wmask_in[260] + PIN w0_wmask_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 90.632 1.665 90.686 ; + END + END w0_wmask_in[261] + PIN w0_wmask_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 90.632 1.953 90.686 ; + END + END w0_wmask_in[262] + PIN w0_wmask_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 90.632 2.241 90.686 ; + END + END w0_wmask_in[263] + PIN w0_wmask_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 90.632 2.529 90.686 ; + END + END w0_wmask_in[264] + PIN w0_wmask_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 90.632 2.817 90.686 ; + END + END w0_wmask_in[265] + PIN w0_wmask_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 90.632 3.105 90.686 ; + END + END w0_wmask_in[266] + PIN w0_wmask_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 90.632 3.393 90.686 ; + END + END w0_wmask_in[267] + PIN w0_wmask_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 90.632 3.681 90.686 ; + END + END w0_wmask_in[268] + PIN w0_wmask_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 90.632 3.969 90.686 ; + END + END w0_wmask_in[269] + PIN w0_wmask_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 90.632 4.257 90.686 ; + END + END w0_wmask_in[270] + PIN w0_wmask_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 90.632 4.545 90.686 ; + END + END w0_wmask_in[271] + PIN w0_wmask_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 90.632 4.833 90.686 ; + END + END w0_wmask_in[272] + PIN w0_wmask_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 90.632 5.121 90.686 ; + END + END w0_wmask_in[273] + PIN w0_wmask_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 90.632 5.409 90.686 ; + END + END w0_wmask_in[274] + PIN w0_wmask_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 90.632 5.697 90.686 ; + END + END w0_wmask_in[275] + PIN w0_wmask_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 90.632 5.985 90.686 ; + END + END w0_wmask_in[276] + PIN w0_wmask_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 90.632 6.273 90.686 ; + END + END w0_wmask_in[277] + PIN w0_wmask_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 90.632 6.561 90.686 ; + END + END w0_wmask_in[278] + PIN w0_wmask_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 90.632 6.849 90.686 ; + END + END w0_wmask_in[279] + PIN w0_wmask_in[280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 90.632 7.137 90.686 ; + END + END w0_wmask_in[280] + PIN w0_wmask_in[281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 90.632 7.425 90.686 ; + END + END w0_wmask_in[281] + PIN w0_wmask_in[282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 90.632 7.713 90.686 ; + END + END w0_wmask_in[282] + PIN w0_wmask_in[283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 90.632 8.001 90.686 ; + END + END w0_wmask_in[283] + PIN w0_wmask_in[284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 90.632 8.289 90.686 ; + END + END w0_wmask_in[284] + PIN w0_wmask_in[285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 90.632 8.577 90.686 ; + END + END w0_wmask_in[285] + PIN w0_wmask_in[286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 90.632 8.865 90.686 ; + END + END w0_wmask_in[286] + PIN w0_wmask_in[287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 90.632 9.153 90.686 ; + END + END w0_wmask_in[287] + PIN w0_wmask_in[288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 90.632 9.441 90.686 ; + END + END w0_wmask_in[288] + PIN w0_wmask_in[289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 90.632 9.729 90.686 ; + END + END w0_wmask_in[289] + PIN w0_wmask_in[290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 90.632 10.017 90.686 ; + END + END w0_wmask_in[290] + PIN w0_wmask_in[291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 90.632 10.305 90.686 ; + END + END w0_wmask_in[291] + PIN w0_wmask_in[292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 90.632 10.593 90.686 ; + END + END w0_wmask_in[292] + PIN w0_wmask_in[293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 90.632 10.881 90.686 ; + END + END w0_wmask_in[293] + PIN w0_wmask_in[294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 90.632 11.169 90.686 ; + END + END w0_wmask_in[294] + PIN w0_wmask_in[295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 90.632 11.457 90.686 ; + END + END w0_wmask_in[295] + PIN w0_wmask_in[296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 90.632 11.745 90.686 ; + END + END w0_wmask_in[296] + PIN w0_wmask_in[297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 90.632 12.033 90.686 ; + END + END w0_wmask_in[297] + PIN w0_wmask_in[298] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 90.632 12.321 90.686 ; + END + END w0_wmask_in[298] + PIN w0_wmask_in[299] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 90.632 12.609 90.686 ; + END + END w0_wmask_in[299] + PIN w0_wmask_in[300] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 90.632 12.897 90.686 ; + END + END w0_wmask_in[300] + PIN w0_wmask_in[301] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 90.632 13.185 90.686 ; + END + END w0_wmask_in[301] + PIN w0_wmask_in[302] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 90.632 13.473 90.686 ; + END + END w0_wmask_in[302] + PIN w0_wmask_in[303] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 90.632 13.761 90.686 ; + END + END w0_wmask_in[303] + PIN w0_wmask_in[304] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 90.632 14.049 90.686 ; + END + END w0_wmask_in[304] + PIN w0_wmask_in[305] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 90.632 14.337 90.686 ; + END + END w0_wmask_in[305] + PIN w0_wmask_in[306] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 90.632 14.625 90.686 ; + END + END w0_wmask_in[306] + PIN w0_wmask_in[307] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 90.632 14.913 90.686 ; + END + END w0_wmask_in[307] + PIN w0_wmask_in[308] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 90.632 15.201 90.686 ; + END + END w0_wmask_in[308] + PIN w0_wmask_in[309] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 90.632 15.489 90.686 ; + END + END w0_wmask_in[309] + PIN w0_wmask_in[310] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 90.632 15.777 90.686 ; + END + END w0_wmask_in[310] + PIN w0_wmask_in[311] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 90.632 16.065 90.686 ; + END + END w0_wmask_in[311] + PIN w0_wmask_in[312] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 90.632 16.353 90.686 ; + END + END w0_wmask_in[312] + PIN w0_wmask_in[313] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 90.632 16.641 90.686 ; + END + END w0_wmask_in[313] + PIN w0_wmask_in[314] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 90.632 16.929 90.686 ; + END + END w0_wmask_in[314] + PIN w0_wmask_in[315] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 90.632 17.217 90.686 ; + END + END w0_wmask_in[315] + PIN w0_wmask_in[316] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 90.632 17.505 90.686 ; + END + END w0_wmask_in[316] + PIN w0_wmask_in[317] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 90.632 17.793 90.686 ; + END + END w0_wmask_in[317] + PIN w0_wmask_in[318] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 90.632 18.081 90.686 ; + END + END w0_wmask_in[318] + PIN w0_wmask_in[319] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 90.632 18.369 90.686 ; + END + END w0_wmask_in[319] + PIN w0_wmask_in[320] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 90.632 18.657 90.686 ; + END + END w0_wmask_in[320] + PIN w0_wmask_in[321] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 90.632 18.945 90.686 ; + END + END w0_wmask_in[321] + PIN w0_wmask_in[322] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 90.632 19.233 90.686 ; + END + END w0_wmask_in[322] + PIN w0_wmask_in[323] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 90.632 19.521 90.686 ; + END + END w0_wmask_in[323] + PIN w0_wmask_in[324] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 90.632 19.809 90.686 ; + END + END w0_wmask_in[324] + PIN w0_wmask_in[325] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 90.632 20.097 90.686 ; + END + END w0_wmask_in[325] + PIN w0_wmask_in[326] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 90.632 20.385 90.686 ; + END + END w0_wmask_in[326] + PIN w0_wmask_in[327] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 90.632 20.673 90.686 ; + END + END w0_wmask_in[327] + PIN w0_wmask_in[328] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 90.632 20.961 90.686 ; + END + END w0_wmask_in[328] + PIN w0_wmask_in[329] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 90.632 21.249 90.686 ; + END + END w0_wmask_in[329] + PIN w0_wmask_in[330] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 90.632 21.537 90.686 ; + END + END w0_wmask_in[330] + PIN w0_wmask_in[331] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 90.632 21.825 90.686 ; + END + END w0_wmask_in[331] + PIN w0_wmask_in[332] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 90.632 22.113 90.686 ; + END + END w0_wmask_in[332] + PIN w0_wmask_in[333] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 90.632 22.401 90.686 ; + END + END w0_wmask_in[333] + PIN w0_wmask_in[334] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 90.632 22.689 90.686 ; + END + END w0_wmask_in[334] + PIN w0_wmask_in[335] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 90.632 22.977 90.686 ; + END + END w0_wmask_in[335] + PIN w0_wmask_in[336] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 90.632 23.265 90.686 ; + END + END w0_wmask_in[336] + PIN w0_wmask_in[337] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 90.632 23.553 90.686 ; + END + END w0_wmask_in[337] + PIN w0_wmask_in[338] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 90.632 23.841 90.686 ; + END + END w0_wmask_in[338] + PIN w0_wmask_in[339] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 90.632 24.129 90.686 ; + END + END w0_wmask_in[339] + PIN w0_wmask_in[340] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 90.632 24.417 90.686 ; + END + END w0_wmask_in[340] + PIN w0_wmask_in[341] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 90.632 24.705 90.686 ; + END + END w0_wmask_in[341] + PIN w0_wmask_in[342] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 90.632 24.993 90.686 ; + END + END w0_wmask_in[342] + PIN w0_wmask_in[343] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 90.632 25.281 90.686 ; + END + END w0_wmask_in[343] + PIN w0_wmask_in[344] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 90.632 25.569 90.686 ; + END + END w0_wmask_in[344] + PIN w0_wmask_in[345] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 90.632 25.857 90.686 ; + END + END w0_wmask_in[345] + PIN w0_wmask_in[346] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 90.632 26.145 90.686 ; + END + END w0_wmask_in[346] + PIN w0_wmask_in[347] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 90.632 26.433 90.686 ; + END + END w0_wmask_in[347] + PIN w0_wmask_in[348] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 90.632 26.721 90.686 ; + END + END w0_wmask_in[348] + PIN w0_wmask_in[349] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 90.632 27.009 90.686 ; + END + END w0_wmask_in[349] + PIN w0_wmask_in[350] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 90.632 27.297 90.686 ; + END + END w0_wmask_in[350] + PIN w0_wmask_in[351] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 90.632 27.585 90.686 ; + END + END w0_wmask_in[351] + PIN w0_wmask_in[352] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 90.632 27.873 90.686 ; + END + END w0_wmask_in[352] + PIN w0_wmask_in[353] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 90.632 28.161 90.686 ; + END + END w0_wmask_in[353] + PIN w0_wmask_in[354] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 90.632 28.449 90.686 ; + END + END w0_wmask_in[354] + PIN w0_wmask_in[355] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 90.632 28.737 90.686 ; + END + END w0_wmask_in[355] + PIN w0_wmask_in[356] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 90.632 29.025 90.686 ; + END + END w0_wmask_in[356] + PIN w0_wmask_in[357] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 90.632 29.313 90.686 ; + END + END w0_wmask_in[357] + PIN w0_wmask_in[358] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 90.632 29.601 90.686 ; + END + END w0_wmask_in[358] + PIN w0_wmask_in[359] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 90.632 29.889 90.686 ; + END + END w0_wmask_in[359] + PIN w0_wmask_in[360] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 90.632 30.177 90.686 ; + END + END w0_wmask_in[360] + PIN w0_wmask_in[361] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 90.632 30.465 90.686 ; + END + END w0_wmask_in[361] + PIN w0_wmask_in[362] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 90.632 30.753 90.686 ; + END + END w0_wmask_in[362] + PIN w0_wmask_in[363] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 90.632 31.041 90.686 ; + END + END w0_wmask_in[363] + PIN w0_wmask_in[364] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 90.632 31.329 90.686 ; + END + END w0_wmask_in[364] + PIN w0_wmask_in[365] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 90.632 31.617 90.686 ; + END + END w0_wmask_in[365] + PIN w0_wmask_in[366] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 90.632 31.905 90.686 ; + END + END w0_wmask_in[366] + PIN w0_wmask_in[367] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 90.632 32.193 90.686 ; + END + END w0_wmask_in[367] + PIN w0_wmask_in[368] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 90.632 32.481 90.686 ; + END + END w0_wmask_in[368] + PIN w0_wmask_in[369] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 90.632 32.769 90.686 ; + END + END w0_wmask_in[369] + PIN w0_wmask_in[370] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 90.632 33.057 90.686 ; + END + END w0_wmask_in[370] + PIN w0_wmask_in[371] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 90.632 33.345 90.686 ; + END + END w0_wmask_in[371] + PIN w0_wmask_in[372] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 90.632 33.633 90.686 ; + END + END w0_wmask_in[372] + PIN w0_wmask_in[373] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 90.632 33.921 90.686 ; + END + END w0_wmask_in[373] + PIN w0_wmask_in[374] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 90.632 34.209 90.686 ; + END + END w0_wmask_in[374] + PIN w0_wmask_in[375] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 90.632 34.497 90.686 ; + END + END w0_wmask_in[375] + PIN w0_wmask_in[376] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 90.632 34.785 90.686 ; + END + END w0_wmask_in[376] + PIN w0_wmask_in[377] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 90.632 35.073 90.686 ; + END + END w0_wmask_in[377] + PIN w0_wmask_in[378] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 90.632 35.361 90.686 ; + END + END w0_wmask_in[378] + PIN w0_wmask_in[379] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 90.632 35.649 90.686 ; + END + END w0_wmask_in[379] + PIN w0_wmask_in[380] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 90.632 35.937 90.686 ; + END + END w0_wmask_in[380] + PIN w0_wmask_in[381] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 90.632 36.225 90.686 ; + END + END w0_wmask_in[381] + PIN w0_wmask_in[382] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 90.632 36.513 90.686 ; + END + END w0_wmask_in[382] + PIN w0_wmask_in[383] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 90.632 36.801 90.686 ; + END + END w0_wmask_in[383] + PIN w0_wmask_in[384] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 90.632 37.089 90.686 ; + END + END w0_wmask_in[384] + PIN w0_wmask_in[385] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 90.632 37.377 90.686 ; + END + END w0_wmask_in[385] + PIN w0_wmask_in[386] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 90.632 37.665 90.686 ; + END + END w0_wmask_in[386] + PIN w0_wmask_in[387] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 90.632 37.953 90.686 ; + END + END w0_wmask_in[387] + PIN w0_wmask_in[388] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 90.632 38.241 90.686 ; + END + END w0_wmask_in[388] + PIN w0_wmask_in[389] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 90.632 38.529 90.686 ; + END + END w0_wmask_in[389] + PIN w0_wmask_in[390] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 90.632 38.817 90.686 ; + END + END w0_wmask_in[390] + PIN w0_wmask_in[391] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 90.632 39.105 90.686 ; + END + END w0_wmask_in[391] + PIN w0_wmask_in[392] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 90.632 39.393 90.686 ; + END + END w0_wmask_in[392] + PIN w0_wmask_in[393] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 90.632 39.681 90.686 ; + END + END w0_wmask_in[393] + PIN w0_wmask_in[394] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 90.632 39.969 90.686 ; + END + END w0_wmask_in[394] + PIN w0_wmask_in[395] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 90.632 40.257 90.686 ; + END + END w0_wmask_in[395] + PIN w0_wmask_in[396] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 90.632 40.545 90.686 ; + END + END w0_wmask_in[396] + PIN w0_wmask_in[397] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 90.632 40.833 90.686 ; + END + END w0_wmask_in[397] + PIN w0_wmask_in[398] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 90.632 41.121 90.686 ; + END + END w0_wmask_in[398] + PIN w0_wmask_in[399] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 90.632 41.409 90.686 ; + END + END w0_wmask_in[399] + PIN w0_wmask_in[400] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 90.632 41.697 90.686 ; + END + END w0_wmask_in[400] + PIN w0_wmask_in[401] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 90.632 41.985 90.686 ; + END + END w0_wmask_in[401] + PIN w0_wmask_in[402] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 90.632 42.273 90.686 ; + END + END w0_wmask_in[402] + PIN w0_wmask_in[403] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 90.632 42.561 90.686 ; + END + END w0_wmask_in[403] + PIN w0_wmask_in[404] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 90.632 42.849 90.686 ; + END + END w0_wmask_in[404] + PIN w0_wmask_in[405] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 90.632 43.137 90.686 ; + END + END w0_wmask_in[405] + PIN w0_wmask_in[406] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 90.632 43.425 90.686 ; + END + END w0_wmask_in[406] + PIN w0_wmask_in[407] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 90.632 43.713 90.686 ; + END + END w0_wmask_in[407] + PIN w0_wmask_in[408] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 90.632 44.001 90.686 ; + END + END w0_wmask_in[408] + PIN w0_wmask_in[409] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 90.632 44.289 90.686 ; + END + END w0_wmask_in[409] + PIN w0_wmask_in[410] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 90.632 44.577 90.686 ; + END + END w0_wmask_in[410] + PIN w0_wmask_in[411] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 90.632 44.865 90.686 ; + END + END w0_wmask_in[411] + PIN w0_wmask_in[412] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 90.632 45.153 90.686 ; + END + END w0_wmask_in[412] + PIN w0_wmask_in[413] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 90.632 45.441 90.686 ; + END + END w0_wmask_in[413] + PIN w0_wmask_in[414] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 90.632 45.729 90.686 ; + END + END w0_wmask_in[414] + PIN w0_wmask_in[415] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 90.632 46.017 90.686 ; + END + END w0_wmask_in[415] + PIN w0_wmask_in[416] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 90.632 46.305 90.686 ; + END + END w0_wmask_in[416] + PIN w0_wmask_in[417] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 90.632 46.593 90.686 ; + END + END w0_wmask_in[417] + PIN w0_wmask_in[418] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 90.632 46.881 90.686 ; + END + END w0_wmask_in[418] + PIN w0_wmask_in[419] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 90.632 47.169 90.686 ; + END + END w0_wmask_in[419] + PIN w0_wmask_in[420] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 90.632 47.457 90.686 ; + END + END w0_wmask_in[420] + PIN w0_wmask_in[421] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 90.632 47.745 90.686 ; + END + END w0_wmask_in[421] + PIN w0_wmask_in[422] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 90.632 48.033 90.686 ; + END + END w0_wmask_in[422] + PIN w0_wmask_in[423] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 90.632 48.321 90.686 ; + END + END w0_wmask_in[423] + PIN w0_wmask_in[424] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 90.632 48.609 90.686 ; + END + END w0_wmask_in[424] + PIN w0_wmask_in[425] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 90.632 48.897 90.686 ; + END + END w0_wmask_in[425] + PIN w0_wmask_in[426] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 90.632 49.185 90.686 ; + END + END w0_wmask_in[426] + PIN w0_wmask_in[427] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 90.632 49.473 90.686 ; + END + END w0_wmask_in[427] + PIN w0_wmask_in[428] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 90.632 49.761 90.686 ; + END + END w0_wmask_in[428] + PIN w0_wmask_in[429] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 90.632 50.049 90.686 ; + END + END w0_wmask_in[429] + PIN w0_wmask_in[430] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 90.632 50.337 90.686 ; + END + END w0_wmask_in[430] + PIN w0_wmask_in[431] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 90.632 50.625 90.686 ; + END + END w0_wmask_in[431] + PIN w0_wmask_in[432] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 90.632 50.913 90.686 ; + END + END w0_wmask_in[432] + PIN w0_wmask_in[433] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 90.632 51.201 90.686 ; + END + END w0_wmask_in[433] + PIN w0_wmask_in[434] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 90.632 51.489 90.686 ; + END + END w0_wmask_in[434] + PIN w0_wmask_in[435] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 90.632 51.777 90.686 ; + END + END w0_wmask_in[435] + PIN w0_wmask_in[436] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 90.632 52.065 90.686 ; + END + END w0_wmask_in[436] + PIN w0_wmask_in[437] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 90.632 52.353 90.686 ; + END + END w0_wmask_in[437] + PIN w0_wmask_in[438] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 90.632 52.641 90.686 ; + END + END w0_wmask_in[438] + PIN w0_wmask_in[439] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 90.632 52.929 90.686 ; + END + END w0_wmask_in[439] + PIN w0_wmask_in[440] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 90.632 53.217 90.686 ; + END + END w0_wmask_in[440] + PIN w0_wmask_in[441] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 90.632 53.505 90.686 ; + END + END w0_wmask_in[441] + PIN w0_wmask_in[442] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 90.632 53.793 90.686 ; + END + END w0_wmask_in[442] + PIN w0_wmask_in[443] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 90.632 54.081 90.686 ; + END + END w0_wmask_in[443] + PIN w0_wmask_in[444] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 90.632 54.369 90.686 ; + END + END w0_wmask_in[444] + PIN w0_wmask_in[445] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 90.632 54.657 90.686 ; + END + END w0_wmask_in[445] + PIN w0_wmask_in[446] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 90.632 54.945 90.686 ; + END + END w0_wmask_in[446] + PIN w0_wmask_in[447] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 90.632 55.233 90.686 ; + END + END w0_wmask_in[447] + PIN w0_wmask_in[448] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 90.632 55.521 90.686 ; + END + END w0_wmask_in[448] + PIN w0_wmask_in[449] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 90.632 55.809 90.686 ; + END + END w0_wmask_in[449] + PIN w0_wmask_in[450] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 90.632 56.097 90.686 ; + END + END w0_wmask_in[450] + PIN w0_wmask_in[451] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 90.632 56.385 90.686 ; + END + END w0_wmask_in[451] + PIN w0_wmask_in[452] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 90.632 56.673 90.686 ; + END + END w0_wmask_in[452] + PIN w0_wmask_in[453] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 90.632 56.961 90.686 ; + END + END w0_wmask_in[453] + PIN w0_wmask_in[454] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 90.632 57.249 90.686 ; + END + END w0_wmask_in[454] + PIN w0_wmask_in[455] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 90.632 57.537 90.686 ; + END + END w0_wmask_in[455] + PIN w0_wmask_in[456] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 90.632 57.825 90.686 ; + END + END w0_wmask_in[456] + PIN w0_wmask_in[457] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 90.632 58.113 90.686 ; + END + END w0_wmask_in[457] + PIN w0_wmask_in[458] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 90.632 58.401 90.686 ; + END + END w0_wmask_in[458] + PIN w0_wmask_in[459] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 90.632 58.689 90.686 ; + END + END w0_wmask_in[459] + PIN w0_wmask_in[460] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 90.632 58.977 90.686 ; + END + END w0_wmask_in[460] + PIN w0_wmask_in[461] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 90.632 59.265 90.686 ; + END + END w0_wmask_in[461] + PIN w0_wmask_in[462] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 90.632 59.553 90.686 ; + END + END w0_wmask_in[462] + PIN w0_wmask_in[463] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 90.632 59.841 90.686 ; + END + END w0_wmask_in[463] + PIN w0_wmask_in[464] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 90.632 60.129 90.686 ; + END + END w0_wmask_in[464] + PIN w0_wmask_in[465] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 90.632 60.417 90.686 ; + END + END w0_wmask_in[465] + PIN w0_wmask_in[466] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 90.632 60.705 90.686 ; + END + END w0_wmask_in[466] + PIN w0_wmask_in[467] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 90.632 60.993 90.686 ; + END + END w0_wmask_in[467] + PIN w0_wmask_in[468] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 90.632 61.281 90.686 ; + END + END w0_wmask_in[468] + PIN w0_wmask_in[469] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 90.632 61.569 90.686 ; + END + END w0_wmask_in[469] + PIN w0_wmask_in[470] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 90.632 61.857 90.686 ; + END + END w0_wmask_in[470] + PIN w0_wmask_in[471] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 90.632 62.145 90.686 ; + END + END w0_wmask_in[471] + PIN w0_wmask_in[472] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 90.632 62.433 90.686 ; + END + END w0_wmask_in[472] + PIN w0_wmask_in[473] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 90.632 62.721 90.686 ; + END + END w0_wmask_in[473] + PIN w0_wmask_in[474] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 90.632 63.009 90.686 ; + END + END w0_wmask_in[474] + PIN w0_wmask_in[475] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 90.632 63.297 90.686 ; + END + END w0_wmask_in[475] + PIN w0_wmask_in[476] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 90.632 63.585 90.686 ; + END + END w0_wmask_in[476] + PIN w0_wmask_in[477] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 90.632 63.873 90.686 ; + END + END w0_wmask_in[477] + PIN w0_wmask_in[478] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 90.632 64.161 90.686 ; + END + END w0_wmask_in[478] + PIN w0_wmask_in[479] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 90.632 64.449 90.686 ; + END + END w0_wmask_in[479] + PIN w0_wmask_in[480] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 90.632 64.737 90.686 ; + END + END w0_wmask_in[480] + PIN w0_wmask_in[481] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 90.632 65.025 90.686 ; + END + END w0_wmask_in[481] + PIN w0_wmask_in[482] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 90.632 65.313 90.686 ; + END + END w0_wmask_in[482] + PIN w0_wmask_in[483] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 90.632 65.601 90.686 ; + END + END w0_wmask_in[483] + PIN w0_wmask_in[484] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 90.632 65.889 90.686 ; + END + END w0_wmask_in[484] + PIN w0_wmask_in[485] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 90.632 66.177 90.686 ; + END + END w0_wmask_in[485] + PIN w0_wmask_in[486] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 90.632 66.465 90.686 ; + END + END w0_wmask_in[486] + PIN w0_wmask_in[487] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 90.632 66.753 90.686 ; + END + END w0_wmask_in[487] + PIN w0_wmask_in[488] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 90.632 67.041 90.686 ; + END + END w0_wmask_in[488] + PIN w0_wmask_in[489] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 90.632 67.329 90.686 ; + END + END w0_wmask_in[489] + PIN w0_wmask_in[490] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 90.632 67.617 90.686 ; + END + END w0_wmask_in[490] + PIN w0_wmask_in[491] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 90.632 67.905 90.686 ; + END + END w0_wmask_in[491] + PIN w0_wmask_in[492] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 90.632 68.193 90.686 ; + END + END w0_wmask_in[492] + PIN w0_wmask_in[493] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 90.632 68.481 90.686 ; + END + END w0_wmask_in[493] + PIN w0_wmask_in[494] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 90.632 68.769 90.686 ; + END + END w0_wmask_in[494] + PIN w0_wmask_in[495] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 90.632 69.057 90.686 ; + END + END w0_wmask_in[495] + PIN w0_wmask_in[496] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 90.632 69.345 90.686 ; + END + END w0_wmask_in[496] + PIN w0_wmask_in[497] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 90.632 69.633 90.686 ; + END + END w0_wmask_in[497] + PIN w0_wmask_in[498] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 90.632 69.921 90.686 ; + END + END w0_wmask_in[498] + PIN w0_wmask_in[499] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 90.632 70.209 90.686 ; + END + END w0_wmask_in[499] + PIN w0_wmask_in[500] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 90.632 70.497 90.686 ; + END + END w0_wmask_in[500] + PIN w0_wmask_in[501] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 90.632 70.785 90.686 ; + END + END w0_wmask_in[501] + PIN w0_wmask_in[502] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 90.632 71.073 90.686 ; + END + END w0_wmask_in[502] + PIN w0_wmask_in[503] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 90.632 71.361 90.686 ; + END + END w0_wmask_in[503] + PIN w0_wmask_in[504] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 90.632 71.649 90.686 ; + END + END w0_wmask_in[504] + PIN w0_wmask_in[505] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 90.632 71.937 90.686 ; + END + END w0_wmask_in[505] + PIN w0_wmask_in[506] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 90.632 72.225 90.686 ; + END + END w0_wmask_in[506] + PIN w0_wmask_in[507] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 90.632 72.513 90.686 ; + END + END w0_wmask_in[507] + PIN w0_wmask_in[508] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 90.632 72.801 90.686 ; + END + END w0_wmask_in[508] + PIN w0_wmask_in[509] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 90.632 73.089 90.686 ; + END + END w0_wmask_in[509] + PIN w0_wmask_in[510] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 90.632 73.377 90.686 ; + END + END w0_wmask_in[510] + PIN w0_wmask_in[511] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 90.632 73.665 90.686 ; + END + END w0_wmask_in[511] PIN w0_wd_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; + RECT 0.000 43.284 0.072 43.308 ; END END w0_wd_in[0] PIN w0_wd_in[1] @@ -20,7 +4628,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.420 0.024 0.444 ; + RECT 0.000 43.620 0.072 43.644 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +4637,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.564 0.024 0.588 ; + RECT 0.000 43.956 0.072 43.980 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +4646,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.708 0.024 0.732 ; + RECT 0.000 44.292 0.072 44.316 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +4655,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.852 0.024 0.876 ; + RECT 0.000 44.628 0.072 44.652 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +4664,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.996 0.024 1.020 ; + RECT 0.000 44.964 0.072 44.988 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +4673,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.140 0.024 1.164 ; + RECT 0.000 45.300 0.072 45.324 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +4682,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.284 0.024 1.308 ; + RECT 0.000 45.636 0.072 45.660 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +4691,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.428 0.024 1.452 ; + RECT 0.000 45.972 0.072 45.996 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,7 +4700,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.572 0.024 1.596 ; + RECT 0.000 46.308 0.072 46.332 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,7 +4709,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.716 0.024 1.740 ; + RECT 0.000 46.644 0.072 46.668 ; END END w0_wd_in[10] PIN w0_wd_in[11] @@ -110,7 +4718,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.860 0.024 1.884 ; + RECT 0.000 46.980 0.072 47.004 ; END END w0_wd_in[11] PIN w0_wd_in[12] @@ -119,7 +4727,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.004 0.024 2.028 ; + RECT 0.000 47.316 0.072 47.340 ; END END w0_wd_in[12] PIN w0_wd_in[13] @@ -128,7 +4736,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.148 0.024 2.172 ; + RECT 0.000 47.652 0.072 47.676 ; END END w0_wd_in[13] PIN w0_wd_in[14] @@ -137,7 +4745,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.292 0.024 2.316 ; + RECT 0.000 47.988 0.072 48.012 ; END END w0_wd_in[14] PIN w0_wd_in[15] @@ -146,7 +4754,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.436 0.024 2.460 ; + RECT 0.000 48.324 0.072 48.348 ; END END w0_wd_in[15] PIN w0_wd_in[16] @@ -155,7 +4763,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.580 0.024 2.604 ; + RECT 0.000 48.660 0.072 48.684 ; END END w0_wd_in[16] PIN w0_wd_in[17] @@ -164,7 +4772,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.724 0.024 2.748 ; + RECT 0.000 48.996 0.072 49.020 ; END END w0_wd_in[17] PIN w0_wd_in[18] @@ -173,7 +4781,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.868 0.024 2.892 ; + RECT 0.000 49.332 0.072 49.356 ; END END w0_wd_in[18] PIN w0_wd_in[19] @@ -182,7 +4790,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.012 0.024 3.036 ; + RECT 0.000 49.668 0.072 49.692 ; END END w0_wd_in[19] PIN w0_wd_in[20] @@ -191,7 +4799,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.156 0.024 3.180 ; + RECT 0.000 50.004 0.072 50.028 ; END END w0_wd_in[20] PIN w0_wd_in[21] @@ -200,7 +4808,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.300 0.024 3.324 ; + RECT 0.000 50.340 0.072 50.364 ; END END w0_wd_in[21] PIN w0_wd_in[22] @@ -209,7 +4817,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.444 0.024 3.468 ; + RECT 0.000 50.676 0.072 50.700 ; END END w0_wd_in[22] PIN w0_wd_in[23] @@ -218,7 +4826,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.588 0.024 3.612 ; + RECT 0.000 51.012 0.072 51.036 ; END END w0_wd_in[23] PIN w0_wd_in[24] @@ -227,7 +4835,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.732 0.024 3.756 ; + RECT 0.000 51.348 0.072 51.372 ; END END w0_wd_in[24] PIN w0_wd_in[25] @@ -236,7 +4844,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.876 0.024 3.900 ; + RECT 0.000 51.684 0.072 51.708 ; END END w0_wd_in[25] PIN w0_wd_in[26] @@ -245,7 +4853,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.020 0.024 4.044 ; + RECT 0.000 52.020 0.072 52.044 ; END END w0_wd_in[26] PIN w0_wd_in[27] @@ -254,7 +4862,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.164 0.024 4.188 ; + RECT 0.000 52.356 0.072 52.380 ; END END w0_wd_in[27] PIN w0_wd_in[28] @@ -263,7 +4871,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.308 0.024 4.332 ; + RECT 0.000 52.692 0.072 52.716 ; END END w0_wd_in[28] PIN w0_wd_in[29] @@ -272,7 +4880,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.452 0.024 4.476 ; + RECT 0.000 53.028 0.072 53.052 ; END END w0_wd_in[29] PIN w0_wd_in[30] @@ -281,7 +4889,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.596 0.024 4.620 ; + RECT 0.000 53.364 0.072 53.388 ; END END w0_wd_in[30] PIN w0_wd_in[31] @@ -290,7 +4898,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.740 0.024 4.764 ; + RECT 0.000 53.700 0.072 53.724 ; END END w0_wd_in[31] PIN w0_wd_in[32] @@ -299,7 +4907,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.884 0.024 4.908 ; + RECT 0.000 54.036 0.072 54.060 ; END END w0_wd_in[32] PIN w0_wd_in[33] @@ -308,7 +4916,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.028 0.024 5.052 ; + RECT 0.000 54.372 0.072 54.396 ; END END w0_wd_in[33] PIN w0_wd_in[34] @@ -317,7 +4925,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.172 0.024 5.196 ; + RECT 0.000 54.708 0.072 54.732 ; END END w0_wd_in[34] PIN w0_wd_in[35] @@ -326,7 +4934,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.316 0.024 5.340 ; + RECT 0.000 55.044 0.072 55.068 ; END END w0_wd_in[35] PIN w0_wd_in[36] @@ -335,7 +4943,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.460 0.024 5.484 ; + RECT 0.000 55.380 0.072 55.404 ; END END w0_wd_in[36] PIN w0_wd_in[37] @@ -344,7 +4952,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.604 0.024 5.628 ; + RECT 0.000 55.716 0.072 55.740 ; END END w0_wd_in[37] PIN w0_wd_in[38] @@ -353,7 +4961,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.748 0.024 5.772 ; + RECT 0.000 56.052 0.072 56.076 ; END END w0_wd_in[38] PIN w0_wd_in[39] @@ -362,7 +4970,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.892 0.024 5.916 ; + RECT 0.000 56.388 0.072 56.412 ; END END w0_wd_in[39] PIN w0_wd_in[40] @@ -371,7 +4979,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.036 0.024 6.060 ; + RECT 0.000 56.724 0.072 56.748 ; END END w0_wd_in[40] PIN w0_wd_in[41] @@ -380,7 +4988,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.180 0.024 6.204 ; + RECT 0.000 57.060 0.072 57.084 ; END END w0_wd_in[41] PIN w0_wd_in[42] @@ -389,7 +4997,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.324 0.024 6.348 ; + RECT 0.000 57.396 0.072 57.420 ; END END w0_wd_in[42] PIN w0_wd_in[43] @@ -398,7 +5006,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.468 0.024 6.492 ; + RECT 0.000 57.732 0.072 57.756 ; END END w0_wd_in[43] PIN w0_wd_in[44] @@ -407,7 +5015,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.612 0.024 6.636 ; + RECT 0.000 58.068 0.072 58.092 ; END END w0_wd_in[44] PIN w0_wd_in[45] @@ -416,7 +5024,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.756 0.024 6.780 ; + RECT 0.000 58.404 0.072 58.428 ; END END w0_wd_in[45] PIN w0_wd_in[46] @@ -425,7 +5033,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.900 0.024 6.924 ; + RECT 0.000 58.740 0.072 58.764 ; END END w0_wd_in[46] PIN w0_wd_in[47] @@ -434,7 +5042,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.044 0.024 7.068 ; + RECT 0.000 59.076 0.072 59.100 ; END END w0_wd_in[47] PIN w0_wd_in[48] @@ -443,7 +5051,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.188 0.024 7.212 ; + RECT 0.000 59.412 0.072 59.436 ; END END w0_wd_in[48] PIN w0_wd_in[49] @@ -452,7 +5060,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.332 0.024 7.356 ; + RECT 0.000 59.748 0.072 59.772 ; END END w0_wd_in[49] PIN w0_wd_in[50] @@ -461,7 +5069,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.476 0.024 7.500 ; + RECT 0.000 60.084 0.072 60.108 ; END END w0_wd_in[50] PIN w0_wd_in[51] @@ -470,7 +5078,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.620 0.024 7.644 ; + RECT 0.000 60.420 0.072 60.444 ; END END w0_wd_in[51] PIN w0_wd_in[52] @@ -479,7 +5087,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.764 0.024 7.788 ; + RECT 0.000 60.756 0.072 60.780 ; END END w0_wd_in[52] PIN w0_wd_in[53] @@ -488,7 +5096,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.908 0.024 7.932 ; + RECT 0.000 61.092 0.072 61.116 ; END END w0_wd_in[53] PIN w0_wd_in[54] @@ -497,7 +5105,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.052 0.024 8.076 ; + RECT 0.000 61.428 0.072 61.452 ; END END w0_wd_in[54] PIN w0_wd_in[55] @@ -506,7 +5114,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.196 0.024 8.220 ; + RECT 0.000 61.764 0.072 61.788 ; END END w0_wd_in[55] PIN w0_wd_in[56] @@ -515,7 +5123,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.340 0.024 8.364 ; + RECT 0.000 62.100 0.072 62.124 ; END END w0_wd_in[56] PIN w0_wd_in[57] @@ -524,7 +5132,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.484 0.024 8.508 ; + RECT 0.000 62.436 0.072 62.460 ; END END w0_wd_in[57] PIN w0_wd_in[58] @@ -533,7 +5141,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.628 0.024 8.652 ; + RECT 0.000 62.772 0.072 62.796 ; END END w0_wd_in[58] PIN w0_wd_in[59] @@ -542,7 +5150,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.772 0.024 8.796 ; + RECT 0.000 63.108 0.072 63.132 ; END END w0_wd_in[59] PIN w0_wd_in[60] @@ -551,7 +5159,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.916 0.024 8.940 ; + RECT 0.000 63.444 0.072 63.468 ; END END w0_wd_in[60] PIN w0_wd_in[61] @@ -560,7 +5168,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.060 0.024 9.084 ; + RECT 0.000 63.780 0.072 63.804 ; END END w0_wd_in[61] PIN w0_wd_in[62] @@ -569,7 +5177,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.204 0.024 9.228 ; + RECT 0.000 64.116 0.072 64.140 ; END END w0_wd_in[62] PIN w0_wd_in[63] @@ -578,7 +5186,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.348 0.024 9.372 ; + RECT 0.000 64.452 0.072 64.476 ; END END w0_wd_in[63] PIN w0_wd_in[64] @@ -587,7 +5195,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.492 0.024 9.516 ; + RECT 0.000 64.788 0.072 64.812 ; END END w0_wd_in[64] PIN w0_wd_in[65] @@ -596,7 +5204,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.636 0.024 9.660 ; + RECT 0.000 65.124 0.072 65.148 ; END END w0_wd_in[65] PIN w0_wd_in[66] @@ -605,7 +5213,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.780 0.024 9.804 ; + RECT 0.000 65.460 0.072 65.484 ; END END w0_wd_in[66] PIN w0_wd_in[67] @@ -614,7 +5222,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.924 0.024 9.948 ; + RECT 0.000 65.796 0.072 65.820 ; END END w0_wd_in[67] PIN w0_wd_in[68] @@ -623,7 +5231,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 10.068 0.024 10.092 ; + RECT 0.000 66.132 0.072 66.156 ; END END w0_wd_in[68] PIN w0_wd_in[69] @@ -632,7 +5240,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 10.212 0.024 10.236 ; + RECT 0.000 66.468 0.072 66.492 ; END END w0_wd_in[69] PIN w0_wd_in[70] @@ -641,7 +5249,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 10.356 0.024 10.380 ; + RECT 0.000 66.804 0.072 66.828 ; END END w0_wd_in[70] PIN w0_wd_in[71] @@ -650,7 +5258,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 10.500 0.024 10.524 ; + RECT 0.000 67.140 0.072 67.164 ; END END w0_wd_in[71] PIN w0_wd_in[72] @@ -659,7 +5267,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 10.644 0.024 10.668 ; + RECT 0.000 67.476 0.072 67.500 ; END END w0_wd_in[72] PIN w0_wd_in[73] @@ -668,7 +5276,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 10.788 0.024 10.812 ; + RECT 0.000 67.812 0.072 67.836 ; END END w0_wd_in[73] PIN w0_wd_in[74] @@ -677,7 +5285,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 10.932 0.024 10.956 ; + RECT 0.000 68.148 0.072 68.172 ; END END w0_wd_in[74] PIN w0_wd_in[75] @@ -686,7 +5294,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 11.076 0.024 11.100 ; + RECT 0.000 68.484 0.072 68.508 ; END END w0_wd_in[75] PIN w0_wd_in[76] @@ -695,7 +5303,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 11.220 0.024 11.244 ; + RECT 0.000 68.820 0.072 68.844 ; END END w0_wd_in[76] PIN w0_wd_in[77] @@ -704,7 +5312,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 11.364 0.024 11.388 ; + RECT 0.000 69.156 0.072 69.180 ; END END w0_wd_in[77] PIN w0_wd_in[78] @@ -713,7 +5321,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 11.508 0.024 11.532 ; + RECT 0.000 69.492 0.072 69.516 ; END END w0_wd_in[78] PIN w0_wd_in[79] @@ -722,7 +5330,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 11.652 0.024 11.676 ; + RECT 0.000 69.828 0.072 69.852 ; END END w0_wd_in[79] PIN w0_wd_in[80] @@ -731,7 +5339,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 11.796 0.024 11.820 ; + RECT 0.000 70.164 0.072 70.188 ; END END w0_wd_in[80] PIN w0_wd_in[81] @@ -740,7 +5348,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 11.940 0.024 11.964 ; + RECT 0.000 70.500 0.072 70.524 ; END END w0_wd_in[81] PIN w0_wd_in[82] @@ -749,7 +5357,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 12.084 0.024 12.108 ; + RECT 0.000 70.836 0.072 70.860 ; END END w0_wd_in[82] PIN w0_wd_in[83] @@ -758,7 +5366,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 12.228 0.024 12.252 ; + RECT 0.000 71.172 0.072 71.196 ; END END w0_wd_in[83] PIN w0_wd_in[84] @@ -767,7 +5375,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 12.372 0.024 12.396 ; + RECT 0.000 71.508 0.072 71.532 ; END END w0_wd_in[84] PIN w0_wd_in[85] @@ -776,7 +5384,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 12.516 0.024 12.540 ; + RECT 0.000 71.844 0.072 71.868 ; END END w0_wd_in[85] PIN w0_wd_in[86] @@ -785,7 +5393,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 12.660 0.024 12.684 ; + RECT 0.000 72.180 0.072 72.204 ; END END w0_wd_in[86] PIN w0_wd_in[87] @@ -794,7 +5402,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 12.804 0.024 12.828 ; + RECT 0.000 72.516 0.072 72.540 ; END END w0_wd_in[87] PIN w0_wd_in[88] @@ -803,7 +5411,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 12.948 0.024 12.972 ; + RECT 0.000 72.852 0.072 72.876 ; END END w0_wd_in[88] PIN w0_wd_in[89] @@ -812,7 +5420,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 13.092 0.024 13.116 ; + RECT 0.000 73.188 0.072 73.212 ; END END w0_wd_in[89] PIN w0_wd_in[90] @@ -821,7 +5429,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 13.236 0.024 13.260 ; + RECT 0.000 73.524 0.072 73.548 ; END END w0_wd_in[90] PIN w0_wd_in[91] @@ -830,7 +5438,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 13.380 0.024 13.404 ; + RECT 0.000 73.860 0.072 73.884 ; END END w0_wd_in[91] PIN w0_wd_in[92] @@ -839,7 +5447,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 13.524 0.024 13.548 ; + RECT 0.000 74.196 0.072 74.220 ; END END w0_wd_in[92] PIN w0_wd_in[93] @@ -848,7 +5456,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 13.668 0.024 13.692 ; + RECT 0.000 74.532 0.072 74.556 ; END END w0_wd_in[93] PIN w0_wd_in[94] @@ -857,7 +5465,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 13.812 0.024 13.836 ; + RECT 0.000 74.868 0.072 74.892 ; END END w0_wd_in[94] PIN w0_wd_in[95] @@ -866,7 +5474,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 13.956 0.024 13.980 ; + RECT 0.000 75.204 0.072 75.228 ; END END w0_wd_in[95] PIN w0_wd_in[96] @@ -875,7 +5483,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 14.100 0.024 14.124 ; + RECT 0.000 75.540 0.072 75.564 ; END END w0_wd_in[96] PIN w0_wd_in[97] @@ -884,7 +5492,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 14.244 0.024 14.268 ; + RECT 0.000 75.876 0.072 75.900 ; END END w0_wd_in[97] PIN w0_wd_in[98] @@ -893,7 +5501,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 14.388 0.024 14.412 ; + RECT 0.000 76.212 0.072 76.236 ; END END w0_wd_in[98] PIN w0_wd_in[99] @@ -902,7 +5510,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 14.532 0.024 14.556 ; + RECT 0.000 76.548 0.072 76.572 ; END END w0_wd_in[99] PIN w0_wd_in[100] @@ -911,7 +5519,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 14.676 0.024 14.700 ; + RECT 0.000 76.884 0.072 76.908 ; END END w0_wd_in[100] PIN w0_wd_in[101] @@ -920,7 +5528,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 14.820 0.024 14.844 ; + RECT 0.000 77.220 0.072 77.244 ; END END w0_wd_in[101] PIN w0_wd_in[102] @@ -929,7 +5537,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 14.964 0.024 14.988 ; + RECT 0.000 77.556 0.072 77.580 ; END END w0_wd_in[102] PIN w0_wd_in[103] @@ -938,7 +5546,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 15.108 0.024 15.132 ; + RECT 0.000 77.892 0.072 77.916 ; END END w0_wd_in[103] PIN w0_wd_in[104] @@ -947,7 +5555,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 15.252 0.024 15.276 ; + RECT 0.000 78.228 0.072 78.252 ; END END w0_wd_in[104] PIN w0_wd_in[105] @@ -956,7 +5564,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 15.396 0.024 15.420 ; + RECT 0.000 78.564 0.072 78.588 ; END END w0_wd_in[105] PIN w0_wd_in[106] @@ -965,7 +5573,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 15.540 0.024 15.564 ; + RECT 0.000 78.900 0.072 78.924 ; END END w0_wd_in[106] PIN w0_wd_in[107] @@ -974,7 +5582,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 15.684 0.024 15.708 ; + RECT 0.000 79.236 0.072 79.260 ; END END w0_wd_in[107] PIN w0_wd_in[108] @@ -983,7 +5591,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 15.828 0.024 15.852 ; + RECT 0.000 79.572 0.072 79.596 ; END END w0_wd_in[108] PIN w0_wd_in[109] @@ -992,7 +5600,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 15.972 0.024 15.996 ; + RECT 0.000 79.908 0.072 79.932 ; END END w0_wd_in[109] PIN w0_wd_in[110] @@ -1001,7 +5609,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 16.116 0.024 16.140 ; + RECT 0.000 80.244 0.072 80.268 ; END END w0_wd_in[110] PIN w0_wd_in[111] @@ -1010,7 +5618,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 16.260 0.024 16.284 ; + RECT 0.000 80.580 0.072 80.604 ; END END w0_wd_in[111] PIN w0_wd_in[112] @@ -1019,7 +5627,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 16.404 0.024 16.428 ; + RECT 0.000 80.916 0.072 80.940 ; END END w0_wd_in[112] PIN w0_wd_in[113] @@ -1028,7 +5636,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 16.548 0.024 16.572 ; + RECT 0.000 81.252 0.072 81.276 ; END END w0_wd_in[113] PIN w0_wd_in[114] @@ -1037,7 +5645,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 16.692 0.024 16.716 ; + RECT 0.000 81.588 0.072 81.612 ; END END w0_wd_in[114] PIN w0_wd_in[115] @@ -1046,7 +5654,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 16.836 0.024 16.860 ; + RECT 0.000 81.924 0.072 81.948 ; END END w0_wd_in[115] PIN w0_wd_in[116] @@ -1055,7 +5663,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 16.980 0.024 17.004 ; + RECT 0.000 82.260 0.072 82.284 ; END END w0_wd_in[116] PIN w0_wd_in[117] @@ -1064,7 +5672,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 17.124 0.024 17.148 ; + RECT 0.000 82.596 0.072 82.620 ; END END w0_wd_in[117] PIN w0_wd_in[118] @@ -1073,7 +5681,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 17.268 0.024 17.292 ; + RECT 0.000 82.932 0.072 82.956 ; END END w0_wd_in[118] PIN w0_wd_in[119] @@ -1082,7 +5690,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 17.412 0.024 17.436 ; + RECT 0.000 83.268 0.072 83.292 ; END END w0_wd_in[119] PIN w0_wd_in[120] @@ -1091,7 +5699,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 17.556 0.024 17.580 ; + RECT 0.000 83.604 0.072 83.628 ; END END w0_wd_in[120] PIN w0_wd_in[121] @@ -1100,7 +5708,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 17.700 0.024 17.724 ; + RECT 0.000 83.940 0.072 83.964 ; END END w0_wd_in[121] PIN w0_wd_in[122] @@ -1109,7 +5717,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 17.844 0.024 17.868 ; + RECT 0.000 84.276 0.072 84.300 ; END END w0_wd_in[122] PIN w0_wd_in[123] @@ -1118,7 +5726,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 17.988 0.024 18.012 ; + RECT 0.000 84.612 0.072 84.636 ; END END w0_wd_in[123] PIN w0_wd_in[124] @@ -1127,7 +5735,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 18.132 0.024 18.156 ; + RECT 0.000 84.948 0.072 84.972 ; END END w0_wd_in[124] PIN w0_wd_in[125] @@ -1136,7 +5744,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 18.276 0.024 18.300 ; + RECT 0.000 85.284 0.072 85.308 ; END END w0_wd_in[125] PIN w0_wd_in[126] @@ -1145,7 +5753,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 18.420 0.024 18.444 ; + RECT 0.000 85.620 0.072 85.644 ; END END w0_wd_in[126] PIN w0_wd_in[127] @@ -1154,7 +5762,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 18.564 0.024 18.588 ; + RECT 0.000 85.956 0.072 85.980 ; END END w0_wd_in[127] PIN w0_wd_in[128] @@ -1163,7 +5771,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 0.276 265.421 0.300 ; + RECT 163.162 43.284 163.234 43.308 ; END END w0_wd_in[128] PIN w0_wd_in[129] @@ -1172,7 +5780,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 0.420 265.421 0.444 ; + RECT 163.162 43.620 163.234 43.644 ; END END w0_wd_in[129] PIN w0_wd_in[130] @@ -1181,7 +5789,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 0.564 265.421 0.588 ; + RECT 163.162 43.956 163.234 43.980 ; END END w0_wd_in[130] PIN w0_wd_in[131] @@ -1190,7 +5798,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 0.708 265.421 0.732 ; + RECT 163.162 44.292 163.234 44.316 ; END END w0_wd_in[131] PIN w0_wd_in[132] @@ -1199,7 +5807,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 0.852 265.421 0.876 ; + RECT 163.162 44.628 163.234 44.652 ; END END w0_wd_in[132] PIN w0_wd_in[133] @@ -1208,7 +5816,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 0.996 265.421 1.020 ; + RECT 163.162 44.964 163.234 44.988 ; END END w0_wd_in[133] PIN w0_wd_in[134] @@ -1217,7 +5825,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 1.140 265.421 1.164 ; + RECT 163.162 45.300 163.234 45.324 ; END END w0_wd_in[134] PIN w0_wd_in[135] @@ -1226,7 +5834,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 1.284 265.421 1.308 ; + RECT 163.162 45.636 163.234 45.660 ; END END w0_wd_in[135] PIN w0_wd_in[136] @@ -1235,7 +5843,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 1.428 265.421 1.452 ; + RECT 163.162 45.972 163.234 45.996 ; END END w0_wd_in[136] PIN w0_wd_in[137] @@ -1244,7 +5852,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 1.572 265.421 1.596 ; + RECT 163.162 46.308 163.234 46.332 ; END END w0_wd_in[137] PIN w0_wd_in[138] @@ -1253,7 +5861,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 1.716 265.421 1.740 ; + RECT 163.162 46.644 163.234 46.668 ; END END w0_wd_in[138] PIN w0_wd_in[139] @@ -1262,7 +5870,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 1.860 265.421 1.884 ; + RECT 163.162 46.980 163.234 47.004 ; END END w0_wd_in[139] PIN w0_wd_in[140] @@ -1271,7 +5879,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 2.004 265.421 2.028 ; + RECT 163.162 47.316 163.234 47.340 ; END END w0_wd_in[140] PIN w0_wd_in[141] @@ -1280,7 +5888,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 2.148 265.421 2.172 ; + RECT 163.162 47.652 163.234 47.676 ; END END w0_wd_in[141] PIN w0_wd_in[142] @@ -1289,7 +5897,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 2.292 265.421 2.316 ; + RECT 163.162 47.988 163.234 48.012 ; END END w0_wd_in[142] PIN w0_wd_in[143] @@ -1298,7 +5906,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 2.436 265.421 2.460 ; + RECT 163.162 48.324 163.234 48.348 ; END END w0_wd_in[143] PIN w0_wd_in[144] @@ -1307,7 +5915,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 2.580 265.421 2.604 ; + RECT 163.162 48.660 163.234 48.684 ; END END w0_wd_in[144] PIN w0_wd_in[145] @@ -1316,7 +5924,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 2.724 265.421 2.748 ; + RECT 163.162 48.996 163.234 49.020 ; END END w0_wd_in[145] PIN w0_wd_in[146] @@ -1325,7 +5933,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 2.868 265.421 2.892 ; + RECT 163.162 49.332 163.234 49.356 ; END END w0_wd_in[146] PIN w0_wd_in[147] @@ -1334,7 +5942,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 3.012 265.421 3.036 ; + RECT 163.162 49.668 163.234 49.692 ; END END w0_wd_in[147] PIN w0_wd_in[148] @@ -1343,7 +5951,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 3.156 265.421 3.180 ; + RECT 163.162 50.004 163.234 50.028 ; END END w0_wd_in[148] PIN w0_wd_in[149] @@ -1352,7 +5960,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 3.300 265.421 3.324 ; + RECT 163.162 50.340 163.234 50.364 ; END END w0_wd_in[149] PIN w0_wd_in[150] @@ -1361,7 +5969,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 3.444 265.421 3.468 ; + RECT 163.162 50.676 163.234 50.700 ; END END w0_wd_in[150] PIN w0_wd_in[151] @@ -1370,7 +5978,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 3.588 265.421 3.612 ; + RECT 163.162 51.012 163.234 51.036 ; END END w0_wd_in[151] PIN w0_wd_in[152] @@ -1379,7 +5987,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 3.732 265.421 3.756 ; + RECT 163.162 51.348 163.234 51.372 ; END END w0_wd_in[152] PIN w0_wd_in[153] @@ -1388,7 +5996,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 3.876 265.421 3.900 ; + RECT 163.162 51.684 163.234 51.708 ; END END w0_wd_in[153] PIN w0_wd_in[154] @@ -1397,7 +6005,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 4.020 265.421 4.044 ; + RECT 163.162 52.020 163.234 52.044 ; END END w0_wd_in[154] PIN w0_wd_in[155] @@ -1406,7 +6014,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 4.164 265.421 4.188 ; + RECT 163.162 52.356 163.234 52.380 ; END END w0_wd_in[155] PIN w0_wd_in[156] @@ -1415,7 +6023,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 4.308 265.421 4.332 ; + RECT 163.162 52.692 163.234 52.716 ; END END w0_wd_in[156] PIN w0_wd_in[157] @@ -1424,7 +6032,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 4.452 265.421 4.476 ; + RECT 163.162 53.028 163.234 53.052 ; END END w0_wd_in[157] PIN w0_wd_in[158] @@ -1433,7 +6041,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 4.596 265.421 4.620 ; + RECT 163.162 53.364 163.234 53.388 ; END END w0_wd_in[158] PIN w0_wd_in[159] @@ -1442,7 +6050,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 4.740 265.421 4.764 ; + RECT 163.162 53.700 163.234 53.724 ; END END w0_wd_in[159] PIN w0_wd_in[160] @@ -1451,7 +6059,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 4.884 265.421 4.908 ; + RECT 163.162 54.036 163.234 54.060 ; END END w0_wd_in[160] PIN w0_wd_in[161] @@ -1460,7 +6068,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 5.028 265.421 5.052 ; + RECT 163.162 54.372 163.234 54.396 ; END END w0_wd_in[161] PIN w0_wd_in[162] @@ -1469,7 +6077,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 5.172 265.421 5.196 ; + RECT 163.162 54.708 163.234 54.732 ; END END w0_wd_in[162] PIN w0_wd_in[163] @@ -1478,7 +6086,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 5.316 265.421 5.340 ; + RECT 163.162 55.044 163.234 55.068 ; END END w0_wd_in[163] PIN w0_wd_in[164] @@ -1487,7 +6095,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 5.460 265.421 5.484 ; + RECT 163.162 55.380 163.234 55.404 ; END END w0_wd_in[164] PIN w0_wd_in[165] @@ -1496,7 +6104,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 5.604 265.421 5.628 ; + RECT 163.162 55.716 163.234 55.740 ; END END w0_wd_in[165] PIN w0_wd_in[166] @@ -1505,7 +6113,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 5.748 265.421 5.772 ; + RECT 163.162 56.052 163.234 56.076 ; END END w0_wd_in[166] PIN w0_wd_in[167] @@ -1514,7 +6122,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 5.892 265.421 5.916 ; + RECT 163.162 56.388 163.234 56.412 ; END END w0_wd_in[167] PIN w0_wd_in[168] @@ -1523,7 +6131,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 6.036 265.421 6.060 ; + RECT 163.162 56.724 163.234 56.748 ; END END w0_wd_in[168] PIN w0_wd_in[169] @@ -1532,7 +6140,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 6.180 265.421 6.204 ; + RECT 163.162 57.060 163.234 57.084 ; END END w0_wd_in[169] PIN w0_wd_in[170] @@ -1541,7 +6149,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 6.324 265.421 6.348 ; + RECT 163.162 57.396 163.234 57.420 ; END END w0_wd_in[170] PIN w0_wd_in[171] @@ -1550,7 +6158,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 6.468 265.421 6.492 ; + RECT 163.162 57.732 163.234 57.756 ; END END w0_wd_in[171] PIN w0_wd_in[172] @@ -1559,7 +6167,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 6.612 265.421 6.636 ; + RECT 163.162 58.068 163.234 58.092 ; END END w0_wd_in[172] PIN w0_wd_in[173] @@ -1568,7 +6176,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 6.756 265.421 6.780 ; + RECT 163.162 58.404 163.234 58.428 ; END END w0_wd_in[173] PIN w0_wd_in[174] @@ -1577,7 +6185,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 6.900 265.421 6.924 ; + RECT 163.162 58.740 163.234 58.764 ; END END w0_wd_in[174] PIN w0_wd_in[175] @@ -1586,7 +6194,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 7.044 265.421 7.068 ; + RECT 163.162 59.076 163.234 59.100 ; END END w0_wd_in[175] PIN w0_wd_in[176] @@ -1595,7 +6203,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 7.188 265.421 7.212 ; + RECT 163.162 59.412 163.234 59.436 ; END END w0_wd_in[176] PIN w0_wd_in[177] @@ -1604,7 +6212,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 7.332 265.421 7.356 ; + RECT 163.162 59.748 163.234 59.772 ; END END w0_wd_in[177] PIN w0_wd_in[178] @@ -1613,7 +6221,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 7.476 265.421 7.500 ; + RECT 163.162 60.084 163.234 60.108 ; END END w0_wd_in[178] PIN w0_wd_in[179] @@ -1622,7 +6230,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 7.620 265.421 7.644 ; + RECT 163.162 60.420 163.234 60.444 ; END END w0_wd_in[179] PIN w0_wd_in[180] @@ -1631,7 +6239,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 7.764 265.421 7.788 ; + RECT 163.162 60.756 163.234 60.780 ; END END w0_wd_in[180] PIN w0_wd_in[181] @@ -1640,7 +6248,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 7.908 265.421 7.932 ; + RECT 163.162 61.092 163.234 61.116 ; END END w0_wd_in[181] PIN w0_wd_in[182] @@ -1649,7 +6257,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 8.052 265.421 8.076 ; + RECT 163.162 61.428 163.234 61.452 ; END END w0_wd_in[182] PIN w0_wd_in[183] @@ -1658,7 +6266,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 8.196 265.421 8.220 ; + RECT 163.162 61.764 163.234 61.788 ; END END w0_wd_in[183] PIN w0_wd_in[184] @@ -1667,7 +6275,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 8.340 265.421 8.364 ; + RECT 163.162 62.100 163.234 62.124 ; END END w0_wd_in[184] PIN w0_wd_in[185] @@ -1676,7 +6284,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 8.484 265.421 8.508 ; + RECT 163.162 62.436 163.234 62.460 ; END END w0_wd_in[185] PIN w0_wd_in[186] @@ -1685,7 +6293,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 8.628 265.421 8.652 ; + RECT 163.162 62.772 163.234 62.796 ; END END w0_wd_in[186] PIN w0_wd_in[187] @@ -1694,7 +6302,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 8.772 265.421 8.796 ; + RECT 163.162 63.108 163.234 63.132 ; END END w0_wd_in[187] PIN w0_wd_in[188] @@ -1703,7 +6311,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 8.916 265.421 8.940 ; + RECT 163.162 63.444 163.234 63.468 ; END END w0_wd_in[188] PIN w0_wd_in[189] @@ -1712,7 +6320,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 9.060 265.421 9.084 ; + RECT 163.162 63.780 163.234 63.804 ; END END w0_wd_in[189] PIN w0_wd_in[190] @@ -1721,7 +6329,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 9.204 265.421 9.228 ; + RECT 163.162 64.116 163.234 64.140 ; END END w0_wd_in[190] PIN w0_wd_in[191] @@ -1730,7 +6338,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 9.348 265.421 9.372 ; + RECT 163.162 64.452 163.234 64.476 ; END END w0_wd_in[191] PIN w0_wd_in[192] @@ -1739,7 +6347,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 9.492 265.421 9.516 ; + RECT 163.162 64.788 163.234 64.812 ; END END w0_wd_in[192] PIN w0_wd_in[193] @@ -1748,7 +6356,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 9.636 265.421 9.660 ; + RECT 163.162 65.124 163.234 65.148 ; END END w0_wd_in[193] PIN w0_wd_in[194] @@ -1757,7 +6365,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 9.780 265.421 9.804 ; + RECT 163.162 65.460 163.234 65.484 ; END END w0_wd_in[194] PIN w0_wd_in[195] @@ -1766,7 +6374,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 9.924 265.421 9.948 ; + RECT 163.162 65.796 163.234 65.820 ; END END w0_wd_in[195] PIN w0_wd_in[196] @@ -1775,7 +6383,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 10.068 265.421 10.092 ; + RECT 163.162 66.132 163.234 66.156 ; END END w0_wd_in[196] PIN w0_wd_in[197] @@ -1784,7 +6392,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 10.212 265.421 10.236 ; + RECT 163.162 66.468 163.234 66.492 ; END END w0_wd_in[197] PIN w0_wd_in[198] @@ -1793,7 +6401,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 10.356 265.421 10.380 ; + RECT 163.162 66.804 163.234 66.828 ; END END w0_wd_in[198] PIN w0_wd_in[199] @@ -1802,7 +6410,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 10.500 265.421 10.524 ; + RECT 163.162 67.140 163.234 67.164 ; END END w0_wd_in[199] PIN w0_wd_in[200] @@ -1811,7 +6419,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 10.644 265.421 10.668 ; + RECT 163.162 67.476 163.234 67.500 ; END END w0_wd_in[200] PIN w0_wd_in[201] @@ -1820,7 +6428,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 10.788 265.421 10.812 ; + RECT 163.162 67.812 163.234 67.836 ; END END w0_wd_in[201] PIN w0_wd_in[202] @@ -1829,7 +6437,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 10.932 265.421 10.956 ; + RECT 163.162 68.148 163.234 68.172 ; END END w0_wd_in[202] PIN w0_wd_in[203] @@ -1838,7 +6446,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 11.076 265.421 11.100 ; + RECT 163.162 68.484 163.234 68.508 ; END END w0_wd_in[203] PIN w0_wd_in[204] @@ -1847,7 +6455,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 11.220 265.421 11.244 ; + RECT 163.162 68.820 163.234 68.844 ; END END w0_wd_in[204] PIN w0_wd_in[205] @@ -1856,7 +6464,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 11.364 265.421 11.388 ; + RECT 163.162 69.156 163.234 69.180 ; END END w0_wd_in[205] PIN w0_wd_in[206] @@ -1865,7 +6473,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 11.508 265.421 11.532 ; + RECT 163.162 69.492 163.234 69.516 ; END END w0_wd_in[206] PIN w0_wd_in[207] @@ -1874,7 +6482,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 11.652 265.421 11.676 ; + RECT 163.162 69.828 163.234 69.852 ; END END w0_wd_in[207] PIN w0_wd_in[208] @@ -1883,7 +6491,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 11.796 265.421 11.820 ; + RECT 163.162 70.164 163.234 70.188 ; END END w0_wd_in[208] PIN w0_wd_in[209] @@ -1892,7 +6500,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 11.940 265.421 11.964 ; + RECT 163.162 70.500 163.234 70.524 ; END END w0_wd_in[209] PIN w0_wd_in[210] @@ -1901,7 +6509,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 12.084 265.421 12.108 ; + RECT 163.162 70.836 163.234 70.860 ; END END w0_wd_in[210] PIN w0_wd_in[211] @@ -1910,7 +6518,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 12.228 265.421 12.252 ; + RECT 163.162 71.172 163.234 71.196 ; END END w0_wd_in[211] PIN w0_wd_in[212] @@ -1919,7 +6527,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 12.372 265.421 12.396 ; + RECT 163.162 71.508 163.234 71.532 ; END END w0_wd_in[212] PIN w0_wd_in[213] @@ -1928,7 +6536,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 12.516 265.421 12.540 ; + RECT 163.162 71.844 163.234 71.868 ; END END w0_wd_in[213] PIN w0_wd_in[214] @@ -1937,7 +6545,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 12.660 265.421 12.684 ; + RECT 163.162 72.180 163.234 72.204 ; END END w0_wd_in[214] PIN w0_wd_in[215] @@ -1946,7 +6554,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 12.804 265.421 12.828 ; + RECT 163.162 72.516 163.234 72.540 ; END END w0_wd_in[215] PIN w0_wd_in[216] @@ -1955,7 +6563,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 12.948 265.421 12.972 ; + RECT 163.162 72.852 163.234 72.876 ; END END w0_wd_in[216] PIN w0_wd_in[217] @@ -1964,7 +6572,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 13.092 265.421 13.116 ; + RECT 163.162 73.188 163.234 73.212 ; END END w0_wd_in[217] PIN w0_wd_in[218] @@ -1973,7 +6581,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 13.236 265.421 13.260 ; + RECT 163.162 73.524 163.234 73.548 ; END END w0_wd_in[218] PIN w0_wd_in[219] @@ -1982,7 +6590,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 13.380 265.421 13.404 ; + RECT 163.162 73.860 163.234 73.884 ; END END w0_wd_in[219] PIN w0_wd_in[220] @@ -1991,7 +6599,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 13.524 265.421 13.548 ; + RECT 163.162 74.196 163.234 74.220 ; END END w0_wd_in[220] PIN w0_wd_in[221] @@ -2000,7 +6608,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 13.668 265.421 13.692 ; + RECT 163.162 74.532 163.234 74.556 ; END END w0_wd_in[221] PIN w0_wd_in[222] @@ -2009,7 +6617,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 13.812 265.421 13.836 ; + RECT 163.162 74.868 163.234 74.892 ; END END w0_wd_in[222] PIN w0_wd_in[223] @@ -2018,7 +6626,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 13.956 265.421 13.980 ; + RECT 163.162 75.204 163.234 75.228 ; END END w0_wd_in[223] PIN w0_wd_in[224] @@ -2027,7 +6635,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 14.100 265.421 14.124 ; + RECT 163.162 75.540 163.234 75.564 ; END END w0_wd_in[224] PIN w0_wd_in[225] @@ -2036,7 +6644,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 14.244 265.421 14.268 ; + RECT 163.162 75.876 163.234 75.900 ; END END w0_wd_in[225] PIN w0_wd_in[226] @@ -2045,7 +6653,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 14.388 265.421 14.412 ; + RECT 163.162 76.212 163.234 76.236 ; END END w0_wd_in[226] PIN w0_wd_in[227] @@ -2054,7 +6662,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 14.532 265.421 14.556 ; + RECT 163.162 76.548 163.234 76.572 ; END END w0_wd_in[227] PIN w0_wd_in[228] @@ -2063,7 +6671,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 14.676 265.421 14.700 ; + RECT 163.162 76.884 163.234 76.908 ; END END w0_wd_in[228] PIN w0_wd_in[229] @@ -2072,7 +6680,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 14.820 265.421 14.844 ; + RECT 163.162 77.220 163.234 77.244 ; END END w0_wd_in[229] PIN w0_wd_in[230] @@ -2081,7 +6689,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 14.964 265.421 14.988 ; + RECT 163.162 77.556 163.234 77.580 ; END END w0_wd_in[230] PIN w0_wd_in[231] @@ -2090,7 +6698,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 15.108 265.421 15.132 ; + RECT 163.162 77.892 163.234 77.916 ; END END w0_wd_in[231] PIN w0_wd_in[232] @@ -2099,7 +6707,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 15.252 265.421 15.276 ; + RECT 163.162 78.228 163.234 78.252 ; END END w0_wd_in[232] PIN w0_wd_in[233] @@ -2108,7 +6716,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 15.396 265.421 15.420 ; + RECT 163.162 78.564 163.234 78.588 ; END END w0_wd_in[233] PIN w0_wd_in[234] @@ -2117,7 +6725,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 15.540 265.421 15.564 ; + RECT 163.162 78.900 163.234 78.924 ; END END w0_wd_in[234] PIN w0_wd_in[235] @@ -2126,7 +6734,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 15.684 265.421 15.708 ; + RECT 163.162 79.236 163.234 79.260 ; END END w0_wd_in[235] PIN w0_wd_in[236] @@ -2135,7 +6743,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 15.828 265.421 15.852 ; + RECT 163.162 79.572 163.234 79.596 ; END END w0_wd_in[236] PIN w0_wd_in[237] @@ -2144,7 +6752,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 15.972 265.421 15.996 ; + RECT 163.162 79.908 163.234 79.932 ; END END w0_wd_in[237] PIN w0_wd_in[238] @@ -2153,7 +6761,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 16.116 265.421 16.140 ; + RECT 163.162 80.244 163.234 80.268 ; END END w0_wd_in[238] PIN w0_wd_in[239] @@ -2162,7 +6770,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 16.260 265.421 16.284 ; + RECT 163.162 80.580 163.234 80.604 ; END END w0_wd_in[239] PIN w0_wd_in[240] @@ -2171,7 +6779,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 16.404 265.421 16.428 ; + RECT 163.162 80.916 163.234 80.940 ; END END w0_wd_in[240] PIN w0_wd_in[241] @@ -2180,7 +6788,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 16.548 265.421 16.572 ; + RECT 163.162 81.252 163.234 81.276 ; END END w0_wd_in[241] PIN w0_wd_in[242] @@ -2189,7 +6797,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 16.692 265.421 16.716 ; + RECT 163.162 81.588 163.234 81.612 ; END END w0_wd_in[242] PIN w0_wd_in[243] @@ -2198,7 +6806,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 16.836 265.421 16.860 ; + RECT 163.162 81.924 163.234 81.948 ; END END w0_wd_in[243] PIN w0_wd_in[244] @@ -2207,7 +6815,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 16.980 265.421 17.004 ; + RECT 163.162 82.260 163.234 82.284 ; END END w0_wd_in[244] PIN w0_wd_in[245] @@ -2216,7 +6824,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 17.124 265.421 17.148 ; + RECT 163.162 82.596 163.234 82.620 ; END END w0_wd_in[245] PIN w0_wd_in[246] @@ -2225,7 +6833,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 17.268 265.421 17.292 ; + RECT 163.162 82.932 163.234 82.956 ; END END w0_wd_in[246] PIN w0_wd_in[247] @@ -2234,7 +6842,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 17.412 265.421 17.436 ; + RECT 163.162 83.268 163.234 83.292 ; END END w0_wd_in[247] PIN w0_wd_in[248] @@ -2243,7 +6851,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 17.556 265.421 17.580 ; + RECT 163.162 83.604 163.234 83.628 ; END END w0_wd_in[248] PIN w0_wd_in[249] @@ -2252,7 +6860,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 17.700 265.421 17.724 ; + RECT 163.162 83.940 163.234 83.964 ; END END w0_wd_in[249] PIN w0_wd_in[250] @@ -2261,7 +6869,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 17.844 265.421 17.868 ; + RECT 163.162 84.276 163.234 84.300 ; END END w0_wd_in[250] PIN w0_wd_in[251] @@ -2270,7 +6878,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 17.988 265.421 18.012 ; + RECT 163.162 84.612 163.234 84.636 ; END END w0_wd_in[251] PIN w0_wd_in[252] @@ -2279,7 +6887,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 18.132 265.421 18.156 ; + RECT 163.162 84.948 163.234 84.972 ; END END w0_wd_in[252] PIN w0_wd_in[253] @@ -2288,7 +6896,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 18.276 265.421 18.300 ; + RECT 163.162 85.284 163.234 85.308 ; END END w0_wd_in[253] PIN w0_wd_in[254] @@ -2297,7 +6905,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 18.420 265.421 18.444 ; + RECT 163.162 85.620 163.234 85.644 ; END END w0_wd_in[254] PIN w0_wd_in[255] @@ -2306,7 +6914,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 18.564 265.421 18.588 ; + RECT 163.162 85.956 163.234 85.980 ; END END w0_wd_in[255] PIN w0_wd_in[256] @@ -2315,7 +6923,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; + RECT 0.207 0.000 0.225 0.054 ; END END w0_wd_in[256] PIN w0_wd_in[257] @@ -2324,7 +6932,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.711 0.000 0.729 0.018 ; + RECT 0.495 0.000 0.513 0.054 ; END END w0_wd_in[257] PIN w0_wd_in[258] @@ -2333,7 +6941,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.215 0.000 1.233 0.018 ; + RECT 0.783 0.000 0.801 0.054 ; END END w0_wd_in[258] PIN w0_wd_in[259] @@ -2342,7 +6950,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.719 0.000 1.737 0.018 ; + RECT 1.071 0.000 1.089 0.054 ; END END w0_wd_in[259] PIN w0_wd_in[260] @@ -2351,7 +6959,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.223 0.000 2.241 0.018 ; + RECT 1.359 0.000 1.377 0.054 ; END END w0_wd_in[260] PIN w0_wd_in[261] @@ -2360,7 +6968,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.727 0.000 2.745 0.018 ; + RECT 1.647 0.000 1.665 0.054 ; END END w0_wd_in[261] PIN w0_wd_in[262] @@ -2369,7 +6977,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.231 0.000 3.249 0.018 ; + RECT 1.935 0.000 1.953 0.054 ; END END w0_wd_in[262] PIN w0_wd_in[263] @@ -2378,7 +6986,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.735 0.000 3.753 0.018 ; + RECT 2.223 0.000 2.241 0.054 ; END END w0_wd_in[263] PIN w0_wd_in[264] @@ -2387,7 +6995,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.239 0.000 4.257 0.018 ; + RECT 2.511 0.000 2.529 0.054 ; END END w0_wd_in[264] PIN w0_wd_in[265] @@ -2396,7 +7004,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.743 0.000 4.761 0.018 ; + RECT 2.799 0.000 2.817 0.054 ; END END w0_wd_in[265] PIN w0_wd_in[266] @@ -2405,7 +7013,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.247 0.000 5.265 0.018 ; + RECT 3.087 0.000 3.105 0.054 ; END END w0_wd_in[266] PIN w0_wd_in[267] @@ -2414,7 +7022,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.751 0.000 5.769 0.018 ; + RECT 3.375 0.000 3.393 0.054 ; END END w0_wd_in[267] PIN w0_wd_in[268] @@ -2423,7 +7031,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.255 0.000 6.273 0.018 ; + RECT 3.663 0.000 3.681 0.054 ; END END w0_wd_in[268] PIN w0_wd_in[269] @@ -2432,7 +7040,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.759 0.000 6.777 0.018 ; + RECT 3.951 0.000 3.969 0.054 ; END END w0_wd_in[269] PIN w0_wd_in[270] @@ -2441,7 +7049,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.263 0.000 7.281 0.018 ; + RECT 4.239 0.000 4.257 0.054 ; END END w0_wd_in[270] PIN w0_wd_in[271] @@ -2450,7 +7058,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.767 0.000 7.785 0.018 ; + RECT 4.527 0.000 4.545 0.054 ; END END w0_wd_in[271] PIN w0_wd_in[272] @@ -2459,7 +7067,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.271 0.000 8.289 0.018 ; + RECT 4.815 0.000 4.833 0.054 ; END END w0_wd_in[272] PIN w0_wd_in[273] @@ -2468,7 +7076,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.775 0.000 8.793 0.018 ; + RECT 5.103 0.000 5.121 0.054 ; END END w0_wd_in[273] PIN w0_wd_in[274] @@ -2477,7 +7085,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.279 0.000 9.297 0.018 ; + RECT 5.391 0.000 5.409 0.054 ; END END w0_wd_in[274] PIN w0_wd_in[275] @@ -2486,7 +7094,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.783 0.000 9.801 0.018 ; + RECT 5.679 0.000 5.697 0.054 ; END END w0_wd_in[275] PIN w0_wd_in[276] @@ -2495,7 +7103,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.287 0.000 10.305 0.018 ; + RECT 5.967 0.000 5.985 0.054 ; END END w0_wd_in[276] PIN w0_wd_in[277] @@ -2504,7 +7112,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.791 0.000 10.809 0.018 ; + RECT 6.255 0.000 6.273 0.054 ; END END w0_wd_in[277] PIN w0_wd_in[278] @@ -2513,7 +7121,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.295 0.000 11.313 0.018 ; + RECT 6.543 0.000 6.561 0.054 ; END END w0_wd_in[278] PIN w0_wd_in[279] @@ -2522,7 +7130,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.799 0.000 11.817 0.018 ; + RECT 6.831 0.000 6.849 0.054 ; END END w0_wd_in[279] PIN w0_wd_in[280] @@ -2531,7 +7139,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.303 0.000 12.321 0.018 ; + RECT 7.119 0.000 7.137 0.054 ; END END w0_wd_in[280] PIN w0_wd_in[281] @@ -2540,7 +7148,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.807 0.000 12.825 0.018 ; + RECT 7.407 0.000 7.425 0.054 ; END END w0_wd_in[281] PIN w0_wd_in[282] @@ -2549,7 +7157,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.311 0.000 13.329 0.018 ; + RECT 7.695 0.000 7.713 0.054 ; END END w0_wd_in[282] PIN w0_wd_in[283] @@ -2558,7 +7166,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.815 0.000 13.833 0.018 ; + RECT 7.983 0.000 8.001 0.054 ; END END w0_wd_in[283] PIN w0_wd_in[284] @@ -2567,7 +7175,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.319 0.000 14.337 0.018 ; + RECT 8.271 0.000 8.289 0.054 ; END END w0_wd_in[284] PIN w0_wd_in[285] @@ -2576,7 +7184,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.823 0.000 14.841 0.018 ; + RECT 8.559 0.000 8.577 0.054 ; END END w0_wd_in[285] PIN w0_wd_in[286] @@ -2585,7 +7193,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 15.327 0.000 15.345 0.018 ; + RECT 8.847 0.000 8.865 0.054 ; END END w0_wd_in[286] PIN w0_wd_in[287] @@ -2594,7 +7202,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 15.831 0.000 15.849 0.018 ; + RECT 9.135 0.000 9.153 0.054 ; END END w0_wd_in[287] PIN w0_wd_in[288] @@ -2603,7 +7211,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 16.335 0.000 16.353 0.018 ; + RECT 9.423 0.000 9.441 0.054 ; END END w0_wd_in[288] PIN w0_wd_in[289] @@ -2612,7 +7220,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 16.839 0.000 16.857 0.018 ; + RECT 9.711 0.000 9.729 0.054 ; END END w0_wd_in[289] PIN w0_wd_in[290] @@ -2621,7 +7229,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 17.343 0.000 17.361 0.018 ; + RECT 9.999 0.000 10.017 0.054 ; END END w0_wd_in[290] PIN w0_wd_in[291] @@ -2630,7 +7238,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 17.847 0.000 17.865 0.018 ; + RECT 10.287 0.000 10.305 0.054 ; END END w0_wd_in[291] PIN w0_wd_in[292] @@ -2639,7 +7247,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 18.351 0.000 18.369 0.018 ; + RECT 10.575 0.000 10.593 0.054 ; END END w0_wd_in[292] PIN w0_wd_in[293] @@ -2648,7 +7256,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 18.855 0.000 18.873 0.018 ; + RECT 10.863 0.000 10.881 0.054 ; END END w0_wd_in[293] PIN w0_wd_in[294] @@ -2657,7 +7265,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 19.359 0.000 19.377 0.018 ; + RECT 11.151 0.000 11.169 0.054 ; END END w0_wd_in[294] PIN w0_wd_in[295] @@ -2666,7 +7274,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 19.863 0.000 19.881 0.018 ; + RECT 11.439 0.000 11.457 0.054 ; END END w0_wd_in[295] PIN w0_wd_in[296] @@ -2675,7 +7283,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 20.367 0.000 20.385 0.018 ; + RECT 11.727 0.000 11.745 0.054 ; END END w0_wd_in[296] PIN w0_wd_in[297] @@ -2684,7 +7292,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 20.871 0.000 20.889 0.018 ; + RECT 12.015 0.000 12.033 0.054 ; END END w0_wd_in[297] PIN w0_wd_in[298] @@ -2693,7 +7301,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 21.375 0.000 21.393 0.018 ; + RECT 12.303 0.000 12.321 0.054 ; END END w0_wd_in[298] PIN w0_wd_in[299] @@ -2702,7 +7310,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 21.879 0.000 21.897 0.018 ; + RECT 12.591 0.000 12.609 0.054 ; END END w0_wd_in[299] PIN w0_wd_in[300] @@ -2711,7 +7319,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 22.383 0.000 22.401 0.018 ; + RECT 12.879 0.000 12.897 0.054 ; END END w0_wd_in[300] PIN w0_wd_in[301] @@ -2720,7 +7328,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 22.887 0.000 22.905 0.018 ; + RECT 13.167 0.000 13.185 0.054 ; END END w0_wd_in[301] PIN w0_wd_in[302] @@ -2729,7 +7337,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 23.391 0.000 23.409 0.018 ; + RECT 13.455 0.000 13.473 0.054 ; END END w0_wd_in[302] PIN w0_wd_in[303] @@ -2738,7 +7346,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 23.895 0.000 23.913 0.018 ; + RECT 13.743 0.000 13.761 0.054 ; END END w0_wd_in[303] PIN w0_wd_in[304] @@ -2747,7 +7355,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 24.399 0.000 24.417 0.018 ; + RECT 14.031 0.000 14.049 0.054 ; END END w0_wd_in[304] PIN w0_wd_in[305] @@ -2756,7 +7364,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 24.903 0.000 24.921 0.018 ; + RECT 14.319 0.000 14.337 0.054 ; END END w0_wd_in[305] PIN w0_wd_in[306] @@ -2765,7 +7373,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 25.407 0.000 25.425 0.018 ; + RECT 14.607 0.000 14.625 0.054 ; END END w0_wd_in[306] PIN w0_wd_in[307] @@ -2774,7 +7382,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 25.911 0.000 25.929 0.018 ; + RECT 14.895 0.000 14.913 0.054 ; END END w0_wd_in[307] PIN w0_wd_in[308] @@ -2783,7 +7391,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 26.415 0.000 26.433 0.018 ; + RECT 15.183 0.000 15.201 0.054 ; END END w0_wd_in[308] PIN w0_wd_in[309] @@ -2792,7 +7400,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 26.919 0.000 26.937 0.018 ; + RECT 15.471 0.000 15.489 0.054 ; END END w0_wd_in[309] PIN w0_wd_in[310] @@ -2801,7 +7409,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 27.423 0.000 27.441 0.018 ; + RECT 15.759 0.000 15.777 0.054 ; END END w0_wd_in[310] PIN w0_wd_in[311] @@ -2810,7 +7418,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 27.927 0.000 27.945 0.018 ; + RECT 16.047 0.000 16.065 0.054 ; END END w0_wd_in[311] PIN w0_wd_in[312] @@ -2819,7 +7427,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 28.431 0.000 28.449 0.018 ; + RECT 16.335 0.000 16.353 0.054 ; END END w0_wd_in[312] PIN w0_wd_in[313] @@ -2828,7 +7436,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 28.935 0.000 28.953 0.018 ; + RECT 16.623 0.000 16.641 0.054 ; END END w0_wd_in[313] PIN w0_wd_in[314] @@ -2837,7 +7445,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 29.439 0.000 29.457 0.018 ; + RECT 16.911 0.000 16.929 0.054 ; END END w0_wd_in[314] PIN w0_wd_in[315] @@ -2846,7 +7454,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 29.943 0.000 29.961 0.018 ; + RECT 17.199 0.000 17.217 0.054 ; END END w0_wd_in[315] PIN w0_wd_in[316] @@ -2855,7 +7463,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 30.447 0.000 30.465 0.018 ; + RECT 17.487 0.000 17.505 0.054 ; END END w0_wd_in[316] PIN w0_wd_in[317] @@ -2864,7 +7472,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 30.951 0.000 30.969 0.018 ; + RECT 17.775 0.000 17.793 0.054 ; END END w0_wd_in[317] PIN w0_wd_in[318] @@ -2873,7 +7481,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 31.455 0.000 31.473 0.018 ; + RECT 18.063 0.000 18.081 0.054 ; END END w0_wd_in[318] PIN w0_wd_in[319] @@ -2882,7 +7490,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 31.959 0.000 31.977 0.018 ; + RECT 18.351 0.000 18.369 0.054 ; END END w0_wd_in[319] PIN w0_wd_in[320] @@ -2891,7 +7499,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 32.463 0.000 32.481 0.018 ; + RECT 18.639 0.000 18.657 0.054 ; END END w0_wd_in[320] PIN w0_wd_in[321] @@ -2900,7 +7508,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 32.967 0.000 32.985 0.018 ; + RECT 18.927 0.000 18.945 0.054 ; END END w0_wd_in[321] PIN w0_wd_in[322] @@ -2909,7 +7517,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 33.471 0.000 33.489 0.018 ; + RECT 19.215 0.000 19.233 0.054 ; END END w0_wd_in[322] PIN w0_wd_in[323] @@ -2918,7 +7526,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 33.975 0.000 33.993 0.018 ; + RECT 19.503 0.000 19.521 0.054 ; END END w0_wd_in[323] PIN w0_wd_in[324] @@ -2927,7 +7535,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 34.479 0.000 34.497 0.018 ; + RECT 19.791 0.000 19.809 0.054 ; END END w0_wd_in[324] PIN w0_wd_in[325] @@ -2936,7 +7544,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 34.983 0.000 35.001 0.018 ; + RECT 20.079 0.000 20.097 0.054 ; END END w0_wd_in[325] PIN w0_wd_in[326] @@ -2945,7 +7553,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 35.487 0.000 35.505 0.018 ; + RECT 20.367 0.000 20.385 0.054 ; END END w0_wd_in[326] PIN w0_wd_in[327] @@ -2954,7 +7562,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 35.991 0.000 36.009 0.018 ; + RECT 20.655 0.000 20.673 0.054 ; END END w0_wd_in[327] PIN w0_wd_in[328] @@ -2963,7 +7571,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 36.495 0.000 36.513 0.018 ; + RECT 20.943 0.000 20.961 0.054 ; END END w0_wd_in[328] PIN w0_wd_in[329] @@ -2972,7 +7580,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 36.999 0.000 37.017 0.018 ; + RECT 21.231 0.000 21.249 0.054 ; END END w0_wd_in[329] PIN w0_wd_in[330] @@ -2981,7 +7589,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 37.503 0.000 37.521 0.018 ; + RECT 21.519 0.000 21.537 0.054 ; END END w0_wd_in[330] PIN w0_wd_in[331] @@ -2990,7 +7598,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 38.007 0.000 38.025 0.018 ; + RECT 21.807 0.000 21.825 0.054 ; END END w0_wd_in[331] PIN w0_wd_in[332] @@ -2999,7 +7607,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 38.511 0.000 38.529 0.018 ; + RECT 22.095 0.000 22.113 0.054 ; END END w0_wd_in[332] PIN w0_wd_in[333] @@ -3008,7 +7616,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 39.015 0.000 39.033 0.018 ; + RECT 22.383 0.000 22.401 0.054 ; END END w0_wd_in[333] PIN w0_wd_in[334] @@ -3017,7 +7625,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 39.519 0.000 39.537 0.018 ; + RECT 22.671 0.000 22.689 0.054 ; END END w0_wd_in[334] PIN w0_wd_in[335] @@ -3026,7 +7634,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 40.023 0.000 40.041 0.018 ; + RECT 22.959 0.000 22.977 0.054 ; END END w0_wd_in[335] PIN w0_wd_in[336] @@ -3035,7 +7643,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 40.527 0.000 40.545 0.018 ; + RECT 23.247 0.000 23.265 0.054 ; END END w0_wd_in[336] PIN w0_wd_in[337] @@ -3044,7 +7652,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 41.031 0.000 41.049 0.018 ; + RECT 23.535 0.000 23.553 0.054 ; END END w0_wd_in[337] PIN w0_wd_in[338] @@ -3053,7 +7661,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 41.535 0.000 41.553 0.018 ; + RECT 23.823 0.000 23.841 0.054 ; END END w0_wd_in[338] PIN w0_wd_in[339] @@ -3062,7 +7670,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 42.039 0.000 42.057 0.018 ; + RECT 24.111 0.000 24.129 0.054 ; END END w0_wd_in[339] PIN w0_wd_in[340] @@ -3071,7 +7679,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 42.543 0.000 42.561 0.018 ; + RECT 24.399 0.000 24.417 0.054 ; END END w0_wd_in[340] PIN w0_wd_in[341] @@ -3080,7 +7688,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 43.047 0.000 43.065 0.018 ; + RECT 24.687 0.000 24.705 0.054 ; END END w0_wd_in[341] PIN w0_wd_in[342] @@ -3089,7 +7697,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 43.551 0.000 43.569 0.018 ; + RECT 24.975 0.000 24.993 0.054 ; END END w0_wd_in[342] PIN w0_wd_in[343] @@ -3098,7 +7706,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 44.055 0.000 44.073 0.018 ; + RECT 25.263 0.000 25.281 0.054 ; END END w0_wd_in[343] PIN w0_wd_in[344] @@ -3107,7 +7715,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 44.559 0.000 44.577 0.018 ; + RECT 25.551 0.000 25.569 0.054 ; END END w0_wd_in[344] PIN w0_wd_in[345] @@ -3116,7 +7724,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 45.063 0.000 45.081 0.018 ; + RECT 25.839 0.000 25.857 0.054 ; END END w0_wd_in[345] PIN w0_wd_in[346] @@ -3125,7 +7733,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 45.567 0.000 45.585 0.018 ; + RECT 26.127 0.000 26.145 0.054 ; END END w0_wd_in[346] PIN w0_wd_in[347] @@ -3134,7 +7742,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 46.071 0.000 46.089 0.018 ; + RECT 26.415 0.000 26.433 0.054 ; END END w0_wd_in[347] PIN w0_wd_in[348] @@ -3143,7 +7751,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 46.575 0.000 46.593 0.018 ; + RECT 26.703 0.000 26.721 0.054 ; END END w0_wd_in[348] PIN w0_wd_in[349] @@ -3152,7 +7760,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 47.079 0.000 47.097 0.018 ; + RECT 26.991 0.000 27.009 0.054 ; END END w0_wd_in[349] PIN w0_wd_in[350] @@ -3161,7 +7769,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 47.583 0.000 47.601 0.018 ; + RECT 27.279 0.000 27.297 0.054 ; END END w0_wd_in[350] PIN w0_wd_in[351] @@ -3170,7 +7778,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 48.087 0.000 48.105 0.018 ; + RECT 27.567 0.000 27.585 0.054 ; END END w0_wd_in[351] PIN w0_wd_in[352] @@ -3179,7 +7787,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 48.591 0.000 48.609 0.018 ; + RECT 27.855 0.000 27.873 0.054 ; END END w0_wd_in[352] PIN w0_wd_in[353] @@ -3188,7 +7796,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 49.095 0.000 49.113 0.018 ; + RECT 28.143 0.000 28.161 0.054 ; END END w0_wd_in[353] PIN w0_wd_in[354] @@ -3197,7 +7805,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 49.599 0.000 49.617 0.018 ; + RECT 28.431 0.000 28.449 0.054 ; END END w0_wd_in[354] PIN w0_wd_in[355] @@ -3206,7 +7814,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 50.103 0.000 50.121 0.018 ; + RECT 28.719 0.000 28.737 0.054 ; END END w0_wd_in[355] PIN w0_wd_in[356] @@ -3215,7 +7823,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 50.607 0.000 50.625 0.018 ; + RECT 29.007 0.000 29.025 0.054 ; END END w0_wd_in[356] PIN w0_wd_in[357] @@ -3224,7 +7832,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 51.111 0.000 51.129 0.018 ; + RECT 29.295 0.000 29.313 0.054 ; END END w0_wd_in[357] PIN w0_wd_in[358] @@ -3233,7 +7841,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 51.615 0.000 51.633 0.018 ; + RECT 29.583 0.000 29.601 0.054 ; END END w0_wd_in[358] PIN w0_wd_in[359] @@ -3242,7 +7850,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 52.119 0.000 52.137 0.018 ; + RECT 29.871 0.000 29.889 0.054 ; END END w0_wd_in[359] PIN w0_wd_in[360] @@ -3251,7 +7859,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 52.623 0.000 52.641 0.018 ; + RECT 30.159 0.000 30.177 0.054 ; END END w0_wd_in[360] PIN w0_wd_in[361] @@ -3260,7 +7868,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 53.127 0.000 53.145 0.018 ; + RECT 30.447 0.000 30.465 0.054 ; END END w0_wd_in[361] PIN w0_wd_in[362] @@ -3269,7 +7877,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 53.631 0.000 53.649 0.018 ; + RECT 30.735 0.000 30.753 0.054 ; END END w0_wd_in[362] PIN w0_wd_in[363] @@ -3278,7 +7886,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 54.135 0.000 54.153 0.018 ; + RECT 31.023 0.000 31.041 0.054 ; END END w0_wd_in[363] PIN w0_wd_in[364] @@ -3287,7 +7895,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 54.639 0.000 54.657 0.018 ; + RECT 31.311 0.000 31.329 0.054 ; END END w0_wd_in[364] PIN w0_wd_in[365] @@ -3296,7 +7904,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 55.143 0.000 55.161 0.018 ; + RECT 31.599 0.000 31.617 0.054 ; END END w0_wd_in[365] PIN w0_wd_in[366] @@ -3305,7 +7913,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 55.647 0.000 55.665 0.018 ; + RECT 31.887 0.000 31.905 0.054 ; END END w0_wd_in[366] PIN w0_wd_in[367] @@ -3314,7 +7922,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 56.151 0.000 56.169 0.018 ; + RECT 32.175 0.000 32.193 0.054 ; END END w0_wd_in[367] PIN w0_wd_in[368] @@ -3323,7 +7931,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 56.655 0.000 56.673 0.018 ; + RECT 32.463 0.000 32.481 0.054 ; END END w0_wd_in[368] PIN w0_wd_in[369] @@ -3332,7 +7940,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 57.159 0.000 57.177 0.018 ; + RECT 32.751 0.000 32.769 0.054 ; END END w0_wd_in[369] PIN w0_wd_in[370] @@ -3341,7 +7949,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 57.663 0.000 57.681 0.018 ; + RECT 33.039 0.000 33.057 0.054 ; END END w0_wd_in[370] PIN w0_wd_in[371] @@ -3350,7 +7958,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 58.167 0.000 58.185 0.018 ; + RECT 33.327 0.000 33.345 0.054 ; END END w0_wd_in[371] PIN w0_wd_in[372] @@ -3359,7 +7967,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 58.671 0.000 58.689 0.018 ; + RECT 33.615 0.000 33.633 0.054 ; END END w0_wd_in[372] PIN w0_wd_in[373] @@ -3368,7 +7976,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 59.175 0.000 59.193 0.018 ; + RECT 33.903 0.000 33.921 0.054 ; END END w0_wd_in[373] PIN w0_wd_in[374] @@ -3377,7 +7985,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 59.679 0.000 59.697 0.018 ; + RECT 34.191 0.000 34.209 0.054 ; END END w0_wd_in[374] PIN w0_wd_in[375] @@ -3386,7 +7994,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 60.183 0.000 60.201 0.018 ; + RECT 34.479 0.000 34.497 0.054 ; END END w0_wd_in[375] PIN w0_wd_in[376] @@ -3395,7 +8003,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 60.687 0.000 60.705 0.018 ; + RECT 34.767 0.000 34.785 0.054 ; END END w0_wd_in[376] PIN w0_wd_in[377] @@ -3404,7 +8012,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 61.191 0.000 61.209 0.018 ; + RECT 35.055 0.000 35.073 0.054 ; END END w0_wd_in[377] PIN w0_wd_in[378] @@ -3413,7 +8021,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 61.695 0.000 61.713 0.018 ; + RECT 35.343 0.000 35.361 0.054 ; END END w0_wd_in[378] PIN w0_wd_in[379] @@ -3422,7 +8030,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 62.199 0.000 62.217 0.018 ; + RECT 35.631 0.000 35.649 0.054 ; END END w0_wd_in[379] PIN w0_wd_in[380] @@ -3431,7 +8039,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 62.703 0.000 62.721 0.018 ; + RECT 35.919 0.000 35.937 0.054 ; END END w0_wd_in[380] PIN w0_wd_in[381] @@ -3440,7 +8048,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 63.207 0.000 63.225 0.018 ; + RECT 36.207 0.000 36.225 0.054 ; END END w0_wd_in[381] PIN w0_wd_in[382] @@ -3449,7 +8057,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 63.711 0.000 63.729 0.018 ; + RECT 36.495 0.000 36.513 0.054 ; END END w0_wd_in[382] PIN w0_wd_in[383] @@ -3458,7 +8066,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 64.215 0.000 64.233 0.018 ; + RECT 36.783 0.000 36.801 0.054 ; END END w0_wd_in[383] PIN w0_wd_in[384] @@ -3467,7 +8075,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 64.719 0.000 64.737 0.018 ; + RECT 37.071 0.000 37.089 0.054 ; END END w0_wd_in[384] PIN w0_wd_in[385] @@ -3476,7 +8084,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 65.223 0.000 65.241 0.018 ; + RECT 37.359 0.000 37.377 0.054 ; END END w0_wd_in[385] PIN w0_wd_in[386] @@ -3485,7 +8093,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 65.727 0.000 65.745 0.018 ; + RECT 37.647 0.000 37.665 0.054 ; END END w0_wd_in[386] PIN w0_wd_in[387] @@ -3494,7 +8102,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 66.231 0.000 66.249 0.018 ; + RECT 37.935 0.000 37.953 0.054 ; END END w0_wd_in[387] PIN w0_wd_in[388] @@ -3503,7 +8111,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 66.735 0.000 66.753 0.018 ; + RECT 38.223 0.000 38.241 0.054 ; END END w0_wd_in[388] PIN w0_wd_in[389] @@ -3512,7 +8120,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 67.239 0.000 67.257 0.018 ; + RECT 38.511 0.000 38.529 0.054 ; END END w0_wd_in[389] PIN w0_wd_in[390] @@ -3521,7 +8129,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 67.743 0.000 67.761 0.018 ; + RECT 38.799 0.000 38.817 0.054 ; END END w0_wd_in[390] PIN w0_wd_in[391] @@ -3530,7 +8138,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 68.247 0.000 68.265 0.018 ; + RECT 39.087 0.000 39.105 0.054 ; END END w0_wd_in[391] PIN w0_wd_in[392] @@ -3539,7 +8147,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 68.751 0.000 68.769 0.018 ; + RECT 39.375 0.000 39.393 0.054 ; END END w0_wd_in[392] PIN w0_wd_in[393] @@ -3548,7 +8156,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 69.255 0.000 69.273 0.018 ; + RECT 39.663 0.000 39.681 0.054 ; END END w0_wd_in[393] PIN w0_wd_in[394] @@ -3557,7 +8165,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 69.759 0.000 69.777 0.018 ; + RECT 39.951 0.000 39.969 0.054 ; END END w0_wd_in[394] PIN w0_wd_in[395] @@ -3566,7 +8174,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 70.263 0.000 70.281 0.018 ; + RECT 40.239 0.000 40.257 0.054 ; END END w0_wd_in[395] PIN w0_wd_in[396] @@ -3575,7 +8183,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 70.767 0.000 70.785 0.018 ; + RECT 40.527 0.000 40.545 0.054 ; END END w0_wd_in[396] PIN w0_wd_in[397] @@ -3584,7 +8192,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 71.271 0.000 71.289 0.018 ; + RECT 40.815 0.000 40.833 0.054 ; END END w0_wd_in[397] PIN w0_wd_in[398] @@ -3593,7 +8201,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 71.775 0.000 71.793 0.018 ; + RECT 41.103 0.000 41.121 0.054 ; END END w0_wd_in[398] PIN w0_wd_in[399] @@ -3602,7 +8210,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 72.279 0.000 72.297 0.018 ; + RECT 41.391 0.000 41.409 0.054 ; END END w0_wd_in[399] PIN w0_wd_in[400] @@ -3611,7 +8219,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 72.783 0.000 72.801 0.018 ; + RECT 41.679 0.000 41.697 0.054 ; END END w0_wd_in[400] PIN w0_wd_in[401] @@ -3620,7 +8228,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 73.287 0.000 73.305 0.018 ; + RECT 41.967 0.000 41.985 0.054 ; END END w0_wd_in[401] PIN w0_wd_in[402] @@ -3629,7 +8237,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 73.791 0.000 73.809 0.018 ; + RECT 42.255 0.000 42.273 0.054 ; END END w0_wd_in[402] PIN w0_wd_in[403] @@ -3638,7 +8246,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 74.295 0.000 74.313 0.018 ; + RECT 42.543 0.000 42.561 0.054 ; END END w0_wd_in[403] PIN w0_wd_in[404] @@ -3647,7 +8255,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 74.799 0.000 74.817 0.018 ; + RECT 42.831 0.000 42.849 0.054 ; END END w0_wd_in[404] PIN w0_wd_in[405] @@ -3656,7 +8264,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 75.303 0.000 75.321 0.018 ; + RECT 43.119 0.000 43.137 0.054 ; END END w0_wd_in[405] PIN w0_wd_in[406] @@ -3665,7 +8273,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 75.807 0.000 75.825 0.018 ; + RECT 43.407 0.000 43.425 0.054 ; END END w0_wd_in[406] PIN w0_wd_in[407] @@ -3674,7 +8282,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 76.311 0.000 76.329 0.018 ; + RECT 43.695 0.000 43.713 0.054 ; END END w0_wd_in[407] PIN w0_wd_in[408] @@ -3683,7 +8291,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 76.815 0.000 76.833 0.018 ; + RECT 43.983 0.000 44.001 0.054 ; END END w0_wd_in[408] PIN w0_wd_in[409] @@ -3692,7 +8300,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 77.319 0.000 77.337 0.018 ; + RECT 44.271 0.000 44.289 0.054 ; END END w0_wd_in[409] PIN w0_wd_in[410] @@ -3701,7 +8309,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 77.823 0.000 77.841 0.018 ; + RECT 44.559 0.000 44.577 0.054 ; END END w0_wd_in[410] PIN w0_wd_in[411] @@ -3710,7 +8318,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 78.327 0.000 78.345 0.018 ; + RECT 44.847 0.000 44.865 0.054 ; END END w0_wd_in[411] PIN w0_wd_in[412] @@ -3719,7 +8327,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 78.831 0.000 78.849 0.018 ; + RECT 45.135 0.000 45.153 0.054 ; END END w0_wd_in[412] PIN w0_wd_in[413] @@ -3728,7 +8336,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 79.335 0.000 79.353 0.018 ; + RECT 45.423 0.000 45.441 0.054 ; END END w0_wd_in[413] PIN w0_wd_in[414] @@ -3737,7 +8345,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 79.839 0.000 79.857 0.018 ; + RECT 45.711 0.000 45.729 0.054 ; END END w0_wd_in[414] PIN w0_wd_in[415] @@ -3746,7 +8354,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 80.343 0.000 80.361 0.018 ; + RECT 45.999 0.000 46.017 0.054 ; END END w0_wd_in[415] PIN w0_wd_in[416] @@ -3755,7 +8363,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 80.847 0.000 80.865 0.018 ; + RECT 46.287 0.000 46.305 0.054 ; END END w0_wd_in[416] PIN w0_wd_in[417] @@ -3764,7 +8372,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 81.351 0.000 81.369 0.018 ; + RECT 46.575 0.000 46.593 0.054 ; END END w0_wd_in[417] PIN w0_wd_in[418] @@ -3773,7 +8381,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 81.855 0.000 81.873 0.018 ; + RECT 46.863 0.000 46.881 0.054 ; END END w0_wd_in[418] PIN w0_wd_in[419] @@ -3782,7 +8390,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 82.359 0.000 82.377 0.018 ; + RECT 47.151 0.000 47.169 0.054 ; END END w0_wd_in[419] PIN w0_wd_in[420] @@ -3791,7 +8399,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 82.863 0.000 82.881 0.018 ; + RECT 47.439 0.000 47.457 0.054 ; END END w0_wd_in[420] PIN w0_wd_in[421] @@ -3800,7 +8408,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 83.367 0.000 83.385 0.018 ; + RECT 47.727 0.000 47.745 0.054 ; END END w0_wd_in[421] PIN w0_wd_in[422] @@ -3809,7 +8417,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 83.871 0.000 83.889 0.018 ; + RECT 48.015 0.000 48.033 0.054 ; END END w0_wd_in[422] PIN w0_wd_in[423] @@ -3818,7 +8426,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 84.375 0.000 84.393 0.018 ; + RECT 48.303 0.000 48.321 0.054 ; END END w0_wd_in[423] PIN w0_wd_in[424] @@ -3827,7 +8435,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 84.879 0.000 84.897 0.018 ; + RECT 48.591 0.000 48.609 0.054 ; END END w0_wd_in[424] PIN w0_wd_in[425] @@ -3836,7 +8444,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 85.383 0.000 85.401 0.018 ; + RECT 48.879 0.000 48.897 0.054 ; END END w0_wd_in[425] PIN w0_wd_in[426] @@ -3845,7 +8453,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 85.887 0.000 85.905 0.018 ; + RECT 49.167 0.000 49.185 0.054 ; END END w0_wd_in[426] PIN w0_wd_in[427] @@ -3854,7 +8462,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 86.391 0.000 86.409 0.018 ; + RECT 49.455 0.000 49.473 0.054 ; END END w0_wd_in[427] PIN w0_wd_in[428] @@ -3863,7 +8471,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 86.895 0.000 86.913 0.018 ; + RECT 49.743 0.000 49.761 0.054 ; END END w0_wd_in[428] PIN w0_wd_in[429] @@ -3872,7 +8480,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 87.399 0.000 87.417 0.018 ; + RECT 50.031 0.000 50.049 0.054 ; END END w0_wd_in[429] PIN w0_wd_in[430] @@ -3881,7 +8489,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 87.903 0.000 87.921 0.018 ; + RECT 50.319 0.000 50.337 0.054 ; END END w0_wd_in[430] PIN w0_wd_in[431] @@ -3890,7 +8498,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 88.407 0.000 88.425 0.018 ; + RECT 50.607 0.000 50.625 0.054 ; END END w0_wd_in[431] PIN w0_wd_in[432] @@ -3899,7 +8507,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 88.911 0.000 88.929 0.018 ; + RECT 50.895 0.000 50.913 0.054 ; END END w0_wd_in[432] PIN w0_wd_in[433] @@ -3908,7 +8516,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 89.415 0.000 89.433 0.018 ; + RECT 51.183 0.000 51.201 0.054 ; END END w0_wd_in[433] PIN w0_wd_in[434] @@ -3917,7 +8525,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 89.919 0.000 89.937 0.018 ; + RECT 51.471 0.000 51.489 0.054 ; END END w0_wd_in[434] PIN w0_wd_in[435] @@ -3926,7 +8534,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 90.423 0.000 90.441 0.018 ; + RECT 51.759 0.000 51.777 0.054 ; END END w0_wd_in[435] PIN w0_wd_in[436] @@ -3935,7 +8543,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 90.927 0.000 90.945 0.018 ; + RECT 52.047 0.000 52.065 0.054 ; END END w0_wd_in[436] PIN w0_wd_in[437] @@ -3944,7 +8552,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 91.431 0.000 91.449 0.018 ; + RECT 52.335 0.000 52.353 0.054 ; END END w0_wd_in[437] PIN w0_wd_in[438] @@ -3953,7 +8561,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 91.935 0.000 91.953 0.018 ; + RECT 52.623 0.000 52.641 0.054 ; END END w0_wd_in[438] PIN w0_wd_in[439] @@ -3962,7 +8570,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 92.439 0.000 92.457 0.018 ; + RECT 52.911 0.000 52.929 0.054 ; END END w0_wd_in[439] PIN w0_wd_in[440] @@ -3971,7 +8579,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 92.943 0.000 92.961 0.018 ; + RECT 53.199 0.000 53.217 0.054 ; END END w0_wd_in[440] PIN w0_wd_in[441] @@ -3980,7 +8588,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 93.447 0.000 93.465 0.018 ; + RECT 53.487 0.000 53.505 0.054 ; END END w0_wd_in[441] PIN w0_wd_in[442] @@ -3989,7 +8597,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 93.951 0.000 93.969 0.018 ; + RECT 53.775 0.000 53.793 0.054 ; END END w0_wd_in[442] PIN w0_wd_in[443] @@ -3998,7 +8606,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 94.455 0.000 94.473 0.018 ; + RECT 54.063 0.000 54.081 0.054 ; END END w0_wd_in[443] PIN w0_wd_in[444] @@ -4007,7 +8615,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 94.959 0.000 94.977 0.018 ; + RECT 54.351 0.000 54.369 0.054 ; END END w0_wd_in[444] PIN w0_wd_in[445] @@ -4016,7 +8624,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 95.463 0.000 95.481 0.018 ; + RECT 54.639 0.000 54.657 0.054 ; END END w0_wd_in[445] PIN w0_wd_in[446] @@ -4025,7 +8633,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 95.967 0.000 95.985 0.018 ; + RECT 54.927 0.000 54.945 0.054 ; END END w0_wd_in[446] PIN w0_wd_in[447] @@ -4034,7 +8642,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 96.471 0.000 96.489 0.018 ; + RECT 55.215 0.000 55.233 0.054 ; END END w0_wd_in[447] PIN w0_wd_in[448] @@ -4043,7 +8651,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 96.975 0.000 96.993 0.018 ; + RECT 55.503 0.000 55.521 0.054 ; END END w0_wd_in[448] PIN w0_wd_in[449] @@ -4052,7 +8660,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 97.479 0.000 97.497 0.018 ; + RECT 55.791 0.000 55.809 0.054 ; END END w0_wd_in[449] PIN w0_wd_in[450] @@ -4061,7 +8669,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 97.983 0.000 98.001 0.018 ; + RECT 56.079 0.000 56.097 0.054 ; END END w0_wd_in[450] PIN w0_wd_in[451] @@ -4070,7 +8678,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 98.487 0.000 98.505 0.018 ; + RECT 56.367 0.000 56.385 0.054 ; END END w0_wd_in[451] PIN w0_wd_in[452] @@ -4079,7 +8687,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 98.991 0.000 99.009 0.018 ; + RECT 56.655 0.000 56.673 0.054 ; END END w0_wd_in[452] PIN w0_wd_in[453] @@ -4088,7 +8696,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 99.495 0.000 99.513 0.018 ; + RECT 56.943 0.000 56.961 0.054 ; END END w0_wd_in[453] PIN w0_wd_in[454] @@ -4097,7 +8705,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 99.999 0.000 100.017 0.018 ; + RECT 57.231 0.000 57.249 0.054 ; END END w0_wd_in[454] PIN w0_wd_in[455] @@ -4106,7 +8714,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 100.503 0.000 100.521 0.018 ; + RECT 57.519 0.000 57.537 0.054 ; END END w0_wd_in[455] PIN w0_wd_in[456] @@ -4115,7 +8723,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 101.007 0.000 101.025 0.018 ; + RECT 57.807 0.000 57.825 0.054 ; END END w0_wd_in[456] PIN w0_wd_in[457] @@ -4124,7 +8732,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 101.511 0.000 101.529 0.018 ; + RECT 58.095 0.000 58.113 0.054 ; END END w0_wd_in[457] PIN w0_wd_in[458] @@ -4133,7 +8741,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 102.015 0.000 102.033 0.018 ; + RECT 58.383 0.000 58.401 0.054 ; END END w0_wd_in[458] PIN w0_wd_in[459] @@ -4142,7 +8750,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 102.519 0.000 102.537 0.018 ; + RECT 58.671 0.000 58.689 0.054 ; END END w0_wd_in[459] PIN w0_wd_in[460] @@ -4151,7 +8759,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 103.023 0.000 103.041 0.018 ; + RECT 58.959 0.000 58.977 0.054 ; END END w0_wd_in[460] PIN w0_wd_in[461] @@ -4160,7 +8768,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 103.527 0.000 103.545 0.018 ; + RECT 59.247 0.000 59.265 0.054 ; END END w0_wd_in[461] PIN w0_wd_in[462] @@ -4169,7 +8777,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 104.031 0.000 104.049 0.018 ; + RECT 59.535 0.000 59.553 0.054 ; END END w0_wd_in[462] PIN w0_wd_in[463] @@ -4178,7 +8786,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 104.535 0.000 104.553 0.018 ; + RECT 59.823 0.000 59.841 0.054 ; END END w0_wd_in[463] PIN w0_wd_in[464] @@ -4187,7 +8795,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 105.039 0.000 105.057 0.018 ; + RECT 60.111 0.000 60.129 0.054 ; END END w0_wd_in[464] PIN w0_wd_in[465] @@ -4196,7 +8804,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 105.543 0.000 105.561 0.018 ; + RECT 60.399 0.000 60.417 0.054 ; END END w0_wd_in[465] PIN w0_wd_in[466] @@ -4205,7 +8813,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 106.047 0.000 106.065 0.018 ; + RECT 60.687 0.000 60.705 0.054 ; END END w0_wd_in[466] PIN w0_wd_in[467] @@ -4214,7 +8822,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 106.551 0.000 106.569 0.018 ; + RECT 60.975 0.000 60.993 0.054 ; END END w0_wd_in[467] PIN w0_wd_in[468] @@ -4223,7 +8831,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 107.055 0.000 107.073 0.018 ; + RECT 61.263 0.000 61.281 0.054 ; END END w0_wd_in[468] PIN w0_wd_in[469] @@ -4232,7 +8840,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 107.559 0.000 107.577 0.018 ; + RECT 61.551 0.000 61.569 0.054 ; END END w0_wd_in[469] PIN w0_wd_in[470] @@ -4241,7 +8849,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 108.063 0.000 108.081 0.018 ; + RECT 61.839 0.000 61.857 0.054 ; END END w0_wd_in[470] PIN w0_wd_in[471] @@ -4250,7 +8858,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 108.567 0.000 108.585 0.018 ; + RECT 62.127 0.000 62.145 0.054 ; END END w0_wd_in[471] PIN w0_wd_in[472] @@ -4259,7 +8867,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 109.071 0.000 109.089 0.018 ; + RECT 62.415 0.000 62.433 0.054 ; END END w0_wd_in[472] PIN w0_wd_in[473] @@ -4268,7 +8876,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 109.575 0.000 109.593 0.018 ; + RECT 62.703 0.000 62.721 0.054 ; END END w0_wd_in[473] PIN w0_wd_in[474] @@ -4277,7 +8885,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 110.079 0.000 110.097 0.018 ; + RECT 62.991 0.000 63.009 0.054 ; END END w0_wd_in[474] PIN w0_wd_in[475] @@ -4286,7 +8894,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 110.583 0.000 110.601 0.018 ; + RECT 63.279 0.000 63.297 0.054 ; END END w0_wd_in[475] PIN w0_wd_in[476] @@ -4295,7 +8903,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 111.087 0.000 111.105 0.018 ; + RECT 63.567 0.000 63.585 0.054 ; END END w0_wd_in[476] PIN w0_wd_in[477] @@ -4304,7 +8912,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 111.591 0.000 111.609 0.018 ; + RECT 63.855 0.000 63.873 0.054 ; END END w0_wd_in[477] PIN w0_wd_in[478] @@ -4313,7 +8921,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 112.095 0.000 112.113 0.018 ; + RECT 64.143 0.000 64.161 0.054 ; END END w0_wd_in[478] PIN w0_wd_in[479] @@ -4322,7 +8930,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 112.599 0.000 112.617 0.018 ; + RECT 64.431 0.000 64.449 0.054 ; END END w0_wd_in[479] PIN w0_wd_in[480] @@ -4331,7 +8939,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 113.103 0.000 113.121 0.018 ; + RECT 64.719 0.000 64.737 0.054 ; END END w0_wd_in[480] PIN w0_wd_in[481] @@ -4340,7 +8948,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 113.607 0.000 113.625 0.018 ; + RECT 65.007 0.000 65.025 0.054 ; END END w0_wd_in[481] PIN w0_wd_in[482] @@ -4349,7 +8957,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 114.111 0.000 114.129 0.018 ; + RECT 65.295 0.000 65.313 0.054 ; END END w0_wd_in[482] PIN w0_wd_in[483] @@ -4358,7 +8966,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 114.615 0.000 114.633 0.018 ; + RECT 65.583 0.000 65.601 0.054 ; END END w0_wd_in[483] PIN w0_wd_in[484] @@ -4367,7 +8975,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 115.119 0.000 115.137 0.018 ; + RECT 65.871 0.000 65.889 0.054 ; END END w0_wd_in[484] PIN w0_wd_in[485] @@ -4376,7 +8984,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 115.623 0.000 115.641 0.018 ; + RECT 66.159 0.000 66.177 0.054 ; END END w0_wd_in[485] PIN w0_wd_in[486] @@ -4385,7 +8993,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 116.127 0.000 116.145 0.018 ; + RECT 66.447 0.000 66.465 0.054 ; END END w0_wd_in[486] PIN w0_wd_in[487] @@ -4394,7 +9002,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 116.631 0.000 116.649 0.018 ; + RECT 66.735 0.000 66.753 0.054 ; END END w0_wd_in[487] PIN w0_wd_in[488] @@ -4403,7 +9011,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 117.135 0.000 117.153 0.018 ; + RECT 67.023 0.000 67.041 0.054 ; END END w0_wd_in[488] PIN w0_wd_in[489] @@ -4412,7 +9020,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 117.639 0.000 117.657 0.018 ; + RECT 67.311 0.000 67.329 0.054 ; END END w0_wd_in[489] PIN w0_wd_in[490] @@ -4421,7 +9029,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 118.143 0.000 118.161 0.018 ; + RECT 67.599 0.000 67.617 0.054 ; END END w0_wd_in[490] PIN w0_wd_in[491] @@ -4430,7 +9038,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 118.647 0.000 118.665 0.018 ; + RECT 67.887 0.000 67.905 0.054 ; END END w0_wd_in[491] PIN w0_wd_in[492] @@ -4439,7 +9047,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 119.151 0.000 119.169 0.018 ; + RECT 68.175 0.000 68.193 0.054 ; END END w0_wd_in[492] PIN w0_wd_in[493] @@ -4448,7 +9056,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 119.655 0.000 119.673 0.018 ; + RECT 68.463 0.000 68.481 0.054 ; END END w0_wd_in[493] PIN w0_wd_in[494] @@ -4457,7 +9065,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 120.159 0.000 120.177 0.018 ; + RECT 68.751 0.000 68.769 0.054 ; END END w0_wd_in[494] PIN w0_wd_in[495] @@ -4466,7 +9074,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 120.663 0.000 120.681 0.018 ; + RECT 69.039 0.000 69.057 0.054 ; END END w0_wd_in[495] PIN w0_wd_in[496] @@ -4475,7 +9083,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 121.167 0.000 121.185 0.018 ; + RECT 69.327 0.000 69.345 0.054 ; END END w0_wd_in[496] PIN w0_wd_in[497] @@ -4484,7 +9092,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 121.671 0.000 121.689 0.018 ; + RECT 69.615 0.000 69.633 0.054 ; END END w0_wd_in[497] PIN w0_wd_in[498] @@ -4493,7 +9101,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 122.175 0.000 122.193 0.018 ; + RECT 69.903 0.000 69.921 0.054 ; END END w0_wd_in[498] PIN w0_wd_in[499] @@ -4502,7 +9110,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 122.679 0.000 122.697 0.018 ; + RECT 70.191 0.000 70.209 0.054 ; END END w0_wd_in[499] PIN w0_wd_in[500] @@ -4511,7 +9119,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 123.183 0.000 123.201 0.018 ; + RECT 70.479 0.000 70.497 0.054 ; END END w0_wd_in[500] PIN w0_wd_in[501] @@ -4520,7 +9128,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 123.687 0.000 123.705 0.018 ; + RECT 70.767 0.000 70.785 0.054 ; END END w0_wd_in[501] PIN w0_wd_in[502] @@ -4529,7 +9137,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 124.191 0.000 124.209 0.018 ; + RECT 71.055 0.000 71.073 0.054 ; END END w0_wd_in[502] PIN w0_wd_in[503] @@ -4538,7 +9146,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 124.695 0.000 124.713 0.018 ; + RECT 71.343 0.000 71.361 0.054 ; END END w0_wd_in[503] PIN w0_wd_in[504] @@ -4547,7 +9155,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 125.199 0.000 125.217 0.018 ; + RECT 71.631 0.000 71.649 0.054 ; END END w0_wd_in[504] PIN w0_wd_in[505] @@ -4556,7 +9164,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 125.703 0.000 125.721 0.018 ; + RECT 71.919 0.000 71.937 0.054 ; END END w0_wd_in[505] PIN w0_wd_in[506] @@ -4565,7 +9173,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 126.207 0.000 126.225 0.018 ; + RECT 72.207 0.000 72.225 0.054 ; END END w0_wd_in[506] PIN w0_wd_in[507] @@ -4574,7 +9182,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 126.711 0.000 126.729 0.018 ; + RECT 72.495 0.000 72.513 0.054 ; END END w0_wd_in[507] PIN w0_wd_in[508] @@ -4583,7 +9191,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 127.215 0.000 127.233 0.018 ; + RECT 72.783 0.000 72.801 0.054 ; END END w0_wd_in[508] PIN w0_wd_in[509] @@ -4592,7 +9200,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 127.719 0.000 127.737 0.018 ; + RECT 73.071 0.000 73.089 0.054 ; END END w0_wd_in[509] PIN w0_wd_in[510] @@ -4601,7 +9209,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 128.223 0.000 128.241 0.018 ; + RECT 73.359 0.000 73.377 0.054 ; END END w0_wd_in[510] PIN w0_wd_in[511] @@ -4610,7 +9218,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 128.727 0.000 128.745 0.018 ; + RECT 73.647 0.000 73.665 0.054 ; END END w0_wd_in[511] PIN r0_rd_out[0] @@ -4619,7 +9227,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 129.231 0.000 129.249 0.018 ; + RECT 73.935 0.000 73.953 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -4628,7 +9236,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 129.735 0.000 129.753 0.018 ; + RECT 74.223 0.000 74.241 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -4637,7 +9245,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 130.239 0.000 130.257 0.018 ; + RECT 74.511 0.000 74.529 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -4646,7 +9254,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 130.743 0.000 130.761 0.018 ; + RECT 74.799 0.000 74.817 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -4655,7 +9263,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 131.247 0.000 131.265 0.018 ; + RECT 75.087 0.000 75.105 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -4664,7 +9272,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 131.751 0.000 131.769 0.018 ; + RECT 75.375 0.000 75.393 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -4673,7 +9281,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 132.255 0.000 132.273 0.018 ; + RECT 75.663 0.000 75.681 0.054 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -4682,7 +9290,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 132.759 0.000 132.777 0.018 ; + RECT 75.951 0.000 75.969 0.054 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -4691,7 +9299,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 133.263 0.000 133.281 0.018 ; + RECT 76.239 0.000 76.257 0.054 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -4700,7 +9308,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 133.767 0.000 133.785 0.018 ; + RECT 76.527 0.000 76.545 0.054 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -4709,7 +9317,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 134.271 0.000 134.289 0.018 ; + RECT 76.815 0.000 76.833 0.054 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -4718,7 +9326,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 134.775 0.000 134.793 0.018 ; + RECT 77.103 0.000 77.121 0.054 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -4727,7 +9335,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 135.279 0.000 135.297 0.018 ; + RECT 77.391 0.000 77.409 0.054 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -4736,7 +9344,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 135.783 0.000 135.801 0.018 ; + RECT 77.679 0.000 77.697 0.054 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -4745,7 +9353,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 136.287 0.000 136.305 0.018 ; + RECT 77.967 0.000 77.985 0.054 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -4754,7 +9362,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 136.791 0.000 136.809 0.018 ; + RECT 78.255 0.000 78.273 0.054 ; END END r0_rd_out[15] PIN r0_rd_out[16] @@ -4763,7 +9371,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 137.295 0.000 137.313 0.018 ; + RECT 78.543 0.000 78.561 0.054 ; END END r0_rd_out[16] PIN r0_rd_out[17] @@ -4772,7 +9380,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 137.799 0.000 137.817 0.018 ; + RECT 78.831 0.000 78.849 0.054 ; END END r0_rd_out[17] PIN r0_rd_out[18] @@ -4781,7 +9389,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 138.303 0.000 138.321 0.018 ; + RECT 79.119 0.000 79.137 0.054 ; END END r0_rd_out[18] PIN r0_rd_out[19] @@ -4790,7 +9398,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 138.807 0.000 138.825 0.018 ; + RECT 79.407 0.000 79.425 0.054 ; END END r0_rd_out[19] PIN r0_rd_out[20] @@ -4799,7 +9407,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 139.311 0.000 139.329 0.018 ; + RECT 79.695 0.000 79.713 0.054 ; END END r0_rd_out[20] PIN r0_rd_out[21] @@ -4808,7 +9416,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 139.815 0.000 139.833 0.018 ; + RECT 79.983 0.000 80.001 0.054 ; END END r0_rd_out[21] PIN r0_rd_out[22] @@ -4817,7 +9425,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 140.319 0.000 140.337 0.018 ; + RECT 80.271 0.000 80.289 0.054 ; END END r0_rd_out[22] PIN r0_rd_out[23] @@ -4826,7 +9434,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 140.823 0.000 140.841 0.018 ; + RECT 80.559 0.000 80.577 0.054 ; END END r0_rd_out[23] PIN r0_rd_out[24] @@ -4835,7 +9443,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 141.327 0.000 141.345 0.018 ; + RECT 80.847 0.000 80.865 0.054 ; END END r0_rd_out[24] PIN r0_rd_out[25] @@ -4844,7 +9452,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 141.831 0.000 141.849 0.018 ; + RECT 81.135 0.000 81.153 0.054 ; END END r0_rd_out[25] PIN r0_rd_out[26] @@ -4853,7 +9461,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 142.335 0.000 142.353 0.018 ; + RECT 81.423 0.000 81.441 0.054 ; END END r0_rd_out[26] PIN r0_rd_out[27] @@ -4862,7 +9470,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 142.839 0.000 142.857 0.018 ; + RECT 81.711 0.000 81.729 0.054 ; END END r0_rd_out[27] PIN r0_rd_out[28] @@ -4871,7 +9479,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 143.343 0.000 143.361 0.018 ; + RECT 81.999 0.000 82.017 0.054 ; END END r0_rd_out[28] PIN r0_rd_out[29] @@ -4880,7 +9488,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 143.847 0.000 143.865 0.018 ; + RECT 82.287 0.000 82.305 0.054 ; END END r0_rd_out[29] PIN r0_rd_out[30] @@ -4889,7 +9497,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 144.351 0.000 144.369 0.018 ; + RECT 82.575 0.000 82.593 0.054 ; END END r0_rd_out[30] PIN r0_rd_out[31] @@ -4898,7 +9506,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 144.855 0.000 144.873 0.018 ; + RECT 82.863 0.000 82.881 0.054 ; END END r0_rd_out[31] PIN r0_rd_out[32] @@ -4907,7 +9515,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 145.359 0.000 145.377 0.018 ; + RECT 83.151 0.000 83.169 0.054 ; END END r0_rd_out[32] PIN r0_rd_out[33] @@ -4916,7 +9524,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 145.863 0.000 145.881 0.018 ; + RECT 83.439 0.000 83.457 0.054 ; END END r0_rd_out[33] PIN r0_rd_out[34] @@ -4925,7 +9533,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 146.367 0.000 146.385 0.018 ; + RECT 83.727 0.000 83.745 0.054 ; END END r0_rd_out[34] PIN r0_rd_out[35] @@ -4934,7 +9542,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 146.871 0.000 146.889 0.018 ; + RECT 84.015 0.000 84.033 0.054 ; END END r0_rd_out[35] PIN r0_rd_out[36] @@ -4943,7 +9551,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 147.375 0.000 147.393 0.018 ; + RECT 84.303 0.000 84.321 0.054 ; END END r0_rd_out[36] PIN r0_rd_out[37] @@ -4952,7 +9560,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 147.879 0.000 147.897 0.018 ; + RECT 84.591 0.000 84.609 0.054 ; END END r0_rd_out[37] PIN r0_rd_out[38] @@ -4961,7 +9569,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 148.383 0.000 148.401 0.018 ; + RECT 84.879 0.000 84.897 0.054 ; END END r0_rd_out[38] PIN r0_rd_out[39] @@ -4970,7 +9578,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 148.887 0.000 148.905 0.018 ; + RECT 85.167 0.000 85.185 0.054 ; END END r0_rd_out[39] PIN r0_rd_out[40] @@ -4979,7 +9587,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 149.391 0.000 149.409 0.018 ; + RECT 85.455 0.000 85.473 0.054 ; END END r0_rd_out[40] PIN r0_rd_out[41] @@ -4988,7 +9596,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 149.895 0.000 149.913 0.018 ; + RECT 85.743 0.000 85.761 0.054 ; END END r0_rd_out[41] PIN r0_rd_out[42] @@ -4997,7 +9605,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 150.399 0.000 150.417 0.018 ; + RECT 86.031 0.000 86.049 0.054 ; END END r0_rd_out[42] PIN r0_rd_out[43] @@ -5006,7 +9614,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 150.903 0.000 150.921 0.018 ; + RECT 86.319 0.000 86.337 0.054 ; END END r0_rd_out[43] PIN r0_rd_out[44] @@ -5015,7 +9623,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 151.407 0.000 151.425 0.018 ; + RECT 86.607 0.000 86.625 0.054 ; END END r0_rd_out[44] PIN r0_rd_out[45] @@ -5024,7 +9632,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 151.911 0.000 151.929 0.018 ; + RECT 86.895 0.000 86.913 0.054 ; END END r0_rd_out[45] PIN r0_rd_out[46] @@ -5033,7 +9641,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 152.415 0.000 152.433 0.018 ; + RECT 87.183 0.000 87.201 0.054 ; END END r0_rd_out[46] PIN r0_rd_out[47] @@ -5042,7 +9650,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 152.919 0.000 152.937 0.018 ; + RECT 87.471 0.000 87.489 0.054 ; END END r0_rd_out[47] PIN r0_rd_out[48] @@ -5051,7 +9659,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 153.423 0.000 153.441 0.018 ; + RECT 87.759 0.000 87.777 0.054 ; END END r0_rd_out[48] PIN r0_rd_out[49] @@ -5060,7 +9668,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 153.927 0.000 153.945 0.018 ; + RECT 88.047 0.000 88.065 0.054 ; END END r0_rd_out[49] PIN r0_rd_out[50] @@ -5069,7 +9677,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 154.431 0.000 154.449 0.018 ; + RECT 88.335 0.000 88.353 0.054 ; END END r0_rd_out[50] PIN r0_rd_out[51] @@ -5078,7 +9686,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 154.935 0.000 154.953 0.018 ; + RECT 88.623 0.000 88.641 0.054 ; END END r0_rd_out[51] PIN r0_rd_out[52] @@ -5087,7 +9695,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 155.439 0.000 155.457 0.018 ; + RECT 88.911 0.000 88.929 0.054 ; END END r0_rd_out[52] PIN r0_rd_out[53] @@ -5096,7 +9704,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 155.943 0.000 155.961 0.018 ; + RECT 89.199 0.000 89.217 0.054 ; END END r0_rd_out[53] PIN r0_rd_out[54] @@ -5105,7 +9713,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 156.447 0.000 156.465 0.018 ; + RECT 89.487 0.000 89.505 0.054 ; END END r0_rd_out[54] PIN r0_rd_out[55] @@ -5114,7 +9722,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 156.951 0.000 156.969 0.018 ; + RECT 89.775 0.000 89.793 0.054 ; END END r0_rd_out[55] PIN r0_rd_out[56] @@ -5123,7 +9731,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 157.455 0.000 157.473 0.018 ; + RECT 90.063 0.000 90.081 0.054 ; END END r0_rd_out[56] PIN r0_rd_out[57] @@ -5132,7 +9740,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 157.959 0.000 157.977 0.018 ; + RECT 90.351 0.000 90.369 0.054 ; END END r0_rd_out[57] PIN r0_rd_out[58] @@ -5141,7 +9749,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 158.463 0.000 158.481 0.018 ; + RECT 90.639 0.000 90.657 0.054 ; END END r0_rd_out[58] PIN r0_rd_out[59] @@ -5150,7 +9758,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 158.967 0.000 158.985 0.018 ; + RECT 90.927 0.000 90.945 0.054 ; END END r0_rd_out[59] PIN r0_rd_out[60] @@ -5159,7 +9767,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 159.471 0.000 159.489 0.018 ; + RECT 91.215 0.000 91.233 0.054 ; END END r0_rd_out[60] PIN r0_rd_out[61] @@ -5168,7 +9776,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 159.975 0.000 159.993 0.018 ; + RECT 91.503 0.000 91.521 0.054 ; END END r0_rd_out[61] PIN r0_rd_out[62] @@ -5177,7 +9785,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 160.479 0.000 160.497 0.018 ; + RECT 91.791 0.000 91.809 0.054 ; END END r0_rd_out[62] PIN r0_rd_out[63] @@ -5186,7 +9794,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 160.983 0.000 161.001 0.018 ; + RECT 92.079 0.000 92.097 0.054 ; END END r0_rd_out[63] PIN r0_rd_out[64] @@ -5195,7 +9803,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 161.487 0.000 161.505 0.018 ; + RECT 92.367 0.000 92.385 0.054 ; END END r0_rd_out[64] PIN r0_rd_out[65] @@ -5204,7 +9812,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 161.991 0.000 162.009 0.018 ; + RECT 92.655 0.000 92.673 0.054 ; END END r0_rd_out[65] PIN r0_rd_out[66] @@ -5213,7 +9821,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 162.495 0.000 162.513 0.018 ; + RECT 92.943 0.000 92.961 0.054 ; END END r0_rd_out[66] PIN r0_rd_out[67] @@ -5222,7 +9830,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 162.999 0.000 163.017 0.018 ; + RECT 93.231 0.000 93.249 0.054 ; END END r0_rd_out[67] PIN r0_rd_out[68] @@ -5231,7 +9839,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 163.503 0.000 163.521 0.018 ; + RECT 93.519 0.000 93.537 0.054 ; END END r0_rd_out[68] PIN r0_rd_out[69] @@ -5240,7 +9848,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 164.007 0.000 164.025 0.018 ; + RECT 93.807 0.000 93.825 0.054 ; END END r0_rd_out[69] PIN r0_rd_out[70] @@ -5249,7 +9857,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 164.511 0.000 164.529 0.018 ; + RECT 94.095 0.000 94.113 0.054 ; END END r0_rd_out[70] PIN r0_rd_out[71] @@ -5258,7 +9866,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 165.015 0.000 165.033 0.018 ; + RECT 94.383 0.000 94.401 0.054 ; END END r0_rd_out[71] PIN r0_rd_out[72] @@ -5267,7 +9875,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 165.519 0.000 165.537 0.018 ; + RECT 94.671 0.000 94.689 0.054 ; END END r0_rd_out[72] PIN r0_rd_out[73] @@ -5276,7 +9884,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 166.023 0.000 166.041 0.018 ; + RECT 94.959 0.000 94.977 0.054 ; END END r0_rd_out[73] PIN r0_rd_out[74] @@ -5285,7 +9893,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 166.527 0.000 166.545 0.018 ; + RECT 95.247 0.000 95.265 0.054 ; END END r0_rd_out[74] PIN r0_rd_out[75] @@ -5294,7 +9902,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 167.031 0.000 167.049 0.018 ; + RECT 95.535 0.000 95.553 0.054 ; END END r0_rd_out[75] PIN r0_rd_out[76] @@ -5303,7 +9911,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 167.535 0.000 167.553 0.018 ; + RECT 95.823 0.000 95.841 0.054 ; END END r0_rd_out[76] PIN r0_rd_out[77] @@ -5312,7 +9920,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 168.039 0.000 168.057 0.018 ; + RECT 96.111 0.000 96.129 0.054 ; END END r0_rd_out[77] PIN r0_rd_out[78] @@ -5321,7 +9929,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 168.543 0.000 168.561 0.018 ; + RECT 96.399 0.000 96.417 0.054 ; END END r0_rd_out[78] PIN r0_rd_out[79] @@ -5330,7 +9938,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 169.047 0.000 169.065 0.018 ; + RECT 96.687 0.000 96.705 0.054 ; END END r0_rd_out[79] PIN r0_rd_out[80] @@ -5339,7 +9947,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 169.551 0.000 169.569 0.018 ; + RECT 96.975 0.000 96.993 0.054 ; END END r0_rd_out[80] PIN r0_rd_out[81] @@ -5348,7 +9956,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 170.055 0.000 170.073 0.018 ; + RECT 97.263 0.000 97.281 0.054 ; END END r0_rd_out[81] PIN r0_rd_out[82] @@ -5357,7 +9965,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 170.559 0.000 170.577 0.018 ; + RECT 97.551 0.000 97.569 0.054 ; END END r0_rd_out[82] PIN r0_rd_out[83] @@ -5366,7 +9974,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 171.063 0.000 171.081 0.018 ; + RECT 97.839 0.000 97.857 0.054 ; END END r0_rd_out[83] PIN r0_rd_out[84] @@ -5375,7 +9983,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 171.567 0.000 171.585 0.018 ; + RECT 98.127 0.000 98.145 0.054 ; END END r0_rd_out[84] PIN r0_rd_out[85] @@ -5384,7 +9992,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 172.071 0.000 172.089 0.018 ; + RECT 98.415 0.000 98.433 0.054 ; END END r0_rd_out[85] PIN r0_rd_out[86] @@ -5393,7 +10001,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 172.575 0.000 172.593 0.018 ; + RECT 98.703 0.000 98.721 0.054 ; END END r0_rd_out[86] PIN r0_rd_out[87] @@ -5402,7 +10010,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 173.079 0.000 173.097 0.018 ; + RECT 98.991 0.000 99.009 0.054 ; END END r0_rd_out[87] PIN r0_rd_out[88] @@ -5411,7 +10019,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 173.583 0.000 173.601 0.018 ; + RECT 99.279 0.000 99.297 0.054 ; END END r0_rd_out[88] PIN r0_rd_out[89] @@ -5420,7 +10028,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 174.087 0.000 174.105 0.018 ; + RECT 99.567 0.000 99.585 0.054 ; END END r0_rd_out[89] PIN r0_rd_out[90] @@ -5429,7 +10037,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 174.591 0.000 174.609 0.018 ; + RECT 99.855 0.000 99.873 0.054 ; END END r0_rd_out[90] PIN r0_rd_out[91] @@ -5438,7 +10046,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 175.095 0.000 175.113 0.018 ; + RECT 100.143 0.000 100.161 0.054 ; END END r0_rd_out[91] PIN r0_rd_out[92] @@ -5447,7 +10055,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 175.599 0.000 175.617 0.018 ; + RECT 100.431 0.000 100.449 0.054 ; END END r0_rd_out[92] PIN r0_rd_out[93] @@ -5456,7 +10064,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 176.103 0.000 176.121 0.018 ; + RECT 100.719 0.000 100.737 0.054 ; END END r0_rd_out[93] PIN r0_rd_out[94] @@ -5465,7 +10073,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 176.607 0.000 176.625 0.018 ; + RECT 101.007 0.000 101.025 0.054 ; END END r0_rd_out[94] PIN r0_rd_out[95] @@ -5474,7 +10082,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 177.111 0.000 177.129 0.018 ; + RECT 101.295 0.000 101.313 0.054 ; END END r0_rd_out[95] PIN r0_rd_out[96] @@ -5483,7 +10091,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 177.615 0.000 177.633 0.018 ; + RECT 101.583 0.000 101.601 0.054 ; END END r0_rd_out[96] PIN r0_rd_out[97] @@ -5492,7 +10100,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 178.119 0.000 178.137 0.018 ; + RECT 101.871 0.000 101.889 0.054 ; END END r0_rd_out[97] PIN r0_rd_out[98] @@ -5501,7 +10109,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 178.623 0.000 178.641 0.018 ; + RECT 102.159 0.000 102.177 0.054 ; END END r0_rd_out[98] PIN r0_rd_out[99] @@ -5510,7 +10118,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 179.127 0.000 179.145 0.018 ; + RECT 102.447 0.000 102.465 0.054 ; END END r0_rd_out[99] PIN r0_rd_out[100] @@ -5519,7 +10127,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 179.631 0.000 179.649 0.018 ; + RECT 102.735 0.000 102.753 0.054 ; END END r0_rd_out[100] PIN r0_rd_out[101] @@ -5528,7 +10136,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 180.135 0.000 180.153 0.018 ; + RECT 103.023 0.000 103.041 0.054 ; END END r0_rd_out[101] PIN r0_rd_out[102] @@ -5537,7 +10145,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 180.639 0.000 180.657 0.018 ; + RECT 103.311 0.000 103.329 0.054 ; END END r0_rd_out[102] PIN r0_rd_out[103] @@ -5546,7 +10154,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 181.143 0.000 181.161 0.018 ; + RECT 103.599 0.000 103.617 0.054 ; END END r0_rd_out[103] PIN r0_rd_out[104] @@ -5555,7 +10163,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 181.647 0.000 181.665 0.018 ; + RECT 103.887 0.000 103.905 0.054 ; END END r0_rd_out[104] PIN r0_rd_out[105] @@ -5564,7 +10172,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 182.151 0.000 182.169 0.018 ; + RECT 104.175 0.000 104.193 0.054 ; END END r0_rd_out[105] PIN r0_rd_out[106] @@ -5573,7 +10181,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 182.655 0.000 182.673 0.018 ; + RECT 104.463 0.000 104.481 0.054 ; END END r0_rd_out[106] PIN r0_rd_out[107] @@ -5582,7 +10190,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 183.159 0.000 183.177 0.018 ; + RECT 104.751 0.000 104.769 0.054 ; END END r0_rd_out[107] PIN r0_rd_out[108] @@ -5591,7 +10199,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 183.663 0.000 183.681 0.018 ; + RECT 105.039 0.000 105.057 0.054 ; END END r0_rd_out[108] PIN r0_rd_out[109] @@ -5600,7 +10208,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 184.167 0.000 184.185 0.018 ; + RECT 105.327 0.000 105.345 0.054 ; END END r0_rd_out[109] PIN r0_rd_out[110] @@ -5609,7 +10217,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 184.671 0.000 184.689 0.018 ; + RECT 105.615 0.000 105.633 0.054 ; END END r0_rd_out[110] PIN r0_rd_out[111] @@ -5618,7 +10226,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 185.175 0.000 185.193 0.018 ; + RECT 105.903 0.000 105.921 0.054 ; END END r0_rd_out[111] PIN r0_rd_out[112] @@ -5627,7 +10235,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 185.679 0.000 185.697 0.018 ; + RECT 106.191 0.000 106.209 0.054 ; END END r0_rd_out[112] PIN r0_rd_out[113] @@ -5636,7 +10244,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 186.183 0.000 186.201 0.018 ; + RECT 106.479 0.000 106.497 0.054 ; END END r0_rd_out[113] PIN r0_rd_out[114] @@ -5645,7 +10253,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 186.687 0.000 186.705 0.018 ; + RECT 106.767 0.000 106.785 0.054 ; END END r0_rd_out[114] PIN r0_rd_out[115] @@ -5654,7 +10262,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 187.191 0.000 187.209 0.018 ; + RECT 107.055 0.000 107.073 0.054 ; END END r0_rd_out[115] PIN r0_rd_out[116] @@ -5663,7 +10271,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 187.695 0.000 187.713 0.018 ; + RECT 107.343 0.000 107.361 0.054 ; END END r0_rd_out[116] PIN r0_rd_out[117] @@ -5672,7 +10280,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 188.199 0.000 188.217 0.018 ; + RECT 107.631 0.000 107.649 0.054 ; END END r0_rd_out[117] PIN r0_rd_out[118] @@ -5681,7 +10289,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 188.703 0.000 188.721 0.018 ; + RECT 107.919 0.000 107.937 0.054 ; END END r0_rd_out[118] PIN r0_rd_out[119] @@ -5690,7 +10298,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 189.207 0.000 189.225 0.018 ; + RECT 108.207 0.000 108.225 0.054 ; END END r0_rd_out[119] PIN r0_rd_out[120] @@ -5699,7 +10307,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 189.711 0.000 189.729 0.018 ; + RECT 108.495 0.000 108.513 0.054 ; END END r0_rd_out[120] PIN r0_rd_out[121] @@ -5708,7 +10316,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 190.215 0.000 190.233 0.018 ; + RECT 108.783 0.000 108.801 0.054 ; END END r0_rd_out[121] PIN r0_rd_out[122] @@ -5717,7 +10325,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 190.719 0.000 190.737 0.018 ; + RECT 109.071 0.000 109.089 0.054 ; END END r0_rd_out[122] PIN r0_rd_out[123] @@ -5726,7 +10334,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 191.223 0.000 191.241 0.018 ; + RECT 109.359 0.000 109.377 0.054 ; END END r0_rd_out[123] PIN r0_rd_out[124] @@ -5735,7 +10343,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 191.727 0.000 191.745 0.018 ; + RECT 109.647 0.000 109.665 0.054 ; END END r0_rd_out[124] PIN r0_rd_out[125] @@ -5744,7 +10352,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 192.231 0.000 192.249 0.018 ; + RECT 109.935 0.000 109.953 0.054 ; END END r0_rd_out[125] PIN r0_rd_out[126] @@ -5753,7 +10361,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 192.735 0.000 192.753 0.018 ; + RECT 110.223 0.000 110.241 0.054 ; END END r0_rd_out[126] PIN r0_rd_out[127] @@ -5762,7 +10370,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 193.239 0.000 193.257 0.018 ; + RECT 110.511 0.000 110.529 0.054 ; END END r0_rd_out[127] PIN r0_rd_out[128] @@ -5771,7 +10379,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 193.743 0.000 193.761 0.018 ; + RECT 110.799 0.000 110.817 0.054 ; END END r0_rd_out[128] PIN r0_rd_out[129] @@ -5780,7 +10388,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 194.247 0.000 194.265 0.018 ; + RECT 111.087 0.000 111.105 0.054 ; END END r0_rd_out[129] PIN r0_rd_out[130] @@ -5789,7 +10397,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 194.751 0.000 194.769 0.018 ; + RECT 111.375 0.000 111.393 0.054 ; END END r0_rd_out[130] PIN r0_rd_out[131] @@ -5798,7 +10406,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 195.255 0.000 195.273 0.018 ; + RECT 111.663 0.000 111.681 0.054 ; END END r0_rd_out[131] PIN r0_rd_out[132] @@ -5807,7 +10415,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 195.759 0.000 195.777 0.018 ; + RECT 111.951 0.000 111.969 0.054 ; END END r0_rd_out[132] PIN r0_rd_out[133] @@ -5816,7 +10424,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 196.263 0.000 196.281 0.018 ; + RECT 112.239 0.000 112.257 0.054 ; END END r0_rd_out[133] PIN r0_rd_out[134] @@ -5825,7 +10433,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 196.767 0.000 196.785 0.018 ; + RECT 112.527 0.000 112.545 0.054 ; END END r0_rd_out[134] PIN r0_rd_out[135] @@ -5834,7 +10442,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 197.271 0.000 197.289 0.018 ; + RECT 112.815 0.000 112.833 0.054 ; END END r0_rd_out[135] PIN r0_rd_out[136] @@ -5843,7 +10451,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 197.775 0.000 197.793 0.018 ; + RECT 113.103 0.000 113.121 0.054 ; END END r0_rd_out[136] PIN r0_rd_out[137] @@ -5852,7 +10460,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 198.279 0.000 198.297 0.018 ; + RECT 113.391 0.000 113.409 0.054 ; END END r0_rd_out[137] PIN r0_rd_out[138] @@ -5861,7 +10469,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 198.783 0.000 198.801 0.018 ; + RECT 113.679 0.000 113.697 0.054 ; END END r0_rd_out[138] PIN r0_rd_out[139] @@ -5870,7 +10478,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 199.287 0.000 199.305 0.018 ; + RECT 113.967 0.000 113.985 0.054 ; END END r0_rd_out[139] PIN r0_rd_out[140] @@ -5879,7 +10487,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 199.791 0.000 199.809 0.018 ; + RECT 114.255 0.000 114.273 0.054 ; END END r0_rd_out[140] PIN r0_rd_out[141] @@ -5888,7 +10496,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 200.295 0.000 200.313 0.018 ; + RECT 114.543 0.000 114.561 0.054 ; END END r0_rd_out[141] PIN r0_rd_out[142] @@ -5897,7 +10505,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 200.799 0.000 200.817 0.018 ; + RECT 114.831 0.000 114.849 0.054 ; END END r0_rd_out[142] PIN r0_rd_out[143] @@ -5906,7 +10514,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 201.303 0.000 201.321 0.018 ; + RECT 115.119 0.000 115.137 0.054 ; END END r0_rd_out[143] PIN r0_rd_out[144] @@ -5915,7 +10523,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 201.807 0.000 201.825 0.018 ; + RECT 115.407 0.000 115.425 0.054 ; END END r0_rd_out[144] PIN r0_rd_out[145] @@ -5924,7 +10532,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 202.311 0.000 202.329 0.018 ; + RECT 115.695 0.000 115.713 0.054 ; END END r0_rd_out[145] PIN r0_rd_out[146] @@ -5933,7 +10541,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 202.815 0.000 202.833 0.018 ; + RECT 115.983 0.000 116.001 0.054 ; END END r0_rd_out[146] PIN r0_rd_out[147] @@ -5942,7 +10550,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 203.319 0.000 203.337 0.018 ; + RECT 116.271 0.000 116.289 0.054 ; END END r0_rd_out[147] PIN r0_rd_out[148] @@ -5951,7 +10559,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 203.823 0.000 203.841 0.018 ; + RECT 116.559 0.000 116.577 0.054 ; END END r0_rd_out[148] PIN r0_rd_out[149] @@ -5960,7 +10568,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 204.327 0.000 204.345 0.018 ; + RECT 116.847 0.000 116.865 0.054 ; END END r0_rd_out[149] PIN r0_rd_out[150] @@ -5969,7 +10577,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 204.831 0.000 204.849 0.018 ; + RECT 117.135 0.000 117.153 0.054 ; END END r0_rd_out[150] PIN r0_rd_out[151] @@ -5978,7 +10586,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 205.335 0.000 205.353 0.018 ; + RECT 117.423 0.000 117.441 0.054 ; END END r0_rd_out[151] PIN r0_rd_out[152] @@ -5987,7 +10595,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 205.839 0.000 205.857 0.018 ; + RECT 117.711 0.000 117.729 0.054 ; END END r0_rd_out[152] PIN r0_rd_out[153] @@ -5996,7 +10604,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 206.343 0.000 206.361 0.018 ; + RECT 117.999 0.000 118.017 0.054 ; END END r0_rd_out[153] PIN r0_rd_out[154] @@ -6005,7 +10613,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 206.847 0.000 206.865 0.018 ; + RECT 118.287 0.000 118.305 0.054 ; END END r0_rd_out[154] PIN r0_rd_out[155] @@ -6014,7 +10622,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 207.351 0.000 207.369 0.018 ; + RECT 118.575 0.000 118.593 0.054 ; END END r0_rd_out[155] PIN r0_rd_out[156] @@ -6023,7 +10631,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 207.855 0.000 207.873 0.018 ; + RECT 118.863 0.000 118.881 0.054 ; END END r0_rd_out[156] PIN r0_rd_out[157] @@ -6032,7 +10640,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 208.359 0.000 208.377 0.018 ; + RECT 119.151 0.000 119.169 0.054 ; END END r0_rd_out[157] PIN r0_rd_out[158] @@ -6041,7 +10649,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 208.863 0.000 208.881 0.018 ; + RECT 119.439 0.000 119.457 0.054 ; END END r0_rd_out[158] PIN r0_rd_out[159] @@ -6050,7 +10658,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 209.367 0.000 209.385 0.018 ; + RECT 119.727 0.000 119.745 0.054 ; END END r0_rd_out[159] PIN r0_rd_out[160] @@ -6059,7 +10667,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 209.871 0.000 209.889 0.018 ; + RECT 120.015 0.000 120.033 0.054 ; END END r0_rd_out[160] PIN r0_rd_out[161] @@ -6068,7 +10676,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 210.375 0.000 210.393 0.018 ; + RECT 120.303 0.000 120.321 0.054 ; END END r0_rd_out[161] PIN r0_rd_out[162] @@ -6077,7 +10685,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 210.879 0.000 210.897 0.018 ; + RECT 120.591 0.000 120.609 0.054 ; END END r0_rd_out[162] PIN r0_rd_out[163] @@ -6086,7 +10694,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 211.383 0.000 211.401 0.018 ; + RECT 120.879 0.000 120.897 0.054 ; END END r0_rd_out[163] PIN r0_rd_out[164] @@ -6095,7 +10703,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 211.887 0.000 211.905 0.018 ; + RECT 121.167 0.000 121.185 0.054 ; END END r0_rd_out[164] PIN r0_rd_out[165] @@ -6104,7 +10712,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 212.391 0.000 212.409 0.018 ; + RECT 121.455 0.000 121.473 0.054 ; END END r0_rd_out[165] PIN r0_rd_out[166] @@ -6113,7 +10721,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 212.895 0.000 212.913 0.018 ; + RECT 121.743 0.000 121.761 0.054 ; END END r0_rd_out[166] PIN r0_rd_out[167] @@ -6122,7 +10730,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 213.399 0.000 213.417 0.018 ; + RECT 122.031 0.000 122.049 0.054 ; END END r0_rd_out[167] PIN r0_rd_out[168] @@ -6131,7 +10739,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 213.903 0.000 213.921 0.018 ; + RECT 122.319 0.000 122.337 0.054 ; END END r0_rd_out[168] PIN r0_rd_out[169] @@ -6140,7 +10748,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 214.407 0.000 214.425 0.018 ; + RECT 122.607 0.000 122.625 0.054 ; END END r0_rd_out[169] PIN r0_rd_out[170] @@ -6149,7 +10757,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 214.911 0.000 214.929 0.018 ; + RECT 122.895 0.000 122.913 0.054 ; END END r0_rd_out[170] PIN r0_rd_out[171] @@ -6158,7 +10766,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 215.415 0.000 215.433 0.018 ; + RECT 123.183 0.000 123.201 0.054 ; END END r0_rd_out[171] PIN r0_rd_out[172] @@ -6167,7 +10775,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 215.919 0.000 215.937 0.018 ; + RECT 123.471 0.000 123.489 0.054 ; END END r0_rd_out[172] PIN r0_rd_out[173] @@ -6176,7 +10784,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 216.423 0.000 216.441 0.018 ; + RECT 123.759 0.000 123.777 0.054 ; END END r0_rd_out[173] PIN r0_rd_out[174] @@ -6185,7 +10793,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 216.927 0.000 216.945 0.018 ; + RECT 124.047 0.000 124.065 0.054 ; END END r0_rd_out[174] PIN r0_rd_out[175] @@ -6194,7 +10802,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 217.431 0.000 217.449 0.018 ; + RECT 124.335 0.000 124.353 0.054 ; END END r0_rd_out[175] PIN r0_rd_out[176] @@ -6203,7 +10811,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 217.935 0.000 217.953 0.018 ; + RECT 124.623 0.000 124.641 0.054 ; END END r0_rd_out[176] PIN r0_rd_out[177] @@ -6212,7 +10820,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 218.439 0.000 218.457 0.018 ; + RECT 124.911 0.000 124.929 0.054 ; END END r0_rd_out[177] PIN r0_rd_out[178] @@ -6221,7 +10829,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 218.943 0.000 218.961 0.018 ; + RECT 125.199 0.000 125.217 0.054 ; END END r0_rd_out[178] PIN r0_rd_out[179] @@ -6230,7 +10838,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 219.447 0.000 219.465 0.018 ; + RECT 125.487 0.000 125.505 0.054 ; END END r0_rd_out[179] PIN r0_rd_out[180] @@ -6239,7 +10847,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 219.951 0.000 219.969 0.018 ; + RECT 125.775 0.000 125.793 0.054 ; END END r0_rd_out[180] PIN r0_rd_out[181] @@ -6248,7 +10856,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 220.455 0.000 220.473 0.018 ; + RECT 126.063 0.000 126.081 0.054 ; END END r0_rd_out[181] PIN r0_rd_out[182] @@ -6257,7 +10865,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 220.959 0.000 220.977 0.018 ; + RECT 126.351 0.000 126.369 0.054 ; END END r0_rd_out[182] PIN r0_rd_out[183] @@ -6266,7 +10874,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 221.463 0.000 221.481 0.018 ; + RECT 126.639 0.000 126.657 0.054 ; END END r0_rd_out[183] PIN r0_rd_out[184] @@ -6275,7 +10883,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 221.967 0.000 221.985 0.018 ; + RECT 126.927 0.000 126.945 0.054 ; END END r0_rd_out[184] PIN r0_rd_out[185] @@ -6284,7 +10892,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 222.471 0.000 222.489 0.018 ; + RECT 127.215 0.000 127.233 0.054 ; END END r0_rd_out[185] PIN r0_rd_out[186] @@ -6293,7 +10901,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 222.975 0.000 222.993 0.018 ; + RECT 127.503 0.000 127.521 0.054 ; END END r0_rd_out[186] PIN r0_rd_out[187] @@ -6302,7 +10910,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 223.479 0.000 223.497 0.018 ; + RECT 127.791 0.000 127.809 0.054 ; END END r0_rd_out[187] PIN r0_rd_out[188] @@ -6311,7 +10919,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 223.983 0.000 224.001 0.018 ; + RECT 128.079 0.000 128.097 0.054 ; END END r0_rd_out[188] PIN r0_rd_out[189] @@ -6320,7 +10928,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 224.487 0.000 224.505 0.018 ; + RECT 128.367 0.000 128.385 0.054 ; END END r0_rd_out[189] PIN r0_rd_out[190] @@ -6329,7 +10937,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 224.991 0.000 225.009 0.018 ; + RECT 128.655 0.000 128.673 0.054 ; END END r0_rd_out[190] PIN r0_rd_out[191] @@ -6338,7 +10946,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 225.495 0.000 225.513 0.018 ; + RECT 128.943 0.000 128.961 0.054 ; END END r0_rd_out[191] PIN r0_rd_out[192] @@ -6347,7 +10955,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 225.999 0.000 226.017 0.018 ; + RECT 129.231 0.000 129.249 0.054 ; END END r0_rd_out[192] PIN r0_rd_out[193] @@ -6356,7 +10964,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 226.503 0.000 226.521 0.018 ; + RECT 129.519 0.000 129.537 0.054 ; END END r0_rd_out[193] PIN r0_rd_out[194] @@ -6365,7 +10973,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 227.007 0.000 227.025 0.018 ; + RECT 129.807 0.000 129.825 0.054 ; END END r0_rd_out[194] PIN r0_rd_out[195] @@ -6374,7 +10982,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 227.511 0.000 227.529 0.018 ; + RECT 130.095 0.000 130.113 0.054 ; END END r0_rd_out[195] PIN r0_rd_out[196] @@ -6383,7 +10991,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 228.015 0.000 228.033 0.018 ; + RECT 130.383 0.000 130.401 0.054 ; END END r0_rd_out[196] PIN r0_rd_out[197] @@ -6392,7 +11000,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 228.519 0.000 228.537 0.018 ; + RECT 130.671 0.000 130.689 0.054 ; END END r0_rd_out[197] PIN r0_rd_out[198] @@ -6401,7 +11009,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 229.023 0.000 229.041 0.018 ; + RECT 130.959 0.000 130.977 0.054 ; END END r0_rd_out[198] PIN r0_rd_out[199] @@ -6410,7 +11018,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 229.527 0.000 229.545 0.018 ; + RECT 131.247 0.000 131.265 0.054 ; END END r0_rd_out[199] PIN r0_rd_out[200] @@ -6419,7 +11027,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 230.031 0.000 230.049 0.018 ; + RECT 131.535 0.000 131.553 0.054 ; END END r0_rd_out[200] PIN r0_rd_out[201] @@ -6428,7 +11036,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 230.535 0.000 230.553 0.018 ; + RECT 131.823 0.000 131.841 0.054 ; END END r0_rd_out[201] PIN r0_rd_out[202] @@ -6437,7 +11045,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 231.039 0.000 231.057 0.018 ; + RECT 132.111 0.000 132.129 0.054 ; END END r0_rd_out[202] PIN r0_rd_out[203] @@ -6446,7 +11054,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 231.543 0.000 231.561 0.018 ; + RECT 132.399 0.000 132.417 0.054 ; END END r0_rd_out[203] PIN r0_rd_out[204] @@ -6455,7 +11063,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 232.047 0.000 232.065 0.018 ; + RECT 132.687 0.000 132.705 0.054 ; END END r0_rd_out[204] PIN r0_rd_out[205] @@ -6464,7 +11072,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 232.551 0.000 232.569 0.018 ; + RECT 132.975 0.000 132.993 0.054 ; END END r0_rd_out[205] PIN r0_rd_out[206] @@ -6473,7 +11081,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 233.055 0.000 233.073 0.018 ; + RECT 133.263 0.000 133.281 0.054 ; END END r0_rd_out[206] PIN r0_rd_out[207] @@ -6482,7 +11090,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 233.559 0.000 233.577 0.018 ; + RECT 133.551 0.000 133.569 0.054 ; END END r0_rd_out[207] PIN r0_rd_out[208] @@ -6491,7 +11099,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 234.063 0.000 234.081 0.018 ; + RECT 133.839 0.000 133.857 0.054 ; END END r0_rd_out[208] PIN r0_rd_out[209] @@ -6500,7 +11108,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 234.567 0.000 234.585 0.018 ; + RECT 134.127 0.000 134.145 0.054 ; END END r0_rd_out[209] PIN r0_rd_out[210] @@ -6509,7 +11117,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 235.071 0.000 235.089 0.018 ; + RECT 134.415 0.000 134.433 0.054 ; END END r0_rd_out[210] PIN r0_rd_out[211] @@ -6518,7 +11126,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 235.575 0.000 235.593 0.018 ; + RECT 134.703 0.000 134.721 0.054 ; END END r0_rd_out[211] PIN r0_rd_out[212] @@ -6527,7 +11135,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 236.079 0.000 236.097 0.018 ; + RECT 134.991 0.000 135.009 0.054 ; END END r0_rd_out[212] PIN r0_rd_out[213] @@ -6536,7 +11144,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 236.583 0.000 236.601 0.018 ; + RECT 135.279 0.000 135.297 0.054 ; END END r0_rd_out[213] PIN r0_rd_out[214] @@ -6545,7 +11153,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 237.087 0.000 237.105 0.018 ; + RECT 135.567 0.000 135.585 0.054 ; END END r0_rd_out[214] PIN r0_rd_out[215] @@ -6554,7 +11162,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 237.591 0.000 237.609 0.018 ; + RECT 135.855 0.000 135.873 0.054 ; END END r0_rd_out[215] PIN r0_rd_out[216] @@ -6563,7 +11171,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 238.095 0.000 238.113 0.018 ; + RECT 136.143 0.000 136.161 0.054 ; END END r0_rd_out[216] PIN r0_rd_out[217] @@ -6572,7 +11180,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 238.599 0.000 238.617 0.018 ; + RECT 136.431 0.000 136.449 0.054 ; END END r0_rd_out[217] PIN r0_rd_out[218] @@ -6581,7 +11189,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 239.103 0.000 239.121 0.018 ; + RECT 136.719 0.000 136.737 0.054 ; END END r0_rd_out[218] PIN r0_rd_out[219] @@ -6590,7 +11198,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 239.607 0.000 239.625 0.018 ; + RECT 137.007 0.000 137.025 0.054 ; END END r0_rd_out[219] PIN r0_rd_out[220] @@ -6599,7 +11207,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 240.111 0.000 240.129 0.018 ; + RECT 137.295 0.000 137.313 0.054 ; END END r0_rd_out[220] PIN r0_rd_out[221] @@ -6608,7 +11216,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 240.615 0.000 240.633 0.018 ; + RECT 137.583 0.000 137.601 0.054 ; END END r0_rd_out[221] PIN r0_rd_out[222] @@ -6617,7 +11225,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 241.119 0.000 241.137 0.018 ; + RECT 137.871 0.000 137.889 0.054 ; END END r0_rd_out[222] PIN r0_rd_out[223] @@ -6626,7 +11234,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 241.623 0.000 241.641 0.018 ; + RECT 138.159 0.000 138.177 0.054 ; END END r0_rd_out[223] PIN r0_rd_out[224] @@ -6635,7 +11243,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 242.127 0.000 242.145 0.018 ; + RECT 138.447 0.000 138.465 0.054 ; END END r0_rd_out[224] PIN r0_rd_out[225] @@ -6644,7 +11252,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 242.631 0.000 242.649 0.018 ; + RECT 138.735 0.000 138.753 0.054 ; END END r0_rd_out[225] PIN r0_rd_out[226] @@ -6653,7 +11261,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 243.135 0.000 243.153 0.018 ; + RECT 139.023 0.000 139.041 0.054 ; END END r0_rd_out[226] PIN r0_rd_out[227] @@ -6662,7 +11270,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 243.639 0.000 243.657 0.018 ; + RECT 139.311 0.000 139.329 0.054 ; END END r0_rd_out[227] PIN r0_rd_out[228] @@ -6671,7 +11279,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 244.143 0.000 244.161 0.018 ; + RECT 139.599 0.000 139.617 0.054 ; END END r0_rd_out[228] PIN r0_rd_out[229] @@ -6680,7 +11288,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 244.647 0.000 244.665 0.018 ; + RECT 139.887 0.000 139.905 0.054 ; END END r0_rd_out[229] PIN r0_rd_out[230] @@ -6689,7 +11297,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 245.151 0.000 245.169 0.018 ; + RECT 140.175 0.000 140.193 0.054 ; END END r0_rd_out[230] PIN r0_rd_out[231] @@ -6698,7 +11306,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 245.655 0.000 245.673 0.018 ; + RECT 140.463 0.000 140.481 0.054 ; END END r0_rd_out[231] PIN r0_rd_out[232] @@ -6707,7 +11315,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 246.159 0.000 246.177 0.018 ; + RECT 140.751 0.000 140.769 0.054 ; END END r0_rd_out[232] PIN r0_rd_out[233] @@ -6716,7 +11324,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 246.663 0.000 246.681 0.018 ; + RECT 141.039 0.000 141.057 0.054 ; END END r0_rd_out[233] PIN r0_rd_out[234] @@ -6725,7 +11333,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 247.167 0.000 247.185 0.018 ; + RECT 141.327 0.000 141.345 0.054 ; END END r0_rd_out[234] PIN r0_rd_out[235] @@ -6734,7 +11342,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 247.671 0.000 247.689 0.018 ; + RECT 141.615 0.000 141.633 0.054 ; END END r0_rd_out[235] PIN r0_rd_out[236] @@ -6743,7 +11351,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 248.175 0.000 248.193 0.018 ; + RECT 141.903 0.000 141.921 0.054 ; END END r0_rd_out[236] PIN r0_rd_out[237] @@ -6752,7 +11360,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 248.679 0.000 248.697 0.018 ; + RECT 142.191 0.000 142.209 0.054 ; END END r0_rd_out[237] PIN r0_rd_out[238] @@ -6761,7 +11369,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 249.183 0.000 249.201 0.018 ; + RECT 142.479 0.000 142.497 0.054 ; END END r0_rd_out[238] PIN r0_rd_out[239] @@ -6770,7 +11378,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 249.687 0.000 249.705 0.018 ; + RECT 142.767 0.000 142.785 0.054 ; END END r0_rd_out[239] PIN r0_rd_out[240] @@ -6779,7 +11387,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 250.191 0.000 250.209 0.018 ; + RECT 143.055 0.000 143.073 0.054 ; END END r0_rd_out[240] PIN r0_rd_out[241] @@ -6788,7 +11396,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 250.695 0.000 250.713 0.018 ; + RECT 143.343 0.000 143.361 0.054 ; END END r0_rd_out[241] PIN r0_rd_out[242] @@ -6797,7 +11405,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 251.199 0.000 251.217 0.018 ; + RECT 143.631 0.000 143.649 0.054 ; END END r0_rd_out[242] PIN r0_rd_out[243] @@ -6806,7 +11414,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 251.703 0.000 251.721 0.018 ; + RECT 143.919 0.000 143.937 0.054 ; END END r0_rd_out[243] PIN r0_rd_out[244] @@ -6815,7 +11423,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 252.207 0.000 252.225 0.018 ; + RECT 144.207 0.000 144.225 0.054 ; END END r0_rd_out[244] PIN r0_rd_out[245] @@ -6824,7 +11432,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 252.711 0.000 252.729 0.018 ; + RECT 144.495 0.000 144.513 0.054 ; END END r0_rd_out[245] PIN r0_rd_out[246] @@ -6833,7 +11441,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 253.215 0.000 253.233 0.018 ; + RECT 144.783 0.000 144.801 0.054 ; END END r0_rd_out[246] PIN r0_rd_out[247] @@ -6842,7 +11450,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 253.719 0.000 253.737 0.018 ; + RECT 145.071 0.000 145.089 0.054 ; END END r0_rd_out[247] PIN r0_rd_out[248] @@ -6851,7 +11459,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 254.223 0.000 254.241 0.018 ; + RECT 145.359 0.000 145.377 0.054 ; END END r0_rd_out[248] PIN r0_rd_out[249] @@ -6860,7 +11468,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 254.727 0.000 254.745 0.018 ; + RECT 145.647 0.000 145.665 0.054 ; END END r0_rd_out[249] PIN r0_rd_out[250] @@ -6869,7 +11477,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 255.231 0.000 255.249 0.018 ; + RECT 145.935 0.000 145.953 0.054 ; END END r0_rd_out[250] PIN r0_rd_out[251] @@ -6878,7 +11486,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 255.735 0.000 255.753 0.018 ; + RECT 146.223 0.000 146.241 0.054 ; END END r0_rd_out[251] PIN r0_rd_out[252] @@ -6887,7 +11495,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 256.239 0.000 256.257 0.018 ; + RECT 146.511 0.000 146.529 0.054 ; END END r0_rd_out[252] PIN r0_rd_out[253] @@ -6896,7 +11504,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 256.743 0.000 256.761 0.018 ; + RECT 146.799 0.000 146.817 0.054 ; END END r0_rd_out[253] PIN r0_rd_out[254] @@ -6905,7 +11513,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 257.247 0.000 257.265 0.018 ; + RECT 147.087 0.000 147.105 0.054 ; END END r0_rd_out[254] PIN r0_rd_out[255] @@ -6914,7 +11522,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 257.751 0.000 257.769 0.018 ; + RECT 147.375 0.000 147.393 0.054 ; END END r0_rd_out[255] PIN r0_rd_out[256] @@ -6923,7 +11531,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 20.718 0.225 20.736 ; + RECT 73.935 90.632 73.953 90.686 ; END END r0_rd_out[256] PIN r0_rd_out[257] @@ -6932,7 +11540,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.215 20.718 1.233 20.736 ; + RECT 74.223 90.632 74.241 90.686 ; END END r0_rd_out[257] PIN r0_rd_out[258] @@ -6941,7 +11549,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.223 20.718 2.241 20.736 ; + RECT 74.511 90.632 74.529 90.686 ; END END r0_rd_out[258] PIN r0_rd_out[259] @@ -6950,7 +11558,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.231 20.718 3.249 20.736 ; + RECT 74.799 90.632 74.817 90.686 ; END END r0_rd_out[259] PIN r0_rd_out[260] @@ -6959,7 +11567,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.239 20.718 4.257 20.736 ; + RECT 75.087 90.632 75.105 90.686 ; END END r0_rd_out[260] PIN r0_rd_out[261] @@ -6968,7 +11576,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.247 20.718 5.265 20.736 ; + RECT 75.375 90.632 75.393 90.686 ; END END r0_rd_out[261] PIN r0_rd_out[262] @@ -6977,7 +11585,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.255 20.718 6.273 20.736 ; + RECT 75.663 90.632 75.681 90.686 ; END END r0_rd_out[262] PIN r0_rd_out[263] @@ -6986,7 +11594,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.263 20.718 7.281 20.736 ; + RECT 75.951 90.632 75.969 90.686 ; END END r0_rd_out[263] PIN r0_rd_out[264] @@ -6995,7 +11603,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.271 20.718 8.289 20.736 ; + RECT 76.239 90.632 76.257 90.686 ; END END r0_rd_out[264] PIN r0_rd_out[265] @@ -7004,7 +11612,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.279 20.718 9.297 20.736 ; + RECT 76.527 90.632 76.545 90.686 ; END END r0_rd_out[265] PIN r0_rd_out[266] @@ -7013,7 +11621,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.287 20.718 10.305 20.736 ; + RECT 76.815 90.632 76.833 90.686 ; END END r0_rd_out[266] PIN r0_rd_out[267] @@ -7022,7 +11630,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.295 20.718 11.313 20.736 ; + RECT 77.103 90.632 77.121 90.686 ; END END r0_rd_out[267] PIN r0_rd_out[268] @@ -7031,7 +11639,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.303 20.718 12.321 20.736 ; + RECT 77.391 90.632 77.409 90.686 ; END END r0_rd_out[268] PIN r0_rd_out[269] @@ -7040,7 +11648,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.311 20.718 13.329 20.736 ; + RECT 77.679 90.632 77.697 90.686 ; END END r0_rd_out[269] PIN r0_rd_out[270] @@ -7049,7 +11657,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.319 20.718 14.337 20.736 ; + RECT 77.967 90.632 77.985 90.686 ; END END r0_rd_out[270] PIN r0_rd_out[271] @@ -7058,7 +11666,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 15.327 20.718 15.345 20.736 ; + RECT 78.255 90.632 78.273 90.686 ; END END r0_rd_out[271] PIN r0_rd_out[272] @@ -7067,7 +11675,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 16.335 20.718 16.353 20.736 ; + RECT 78.543 90.632 78.561 90.686 ; END END r0_rd_out[272] PIN r0_rd_out[273] @@ -7076,7 +11684,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 17.343 20.718 17.361 20.736 ; + RECT 78.831 90.632 78.849 90.686 ; END END r0_rd_out[273] PIN r0_rd_out[274] @@ -7085,7 +11693,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 18.351 20.718 18.369 20.736 ; + RECT 79.119 90.632 79.137 90.686 ; END END r0_rd_out[274] PIN r0_rd_out[275] @@ -7094,7 +11702,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 19.359 20.718 19.377 20.736 ; + RECT 79.407 90.632 79.425 90.686 ; END END r0_rd_out[275] PIN r0_rd_out[276] @@ -7103,7 +11711,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 20.367 20.718 20.385 20.736 ; + RECT 79.695 90.632 79.713 90.686 ; END END r0_rd_out[276] PIN r0_rd_out[277] @@ -7112,7 +11720,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 21.375 20.718 21.393 20.736 ; + RECT 79.983 90.632 80.001 90.686 ; END END r0_rd_out[277] PIN r0_rd_out[278] @@ -7121,7 +11729,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 22.383 20.718 22.401 20.736 ; + RECT 80.271 90.632 80.289 90.686 ; END END r0_rd_out[278] PIN r0_rd_out[279] @@ -7130,7 +11738,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 23.391 20.718 23.409 20.736 ; + RECT 80.559 90.632 80.577 90.686 ; END END r0_rd_out[279] PIN r0_rd_out[280] @@ -7139,7 +11747,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 24.399 20.718 24.417 20.736 ; + RECT 80.847 90.632 80.865 90.686 ; END END r0_rd_out[280] PIN r0_rd_out[281] @@ -7148,7 +11756,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 25.407 20.718 25.425 20.736 ; + RECT 81.135 90.632 81.153 90.686 ; END END r0_rd_out[281] PIN r0_rd_out[282] @@ -7157,7 +11765,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 26.415 20.718 26.433 20.736 ; + RECT 81.423 90.632 81.441 90.686 ; END END r0_rd_out[282] PIN r0_rd_out[283] @@ -7166,7 +11774,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 27.423 20.718 27.441 20.736 ; + RECT 81.711 90.632 81.729 90.686 ; END END r0_rd_out[283] PIN r0_rd_out[284] @@ -7175,7 +11783,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 28.431 20.718 28.449 20.736 ; + RECT 81.999 90.632 82.017 90.686 ; END END r0_rd_out[284] PIN r0_rd_out[285] @@ -7184,7 +11792,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 29.439 20.718 29.457 20.736 ; + RECT 82.287 90.632 82.305 90.686 ; END END r0_rd_out[285] PIN r0_rd_out[286] @@ -7193,7 +11801,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 30.447 20.718 30.465 20.736 ; + RECT 82.575 90.632 82.593 90.686 ; END END r0_rd_out[286] PIN r0_rd_out[287] @@ -7202,7 +11810,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 31.455 20.718 31.473 20.736 ; + RECT 82.863 90.632 82.881 90.686 ; END END r0_rd_out[287] PIN r0_rd_out[288] @@ -7211,7 +11819,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 32.463 20.718 32.481 20.736 ; + RECT 83.151 90.632 83.169 90.686 ; END END r0_rd_out[288] PIN r0_rd_out[289] @@ -7220,7 +11828,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 33.471 20.718 33.489 20.736 ; + RECT 83.439 90.632 83.457 90.686 ; END END r0_rd_out[289] PIN r0_rd_out[290] @@ -7229,7 +11837,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 34.479 20.718 34.497 20.736 ; + RECT 83.727 90.632 83.745 90.686 ; END END r0_rd_out[290] PIN r0_rd_out[291] @@ -7238,7 +11846,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 35.487 20.718 35.505 20.736 ; + RECT 84.015 90.632 84.033 90.686 ; END END r0_rd_out[291] PIN r0_rd_out[292] @@ -7247,7 +11855,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 36.495 20.718 36.513 20.736 ; + RECT 84.303 90.632 84.321 90.686 ; END END r0_rd_out[292] PIN r0_rd_out[293] @@ -7256,7 +11864,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 37.503 20.718 37.521 20.736 ; + RECT 84.591 90.632 84.609 90.686 ; END END r0_rd_out[293] PIN r0_rd_out[294] @@ -7265,7 +11873,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 38.511 20.718 38.529 20.736 ; + RECT 84.879 90.632 84.897 90.686 ; END END r0_rd_out[294] PIN r0_rd_out[295] @@ -7274,7 +11882,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 39.519 20.718 39.537 20.736 ; + RECT 85.167 90.632 85.185 90.686 ; END END r0_rd_out[295] PIN r0_rd_out[296] @@ -7283,7 +11891,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 40.527 20.718 40.545 20.736 ; + RECT 85.455 90.632 85.473 90.686 ; END END r0_rd_out[296] PIN r0_rd_out[297] @@ -7292,7 +11900,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 41.535 20.718 41.553 20.736 ; + RECT 85.743 90.632 85.761 90.686 ; END END r0_rd_out[297] PIN r0_rd_out[298] @@ -7301,7 +11909,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 42.543 20.718 42.561 20.736 ; + RECT 86.031 90.632 86.049 90.686 ; END END r0_rd_out[298] PIN r0_rd_out[299] @@ -7310,7 +11918,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 43.551 20.718 43.569 20.736 ; + RECT 86.319 90.632 86.337 90.686 ; END END r0_rd_out[299] PIN r0_rd_out[300] @@ -7319,7 +11927,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 44.559 20.718 44.577 20.736 ; + RECT 86.607 90.632 86.625 90.686 ; END END r0_rd_out[300] PIN r0_rd_out[301] @@ -7328,7 +11936,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 45.567 20.718 45.585 20.736 ; + RECT 86.895 90.632 86.913 90.686 ; END END r0_rd_out[301] PIN r0_rd_out[302] @@ -7337,7 +11945,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 46.575 20.718 46.593 20.736 ; + RECT 87.183 90.632 87.201 90.686 ; END END r0_rd_out[302] PIN r0_rd_out[303] @@ -7346,7 +11954,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 47.583 20.718 47.601 20.736 ; + RECT 87.471 90.632 87.489 90.686 ; END END r0_rd_out[303] PIN r0_rd_out[304] @@ -7355,7 +11963,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 48.591 20.718 48.609 20.736 ; + RECT 87.759 90.632 87.777 90.686 ; END END r0_rd_out[304] PIN r0_rd_out[305] @@ -7364,7 +11972,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 49.599 20.718 49.617 20.736 ; + RECT 88.047 90.632 88.065 90.686 ; END END r0_rd_out[305] PIN r0_rd_out[306] @@ -7373,7 +11981,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 50.607 20.718 50.625 20.736 ; + RECT 88.335 90.632 88.353 90.686 ; END END r0_rd_out[306] PIN r0_rd_out[307] @@ -7382,7 +11990,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 51.615 20.718 51.633 20.736 ; + RECT 88.623 90.632 88.641 90.686 ; END END r0_rd_out[307] PIN r0_rd_out[308] @@ -7391,7 +11999,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 52.623 20.718 52.641 20.736 ; + RECT 88.911 90.632 88.929 90.686 ; END END r0_rd_out[308] PIN r0_rd_out[309] @@ -7400,7 +12008,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 53.631 20.718 53.649 20.736 ; + RECT 89.199 90.632 89.217 90.686 ; END END r0_rd_out[309] PIN r0_rd_out[310] @@ -7409,7 +12017,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 54.639 20.718 54.657 20.736 ; + RECT 89.487 90.632 89.505 90.686 ; END END r0_rd_out[310] PIN r0_rd_out[311] @@ -7418,7 +12026,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 55.647 20.718 55.665 20.736 ; + RECT 89.775 90.632 89.793 90.686 ; END END r0_rd_out[311] PIN r0_rd_out[312] @@ -7427,7 +12035,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 56.655 20.718 56.673 20.736 ; + RECT 90.063 90.632 90.081 90.686 ; END END r0_rd_out[312] PIN r0_rd_out[313] @@ -7436,7 +12044,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 57.663 20.718 57.681 20.736 ; + RECT 90.351 90.632 90.369 90.686 ; END END r0_rd_out[313] PIN r0_rd_out[314] @@ -7445,7 +12053,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 58.671 20.718 58.689 20.736 ; + RECT 90.639 90.632 90.657 90.686 ; END END r0_rd_out[314] PIN r0_rd_out[315] @@ -7454,7 +12062,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 59.679 20.718 59.697 20.736 ; + RECT 90.927 90.632 90.945 90.686 ; END END r0_rd_out[315] PIN r0_rd_out[316] @@ -7463,7 +12071,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 60.687 20.718 60.705 20.736 ; + RECT 91.215 90.632 91.233 90.686 ; END END r0_rd_out[316] PIN r0_rd_out[317] @@ -7472,7 +12080,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 61.695 20.718 61.713 20.736 ; + RECT 91.503 90.632 91.521 90.686 ; END END r0_rd_out[317] PIN r0_rd_out[318] @@ -7481,7 +12089,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 62.703 20.718 62.721 20.736 ; + RECT 91.791 90.632 91.809 90.686 ; END END r0_rd_out[318] PIN r0_rd_out[319] @@ -7490,7 +12098,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 63.711 20.718 63.729 20.736 ; + RECT 92.079 90.632 92.097 90.686 ; END END r0_rd_out[319] PIN r0_rd_out[320] @@ -7499,7 +12107,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 64.719 20.718 64.737 20.736 ; + RECT 92.367 90.632 92.385 90.686 ; END END r0_rd_out[320] PIN r0_rd_out[321] @@ -7508,7 +12116,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 65.727 20.718 65.745 20.736 ; + RECT 92.655 90.632 92.673 90.686 ; END END r0_rd_out[321] PIN r0_rd_out[322] @@ -7517,7 +12125,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 66.735 20.718 66.753 20.736 ; + RECT 92.943 90.632 92.961 90.686 ; END END r0_rd_out[322] PIN r0_rd_out[323] @@ -7526,7 +12134,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 67.743 20.718 67.761 20.736 ; + RECT 93.231 90.632 93.249 90.686 ; END END r0_rd_out[323] PIN r0_rd_out[324] @@ -7535,7 +12143,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 68.751 20.718 68.769 20.736 ; + RECT 93.519 90.632 93.537 90.686 ; END END r0_rd_out[324] PIN r0_rd_out[325] @@ -7544,7 +12152,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 69.759 20.718 69.777 20.736 ; + RECT 93.807 90.632 93.825 90.686 ; END END r0_rd_out[325] PIN r0_rd_out[326] @@ -7553,7 +12161,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 70.767 20.718 70.785 20.736 ; + RECT 94.095 90.632 94.113 90.686 ; END END r0_rd_out[326] PIN r0_rd_out[327] @@ -7562,7 +12170,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 71.775 20.718 71.793 20.736 ; + RECT 94.383 90.632 94.401 90.686 ; END END r0_rd_out[327] PIN r0_rd_out[328] @@ -7571,7 +12179,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 72.783 20.718 72.801 20.736 ; + RECT 94.671 90.632 94.689 90.686 ; END END r0_rd_out[328] PIN r0_rd_out[329] @@ -7580,7 +12188,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 73.791 20.718 73.809 20.736 ; + RECT 94.959 90.632 94.977 90.686 ; END END r0_rd_out[329] PIN r0_rd_out[330] @@ -7589,7 +12197,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 74.799 20.718 74.817 20.736 ; + RECT 95.247 90.632 95.265 90.686 ; END END r0_rd_out[330] PIN r0_rd_out[331] @@ -7598,7 +12206,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 75.807 20.718 75.825 20.736 ; + RECT 95.535 90.632 95.553 90.686 ; END END r0_rd_out[331] PIN r0_rd_out[332] @@ -7607,7 +12215,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 76.815 20.718 76.833 20.736 ; + RECT 95.823 90.632 95.841 90.686 ; END END r0_rd_out[332] PIN r0_rd_out[333] @@ -7616,7 +12224,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 77.823 20.718 77.841 20.736 ; + RECT 96.111 90.632 96.129 90.686 ; END END r0_rd_out[333] PIN r0_rd_out[334] @@ -7625,7 +12233,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 78.831 20.718 78.849 20.736 ; + RECT 96.399 90.632 96.417 90.686 ; END END r0_rd_out[334] PIN r0_rd_out[335] @@ -7634,7 +12242,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 79.839 20.718 79.857 20.736 ; + RECT 96.687 90.632 96.705 90.686 ; END END r0_rd_out[335] PIN r0_rd_out[336] @@ -7643,7 +12251,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 80.847 20.718 80.865 20.736 ; + RECT 96.975 90.632 96.993 90.686 ; END END r0_rd_out[336] PIN r0_rd_out[337] @@ -7652,7 +12260,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 81.855 20.718 81.873 20.736 ; + RECT 97.263 90.632 97.281 90.686 ; END END r0_rd_out[337] PIN r0_rd_out[338] @@ -7661,7 +12269,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 82.863 20.718 82.881 20.736 ; + RECT 97.551 90.632 97.569 90.686 ; END END r0_rd_out[338] PIN r0_rd_out[339] @@ -7670,7 +12278,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 83.871 20.718 83.889 20.736 ; + RECT 97.839 90.632 97.857 90.686 ; END END r0_rd_out[339] PIN r0_rd_out[340] @@ -7679,7 +12287,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 84.879 20.718 84.897 20.736 ; + RECT 98.127 90.632 98.145 90.686 ; END END r0_rd_out[340] PIN r0_rd_out[341] @@ -7688,7 +12296,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 85.887 20.718 85.905 20.736 ; + RECT 98.415 90.632 98.433 90.686 ; END END r0_rd_out[341] PIN r0_rd_out[342] @@ -7697,7 +12305,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 86.895 20.718 86.913 20.736 ; + RECT 98.703 90.632 98.721 90.686 ; END END r0_rd_out[342] PIN r0_rd_out[343] @@ -7706,7 +12314,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 87.903 20.718 87.921 20.736 ; + RECT 98.991 90.632 99.009 90.686 ; END END r0_rd_out[343] PIN r0_rd_out[344] @@ -7715,7 +12323,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 88.911 20.718 88.929 20.736 ; + RECT 99.279 90.632 99.297 90.686 ; END END r0_rd_out[344] PIN r0_rd_out[345] @@ -7724,7 +12332,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 89.919 20.718 89.937 20.736 ; + RECT 99.567 90.632 99.585 90.686 ; END END r0_rd_out[345] PIN r0_rd_out[346] @@ -7733,7 +12341,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 90.927 20.718 90.945 20.736 ; + RECT 99.855 90.632 99.873 90.686 ; END END r0_rd_out[346] PIN r0_rd_out[347] @@ -7742,7 +12350,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 91.935 20.718 91.953 20.736 ; + RECT 100.143 90.632 100.161 90.686 ; END END r0_rd_out[347] PIN r0_rd_out[348] @@ -7751,7 +12359,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 92.943 20.718 92.961 20.736 ; + RECT 100.431 90.632 100.449 90.686 ; END END r0_rd_out[348] PIN r0_rd_out[349] @@ -7760,7 +12368,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 93.951 20.718 93.969 20.736 ; + RECT 100.719 90.632 100.737 90.686 ; END END r0_rd_out[349] PIN r0_rd_out[350] @@ -7769,7 +12377,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 94.959 20.718 94.977 20.736 ; + RECT 101.007 90.632 101.025 90.686 ; END END r0_rd_out[350] PIN r0_rd_out[351] @@ -7778,7 +12386,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 95.967 20.718 95.985 20.736 ; + RECT 101.295 90.632 101.313 90.686 ; END END r0_rd_out[351] PIN r0_rd_out[352] @@ -7787,7 +12395,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 96.975 20.718 96.993 20.736 ; + RECT 101.583 90.632 101.601 90.686 ; END END r0_rd_out[352] PIN r0_rd_out[353] @@ -7796,7 +12404,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 97.983 20.718 98.001 20.736 ; + RECT 101.871 90.632 101.889 90.686 ; END END r0_rd_out[353] PIN r0_rd_out[354] @@ -7805,7 +12413,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 98.991 20.718 99.009 20.736 ; + RECT 102.159 90.632 102.177 90.686 ; END END r0_rd_out[354] PIN r0_rd_out[355] @@ -7814,7 +12422,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 99.999 20.718 100.017 20.736 ; + RECT 102.447 90.632 102.465 90.686 ; END END r0_rd_out[355] PIN r0_rd_out[356] @@ -7823,7 +12431,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 101.007 20.718 101.025 20.736 ; + RECT 102.735 90.632 102.753 90.686 ; END END r0_rd_out[356] PIN r0_rd_out[357] @@ -7832,7 +12440,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 102.015 20.718 102.033 20.736 ; + RECT 103.023 90.632 103.041 90.686 ; END END r0_rd_out[357] PIN r0_rd_out[358] @@ -7841,7 +12449,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 103.023 20.718 103.041 20.736 ; + RECT 103.311 90.632 103.329 90.686 ; END END r0_rd_out[358] PIN r0_rd_out[359] @@ -7850,7 +12458,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 104.031 20.718 104.049 20.736 ; + RECT 103.599 90.632 103.617 90.686 ; END END r0_rd_out[359] PIN r0_rd_out[360] @@ -7859,7 +12467,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 105.039 20.718 105.057 20.736 ; + RECT 103.887 90.632 103.905 90.686 ; END END r0_rd_out[360] PIN r0_rd_out[361] @@ -7868,7 +12476,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 106.047 20.718 106.065 20.736 ; + RECT 104.175 90.632 104.193 90.686 ; END END r0_rd_out[361] PIN r0_rd_out[362] @@ -7877,7 +12485,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 107.055 20.718 107.073 20.736 ; + RECT 104.463 90.632 104.481 90.686 ; END END r0_rd_out[362] PIN r0_rd_out[363] @@ -7886,7 +12494,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 108.063 20.718 108.081 20.736 ; + RECT 104.751 90.632 104.769 90.686 ; END END r0_rd_out[363] PIN r0_rd_out[364] @@ -7895,7 +12503,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 109.071 20.718 109.089 20.736 ; + RECT 105.039 90.632 105.057 90.686 ; END END r0_rd_out[364] PIN r0_rd_out[365] @@ -7904,7 +12512,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 110.079 20.718 110.097 20.736 ; + RECT 105.327 90.632 105.345 90.686 ; END END r0_rd_out[365] PIN r0_rd_out[366] @@ -7913,7 +12521,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 111.087 20.718 111.105 20.736 ; + RECT 105.615 90.632 105.633 90.686 ; END END r0_rd_out[366] PIN r0_rd_out[367] @@ -7922,7 +12530,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 112.095 20.718 112.113 20.736 ; + RECT 105.903 90.632 105.921 90.686 ; END END r0_rd_out[367] PIN r0_rd_out[368] @@ -7931,7 +12539,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 113.103 20.718 113.121 20.736 ; + RECT 106.191 90.632 106.209 90.686 ; END END r0_rd_out[368] PIN r0_rd_out[369] @@ -7940,7 +12548,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 114.111 20.718 114.129 20.736 ; + RECT 106.479 90.632 106.497 90.686 ; END END r0_rd_out[369] PIN r0_rd_out[370] @@ -7949,7 +12557,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 115.119 20.718 115.137 20.736 ; + RECT 106.767 90.632 106.785 90.686 ; END END r0_rd_out[370] PIN r0_rd_out[371] @@ -7958,7 +12566,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 116.127 20.718 116.145 20.736 ; + RECT 107.055 90.632 107.073 90.686 ; END END r0_rd_out[371] PIN r0_rd_out[372] @@ -7967,7 +12575,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 117.135 20.718 117.153 20.736 ; + RECT 107.343 90.632 107.361 90.686 ; END END r0_rd_out[372] PIN r0_rd_out[373] @@ -7976,7 +12584,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 118.143 20.718 118.161 20.736 ; + RECT 107.631 90.632 107.649 90.686 ; END END r0_rd_out[373] PIN r0_rd_out[374] @@ -7985,7 +12593,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 119.151 20.718 119.169 20.736 ; + RECT 107.919 90.632 107.937 90.686 ; END END r0_rd_out[374] PIN r0_rd_out[375] @@ -7994,7 +12602,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 120.159 20.718 120.177 20.736 ; + RECT 108.207 90.632 108.225 90.686 ; END END r0_rd_out[375] PIN r0_rd_out[376] @@ -8003,7 +12611,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 121.167 20.718 121.185 20.736 ; + RECT 108.495 90.632 108.513 90.686 ; END END r0_rd_out[376] PIN r0_rd_out[377] @@ -8012,7 +12620,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 122.175 20.718 122.193 20.736 ; + RECT 108.783 90.632 108.801 90.686 ; END END r0_rd_out[377] PIN r0_rd_out[378] @@ -8021,7 +12629,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 123.183 20.718 123.201 20.736 ; + RECT 109.071 90.632 109.089 90.686 ; END END r0_rd_out[378] PIN r0_rd_out[379] @@ -8030,7 +12638,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 124.191 20.718 124.209 20.736 ; + RECT 109.359 90.632 109.377 90.686 ; END END r0_rd_out[379] PIN r0_rd_out[380] @@ -8039,7 +12647,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 125.199 20.718 125.217 20.736 ; + RECT 109.647 90.632 109.665 90.686 ; END END r0_rd_out[380] PIN r0_rd_out[381] @@ -8048,7 +12656,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 126.207 20.718 126.225 20.736 ; + RECT 109.935 90.632 109.953 90.686 ; END END r0_rd_out[381] PIN r0_rd_out[382] @@ -8057,7 +12665,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 127.215 20.718 127.233 20.736 ; + RECT 110.223 90.632 110.241 90.686 ; END END r0_rd_out[382] PIN r0_rd_out[383] @@ -8066,7 +12674,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 128.223 20.718 128.241 20.736 ; + RECT 110.511 90.632 110.529 90.686 ; END END r0_rd_out[383] PIN r0_rd_out[384] @@ -8075,7 +12683,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 129.231 20.718 129.249 20.736 ; + RECT 110.799 90.632 110.817 90.686 ; END END r0_rd_out[384] PIN r0_rd_out[385] @@ -8084,7 +12692,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 130.239 20.718 130.257 20.736 ; + RECT 111.087 90.632 111.105 90.686 ; END END r0_rd_out[385] PIN r0_rd_out[386] @@ -8093,7 +12701,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 131.247 20.718 131.265 20.736 ; + RECT 111.375 90.632 111.393 90.686 ; END END r0_rd_out[386] PIN r0_rd_out[387] @@ -8102,7 +12710,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 132.255 20.718 132.273 20.736 ; + RECT 111.663 90.632 111.681 90.686 ; END END r0_rd_out[387] PIN r0_rd_out[388] @@ -8111,7 +12719,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 133.263 20.718 133.281 20.736 ; + RECT 111.951 90.632 111.969 90.686 ; END END r0_rd_out[388] PIN r0_rd_out[389] @@ -8120,7 +12728,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 134.271 20.718 134.289 20.736 ; + RECT 112.239 90.632 112.257 90.686 ; END END r0_rd_out[389] PIN r0_rd_out[390] @@ -8129,7 +12737,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 135.279 20.718 135.297 20.736 ; + RECT 112.527 90.632 112.545 90.686 ; END END r0_rd_out[390] PIN r0_rd_out[391] @@ -8138,7 +12746,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 136.287 20.718 136.305 20.736 ; + RECT 112.815 90.632 112.833 90.686 ; END END r0_rd_out[391] PIN r0_rd_out[392] @@ -8147,7 +12755,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 137.295 20.718 137.313 20.736 ; + RECT 113.103 90.632 113.121 90.686 ; END END r0_rd_out[392] PIN r0_rd_out[393] @@ -8156,7 +12764,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 138.303 20.718 138.321 20.736 ; + RECT 113.391 90.632 113.409 90.686 ; END END r0_rd_out[393] PIN r0_rd_out[394] @@ -8165,7 +12773,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 139.311 20.718 139.329 20.736 ; + RECT 113.679 90.632 113.697 90.686 ; END END r0_rd_out[394] PIN r0_rd_out[395] @@ -8174,7 +12782,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 140.319 20.718 140.337 20.736 ; + RECT 113.967 90.632 113.985 90.686 ; END END r0_rd_out[395] PIN r0_rd_out[396] @@ -8183,7 +12791,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 141.327 20.718 141.345 20.736 ; + RECT 114.255 90.632 114.273 90.686 ; END END r0_rd_out[396] PIN r0_rd_out[397] @@ -8192,7 +12800,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 142.335 20.718 142.353 20.736 ; + RECT 114.543 90.632 114.561 90.686 ; END END r0_rd_out[397] PIN r0_rd_out[398] @@ -8201,7 +12809,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 143.343 20.718 143.361 20.736 ; + RECT 114.831 90.632 114.849 90.686 ; END END r0_rd_out[398] PIN r0_rd_out[399] @@ -8210,7 +12818,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 144.351 20.718 144.369 20.736 ; + RECT 115.119 90.632 115.137 90.686 ; END END r0_rd_out[399] PIN r0_rd_out[400] @@ -8219,7 +12827,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 145.359 20.718 145.377 20.736 ; + RECT 115.407 90.632 115.425 90.686 ; END END r0_rd_out[400] PIN r0_rd_out[401] @@ -8228,7 +12836,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 146.367 20.718 146.385 20.736 ; + RECT 115.695 90.632 115.713 90.686 ; END END r0_rd_out[401] PIN r0_rd_out[402] @@ -8237,7 +12845,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 147.375 20.718 147.393 20.736 ; + RECT 115.983 90.632 116.001 90.686 ; END END r0_rd_out[402] PIN r0_rd_out[403] @@ -8246,7 +12854,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 148.383 20.718 148.401 20.736 ; + RECT 116.271 90.632 116.289 90.686 ; END END r0_rd_out[403] PIN r0_rd_out[404] @@ -8255,7 +12863,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 149.391 20.718 149.409 20.736 ; + RECT 116.559 90.632 116.577 90.686 ; END END r0_rd_out[404] PIN r0_rd_out[405] @@ -8264,7 +12872,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 150.399 20.718 150.417 20.736 ; + RECT 116.847 90.632 116.865 90.686 ; END END r0_rd_out[405] PIN r0_rd_out[406] @@ -8273,7 +12881,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 151.407 20.718 151.425 20.736 ; + RECT 117.135 90.632 117.153 90.686 ; END END r0_rd_out[406] PIN r0_rd_out[407] @@ -8282,7 +12890,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 152.415 20.718 152.433 20.736 ; + RECT 117.423 90.632 117.441 90.686 ; END END r0_rd_out[407] PIN r0_rd_out[408] @@ -8291,7 +12899,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 153.423 20.718 153.441 20.736 ; + RECT 117.711 90.632 117.729 90.686 ; END END r0_rd_out[408] PIN r0_rd_out[409] @@ -8300,7 +12908,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 154.431 20.718 154.449 20.736 ; + RECT 117.999 90.632 118.017 90.686 ; END END r0_rd_out[409] PIN r0_rd_out[410] @@ -8309,7 +12917,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 155.439 20.718 155.457 20.736 ; + RECT 118.287 90.632 118.305 90.686 ; END END r0_rd_out[410] PIN r0_rd_out[411] @@ -8318,7 +12926,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 156.447 20.718 156.465 20.736 ; + RECT 118.575 90.632 118.593 90.686 ; END END r0_rd_out[411] PIN r0_rd_out[412] @@ -8327,7 +12935,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 157.455 20.718 157.473 20.736 ; + RECT 118.863 90.632 118.881 90.686 ; END END r0_rd_out[412] PIN r0_rd_out[413] @@ -8336,7 +12944,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 158.463 20.718 158.481 20.736 ; + RECT 119.151 90.632 119.169 90.686 ; END END r0_rd_out[413] PIN r0_rd_out[414] @@ -8345,7 +12953,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 159.471 20.718 159.489 20.736 ; + RECT 119.439 90.632 119.457 90.686 ; END END r0_rd_out[414] PIN r0_rd_out[415] @@ -8354,7 +12962,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 160.479 20.718 160.497 20.736 ; + RECT 119.727 90.632 119.745 90.686 ; END END r0_rd_out[415] PIN r0_rd_out[416] @@ -8363,7 +12971,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 161.487 20.718 161.505 20.736 ; + RECT 120.015 90.632 120.033 90.686 ; END END r0_rd_out[416] PIN r0_rd_out[417] @@ -8372,7 +12980,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 162.495 20.718 162.513 20.736 ; + RECT 120.303 90.632 120.321 90.686 ; END END r0_rd_out[417] PIN r0_rd_out[418] @@ -8381,7 +12989,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 163.503 20.718 163.521 20.736 ; + RECT 120.591 90.632 120.609 90.686 ; END END r0_rd_out[418] PIN r0_rd_out[419] @@ -8390,7 +12998,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 164.511 20.718 164.529 20.736 ; + RECT 120.879 90.632 120.897 90.686 ; END END r0_rd_out[419] PIN r0_rd_out[420] @@ -8399,7 +13007,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 165.519 20.718 165.537 20.736 ; + RECT 121.167 90.632 121.185 90.686 ; END END r0_rd_out[420] PIN r0_rd_out[421] @@ -8408,7 +13016,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 166.527 20.718 166.545 20.736 ; + RECT 121.455 90.632 121.473 90.686 ; END END r0_rd_out[421] PIN r0_rd_out[422] @@ -8417,7 +13025,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 167.535 20.718 167.553 20.736 ; + RECT 121.743 90.632 121.761 90.686 ; END END r0_rd_out[422] PIN r0_rd_out[423] @@ -8426,7 +13034,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 168.543 20.718 168.561 20.736 ; + RECT 122.031 90.632 122.049 90.686 ; END END r0_rd_out[423] PIN r0_rd_out[424] @@ -8435,7 +13043,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 169.551 20.718 169.569 20.736 ; + RECT 122.319 90.632 122.337 90.686 ; END END r0_rd_out[424] PIN r0_rd_out[425] @@ -8444,7 +13052,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 170.559 20.718 170.577 20.736 ; + RECT 122.607 90.632 122.625 90.686 ; END END r0_rd_out[425] PIN r0_rd_out[426] @@ -8453,7 +13061,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 171.567 20.718 171.585 20.736 ; + RECT 122.895 90.632 122.913 90.686 ; END END r0_rd_out[426] PIN r0_rd_out[427] @@ -8462,7 +13070,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 172.575 20.718 172.593 20.736 ; + RECT 123.183 90.632 123.201 90.686 ; END END r0_rd_out[427] PIN r0_rd_out[428] @@ -8471,7 +13079,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 173.583 20.718 173.601 20.736 ; + RECT 123.471 90.632 123.489 90.686 ; END END r0_rd_out[428] PIN r0_rd_out[429] @@ -8480,7 +13088,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 174.591 20.718 174.609 20.736 ; + RECT 123.759 90.632 123.777 90.686 ; END END r0_rd_out[429] PIN r0_rd_out[430] @@ -8489,7 +13097,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 175.599 20.718 175.617 20.736 ; + RECT 124.047 90.632 124.065 90.686 ; END END r0_rd_out[430] PIN r0_rd_out[431] @@ -8498,7 +13106,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 176.607 20.718 176.625 20.736 ; + RECT 124.335 90.632 124.353 90.686 ; END END r0_rd_out[431] PIN r0_rd_out[432] @@ -8507,7 +13115,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 177.615 20.718 177.633 20.736 ; + RECT 124.623 90.632 124.641 90.686 ; END END r0_rd_out[432] PIN r0_rd_out[433] @@ -8516,7 +13124,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 178.623 20.718 178.641 20.736 ; + RECT 124.911 90.632 124.929 90.686 ; END END r0_rd_out[433] PIN r0_rd_out[434] @@ -8525,7 +13133,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 179.631 20.718 179.649 20.736 ; + RECT 125.199 90.632 125.217 90.686 ; END END r0_rd_out[434] PIN r0_rd_out[435] @@ -8534,7 +13142,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 180.639 20.718 180.657 20.736 ; + RECT 125.487 90.632 125.505 90.686 ; END END r0_rd_out[435] PIN r0_rd_out[436] @@ -8543,7 +13151,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 181.647 20.718 181.665 20.736 ; + RECT 125.775 90.632 125.793 90.686 ; END END r0_rd_out[436] PIN r0_rd_out[437] @@ -8552,7 +13160,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 182.655 20.718 182.673 20.736 ; + RECT 126.063 90.632 126.081 90.686 ; END END r0_rd_out[437] PIN r0_rd_out[438] @@ -8561,7 +13169,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 183.663 20.718 183.681 20.736 ; + RECT 126.351 90.632 126.369 90.686 ; END END r0_rd_out[438] PIN r0_rd_out[439] @@ -8570,7 +13178,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 184.671 20.718 184.689 20.736 ; + RECT 126.639 90.632 126.657 90.686 ; END END r0_rd_out[439] PIN r0_rd_out[440] @@ -8579,7 +13187,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 185.679 20.718 185.697 20.736 ; + RECT 126.927 90.632 126.945 90.686 ; END END r0_rd_out[440] PIN r0_rd_out[441] @@ -8588,7 +13196,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 186.687 20.718 186.705 20.736 ; + RECT 127.215 90.632 127.233 90.686 ; END END r0_rd_out[441] PIN r0_rd_out[442] @@ -8597,7 +13205,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 187.695 20.718 187.713 20.736 ; + RECT 127.503 90.632 127.521 90.686 ; END END r0_rd_out[442] PIN r0_rd_out[443] @@ -8606,7 +13214,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 188.703 20.718 188.721 20.736 ; + RECT 127.791 90.632 127.809 90.686 ; END END r0_rd_out[443] PIN r0_rd_out[444] @@ -8615,7 +13223,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 189.711 20.718 189.729 20.736 ; + RECT 128.079 90.632 128.097 90.686 ; END END r0_rd_out[444] PIN r0_rd_out[445] @@ -8624,7 +13232,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 190.719 20.718 190.737 20.736 ; + RECT 128.367 90.632 128.385 90.686 ; END END r0_rd_out[445] PIN r0_rd_out[446] @@ -8633,7 +13241,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 191.727 20.718 191.745 20.736 ; + RECT 128.655 90.632 128.673 90.686 ; END END r0_rd_out[446] PIN r0_rd_out[447] @@ -8642,7 +13250,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 192.735 20.718 192.753 20.736 ; + RECT 128.943 90.632 128.961 90.686 ; END END r0_rd_out[447] PIN r0_rd_out[448] @@ -8651,7 +13259,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 193.743 20.718 193.761 20.736 ; + RECT 129.231 90.632 129.249 90.686 ; END END r0_rd_out[448] PIN r0_rd_out[449] @@ -8660,7 +13268,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 194.751 20.718 194.769 20.736 ; + RECT 129.519 90.632 129.537 90.686 ; END END r0_rd_out[449] PIN r0_rd_out[450] @@ -8669,7 +13277,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 195.759 20.718 195.777 20.736 ; + RECT 129.807 90.632 129.825 90.686 ; END END r0_rd_out[450] PIN r0_rd_out[451] @@ -8678,7 +13286,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 196.767 20.718 196.785 20.736 ; + RECT 130.095 90.632 130.113 90.686 ; END END r0_rd_out[451] PIN r0_rd_out[452] @@ -8687,7 +13295,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 197.775 20.718 197.793 20.736 ; + RECT 130.383 90.632 130.401 90.686 ; END END r0_rd_out[452] PIN r0_rd_out[453] @@ -8696,7 +13304,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 198.783 20.718 198.801 20.736 ; + RECT 130.671 90.632 130.689 90.686 ; END END r0_rd_out[453] PIN r0_rd_out[454] @@ -8705,7 +13313,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 199.791 20.718 199.809 20.736 ; + RECT 130.959 90.632 130.977 90.686 ; END END r0_rd_out[454] PIN r0_rd_out[455] @@ -8714,7 +13322,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 200.799 20.718 200.817 20.736 ; + RECT 131.247 90.632 131.265 90.686 ; END END r0_rd_out[455] PIN r0_rd_out[456] @@ -8723,7 +13331,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 201.807 20.718 201.825 20.736 ; + RECT 131.535 90.632 131.553 90.686 ; END END r0_rd_out[456] PIN r0_rd_out[457] @@ -8732,7 +13340,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 202.815 20.718 202.833 20.736 ; + RECT 131.823 90.632 131.841 90.686 ; END END r0_rd_out[457] PIN r0_rd_out[458] @@ -8741,7 +13349,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 203.823 20.718 203.841 20.736 ; + RECT 132.111 90.632 132.129 90.686 ; END END r0_rd_out[458] PIN r0_rd_out[459] @@ -8750,7 +13358,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 204.831 20.718 204.849 20.736 ; + RECT 132.399 90.632 132.417 90.686 ; END END r0_rd_out[459] PIN r0_rd_out[460] @@ -8759,7 +13367,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 205.839 20.718 205.857 20.736 ; + RECT 132.687 90.632 132.705 90.686 ; END END r0_rd_out[460] PIN r0_rd_out[461] @@ -8768,7 +13376,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 206.847 20.718 206.865 20.736 ; + RECT 132.975 90.632 132.993 90.686 ; END END r0_rd_out[461] PIN r0_rd_out[462] @@ -8777,7 +13385,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 207.855 20.718 207.873 20.736 ; + RECT 133.263 90.632 133.281 90.686 ; END END r0_rd_out[462] PIN r0_rd_out[463] @@ -8786,7 +13394,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 208.863 20.718 208.881 20.736 ; + RECT 133.551 90.632 133.569 90.686 ; END END r0_rd_out[463] PIN r0_rd_out[464] @@ -8795,7 +13403,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 209.871 20.718 209.889 20.736 ; + RECT 133.839 90.632 133.857 90.686 ; END END r0_rd_out[464] PIN r0_rd_out[465] @@ -8804,7 +13412,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 210.879 20.718 210.897 20.736 ; + RECT 134.127 90.632 134.145 90.686 ; END END r0_rd_out[465] PIN r0_rd_out[466] @@ -8813,7 +13421,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 211.887 20.718 211.905 20.736 ; + RECT 134.415 90.632 134.433 90.686 ; END END r0_rd_out[466] PIN r0_rd_out[467] @@ -8822,7 +13430,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 212.895 20.718 212.913 20.736 ; + RECT 134.703 90.632 134.721 90.686 ; END END r0_rd_out[467] PIN r0_rd_out[468] @@ -8831,7 +13439,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 213.903 20.718 213.921 20.736 ; + RECT 134.991 90.632 135.009 90.686 ; END END r0_rd_out[468] PIN r0_rd_out[469] @@ -8840,7 +13448,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 214.911 20.718 214.929 20.736 ; + RECT 135.279 90.632 135.297 90.686 ; END END r0_rd_out[469] PIN r0_rd_out[470] @@ -8849,7 +13457,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 215.919 20.718 215.937 20.736 ; + RECT 135.567 90.632 135.585 90.686 ; END END r0_rd_out[470] PIN r0_rd_out[471] @@ -8858,7 +13466,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 216.927 20.718 216.945 20.736 ; + RECT 135.855 90.632 135.873 90.686 ; END END r0_rd_out[471] PIN r0_rd_out[472] @@ -8867,7 +13475,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 217.935 20.718 217.953 20.736 ; + RECT 136.143 90.632 136.161 90.686 ; END END r0_rd_out[472] PIN r0_rd_out[473] @@ -8876,7 +13484,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 218.943 20.718 218.961 20.736 ; + RECT 136.431 90.632 136.449 90.686 ; END END r0_rd_out[473] PIN r0_rd_out[474] @@ -8885,7 +13493,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 219.951 20.718 219.969 20.736 ; + RECT 136.719 90.632 136.737 90.686 ; END END r0_rd_out[474] PIN r0_rd_out[475] @@ -8894,7 +13502,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 220.959 20.718 220.977 20.736 ; + RECT 137.007 90.632 137.025 90.686 ; END END r0_rd_out[475] PIN r0_rd_out[476] @@ -8903,7 +13511,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 221.967 20.718 221.985 20.736 ; + RECT 137.295 90.632 137.313 90.686 ; END END r0_rd_out[476] PIN r0_rd_out[477] @@ -8912,7 +13520,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 222.975 20.718 222.993 20.736 ; + RECT 137.583 90.632 137.601 90.686 ; END END r0_rd_out[477] PIN r0_rd_out[478] @@ -8921,7 +13529,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 223.983 20.718 224.001 20.736 ; + RECT 137.871 90.632 137.889 90.686 ; END END r0_rd_out[478] PIN r0_rd_out[479] @@ -8930,7 +13538,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 224.991 20.718 225.009 20.736 ; + RECT 138.159 90.632 138.177 90.686 ; END END r0_rd_out[479] PIN r0_rd_out[480] @@ -8939,7 +13547,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 225.999 20.718 226.017 20.736 ; + RECT 138.447 90.632 138.465 90.686 ; END END r0_rd_out[480] PIN r0_rd_out[481] @@ -8948,7 +13556,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 227.007 20.718 227.025 20.736 ; + RECT 138.735 90.632 138.753 90.686 ; END END r0_rd_out[481] PIN r0_rd_out[482] @@ -8957,7 +13565,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 228.015 20.718 228.033 20.736 ; + RECT 139.023 90.632 139.041 90.686 ; END END r0_rd_out[482] PIN r0_rd_out[483] @@ -8966,7 +13574,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 229.023 20.718 229.041 20.736 ; + RECT 139.311 90.632 139.329 90.686 ; END END r0_rd_out[483] PIN r0_rd_out[484] @@ -8975,7 +13583,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 230.031 20.718 230.049 20.736 ; + RECT 139.599 90.632 139.617 90.686 ; END END r0_rd_out[484] PIN r0_rd_out[485] @@ -8984,7 +13592,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 231.039 20.718 231.057 20.736 ; + RECT 139.887 90.632 139.905 90.686 ; END END r0_rd_out[485] PIN r0_rd_out[486] @@ -8993,7 +13601,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 232.047 20.718 232.065 20.736 ; + RECT 140.175 90.632 140.193 90.686 ; END END r0_rd_out[486] PIN r0_rd_out[487] @@ -9002,7 +13610,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 233.055 20.718 233.073 20.736 ; + RECT 140.463 90.632 140.481 90.686 ; END END r0_rd_out[487] PIN r0_rd_out[488] @@ -9011,7 +13619,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 234.063 20.718 234.081 20.736 ; + RECT 140.751 90.632 140.769 90.686 ; END END r0_rd_out[488] PIN r0_rd_out[489] @@ -9020,7 +13628,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 235.071 20.718 235.089 20.736 ; + RECT 141.039 90.632 141.057 90.686 ; END END r0_rd_out[489] PIN r0_rd_out[490] @@ -9029,7 +13637,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 236.079 20.718 236.097 20.736 ; + RECT 141.327 90.632 141.345 90.686 ; END END r0_rd_out[490] PIN r0_rd_out[491] @@ -9038,7 +13646,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 237.087 20.718 237.105 20.736 ; + RECT 141.615 90.632 141.633 90.686 ; END END r0_rd_out[491] PIN r0_rd_out[492] @@ -9047,7 +13655,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 238.095 20.718 238.113 20.736 ; + RECT 141.903 90.632 141.921 90.686 ; END END r0_rd_out[492] PIN r0_rd_out[493] @@ -9056,7 +13664,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 239.103 20.718 239.121 20.736 ; + RECT 142.191 90.632 142.209 90.686 ; END END r0_rd_out[493] PIN r0_rd_out[494] @@ -9065,7 +13673,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 240.111 20.718 240.129 20.736 ; + RECT 142.479 90.632 142.497 90.686 ; END END r0_rd_out[494] PIN r0_rd_out[495] @@ -9074,7 +13682,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 241.119 20.718 241.137 20.736 ; + RECT 142.767 90.632 142.785 90.686 ; END END r0_rd_out[495] PIN r0_rd_out[496] @@ -9083,7 +13691,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 242.127 20.718 242.145 20.736 ; + RECT 143.055 90.632 143.073 90.686 ; END END r0_rd_out[496] PIN r0_rd_out[497] @@ -9092,7 +13700,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 243.135 20.718 243.153 20.736 ; + RECT 143.343 90.632 143.361 90.686 ; END END r0_rd_out[497] PIN r0_rd_out[498] @@ -9101,7 +13709,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 244.143 20.718 244.161 20.736 ; + RECT 143.631 90.632 143.649 90.686 ; END END r0_rd_out[498] PIN r0_rd_out[499] @@ -9110,7 +13718,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 245.151 20.718 245.169 20.736 ; + RECT 143.919 90.632 143.937 90.686 ; END END r0_rd_out[499] PIN r0_rd_out[500] @@ -9119,7 +13727,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 246.159 20.718 246.177 20.736 ; + RECT 144.207 90.632 144.225 90.686 ; END END r0_rd_out[500] PIN r0_rd_out[501] @@ -9128,7 +13736,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 247.167 20.718 247.185 20.736 ; + RECT 144.495 90.632 144.513 90.686 ; END END r0_rd_out[501] PIN r0_rd_out[502] @@ -9137,7 +13745,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 248.175 20.718 248.193 20.736 ; + RECT 144.783 90.632 144.801 90.686 ; END END r0_rd_out[502] PIN r0_rd_out[503] @@ -9146,7 +13754,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 249.183 20.718 249.201 20.736 ; + RECT 145.071 90.632 145.089 90.686 ; END END r0_rd_out[503] PIN r0_rd_out[504] @@ -9155,7 +13763,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 250.191 20.718 250.209 20.736 ; + RECT 145.359 90.632 145.377 90.686 ; END END r0_rd_out[504] PIN r0_rd_out[505] @@ -9164,7 +13772,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 251.199 20.718 251.217 20.736 ; + RECT 145.647 90.632 145.665 90.686 ; END END r0_rd_out[505] PIN r0_rd_out[506] @@ -9173,7 +13781,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 252.207 20.718 252.225 20.736 ; + RECT 145.935 90.632 145.953 90.686 ; END END r0_rd_out[506] PIN r0_rd_out[507] @@ -9182,7 +13790,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 253.215 20.718 253.233 20.736 ; + RECT 146.223 90.632 146.241 90.686 ; END END r0_rd_out[507] PIN r0_rd_out[508] @@ -9191,7 +13799,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 254.223 20.718 254.241 20.736 ; + RECT 146.511 90.632 146.529 90.686 ; END END r0_rd_out[508] PIN r0_rd_out[509] @@ -9200,7 +13808,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 255.231 20.718 255.249 20.736 ; + RECT 146.799 90.632 146.817 90.686 ; END END r0_rd_out[509] PIN r0_rd_out[510] @@ -9209,7 +13817,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 256.239 20.718 256.257 20.736 ; + RECT 147.087 90.632 147.105 90.686 ; END END r0_rd_out[510] PIN r0_rd_out[511] @@ -9218,7 +13826,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 257.247 20.718 257.265 20.736 ; + RECT 147.375 90.632 147.393 90.686 ; END END r0_rd_out[511] PIN w0_addr_in[0] @@ -9227,7 +13835,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 18.708 0.024 18.732 ; + RECT 0.000 86.292 0.072 86.316 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -9236,7 +13844,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 18.852 0.024 18.876 ; + RECT 0.000 86.628 0.072 86.652 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -9245,7 +13853,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 18.996 0.024 19.020 ; + RECT 0.000 86.964 0.072 86.988 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -9254,7 +13862,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 19.140 0.024 19.164 ; + RECT 0.000 87.300 0.072 87.324 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -9263,7 +13871,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 18.708 265.421 18.732 ; + RECT 163.162 86.292 163.234 86.316 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -9272,7 +13880,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 18.852 265.421 18.876 ; + RECT 163.162 86.628 163.234 86.652 ; END END w0_addr_in[5] PIN w0_addr_in[6] @@ -9281,7 +13889,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 18.996 265.421 19.020 ; + RECT 163.162 86.964 163.234 86.988 ; END END w0_addr_in[6] PIN w0_addr_in[7] @@ -9290,7 +13898,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 19.140 265.421 19.164 ; + RECT 163.162 87.300 163.234 87.324 ; END END w0_addr_in[7] PIN r0_addr_in[0] @@ -9299,7 +13907,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 19.284 0.024 19.308 ; + RECT 0.000 87.636 0.072 87.660 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -9308,7 +13916,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 19.428 0.024 19.452 ; + RECT 0.000 87.972 0.072 87.996 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -9317,7 +13925,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 19.572 0.024 19.596 ; + RECT 0.000 88.308 0.072 88.332 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -9326,7 +13934,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 19.716 0.024 19.740 ; + RECT 0.000 88.644 0.072 88.668 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -9335,7 +13943,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 19.284 265.421 19.308 ; + RECT 163.162 87.636 163.234 87.660 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -9344,7 +13952,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 19.428 265.421 19.452 ; + RECT 163.162 87.972 163.234 87.996 ; END END r0_addr_in[5] PIN r0_addr_in[6] @@ -9353,7 +13961,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 19.572 265.421 19.596 ; + RECT 163.162 88.308 163.234 88.332 ; END END r0_addr_in[6] PIN r0_addr_in[7] @@ -9362,7 +13970,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 265.397 19.716 265.421 19.740 ; + RECT 163.162 88.644 163.234 88.668 ; END END r0_addr_in[7] PIN w0_we_in @@ -9371,7 +13979,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 258.255 20.718 258.273 20.736 ; + RECT 147.663 90.632 147.681 90.686 ; END END w0_we_in PIN w0_ce_in @@ -9380,7 +13988,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 259.263 20.718 259.281 20.736 ; + RECT 147.951 90.632 147.969 90.686 ; END END w0_ce_in PIN w0_clk @@ -9389,7 +13997,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 260.271 20.718 260.289 20.736 ; + RECT 148.239 90.632 148.257 90.686 ; END END w0_clk PIN r0_ce_in @@ -9398,7 +14006,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 261.279 20.718 261.297 20.736 ; + RECT 148.527 90.632 148.545 90.686 ; END END r0_ce_in PIN r0_clk @@ -9407,7 +14015,7 @@ MACRO fakeram_512x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 262.287 20.718 262.305 20.736 ; + RECT 148.815 90.632 148.833 90.686 ; END END r0_clk PIN VSS @@ -9415,33 +14023,124 @@ MACRO fakeram_512x256_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.108 0.192 265.313 0.288 ; - RECT 0.108 0.960 265.313 1.056 ; - RECT 0.108 1.728 265.313 1.824 ; - RECT 0.108 2.496 265.313 2.592 ; - RECT 0.108 3.264 265.313 3.360 ; - RECT 0.108 4.032 265.313 4.128 ; - RECT 0.108 4.800 265.313 4.896 ; - RECT 0.108 5.568 265.313 5.664 ; - RECT 0.108 6.336 265.313 6.432 ; - RECT 0.108 7.104 265.313 7.200 ; - RECT 0.108 7.872 265.313 7.968 ; - RECT 0.108 8.640 265.313 8.736 ; - RECT 0.108 9.408 265.313 9.504 ; - RECT 0.108 10.176 265.313 10.272 ; - RECT 0.108 10.944 265.313 11.040 ; - RECT 0.108 11.712 265.313 11.808 ; - RECT 0.108 12.480 265.313 12.576 ; - RECT 0.108 13.248 265.313 13.344 ; - RECT 0.108 14.016 265.313 14.112 ; - RECT 0.108 14.784 265.313 14.880 ; - RECT 0.108 15.552 265.313 15.648 ; - RECT 0.108 16.320 265.313 16.416 ; - RECT 0.108 17.088 265.313 17.184 ; - RECT 0.108 17.856 265.313 17.952 ; - RECT 0.108 18.624 265.313 18.720 ; - RECT 0.108 19.392 265.313 19.488 ; - RECT 0.108 20.160 265.313 20.256 ; + RECT 0.216 0.240 163.018 0.336 ; + RECT 0.216 1.008 163.018 1.104 ; + RECT 0.216 1.776 163.018 1.872 ; + RECT 0.216 2.544 163.018 2.640 ; + RECT 0.216 3.312 163.018 3.408 ; + RECT 0.216 4.080 163.018 4.176 ; + RECT 0.216 4.848 163.018 4.944 ; + RECT 0.216 5.616 163.018 5.712 ; + RECT 0.216 6.384 163.018 6.480 ; + RECT 0.216 7.152 163.018 7.248 ; + RECT 0.216 7.920 163.018 8.016 ; + RECT 0.216 8.688 163.018 8.784 ; + RECT 0.216 9.456 163.018 9.552 ; + RECT 0.216 10.224 163.018 10.320 ; + RECT 0.216 10.992 163.018 11.088 ; + RECT 0.216 11.760 163.018 11.856 ; + RECT 0.216 12.528 163.018 12.624 ; + RECT 0.216 13.296 163.018 13.392 ; + RECT 0.216 14.064 163.018 14.160 ; + RECT 0.216 14.832 163.018 14.928 ; + RECT 0.216 15.600 163.018 15.696 ; + RECT 0.216 16.368 163.018 16.464 ; + RECT 0.216 17.136 163.018 17.232 ; + RECT 0.216 17.904 163.018 18.000 ; + RECT 0.216 18.672 163.018 18.768 ; + RECT 0.216 19.440 163.018 19.536 ; + RECT 0.216 20.208 163.018 20.304 ; + RECT 0.216 20.976 163.018 21.072 ; + RECT 0.216 21.744 163.018 21.840 ; + RECT 0.216 22.512 163.018 22.608 ; + RECT 0.216 23.280 163.018 23.376 ; + RECT 0.216 24.048 163.018 24.144 ; + RECT 0.216 24.816 163.018 24.912 ; + RECT 0.216 25.584 163.018 25.680 ; + RECT 0.216 26.352 163.018 26.448 ; + RECT 0.216 27.120 163.018 27.216 ; + RECT 0.216 27.888 163.018 27.984 ; + RECT 0.216 28.656 163.018 28.752 ; + RECT 0.216 29.424 163.018 29.520 ; + RECT 0.216 30.192 163.018 30.288 ; + RECT 0.216 30.960 163.018 31.056 ; + RECT 0.216 31.728 163.018 31.824 ; + RECT 0.216 32.496 163.018 32.592 ; + RECT 0.216 33.264 163.018 33.360 ; + RECT 0.216 34.032 163.018 34.128 ; + RECT 0.216 34.800 163.018 34.896 ; + RECT 0.216 35.568 163.018 35.664 ; + RECT 0.216 36.336 163.018 36.432 ; + RECT 0.216 37.104 163.018 37.200 ; + RECT 0.216 37.872 163.018 37.968 ; + RECT 0.216 38.640 163.018 38.736 ; + RECT 0.216 39.408 163.018 39.504 ; + RECT 0.216 40.176 163.018 40.272 ; + RECT 0.216 40.944 163.018 41.040 ; + RECT 0.216 41.712 163.018 41.808 ; + RECT 0.216 42.480 163.018 42.576 ; + RECT 0.216 43.248 163.018 43.344 ; + RECT 0.216 44.016 163.018 44.112 ; + RECT 0.216 44.784 163.018 44.880 ; + RECT 0.216 45.552 163.018 45.648 ; + RECT 0.216 46.320 163.018 46.416 ; + RECT 0.216 47.088 163.018 47.184 ; + RECT 0.216 47.856 163.018 47.952 ; + RECT 0.216 48.624 163.018 48.720 ; + RECT 0.216 49.392 163.018 49.488 ; + RECT 0.216 50.160 163.018 50.256 ; + RECT 0.216 50.928 163.018 51.024 ; + RECT 0.216 51.696 163.018 51.792 ; + RECT 0.216 52.464 163.018 52.560 ; + RECT 0.216 53.232 163.018 53.328 ; + RECT 0.216 54.000 163.018 54.096 ; + RECT 0.216 54.768 163.018 54.864 ; + RECT 0.216 55.536 163.018 55.632 ; + RECT 0.216 56.304 163.018 56.400 ; + RECT 0.216 57.072 163.018 57.168 ; + RECT 0.216 57.840 163.018 57.936 ; + RECT 0.216 58.608 163.018 58.704 ; + RECT 0.216 59.376 163.018 59.472 ; + RECT 0.216 60.144 163.018 60.240 ; + RECT 0.216 60.912 163.018 61.008 ; + RECT 0.216 61.680 163.018 61.776 ; + RECT 0.216 62.448 163.018 62.544 ; + RECT 0.216 63.216 163.018 63.312 ; + RECT 0.216 63.984 163.018 64.080 ; + RECT 0.216 64.752 163.018 64.848 ; + RECT 0.216 65.520 163.018 65.616 ; + RECT 0.216 66.288 163.018 66.384 ; + RECT 0.216 67.056 163.018 67.152 ; + RECT 0.216 67.824 163.018 67.920 ; + RECT 0.216 68.592 163.018 68.688 ; + RECT 0.216 69.360 163.018 69.456 ; + RECT 0.216 70.128 163.018 70.224 ; + RECT 0.216 70.896 163.018 70.992 ; + RECT 0.216 71.664 163.018 71.760 ; + RECT 0.216 72.432 163.018 72.528 ; + RECT 0.216 73.200 163.018 73.296 ; + RECT 0.216 73.968 163.018 74.064 ; + RECT 0.216 74.736 163.018 74.832 ; + RECT 0.216 75.504 163.018 75.600 ; + RECT 0.216 76.272 163.018 76.368 ; + RECT 0.216 77.040 163.018 77.136 ; + RECT 0.216 77.808 163.018 77.904 ; + RECT 0.216 78.576 163.018 78.672 ; + RECT 0.216 79.344 163.018 79.440 ; + RECT 0.216 80.112 163.018 80.208 ; + RECT 0.216 80.880 163.018 80.976 ; + RECT 0.216 81.648 163.018 81.744 ; + RECT 0.216 82.416 163.018 82.512 ; + RECT 0.216 83.184 163.018 83.280 ; + RECT 0.216 83.952 163.018 84.048 ; + RECT 0.216 84.720 163.018 84.816 ; + RECT 0.216 85.488 163.018 85.584 ; + RECT 0.216 86.256 163.018 86.352 ; + RECT 0.216 87.024 163.018 87.120 ; + RECT 0.216 87.792 163.018 87.888 ; + RECT 0.216 88.560 163.018 88.656 ; + RECT 0.216 89.328 163.018 89.424 ; + RECT 0.216 90.096 163.018 90.192 ; END END VSS PIN VDD @@ -9449,44 +14148,135 @@ MACRO fakeram_512x256_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.108 0.192 265.313 0.288 ; - RECT 0.108 0.960 265.313 1.056 ; - RECT 0.108 1.728 265.313 1.824 ; - RECT 0.108 2.496 265.313 2.592 ; - RECT 0.108 3.264 265.313 3.360 ; - RECT 0.108 4.032 265.313 4.128 ; - RECT 0.108 4.800 265.313 4.896 ; - RECT 0.108 5.568 265.313 5.664 ; - RECT 0.108 6.336 265.313 6.432 ; - RECT 0.108 7.104 265.313 7.200 ; - RECT 0.108 7.872 265.313 7.968 ; - RECT 0.108 8.640 265.313 8.736 ; - RECT 0.108 9.408 265.313 9.504 ; - RECT 0.108 10.176 265.313 10.272 ; - RECT 0.108 10.944 265.313 11.040 ; - RECT 0.108 11.712 265.313 11.808 ; - RECT 0.108 12.480 265.313 12.576 ; - RECT 0.108 13.248 265.313 13.344 ; - RECT 0.108 14.016 265.313 14.112 ; - RECT 0.108 14.784 265.313 14.880 ; - RECT 0.108 15.552 265.313 15.648 ; - RECT 0.108 16.320 265.313 16.416 ; - RECT 0.108 17.088 265.313 17.184 ; - RECT 0.108 17.856 265.313 17.952 ; - RECT 0.108 18.624 265.313 18.720 ; - RECT 0.108 19.392 265.313 19.488 ; - RECT 0.108 20.160 265.313 20.256 ; + RECT 0.216 0.240 163.018 0.336 ; + RECT 0.216 1.008 163.018 1.104 ; + RECT 0.216 1.776 163.018 1.872 ; + RECT 0.216 2.544 163.018 2.640 ; + RECT 0.216 3.312 163.018 3.408 ; + RECT 0.216 4.080 163.018 4.176 ; + RECT 0.216 4.848 163.018 4.944 ; + RECT 0.216 5.616 163.018 5.712 ; + RECT 0.216 6.384 163.018 6.480 ; + RECT 0.216 7.152 163.018 7.248 ; + RECT 0.216 7.920 163.018 8.016 ; + RECT 0.216 8.688 163.018 8.784 ; + RECT 0.216 9.456 163.018 9.552 ; + RECT 0.216 10.224 163.018 10.320 ; + RECT 0.216 10.992 163.018 11.088 ; + RECT 0.216 11.760 163.018 11.856 ; + RECT 0.216 12.528 163.018 12.624 ; + RECT 0.216 13.296 163.018 13.392 ; + RECT 0.216 14.064 163.018 14.160 ; + RECT 0.216 14.832 163.018 14.928 ; + RECT 0.216 15.600 163.018 15.696 ; + RECT 0.216 16.368 163.018 16.464 ; + RECT 0.216 17.136 163.018 17.232 ; + RECT 0.216 17.904 163.018 18.000 ; + RECT 0.216 18.672 163.018 18.768 ; + RECT 0.216 19.440 163.018 19.536 ; + RECT 0.216 20.208 163.018 20.304 ; + RECT 0.216 20.976 163.018 21.072 ; + RECT 0.216 21.744 163.018 21.840 ; + RECT 0.216 22.512 163.018 22.608 ; + RECT 0.216 23.280 163.018 23.376 ; + RECT 0.216 24.048 163.018 24.144 ; + RECT 0.216 24.816 163.018 24.912 ; + RECT 0.216 25.584 163.018 25.680 ; + RECT 0.216 26.352 163.018 26.448 ; + RECT 0.216 27.120 163.018 27.216 ; + RECT 0.216 27.888 163.018 27.984 ; + RECT 0.216 28.656 163.018 28.752 ; + RECT 0.216 29.424 163.018 29.520 ; + RECT 0.216 30.192 163.018 30.288 ; + RECT 0.216 30.960 163.018 31.056 ; + RECT 0.216 31.728 163.018 31.824 ; + RECT 0.216 32.496 163.018 32.592 ; + RECT 0.216 33.264 163.018 33.360 ; + RECT 0.216 34.032 163.018 34.128 ; + RECT 0.216 34.800 163.018 34.896 ; + RECT 0.216 35.568 163.018 35.664 ; + RECT 0.216 36.336 163.018 36.432 ; + RECT 0.216 37.104 163.018 37.200 ; + RECT 0.216 37.872 163.018 37.968 ; + RECT 0.216 38.640 163.018 38.736 ; + RECT 0.216 39.408 163.018 39.504 ; + RECT 0.216 40.176 163.018 40.272 ; + RECT 0.216 40.944 163.018 41.040 ; + RECT 0.216 41.712 163.018 41.808 ; + RECT 0.216 42.480 163.018 42.576 ; + RECT 0.216 43.248 163.018 43.344 ; + RECT 0.216 44.016 163.018 44.112 ; + RECT 0.216 44.784 163.018 44.880 ; + RECT 0.216 45.552 163.018 45.648 ; + RECT 0.216 46.320 163.018 46.416 ; + RECT 0.216 47.088 163.018 47.184 ; + RECT 0.216 47.856 163.018 47.952 ; + RECT 0.216 48.624 163.018 48.720 ; + RECT 0.216 49.392 163.018 49.488 ; + RECT 0.216 50.160 163.018 50.256 ; + RECT 0.216 50.928 163.018 51.024 ; + RECT 0.216 51.696 163.018 51.792 ; + RECT 0.216 52.464 163.018 52.560 ; + RECT 0.216 53.232 163.018 53.328 ; + RECT 0.216 54.000 163.018 54.096 ; + RECT 0.216 54.768 163.018 54.864 ; + RECT 0.216 55.536 163.018 55.632 ; + RECT 0.216 56.304 163.018 56.400 ; + RECT 0.216 57.072 163.018 57.168 ; + RECT 0.216 57.840 163.018 57.936 ; + RECT 0.216 58.608 163.018 58.704 ; + RECT 0.216 59.376 163.018 59.472 ; + RECT 0.216 60.144 163.018 60.240 ; + RECT 0.216 60.912 163.018 61.008 ; + RECT 0.216 61.680 163.018 61.776 ; + RECT 0.216 62.448 163.018 62.544 ; + RECT 0.216 63.216 163.018 63.312 ; + RECT 0.216 63.984 163.018 64.080 ; + RECT 0.216 64.752 163.018 64.848 ; + RECT 0.216 65.520 163.018 65.616 ; + RECT 0.216 66.288 163.018 66.384 ; + RECT 0.216 67.056 163.018 67.152 ; + RECT 0.216 67.824 163.018 67.920 ; + RECT 0.216 68.592 163.018 68.688 ; + RECT 0.216 69.360 163.018 69.456 ; + RECT 0.216 70.128 163.018 70.224 ; + RECT 0.216 70.896 163.018 70.992 ; + RECT 0.216 71.664 163.018 71.760 ; + RECT 0.216 72.432 163.018 72.528 ; + RECT 0.216 73.200 163.018 73.296 ; + RECT 0.216 73.968 163.018 74.064 ; + RECT 0.216 74.736 163.018 74.832 ; + RECT 0.216 75.504 163.018 75.600 ; + RECT 0.216 76.272 163.018 76.368 ; + RECT 0.216 77.040 163.018 77.136 ; + RECT 0.216 77.808 163.018 77.904 ; + RECT 0.216 78.576 163.018 78.672 ; + RECT 0.216 79.344 163.018 79.440 ; + RECT 0.216 80.112 163.018 80.208 ; + RECT 0.216 80.880 163.018 80.976 ; + RECT 0.216 81.648 163.018 81.744 ; + RECT 0.216 82.416 163.018 82.512 ; + RECT 0.216 83.184 163.018 83.280 ; + RECT 0.216 83.952 163.018 84.048 ; + RECT 0.216 84.720 163.018 84.816 ; + RECT 0.216 85.488 163.018 85.584 ; + RECT 0.216 86.256 163.018 86.352 ; + RECT 0.216 87.024 163.018 87.120 ; + RECT 0.216 87.792 163.018 87.888 ; + RECT 0.216 88.560 163.018 88.656 ; + RECT 0.216 89.328 163.018 89.424 ; + RECT 0.216 90.096 163.018 90.192 ; END END VDD OBS LAYER M1 ; - RECT 0 0 265.421 20.736 ; + RECT 0 0 163.234 90.686 ; LAYER M2 ; - RECT 0 0 265.421 20.736 ; + RECT 0 0 163.234 90.686 ; LAYER M3 ; - RECT 0 0 265.421 20.736 ; + RECT 0 0 163.234 90.686 ; LAYER M4 ; - RECT 0 0 265.421 20.736 ; + RECT 0 0 163.234 90.686 ; END END fakeram_512x256_1r1w diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_7x256_1r1w.lef b/designs/asap7/NyuziProcessor/sram/lef/fakeram_7x256_1r1w.lef new file mode 100644 index 0000000..80ec90e --- /dev/null +++ b/designs/asap7/NyuziProcessor/sram/lef/fakeram_7x256_1r1w.lef @@ -0,0 +1,532 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_7x256_1r1w + FOREIGN fakeram_7x256_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 10.203 BY 45.963 ; + CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 0.276 10.203 0.300 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 4.020 10.203 4.044 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 45.909 0.225 45.963 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 45.909 0.945 45.963 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 45.909 1.665 45.963 ; + END + END w0_wmask_in[6] + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 7.764 10.203 7.788 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 11.508 10.203 11.532 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.395 0.000 1.413 0.054 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.583 0.000 2.601 0.054 ; + END + END w0_wd_in[6] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.771 0.000 3.789 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.959 0.000 4.977 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 0.000 6.165 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.335 0.000 7.353 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 45.909 2.385 45.963 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 45.909 3.105 45.963 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 45.909 3.825 45.963 ; + END + END r0_rd_out[6] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.484 0.072 26.508 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 15.252 10.203 15.276 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 18.996 10.203 19.020 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 22.740 10.203 22.764 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 26.484 10.203 26.508 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.228 0.072 30.252 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.972 0.072 33.996 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.716 0.072 37.740 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.460 0.072 41.484 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 30.228 10.203 30.252 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 33.972 10.203 33.996 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 37.716 10.203 37.740 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 41.460 10.203 41.484 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 45.909 4.545 45.963 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 45.909 5.265 45.963 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 45.909 5.985 45.963 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 45.909 6.705 45.963 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 45.909 7.425 45.963 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; + RECT 0.216 13.296 9.987 13.392 ; + RECT 0.216 14.064 9.987 14.160 ; + RECT 0.216 14.832 9.987 14.928 ; + RECT 0.216 15.600 9.987 15.696 ; + RECT 0.216 16.368 9.987 16.464 ; + RECT 0.216 17.136 9.987 17.232 ; + RECT 0.216 17.904 9.987 18.000 ; + RECT 0.216 18.672 9.987 18.768 ; + RECT 0.216 19.440 9.987 19.536 ; + RECT 0.216 20.208 9.987 20.304 ; + RECT 0.216 20.976 9.987 21.072 ; + RECT 0.216 21.744 9.987 21.840 ; + RECT 0.216 22.512 9.987 22.608 ; + RECT 0.216 23.280 9.987 23.376 ; + RECT 0.216 24.048 9.987 24.144 ; + RECT 0.216 24.816 9.987 24.912 ; + RECT 0.216 25.584 9.987 25.680 ; + RECT 0.216 26.352 9.987 26.448 ; + RECT 0.216 27.120 9.987 27.216 ; + RECT 0.216 27.888 9.987 27.984 ; + RECT 0.216 28.656 9.987 28.752 ; + RECT 0.216 29.424 9.987 29.520 ; + RECT 0.216 30.192 9.987 30.288 ; + RECT 0.216 30.960 9.987 31.056 ; + RECT 0.216 31.728 9.987 31.824 ; + RECT 0.216 32.496 9.987 32.592 ; + RECT 0.216 33.264 9.987 33.360 ; + RECT 0.216 34.032 9.987 34.128 ; + RECT 0.216 34.800 9.987 34.896 ; + RECT 0.216 35.568 9.987 35.664 ; + RECT 0.216 36.336 9.987 36.432 ; + RECT 0.216 37.104 9.987 37.200 ; + RECT 0.216 37.872 9.987 37.968 ; + RECT 0.216 38.640 9.987 38.736 ; + RECT 0.216 39.408 9.987 39.504 ; + RECT 0.216 40.176 9.987 40.272 ; + RECT 0.216 40.944 9.987 41.040 ; + RECT 0.216 41.712 9.987 41.808 ; + RECT 0.216 42.480 9.987 42.576 ; + RECT 0.216 43.248 9.987 43.344 ; + RECT 0.216 44.016 9.987 44.112 ; + RECT 0.216 44.784 9.987 44.880 ; + RECT 0.216 45.552 9.987 45.648 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; + RECT 0.216 13.296 9.987 13.392 ; + RECT 0.216 14.064 9.987 14.160 ; + RECT 0.216 14.832 9.987 14.928 ; + RECT 0.216 15.600 9.987 15.696 ; + RECT 0.216 16.368 9.987 16.464 ; + RECT 0.216 17.136 9.987 17.232 ; + RECT 0.216 17.904 9.987 18.000 ; + RECT 0.216 18.672 9.987 18.768 ; + RECT 0.216 19.440 9.987 19.536 ; + RECT 0.216 20.208 9.987 20.304 ; + RECT 0.216 20.976 9.987 21.072 ; + RECT 0.216 21.744 9.987 21.840 ; + RECT 0.216 22.512 9.987 22.608 ; + RECT 0.216 23.280 9.987 23.376 ; + RECT 0.216 24.048 9.987 24.144 ; + RECT 0.216 24.816 9.987 24.912 ; + RECT 0.216 25.584 9.987 25.680 ; + RECT 0.216 26.352 9.987 26.448 ; + RECT 0.216 27.120 9.987 27.216 ; + RECT 0.216 27.888 9.987 27.984 ; + RECT 0.216 28.656 9.987 28.752 ; + RECT 0.216 29.424 9.987 29.520 ; + RECT 0.216 30.192 9.987 30.288 ; + RECT 0.216 30.960 9.987 31.056 ; + RECT 0.216 31.728 9.987 31.824 ; + RECT 0.216 32.496 9.987 32.592 ; + RECT 0.216 33.264 9.987 33.360 ; + RECT 0.216 34.032 9.987 34.128 ; + RECT 0.216 34.800 9.987 34.896 ; + RECT 0.216 35.568 9.987 35.664 ; + RECT 0.216 36.336 9.987 36.432 ; + RECT 0.216 37.104 9.987 37.200 ; + RECT 0.216 37.872 9.987 37.968 ; + RECT 0.216 38.640 9.987 38.736 ; + RECT 0.216 39.408 9.987 39.504 ; + RECT 0.216 40.176 9.987 40.272 ; + RECT 0.216 40.944 9.987 41.040 ; + RECT 0.216 41.712 9.987 41.808 ; + RECT 0.216 42.480 9.987 42.576 ; + RECT 0.216 43.248 9.987 43.344 ; + RECT 0.216 44.016 9.987 44.112 ; + RECT 0.216 44.784 9.987 44.880 ; + RECT 0.216 45.552 9.987 45.648 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 10.203 45.963 ; + LAYER M2 ; + RECT 0 0 10.203 45.963 ; + LAYER M3 ; + RECT 0 0 10.203 45.963 ; + LAYER M4 ; + RECT 0 0 10.203 45.963 ; + END +END fakeram_7x256_1r1w + +END LIBRARY diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_16x52_1r1w.lib b/designs/asap7/NyuziProcessor/sram/lib/fakeram_16x52_1r1w.lib index b35bc37..3c1859f 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_16x52_1r1w.lib +++ b/designs/asap7/NyuziProcessor/sram/lib/fakeram_16x52_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_16x52_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-01-05 00:10:33Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -87,8 +87,16 @@ library(fakeram_16x52_1r1w) { bit_to : 0 ; downto : true ; } + type (fakeram_16x52_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 2; + bit_from : 1; + bit_to : 0 ; + downto : true ; + } cell(fakeram_16x52_1r1w) { - area : 43.006; + area : 130.119; interface_timing : true; memory() { type : ram; @@ -399,6 +407,77 @@ cell(fakeram_16x52_1r1w) { } } } + bus(w0_wmask_in) { + bus_type : fakeram_16x52_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x52_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x52_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x52_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x52_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } bus(r0_addr_in) { bus_type : fakeram_16x52_1r1w_ADDRESS; direction : input; diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_18x256_1r1w.lib b/designs/asap7/NyuziProcessor/sram/lib/fakeram_18x256_1r1w.lib index c7caac0..e927e72 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_18x256_1r1w.lib +++ b/designs/asap7/NyuziProcessor/sram/lib/fakeram_18x256_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_18x256_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-01-05 00:10:33Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -87,8 +87,16 @@ library(fakeram_18x256_1r1w) { bit_to : 0 ; downto : true ; } + type (fakeram_18x256_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 2; + bit_from : 1; + bit_to : 0 ; + downto : true ; + } cell(fakeram_18x256_1r1w) { - area : 193.508; + area : 478.898; interface_timing : true; memory() { type : ram; @@ -399,6 +407,77 @@ cell(fakeram_18x256_1r1w) { } } } + bus(w0_wmask_in) { + bus_type : fakeram_18x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } bus(r0_addr_in) { bus_type : fakeram_18x256_1r1w_ADDRESS; direction : input; diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_1x256_1r1w.lib b/designs/asap7/NyuziProcessor/sram/lib/fakeram_1x256_1r1w.lib index c4214cb..745ec79 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_1x256_1r1w.lib +++ b/designs/asap7/NyuziProcessor/sram/lib/fakeram_1x256_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_1x256_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-01-05 00:10:33Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -87,8 +87,16 @@ library(fakeram_1x256_1r1w) { bit_to : 0 ; downto : true ; } + type (fakeram_1x256_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 1; + bit_from : 0; + bit_to : 0 ; + downto : true ; + } cell(fakeram_1x256_1r1w) { - area : 10.783; + area : 463.543; interface_timing : true; memory() { type : ram; @@ -399,6 +407,77 @@ cell(fakeram_1x256_1r1w) { } } } + bus(w0_wmask_in) { + bus_type : fakeram_1x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_1x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_1x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_1x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_1x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } bus(r0_addr_in) { bus_type : fakeram_1x256_1r1w_ADDRESS; direction : input; diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_1r1w.lib b/designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_1r1w.lib index f5e4960..1a6d0b4 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_1r1w.lib +++ b/designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_20x64_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-01-05 00:10:33Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -87,8 +87,16 @@ library(fakeram_20x64_1r1w) { bit_to : 0 ; downto : true ; } + type (fakeram_20x64_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 2; + bit_from : 1; + bit_to : 0 ; + downto : true ; + } cell(fakeram_20x64_1r1w) { - area : 53.748; + area : 133.731; interface_timing : true; memory() { type : ram; @@ -399,6 +407,77 @@ cell(fakeram_20x64_1r1w) { } } } + bus(w0_wmask_in) { + bus_type : fakeram_20x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_20x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_20x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_20x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_20x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } bus(r0_addr_in) { bus_type : fakeram_20x64_1r1w_ADDRESS; direction : input; diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_2r1w.lib b/designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_2r1w.lib index bf05bb6..e8076f0 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_2r1w.lib +++ b/designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_2r1w.lib @@ -2,7 +2,7 @@ library(fakeram_20x64_2r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-01-05 00:10:33Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -87,8 +87,16 @@ library(fakeram_20x64_2r1w) { bit_to : 0 ; downto : true ; } + type (fakeram_20x64_2r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 2; + bit_from : 1; + bit_to : 0 ; + downto : true ; + } cell(fakeram_20x64_2r1w) { - area : 53.748; + area : 187.130; interface_timing : true; memory() { type : ram; @@ -507,6 +515,77 @@ cell(fakeram_20x64_2r1w) { } } } + bus(w0_wmask_in) { + bus_type : fakeram_20x64_2r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_20x64_2r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_20x64_2r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_20x64_2r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_20x64_2r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } bus(r0_addr_in) { bus_type : fakeram_20x64_2r1w_ADDRESS; direction : input; diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_32x128_2r1w.lib b/designs/asap7/NyuziProcessor/sram/lib/fakeram_32x128_2r1w.lib index b5577c5..868722f 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_32x128_2r1w.lib +++ b/designs/asap7/NyuziProcessor/sram/lib/fakeram_32x128_2r1w.lib @@ -2,7 +2,7 @@ library(fakeram_32x128_2r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-01-05 00:10:33Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -87,8 +87,16 @@ library(fakeram_32x128_2r1w) { bit_to : 0 ; downto : true ; } + type (fakeram_32x128_2r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 4; + bit_from : 3; + bit_to : 0 ; + downto : true ; + } cell(fakeram_32x128_2r1w) { - area : 172.005; + area : 364.134; interface_timing : true; memory() { type : ram; @@ -507,6 +515,77 @@ cell(fakeram_32x128_2r1w) { } } } + bus(w0_wmask_in) { + bus_type : fakeram_32x128_2r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x128_2r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_2r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x128_2r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_2r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } bus(r0_addr_in) { bus_type : fakeram_32x128_2r1w_ADDRESS; direction : input; diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_3x64_1r1w.lib b/designs/asap7/NyuziProcessor/sram/lib/fakeram_3x64_1r1w.lib new file mode 100644 index 0000000..0c640b7 --- /dev/null +++ b/designs/asap7/NyuziProcessor/sram/lib/fakeram_3x64_1r1w.lib @@ -0,0 +1,594 @@ +library(fakeram_3x64_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-01-05 00:10:33Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_3x64_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_3x64_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_3x64_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_3x64_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_3x64_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_3x64_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 3; + bit_from : 2; + bit_to : 0 ; + downto : true ; + } + type (fakeram_3x64_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } + type (fakeram_3x64_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 1; + bit_from : 0; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_3x64_1r1w) { + area : 118.375; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 3; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_3x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_3x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_3x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_3x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_3x64_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_3x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_3x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_3x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_3x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_3x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wmask_in) { + bus_type : fakeram_3x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_3x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_3x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_3x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_3x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_512x2048_1r1w.lib b/designs/asap7/NyuziProcessor/sram/lib/fakeram_512x2048_1r1w.lib index 2caeb2d..1b9b292 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_512x2048_1r1w.lib +++ b/designs/asap7/NyuziProcessor/sram/lib/fakeram_512x2048_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_512x2048_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-01-05 00:10:33Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -87,8 +87,16 @@ library(fakeram_512x2048_1r1w) { bit_to : 0 ; downto : true ; } + type (fakeram_512x2048_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } cell(fakeram_512x2048_1r1w) { - area : 44030.325; + area : 66613.347; interface_timing : true; memory() { type : ram; @@ -399,6 +407,77 @@ cell(fakeram_512x2048_1r1w) { } } } + bus(w0_wmask_in) { + bus_type : fakeram_512x2048_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } bus(r0_addr_in) { bus_type : fakeram_512x2048_1r1w_ADDRESS; direction : input; diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_512x256_1r1w.lib b/designs/asap7/NyuziProcessor/sram/lib/fakeram_512x256_1r1w.lib index 34c181b..d5a1062 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_512x256_1r1w.lib +++ b/designs/asap7/NyuziProcessor/sram/lib/fakeram_512x256_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_512x256_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-01-05 00:10:33Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -87,8 +87,16 @@ library(fakeram_512x256_1r1w) { bit_to : 0 ; downto : true ; } + type (fakeram_512x256_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } cell(fakeram_512x256_1r1w) { - area : 5503.791; + area : 14803.039; interface_timing : true; memory() { type : ram; @@ -399,6 +407,77 @@ cell(fakeram_512x256_1r1w) { } } } + bus(w0_wmask_in) { + bus_type : fakeram_512x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } bus(r0_addr_in) { bus_type : fakeram_512x256_1r1w_ADDRESS; direction : input; diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_7x256_1r1w.lib b/designs/asap7/NyuziProcessor/sram/lib/fakeram_7x256_1r1w.lib new file mode 100644 index 0000000..549e8ff --- /dev/null +++ b/designs/asap7/NyuziProcessor/sram/lib/fakeram_7x256_1r1w.lib @@ -0,0 +1,594 @@ +library(fakeram_7x256_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-01-05 00:10:33Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_7x256_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_7x256_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_7x256_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_7x256_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_7x256_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_7x256_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } + type (fakeram_7x256_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } + type (fakeram_7x256_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 1; + bit_from : 0; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_7x256_1r1w) { + area : 468.960; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 7; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_7x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_7x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_7x256_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_7x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_7x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_7x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_7x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_7x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wmask_in) { + bus_type : fakeram_7x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_7x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_7x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/src/NyuziProcessor/NyuziProcessor.v b/designs/src/NyuziProcessor/NyuziProcessor.v index 54684fc..8a3a76e 100644 --- a/designs/src/NyuziProcessor/NyuziProcessor.v +++ b/designs/src/NyuziProcessor/NyuziProcessor.v @@ -1,139 +1,3 @@ -module cache_lru ( - clk, - reset, - fill_en, - fill_set, - fill_way, - access_en, - access_set, - update_en, - update_way -); - reg _sv2v_0; - parameter NUM_SETS = 1; - parameter NUM_WAYS = 4; - parameter SET_INDEX_WIDTH = $clog2(NUM_SETS); - parameter WAY_INDEX_WIDTH = $clog2(NUM_WAYS); - input clk; - input reset; - input fill_en; - input [SET_INDEX_WIDTH - 1:0] fill_set; - output reg [WAY_INDEX_WIDTH - 1:0] fill_way; - input access_en; - input [SET_INDEX_WIDTH - 1:0] access_set; - input update_en; - input [WAY_INDEX_WIDTH - 1:0] update_way; - localparam LRU_FLAG_BITS = (NUM_WAYS == 1 ? 1 : (NUM_WAYS == 2 ? 1 : (NUM_WAYS == 4 ? 3 : 7))); - wire [LRU_FLAG_BITS - 1:0] lru_flags; - wire update_lru_en; - reg [SET_INDEX_WIDTH - 1:0] update_set; - reg [LRU_FLAG_BITS - 1:0] update_flags; - wire [SET_INDEX_WIDTH - 1:0] read_set; - wire read_en; - reg was_fill; - wire [WAY_INDEX_WIDTH - 1:0] new_mru; - assign read_en = access_en || fill_en; - assign read_set = (fill_en ? fill_set : access_set); - assign new_mru = (was_fill ? fill_way : update_way); - assign update_lru_en = was_fill || update_en; - reg [LRU_FLAG_BITS - 1:0] pass_thru_dat; - reg [LRU_FLAG_BITS - 1:0] mem; - reg pass_through_en; - always @(posedge clk) begin - pass_through_en <= (update_lru_en && read_en) && (read_set == update_set); - pass_thru_dat <= update_flags; - if (update_lru_en) - mem <= update_flags; - end - assign lru_flags = (pass_through_en ? pass_thru_dat : mem); - generate - case (NUM_WAYS) - 1: begin : genblk1 - wire [WAY_INDEX_WIDTH:1] sv2v_tmp_F4850; - assign sv2v_tmp_F4850 = 0; - always @(*) fill_way = sv2v_tmp_F4850; - wire [LRU_FLAG_BITS:1] sv2v_tmp_6C66A; - assign sv2v_tmp_6C66A = 0; - always @(*) update_flags = sv2v_tmp_6C66A; - end - 2: begin : genblk1 - wire [WAY_INDEX_WIDTH:1] sv2v_tmp_F4B2A; - assign sv2v_tmp_F4B2A = !lru_flags[0]; - always @(*) fill_way = sv2v_tmp_F4B2A; - wire [1:1] sv2v_tmp_0C2DF; - assign sv2v_tmp_0C2DF = !new_mru; - always @(*) update_flags[0] = sv2v_tmp_0C2DF; - end - 4: begin : genblk1 - always @(*) begin - if (_sv2v_0) - ; - casez (lru_flags) - 3'b00z: fill_way = 0; - 3'b10z: fill_way = 1; - 3'bz10: fill_way = 2; - 3'bz11: fill_way = 3; - default: fill_way = 1'sb0; - endcase - end - always @(*) begin - if (_sv2v_0) - ; - case (new_mru) - 2'd0: update_flags = {2'b11, lru_flags[0]}; - 2'd1: update_flags = {2'b01, lru_flags[0]}; - 2'd2: update_flags = {lru_flags[2], 2'b01}; - 2'd3: update_flags = {lru_flags[2], 2'b00}; - default: update_flags = 1'sb0; - endcase - end - end - 8: begin : genblk1 - always @(*) begin - if (_sv2v_0) - ; - casez (lru_flags) - 7'b00z0zzz: fill_way = 0; - 7'b10z0zzz: fill_way = 1; - 7'bz100zzz: fill_way = 2; - 7'bz110zzz: fill_way = 3; - 7'bzzz100z: fill_way = 4; - 7'bzzz110z: fill_way = 5; - 7'bzzz1z10: fill_way = 6; - 7'bzzz1z11: fill_way = 7; - default: fill_way = 1'sb0; - endcase - end - always @(*) begin - if (_sv2v_0) - ; - case (new_mru) - 3'd0: update_flags = {2'b11, lru_flags[5], 1'b1, lru_flags[2:0]}; - 3'd1: update_flags = {2'b01, lru_flags[5], 1'b1, lru_flags[2:0]}; - 3'd2: update_flags = {lru_flags[6], 3'b011, lru_flags[2:0]}; - 3'd3: update_flags = {lru_flags[6], 3'b001, lru_flags[2:0]}; - 3'd4: update_flags = {lru_flags[6:4], 3'b011, lru_flags[0]}; - 3'd5: update_flags = {lru_flags[6:4], 3'b001, lru_flags[0]}; - 3'd6: update_flags = {lru_flags[6:4], 1'b0, lru_flags[2], 2'b01}; - 3'd7: update_flags = {lru_flags[6:4], 1'b0, lru_flags[2], 2'b00}; - default: update_flags = 1'sb0; - endcase - end - end - default: begin : genblk1 - initial begin - $display("%m invalid number of ways"); - $finish; - end - end - endcase - endgenerate - always @(posedge clk) begin - update_set <= read_set; - was_fill <= fill_en; - end - initial _sv2v_0 = 0; -endmodule module cam ( clk, reset, @@ -2146,7 +2010,7 @@ module dcache_tag_stage ( ppage_idx = fetched_addr[31-:defines_PAGE_NUM_BITS]; end end - cache_lru #( + cache_lru_4x64 #( .NUM_WAYS(4), .NUM_SETS(64) ) lru( @@ -2157,8 +2021,7 @@ module dcache_tag_stage ( .access_set(request_addr_nxt[11-:6]), .update_en(dd_update_lru_en), .update_way(dd_update_lru_way), - .clk(clk), - .reset(reset) + .* ); always @(posedge clk) begin dt_instruction <= of_instruction; @@ -3481,7 +3344,7 @@ module ifetch_tag_stage ( ppage_idx = last_selected_pc[31-:defines_PAGE_NUM_BITS]; end end - cache_lru #( + cache_lru_4x64 #( .NUM_WAYS(4), .NUM_SETS(64) ) cache_lru( @@ -3492,8 +3355,7 @@ module ifetch_tag_stage ( .access_set(pc_to_fetch[11-:6]), .update_en(ifd_update_lru_en), .update_way(ifd_update_lru_way), - .clk(clk), - .reset(reset) + .* ); idx_to_oh #(.NUM_SIGNALS(4)) idx_to_oh_miss_thread( .one_hot(cache_miss_thread_oh), @@ -5306,7 +5168,7 @@ module l2_cache_tag_stage ( output wire [2:0] l2t_fill_way; output reg [511:0] l2t_data_from_memory; output reg l2t_restarted_flush; - cache_lru #( + cache_lru_8x256 #( .NUM_SETS(256), .NUM_WAYS(8) ) cache_lru( @@ -5317,8 +5179,7 @@ module l2_cache_tag_stage ( .access_set(l2a_request[583-:8]), .update_en(l2r_update_lru_en), .update_way(l2r_update_lru_hit_way), - .clk(clk), - .reset(reset) + .* ); genvar _gv_way_idx_7; generate diff --git a/designs/src/NyuziProcessor/cache_lru.v b/designs/src/NyuziProcessor/cache_lru.v new file mode 100644 index 0000000..ee064e3 --- /dev/null +++ b/designs/src/NyuziProcessor/cache_lru.v @@ -0,0 +1,252 @@ +//------------------------------------------------------------------------------ +// Modified from NyuziProcessor: cache_lru.sv +// +// Copyright 2011-2015 Jeff Bush +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Modifications: +// - Split lru policy into a separate module from cache_lru +// - Create multiple cache_lru modules based on the respective cache/ram size +// +// Modified by: Benjamin Goldblatt 2025 +//------------------------------------------------------------------------------ +module lru_policy ( + lru_flags, + new_mru, + fill_way, + update_flags +); + reg _sv2v_0; + parameter NUM_WAYS = 4; + parameter WAY_INDEX_WIDTH = $clog2(NUM_WAYS); + parameter LRU_FLAG_BITS = (NUM_WAYS == 1 ? 1 : (NUM_WAYS == 2 ? 1 : (NUM_WAYS == 4 ? 3 : 7))); + input [LRU_FLAG_BITS - 1:0] lru_flags; + input [WAY_INDEX_WIDTH - 1:0] new_mru; + output reg [WAY_INDEX_WIDTH - 1:0] fill_way; + output reg [LRU_FLAG_BITS - 1:0] update_flags; + generate + case (NUM_WAYS) + 1: begin : genblk1 + wire [WAY_INDEX_WIDTH:1] sv2v_tmp_F4850; + assign sv2v_tmp_F4850 = 0; + always @(*) fill_way = sv2v_tmp_F4850; + wire [LRU_FLAG_BITS:1] sv2v_tmp_6C66A; + assign sv2v_tmp_6C66A = 0; + always @(*) update_flags = sv2v_tmp_6C66A; + end + 2: begin : genblk1 + wire [WAY_INDEX_WIDTH:1] sv2v_tmp_F4B2A; + assign sv2v_tmp_F4B2A = !lru_flags[0]; + always @(*) fill_way = sv2v_tmp_F4B2A; + wire [1:1] sv2v_tmp_0C2DF; + assign sv2v_tmp_0C2DF = !new_mru; + always @(*) update_flags[0] = sv2v_tmp_0C2DF; + end + 4: begin : genblk1 + always @(*) begin + if (_sv2v_0) + ; + casez (lru_flags) + 3'b00z: fill_way = 0; + 3'b10z: fill_way = 1; + 3'bz10: fill_way = 2; + 3'bz11: fill_way = 3; + default: fill_way = 1'sb0; + endcase + end + always @(*) begin + if (_sv2v_0) + ; + case (new_mru) + 2'd0: update_flags = {2'b11, lru_flags[0]}; + 2'd1: update_flags = {2'b01, lru_flags[0]}; + 2'd2: update_flags = {lru_flags[2], 2'b01}; + 2'd3: update_flags = {lru_flags[2], 2'b00}; + default: update_flags = 1'sb0; + endcase + end + end + 8: begin : genblk1 + always @(*) begin + if (_sv2v_0) + ; + casez (lru_flags) + 7'b00z0zzz: fill_way = 0; + 7'b10z0zzz: fill_way = 1; + 7'bz100zzz: fill_way = 2; + 7'bz110zzz: fill_way = 3; + 7'bzzz100z: fill_way = 4; + 7'bzzz110z: fill_way = 5; + 7'bzzz1z10: fill_way = 6; + 7'bzzz1z11: fill_way = 7; + default: fill_way = 1'sb0; + endcase + end + always @(*) begin + if (_sv2v_0) + ; + case (new_mru) + 3'd0: update_flags = {2'b11, lru_flags[5], 1'b1, lru_flags[2:0]}; + 3'd1: update_flags = {2'b01, lru_flags[5], 1'b1, lru_flags[2:0]}; + 3'd2: update_flags = {lru_flags[6], 3'b011, lru_flags[2:0]}; + 3'd3: update_flags = {lru_flags[6], 3'b001, lru_flags[2:0]}; + 3'd4: update_flags = {lru_flags[6:4], 3'b011, lru_flags[0]}; + 3'd5: update_flags = {lru_flags[6:4], 3'b001, lru_flags[0]}; + 3'd6: update_flags = {lru_flags[6:4], 1'b0, lru_flags[2], 2'b01}; + 3'd7: update_flags = {lru_flags[6:4], 1'b0, lru_flags[2], 2'b00}; + default: update_flags = 1'sb0; + endcase + end + end + default: begin : genblk1 + initial begin + $display("%m invalid number of ways"); + $finish; + end + end + endcase + endgenerate + + initial _sv2v_0 = 0; +endmodule +module cache_lru_8x256 ( + clk, + reset, + fill_en, + fill_set, + fill_way, + access_en, + access_set, + update_en, + update_way +); + reg _sv2v_0; + parameter NUM_SETS = 1; + parameter NUM_WAYS = 4; + parameter SET_INDEX_WIDTH = $clog2(NUM_SETS); + parameter WAY_INDEX_WIDTH = $clog2(NUM_WAYS); + input clk; + input reset; + input fill_en; + input [SET_INDEX_WIDTH - 1:0] fill_set; + output reg [WAY_INDEX_WIDTH - 1:0] fill_way; + input access_en; + input [SET_INDEX_WIDTH - 1:0] access_set; + input update_en; + input [WAY_INDEX_WIDTH - 1:0] update_way; + localparam LRU_FLAG_BITS = (NUM_WAYS == 1 ? 1 : (NUM_WAYS == 2 ? 1 : (NUM_WAYS == 4 ? 3 : 7))); + wire [LRU_FLAG_BITS - 1:0] lru_flags; + wire update_lru_en; + reg [SET_INDEX_WIDTH - 1:0] update_set; + reg [LRU_FLAG_BITS - 1:0] update_flags; + wire [SET_INDEX_WIDTH - 1:0] read_set; + wire read_en; + reg was_fill; + wire [WAY_INDEX_WIDTH - 1:0] new_mru; + assign read_en = access_en || fill_en; + assign read_set = (fill_en ? fill_set : access_set); + assign new_mru = (was_fill ? fill_way : update_way); + assign update_lru_en = was_fill || update_en; + fakeram_1r1w_7x256 #( + .DATA_WIDTH(7), + .SIZE(256), + .READ_DURING_WRITE("NEW_DATA") + ) lru_data( + .read_en(read_en), + .read_addr(read_set), + .read_data(lru_flags), + .write_en(update_lru_en), + .write_addr(update_set), + .write_data(update_flags), + .* + ); + lru_policy #( + .NUM_WAYS(NUM_WAYS) + ) lru_policy_inst ( + .lru_flags(lru_flags), + .new_mru(new_mru), + .fill_way(fill_way), + .update_flags(update_flags) + ); + always @(posedge clk) begin + update_set <= read_set; + was_fill <= fill_en; + end + initial _sv2v_0 = 0; +endmodule +module cache_lru_4x64 ( + clk, + reset, + fill_en, + fill_set, + fill_way, + access_en, + access_set, + update_en, + update_way +); + reg _sv2v_0; + parameter NUM_SETS = 1; + parameter NUM_WAYS = 4; + parameter SET_INDEX_WIDTH = $clog2(NUM_SETS); + parameter WAY_INDEX_WIDTH = $clog2(NUM_WAYS); + input clk; + input reset; + input fill_en; + input [SET_INDEX_WIDTH - 1:0] fill_set; + output reg [WAY_INDEX_WIDTH - 1:0] fill_way; + input access_en; + input [SET_INDEX_WIDTH - 1:0] access_set; + input update_en; + input [WAY_INDEX_WIDTH - 1:0] update_way; + localparam LRU_FLAG_BITS = (NUM_WAYS == 1 ? 1 : (NUM_WAYS == 2 ? 1 : (NUM_WAYS == 4 ? 3 : 7))); + wire [LRU_FLAG_BITS - 1:0] lru_flags; + wire update_lru_en; + reg [SET_INDEX_WIDTH - 1:0] update_set; + reg [LRU_FLAG_BITS - 1:0] update_flags; + wire [SET_INDEX_WIDTH - 1:0] read_set; + wire read_en; + reg was_fill; + wire [WAY_INDEX_WIDTH - 1:0] new_mru; + assign read_en = access_en || fill_en; + assign read_set = (fill_en ? fill_set : access_set); + assign new_mru = (was_fill ? fill_way : update_way); + assign update_lru_en = was_fill || update_en; + fakeram_1r1w_3x64 #( + .DATA_WIDTH(3), + .SIZE(64), + .READ_DURING_WRITE("NEW_DATA") + ) lru_data( + .read_en(read_en), + .read_addr(read_set), + .read_data(lru_flags), + .write_en(update_lru_en), + .write_addr(update_set), + .write_data(update_flags), + .* + ); + lru_policy #( + .NUM_WAYS(NUM_WAYS) + ) lru_policy_inst ( + .lru_flags(lru_flags), + .new_mru(new_mru), + .fill_way(fill_way), + .update_flags(update_flags) + ); + always @(posedge clk) begin + update_set <= read_set; + was_fill <= fill_en; + end + initial _sv2v_0 = 0; +endmodule \ No newline at end of file diff --git a/designs/src/NyuziProcessor/dev/patch-all.patch b/designs/src/NyuziProcessor/dev/patch-all.patch index c0ac378..5ba7e24 100644 --- a/designs/src/NyuziProcessor/dev/patch-all.patch +++ b/designs/src/NyuziProcessor/dev/patch-all.patch @@ -1,14 +1,3 @@ ---- cache_lru.sv 2025-07-09 22:39:35.321468016 +0000 -+++ cache_lru_fix.sv 2025-07-09 22:41:13.034912461 +0000 -@@ -112,7 +112,7 @@ - // be evicted. A strict LRU would take three cycles for the node to move to the - // LRU. So, this is close enough to LRU to work well, but much simpler to implement. - // -- sram_1r1w #( -+ fakeram_1r1w_3x1 #( - .DATA_WIDTH(LRU_FLAG_BITS), - .SIZE(NUM_SETS), - .READ_DURING_WRITE("NEW_DATA") --- dcache_data_stage.sv 2025-07-09 22:42:54.320385140 +0000 +++ dcache_data_stage_fix.sv 2025-07-09 22:42:52.093373519 +0000 @@ -472,7 +472,7 @@ @@ -20,17 +9,26 @@ .DATA_WIDTH(CACHE_LINE_BITS), .SIZE(`L1D_WAYS * `L1D_SETS), .READ_DURING_WRITE("NEW_DATA") ---- dcache_tag_stage.sv 2025-07-09 22:44:07.942766681 +0000 -+++ dcache_tag_stage_fix.sv 2025-07-09 22:43:50.793678251 +0000 +--- dcache_tag_stage.sv 2025-11-05 03:31:47.869306193 +0000 ++++ dcache_tag_stage_fix.sv 2025-11-05 03:30:09.028400827 +0000 @@ -177,7 +177,7 @@ // to all be cleared on reset. logic line_valid[`L1D_SETS]; - + - sram_2r1w #( + fakeram_2r1w_20x64 #( .DATA_WIDTH($bits(l1d_tag_t)), .SIZE(`L1D_SETS), .READ_DURING_WRITE("NEW_DATA") +@@ -275,7 +275,7 @@ + end + end + +- cache_lru #( ++ cache_lru_4x64 #( + .NUM_WAYS(`L1D_WAYS), + .NUM_SETS(`L1D_SETS) + ) lru( --- ifetch_data_stage.sv 2025-07-09 22:14:25.832128443 +0000 +++ ifetch_data_stage_fix.sv 2025-07-09 22:16:31.971567357 +0000 @@ -152,7 +152,7 @@ @@ -42,17 +40,26 @@ .DATA_WIDTH(CACHE_LINE_BITS), .SIZE(`L1I_WAYS * `L1I_SETS), .READ_DURING_WRITE("NEW_DATA") ---- ifetch_tag_stage.sv 2025-07-09 22:50:10.217586731 +0000 -+++ ifetch_tag_stage_fix.sv 2025-07-09 22:49:59.507533958 +0000 +--- ifetch_tag_stage.sv 2025-11-05 03:31:48.227305861 +0000 ++++ ifetch_tag_stage_fix.sv 2025-11-05 03:30:23.370386719 +0000 @@ -179,7 +179,7 @@ // to simultaneously be cleared on reset. logic line_valid[`L1I_SETS]; - + - sram_1r1w #( + fakeram_1r1w_20x64 #( .DATA_WIDTH($bits(l1i_tag_t)), .SIZE(`L1I_SETS), .READ_DURING_WRITE("NEW_DATA") +@@ -275,7 +275,7 @@ + end + end + +- cache_lru #( ++ cache_lru_4x64 #( + .NUM_WAYS(`L1I_WAYS), + .NUM_SETS(`L1I_SETS) + ) cache_lru( --- int_execute_stage.sv 2025-07-09 01:05:59.672070430 +0000 +++ int_execute_stage_fix.sv 2025-07-09 19:58:46.419523214 +0000 @@ -101,87 +101,40 @@ @@ -187,12 +194,21 @@ .DATA_WIDTH(CACHE_LINE_BITS), .SIZE(`L2_WAYS * `L2_SETS), .READ_DURING_WRITE("NEW_DATA") ---- l2_cache_tag_stage.sv 2025-07-09 22:53:16.175496050 +0000 -+++ l2_cache_tag_stage_fix.sv 2025-07-09 22:53:08.300457778 +0000 +--- l2_cache_tag_stage.sv 2025-11-05 03:31:47.438306593 +0000 ++++ l2_cache_tag_stage_fix.sv 2025-11-05 03:29:52.497417260 +0000 +@@ -62,7 +62,7 @@ + assert((`L2_SETS & (`L2_SETS - 1)) == 0); + end + +- cache_lru #( ++ cache_lru_8x256 #( + .NUM_SETS(`L2_SETS), + .NUM_WAYS(`L2_WAYS) + ) cache_lru( @@ -84,7 +84,7 @@ begin : way_tags_gen logic line_valid[`L2_SETS]; - + - sram_1r1w #( + fakeram_1r1w_18x256 #( .DATA_WIDTH($bits(l2_tag_t)), @@ -201,7 +217,7 @@ @@ -97,7 +97,7 @@ .write_data(l2r_update_tag_value), .*); - + - sram_1r1w #( + fakeram_1r1w_1x256 #( .DATA_WIDTH(1), diff --git a/designs/src/NyuziProcessor/macros.v b/designs/src/NyuziProcessor/macros.v index 113239f..5bf6b87 100644 --- a/designs/src/NyuziProcessor/macros.v +++ b/designs/src/NyuziProcessor/macros.v @@ -1,3 +1,67 @@ +module fakeram_1r1w_3x64 ( + clk, + read_en, + read_addr, + read_data, + write_en, + write_addr, + write_data +); + parameter DATA_WIDTH = 3; + parameter SIZE = 64; + parameter READ_DURING_WRITE = "NEW_DATA"; + parameter ADDR_WIDTH = $clog2(SIZE); + input clk; + input read_en; + input [ADDR_WIDTH - 1:0] read_addr; + output reg [DATA_WIDTH - 1:0] read_data; + input write_en; + input [ADDR_WIDTH - 1:0] write_addr; + input [DATA_WIDTH - 1:0] write_data; + fakeram_3x64_1r1w sram ( + .r0_clk (clk), + .w0_clk (clk), + .r0_rd_out (read_data), + .r0_addr_in (read_addr), + .w0_addr_in (write_addr), + .w0_we_in (write_en), + .w0_wd_in (write_data), + .r0_ce_in (read_en), + .w0_ce_in (1'b1) + ); +endmodule +module fakeram_1r1w_7x256 ( + clk, + read_en, + read_addr, + read_data, + write_en, + write_addr, + write_data +); + parameter DATA_WIDTH = 7; + parameter SIZE = 256; + parameter READ_DURING_WRITE = "NEW_DATA"; + parameter ADDR_WIDTH = $clog2(SIZE); + input clk; + input read_en; + input [ADDR_WIDTH - 1:0] read_addr; + output reg [DATA_WIDTH - 1:0] read_data; + input write_en; + input [ADDR_WIDTH - 1:0] write_addr; + input [DATA_WIDTH - 1:0] write_data; + fakeram_7x256_1r1w sram ( + .r0_clk (clk), + .w0_clk (clk), + .r0_rd_out (read_data), + .r0_addr_in (read_addr), + .w0_addr_in (write_addr), + .w0_we_in (write_en), + .w0_wd_in (write_data), + .r0_ce_in (read_en), + .w0_ce_in (1'b1) + ); +endmodule module fakeram_1r1w_1x256 ( clk, read_en, diff --git a/designs/src/NyuziProcessor/verilog.mk b/designs/src/NyuziProcessor/verilog.mk index c029e6e..0e4f20f 100644 --- a/designs/src/NyuziProcessor/verilog.mk +++ b/designs/src/NyuziProcessor/verilog.mk @@ -1,3 +1,29 @@ +export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/NyuziProcessor.v \ + $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/macros.v \ + $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/cache_lru.v + +export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_3x64_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_1x256_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_7x256_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_16x52_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_18x256_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_20x64_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_20x64_2r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_32x128_2r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_512x256_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_512x2048_1r1w.lef + +export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_3x64_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_1x256_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_7x256_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_16x52_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_20x64_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_18x256_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_20x64_2r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_32x128_2r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_512x256_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_512x2048_1r1w.lib + ifneq ($(wildcard $(DEV_FLAG)),) export DEV_SRC = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/nyuziTop.v \ $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/repo @@ -6,24 +32,17 @@ ALL_REPO_FILES = $(wildcard $(REPO_SRC_DIR)/*.sv) \ $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/nyuziTop.sv REPO_FILES = $(filter-out \ $(REPO_SRC_DIR)/sram_1r1w.sv \ - $(REPO_SRC_DIR)/sram_2r1w.sv, \ + $(REPO_SRC_DIR)/sram_2r1w.sv \ + $(REPO_SRC_DIR)/cache_lru.sv, \ $(ALL_REPO_FILES)) REPO_INCLUDE_FILES = $(REPO_SRC_DIR)/defines.svh -TARGET_DEV_FILE = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/NyuziProcessor.v +TARGET_FILE_OVERWRITE = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/NyuziProcessor.v -$(TARGET_DEV_FILE) : $(REPO_FILES) - # Bypass error if patch has already been applied (prone to fail if repo code has changed) -#patch -p0 -N --silent --directory=$(REPO_SRC_DIR) < $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/patch-all.patch > /dev/null 2>&1 || [[ $$? == 1 ]] +$(TARGET_FILE_OVERWRITE) : $(REPO_FILES) + # Bypass error if patch has already been applied (prone to cause failure if repo code has changed) + patch -p0 -N --silent --directory=$(REPO_SRC_DIR) < $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/patch-all.patch > /dev/null 2>&1 || [[ $$? == 1 ]] $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/sv2v --top NyuziProcessor -w $@ -I $(REPO_INCLUDE_FILES) $(REPO_FILES) - -export VERILOG_FILES = $(TARGET_DEV_FILE) \ - $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/macros.v -else -export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/NyuziProcessor.v \ - $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/macros.v endif -export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/NyuziProcessor.v \ - $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/macros.v \ No newline at end of file diff --git a/designs/src/lfsr_prbs_gen/verilog.mk b/designs/src/lfsr_prbs_gen/verilog.mk index 3d88517..12f883a 100644 --- a/designs/src/lfsr_prbs_gen/verilog.mk +++ b/designs/src/lfsr_prbs_gen/verilog.mk @@ -1,6 +1 @@ -ifneq ($(wildcard $(DEV_FLAG)),) -export VERILOG_FILES = \ - $(wildcard $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/repo/rtl/*.v) -else -export VERILOG_FILES = $(wildcard $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/*.v) -endif \ No newline at end of file +export VERILOG_FILES = $(wildcard $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/*.v) \ No newline at end of file diff --git a/designs/src/minimax/verilog.mk b/designs/src/minimax/verilog.mk index 12e5755..7a00dec 100644 --- a/designs/src/minimax/verilog.mk +++ b/designs/src/minimax/verilog.mk @@ -1,12 +1,10 @@ +export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/$(DESIGN_NAME).v ifneq ($(wildcard $(DEV_FLAG)),) REPO_FILES = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/repo/rtl/$(DESIGN_NAME).v -export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/$(DESIGN_NAME).v $(VERILOG_FILES): $(REPO_FILES) @echo "Translating $(REPO_FILES) -> $@" $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/sv2v -w $@ $(REPO_FILES) @echo "Done." -else -export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/$(DESIGN_NAME).v endif \ No newline at end of file