info.yaml

# Tiny Tapeout project information
project:
  title:        "HACK CPU"      # Project title
  author:       "Dantong LUO, Nour MHANNA, Charbel SAAD"      # Your name
  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
  description:  "A 16-bit CPU based on the HACK architecture"      # One line description of what your project does
  language:     "SystemVerilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
  clock_hz:     12500000       # Clock frequency in Hz (or 0 if not applicable)

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_hack_cpu"

  # List your project's source files here.
  # Source files must be in ./src and you must list each source file separately, one per line.
  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
  source_files:
    - "tt_um_hack_cpu.v"
    - "alu.sv"
    - "fsm.sv"
    - "shift_register.sv"
    - "spi_mem.sv"
    - "spi_debug.sv"
    - "cpu_top.sv"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
  # Inputs
  ui[0]: "external halt signal (to use when debugging)"
  ui[1]: ""
  ui[2]: ""
  ui[3]: ""
  ui[4]: ""
  ui[5]: ""
  ui[6]: ""
  ui[7]: ""

  # Outputs
  uo[0]: ""
  uo[1]: ""
  uo[2]: ""
  uo[3]: ""
  uo[4]: ""
  uo[5]: ""
  uo[6]: ""
  uo[7]: ""

  # Bidirectional pins
  uio[0]: "GPIO21 - RAM CS"
  uio[1]: "GPIO22 - RAM MOSI"
  uio[2]: "GPIO23 - RAM MISO"
  uio[3]: "GPIO24 - RAM SCK"
  uio[4]: "DEBUG CS"
  uio[5]: "DEBUG MOSI"
  uio[6]: "DEBUG MISO"
  uio[7]: "DEBUG SCK"

# Do not change!
yaml_version: 6