From 1b95e1bb180dcffb7ae9903c195a329b8903cace Mon Sep 17 00:00:00 2001 From: Gaspar de Elias Date: Mon, 14 Nov 2022 13:56:41 -0300 Subject: [PATCH] Adding aludec. Partial work. --- src/aludec/aludec.vhd | 32 ++++++++++++++++++ src/aludec/aludec_tb.vhd | 20 ++++++++++++ src/maindec/maindec.vhd | 67 ++++++-------------------------------- src/maindec/maindec_tb.vhd | 10 +++--- 4 files changed, 67 insertions(+), 62 deletions(-) create mode 100644 src/aludec/aludec.vhd create mode 100644 src/aludec/aludec_tb.vhd diff --git a/src/aludec/aludec.vhd b/src/aludec/aludec.vhd new file mode 100644 index 0000000..2ce7274 --- /dev/null +++ b/src/aludec/aludec.vhd @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.logger.all; +use work.alu_helper.all; +use work.operations.all; + +entity aludec is port( + ALUOp : in std_logic_vector(1 downto 0) := (others => '0'); + instr : in std_logic_vector(10 downto 0) := (others => '0'); + AluControl : out std_logic_vector(3 downto 0) := (others => '0') +); +end entity aludec; + +architecture behavioural of aludec is +begin + if ALUOp = "00" then + AluControl <= ADD_HEX; + elsif ALUOp = "01" then + AluControl <= PASS_HEX; + else + case instr is + when OP_ADD => AluControl <= ADD_HEX; + when OP_SUB => AluControl <= SUB_HEX; + when OP_AND => AluControl <= AND_HEX; + when OP_ORR => AluControl <= OR_HEX; + when others => AluControl <= ADD_HEX; + end case; + end if; +end architecture; + diff --git a/src/aludec/aludec_tb.vhd b/src/aludec/aludec_tb.vhd new file mode 100644 index 0000000..34d3d36 --- /dev/null +++ b/src/aludec/aludec_tb.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.alu_helper.all; +use work.operations.all; + +entity aludec_tb is +end aludec_tb; + +architecture test of aludec_tb is + signal ALUOp : std_logic_vector(1 downto 0) := (others => '0'); + signal instr : std_logic_vector +begin + uut : entity work.aludec port map( + ALUOp => ALUOp, + instr => instr, + AluControl => AluControl + ); +end architecture; diff --git a/src/maindec/maindec.vhd b/src/maindec/maindec.vhd index 574365b..d86f734 100644 --- a/src/maindec/maindec.vhd +++ b/src/maindec/maindec.vhd @@ -9,7 +9,7 @@ use work.operations.all; entity maindec is port( - op : in std_logic_vector(10 downto 0); + Op : in std_logic_vector(10 downto 0); RegToLoc,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch: out std_logic; ALUOp : out std_logic_vector(1 downto 0) ); @@ -19,94 +19,47 @@ architecture behavioural of maindec is -- signals or constants here begin - with op select + with Op select RegToLoc <= '0' when OP_ADD|OP_SUB|OP_AND|OP_ORR|OP_LDUR, '1' when OP_STUR|OP_CBZ_COMPAT, '0' when others; - with op select + with Op select ALUSrc <= '0' when OP_ADD|OP_SUB|OP_AND|OP_ORR|OP_CBZ_COMPAT, '1' when OP_LDUR|OP_STUR, '0' when others; - with op select + with Op select MemToReg <= '0' when OP_ADD|OP_SUB|OP_AND|OP_ORR|OP_STUR|OP_CBZ_COMPAT, '1' when OP_LDUR, '0' when others; - with op select + with Op select RegWrite <= '1' when OP_ADD|OP_SUB|OP_AND|OP_ORR|OP_LDUR, '0' when OP_STUR|OP_CBZ_COMPAT, '0' when others; - with op select + with Op select MemRead <= '0' when OP_ADD|OP_SUB|OP_AND|OP_ORR|OP_STUR|OP_CBZ_COMPAT, '1' when OP_LDUR, '0' when others; - with op select + with Op select MemWrite <= '0' when OP_ADD|OP_SUB|OP_AND|OP_ORR|OP_LDUR|OP_CBZ_COMPAT, '1' when OP_STUR, '0' when others; - with op select + with Op select Branch <= '0' when OP_ADD|OP_SUB|OP_AND|OP_ORR|OP_LDUR|OP_STUR, '1' when OP_CBZ_COMPAT, '0' when others; - with op select + with Op select ALUOp <= "10" when OP_ADD|OP_SUB|OP_AND|OP_ORR, "00" when OP_LDUR|OP_STUR, "01" when OP_CBZ_COMPAT, "00" when others; +end architecture; --- case Op is --- when OP_ADD|OP_SUB|OP_AND|OP_ORR => --- RegToLoc <= '0'; --- ALUSrc <= '0'; --- MemToReg <= '0'; --- RegWrite <= '1'; --- MemRead <= '0'; --- MemWrite <= '0'; --- Branch <= '0'; --- ALUOp <= "10"; --- when OP_LDUR => --- RegToLoc <= '0'; --- ALUSrc <= '1'; --- MemToReg <= '1'; --- RegWrite <= '1'; --- MemRead <= '1'; --- MemWrite <= '0'; --- Branch <= '0'; --- ALUOp <= "00"; --- when OP_STUR => --- RegToLoc <= '1'; --- ALUSrc <= '1'; --- MemToReg <= '0'; --- RegWrite <= '0'; --- MemRead <= '0'; --- MemWrite <= '1'; --- Branch <= '0'; --- ALUOp <= "00"; --- when OP_CBZ => --- RegToLoc <= '1'; --- ALUSrc <= '0'; --- MemToReg <= '0'; --- RegWrite <= '0'; --- MemRead <= '0'; --- MemWrite <= '0'; --- Branch <= '1'; --- ALUOp <= "01"; --- when others => --- RegToLoc <= '0'; --- ALUSrc <= '0'; --- MemToReg <= '0'; --- RegWrite <= '0'; --- MemRead <= '0'; --- MemWrite <= '0'; --- Branch <= '0'; --- ALUOp <= "00"; --- end case; -end architecture; diff --git a/src/maindec/maindec_tb.vhd b/src/maindec/maindec_tb.vhd index a44c8d5..b3039f9 100644 --- a/src/maindec/maindec_tb.vhd +++ b/src/maindec/maindec_tb.vhd @@ -16,18 +16,18 @@ architecture test of maindec_tb is component maindec is port( - op : in op_type; + Op : in op_type; RegToLoc,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch: out std_logic; ALUOp : out alu_op_type ); end component maindec; - signal op : op_type; + signal Op : op_type; signal RegToLoc, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch : std_logic := '0'; signal ALUOp : alu_op_type; type test_vector is record - op : op_type; + Op : op_type; RegToLoc,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch: std_logic; ALUOp : alu_op_type; end record test_vector; @@ -49,7 +49,7 @@ architecture test of maindec_tb is begin UUT: entity work.maindec port map( - op =>op, + Op =>Op, RegToLoc=>RegToLoc, ALUSrc => ALUSrc, MemtoReg=> MemtoReg, @@ -64,7 +64,7 @@ begin begin for i in tests'range loop log("maindec testcase #" & to_string(i+1) & " of " & to_string(tests'length)); - op<=tests(i).op; + Op<=tests(i).Op; wait for 1 ps; assert RegToLoc=tests(i).RegToLoc report "RegToLoc Expected: " & to_string(tests(i).RegToLoc) & " Got: " & to_string(RegToLoc) severity error; assert ALUSrc=tests(i).ALUSrc report "ALUSrc Expected: " & to_string(tests(i).ALUSrc) & " Got: " & to_string(ALUSrc) severity error;