From 8d7856a195afcb38019169a38f351f8ed17db3bf Mon Sep 17 00:00:00 2001 From: Takehana Date: Thu, 6 Jul 2023 19:36:48 +0800 Subject: [PATCH 1/2] CustomCSRs: migrate to rocket --- {diplomatic/src/rocket => rocket/src}/CustomCSRs.scala | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) rename {diplomatic/src/rocket => rocket/src}/CustomCSRs.scala (88%) diff --git a/diplomatic/src/rocket/CustomCSRs.scala b/rocket/src/CustomCSRs.scala similarity index 88% rename from diplomatic/src/rocket/CustomCSRs.scala rename to rocket/src/CustomCSRs.scala index f2424da45..7645393f1 100644 --- a/diplomatic/src/rocket/CustomCSRs.scala +++ b/rocket/src/CustomCSRs.scala @@ -4,21 +4,19 @@ package org.chipsalliance.rockettile import chisel3._ -import org.chipsalliance.cde.config.Parameters - case class CustomCSR(id: Int, mask: BigInt, init: Option[BigInt]) object CustomCSR { def constant(id: Int, value: BigInt): CustomCSR = CustomCSR(id, BigInt(0), Some(value)) } -class CustomCSRIO(implicit p: Parameters) extends CoreBundle { +class CustomCSRIO(xLen: Int) extends Bundle { val wen = Bool() val wdata = UInt(xLen.W) val value = UInt(xLen.W) } -class CustomCSRs(implicit p: Parameters) extends CoreBundle { +class CustomCSRs(xLen: Int) extends Bundle { // Not all cores have these CSRs, but those that do should follow the same // numbering conventions. So we list them here but default them to None. protected def bpmCSRId = 0x7c0 @@ -30,7 +28,7 @@ class CustomCSRs(implicit p: Parameters) extends CoreBundle { // If you override this, you'll want to concatenate super.decls def decls: Seq[CustomCSR] = bpmCSR.toSeq ++ chickenCSR - val csrs = Vec(decls.size, new CustomCSRIO) + val csrs = Vec(decls.size, new CustomCSRIO(xLen)) def flushBTB = getOrElse(bpmCSR, _.wen, false.B) def bpmStatic = getOrElse(bpmCSR, _.value(0), false.B) From efffa9ff3906cf49e243e7d5ae8e5eb4478b1b16 Mon Sep 17 00:00:00 2001 From: Takehana Date: Thu, 6 Jul 2023 19:41:20 +0800 Subject: [PATCH 2/2] CustomCSRs: refactor parameters --- diplomatic/src/rocket/CSR.scala | 2 +- diplomatic/src/rocket/Core.scala | 2 +- diplomatic/src/rocket/RocketCore.scala | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/diplomatic/src/rocket/CSR.scala b/diplomatic/src/rocket/CSR.scala index 51da1e5b9..c3b226122 100644 --- a/diplomatic/src/rocket/CSR.scala +++ b/diplomatic/src/rocket/CSR.scala @@ -305,7 +305,7 @@ class CSRFile( extends CoreModule()(p) with HasCoreParameters { val io = IO(new CSRFileIO { - val customCSRs = Output(Vec(CSRFile.this.customCSRs.size, new CustomCSRIO)) + val customCSRs = Output(Vec(CSRFile.this.customCSRs.size, new CustomCSRIO(xLen))) }) val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) diff --git a/diplomatic/src/rocket/Core.scala b/diplomatic/src/rocket/Core.scala index 0346b219e..aafb40ee4 100644 --- a/diplomatic/src/rocket/Core.scala +++ b/diplomatic/src/rocket/Core.scala @@ -54,7 +54,7 @@ trait CoreParams { val mtvecWritable: Boolean val traceHasWdata: Boolean def customIsaExt: Option[String] = None - def customCSRs(implicit p: Parameters): CustomCSRs = new CustomCSRs + def customCSRs(implicit p: Parameters): CustomCSRs = new CustomCSRs(p(XLen)) def hasSupervisorMode: Boolean = useSupervisor || useVM def hasBitManipCrypto: Boolean = useBitManipCrypto || useCryptoNIST || useCryptoSM diff --git a/diplomatic/src/rocket/RocketCore.scala b/diplomatic/src/rocket/RocketCore.scala index 572674778..372b095c0 100644 --- a/diplomatic/src/rocket/RocketCore.scala +++ b/diplomatic/src/rocket/RocketCore.scala @@ -83,7 +83,7 @@ trait HasRocketCoreParameters extends HasCoreParameters { require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty") } -class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters { +class RocketCustomCSRs(implicit val p: Parameters) extends CustomCSRs(p(XLen)) with HasRocketCoreParameters { override def bpmCSR = { rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0)))) }