diff --git a/diplomatic/src/rocket/BusErrorUnit.scala b/diplomatic/src/rocket/BusErrorUnit.scala
index 36f7469ec..484b24568 100644
--- a/diplomatic/src/rocket/BusErrorUnit.scala
+++ b/diplomatic/src/rocket/BusErrorUnit.scala
@@ -18,8 +18,8 @@ trait BusErrors extends Bundle {
   def toErrorList: List[Option[(Valid[UInt], String, String)]]
 }
 
-class L1BusErrors(implicit p: Parameters) extends CoreBundle()(p) with BusErrors {
-  val icache = new ICacheErrors
+class L1BusErrors(paddrBits :Int, cacheParams : ICacheParams)(implicit p: Parameters) extends CoreBundle()(p) with BusErrors {
+  val icache = new ICacheErrors(paddrBits, cacheParams)
   val dcache = new DCacheErrors
 
   def toErrorList = List(None,
diff --git a/diplomatic/src/rocket/Frontend.scala b/diplomatic/src/rocket/Frontend.scala
index 539a01511..1a9402313 100644
--- a/diplomatic/src/rocket/Frontend.scala
+++ b/diplomatic/src/rocket/Frontend.scala
@@ -60,18 +60,21 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
   val progress = Output(Bool())
 }
 
-class Frontend(val icacheParams: ICacheParams, staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule {
+class Frontend(val icacheParams: ICacheParams, staticIdForMetadataUseOnly: Int, usingVM: Boolean, paddrBits :Int, vaddrBits:Int, ppnBits:Int, vpnBits:Int)(implicit p: Parameters) extends LazyModule {
   lazy val module = new FrontendModule(this)
-  val icache = LazyModule(new ICache(icacheParams, staticIdForMetadataUseOnly))
+  val icache = LazyModule(new ICache(icacheParams, staticIdForMetadataUseOnly, usingVM, paddrBits, vaddrBits, ppnBits, vpnBits))
   val masterNode = icache.masterNode
   val slaveNode = icache.slaveNode
   val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W)))
+
+  val iCacheParams = icacheParams
+  val paddrbits = paddrBits
 }
 
 class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p) {
   val cpu = Flipped(new FrontendIO())
   val ptw = new TLBPTWIO()
-  val errors = new ICacheErrors
+  val errors = new ICacheErrors(outer.paddrbits, outer.iCacheParams)
 }
 
 class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
@@ -382,7 +385,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
 /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
 trait HasICacheFrontend extends CanHavePTW { this: BaseTile =>
   val module: HasICacheFrontendModule
-  val frontend = LazyModule(new Frontend(tileParams.icache.get, staticIdForMetadataUseOnly))
+  val frontend = LazyModule(new Frontend(tileParams.icache.get, staticIdForMetadataUseOnly, usingVM, paddrBits, vaddrBits, ppnBits, vpnBits))
   tlMasterXbar.node := frontend.masterNode
   connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes)
   frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode }
diff --git a/diplomatic/src/rocket/ICache.scala b/diplomatic/src/rocket/ICache.scala
index e51637eb8..e1df2c418 100644
--- a/diplomatic/src/rocket/ICache.scala
+++ b/diplomatic/src/rocket/ICache.scala
@@ -60,12 +60,11 @@ trait HasL1ICacheParameters extends HasL1CacheParameters with HasCoreParameters
   val cacheParams = tileParams.icache.get
 }
 
-class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICacheParameters {
+class ICacheReq(vaddrBits: Int) extends Bundle {
   val addr = UInt(vaddrBits.W)
 }
 
-class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p)
-    with HasL1ICacheParameters
+class ICacheErrors(paddrBits :Int, cacheParams : ICacheParams) extends Bundle
     with CanHaveErrors {
   val correctable = (cacheParams.tagCode.canDetect || cacheParams.dataCode.canDetect).option(Valid(UInt(paddrBits.W)))
   val uncorrectable = (cacheParams.itimAddr.nonEmpty && cacheParams.dataCode.canDetect).option(Valid(UInt(paddrBits.W)))
@@ -119,7 +118,8 @@ class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p)
   * @param icacheParams parameter to this I$.
   * @param staticIdForMetadataUseOnly metadata used for hart id.
   */
-class ICache(val icacheParams: ICacheParams, val staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule {
+class ICache(val icacheParams: ICacheParams, val staticIdForMetadataUseOnly: Int, usingVM: Boolean, paddrBits :Int, vaddrBits:Int, ppnBits:Int, vpnBits:Int) (implicit p: Parameters)
+  extends LazyModule{
   lazy val module = new ICacheModule(this)
 
   /** Diplomatic hartid bundle used for ITIM. */
@@ -133,7 +133,13 @@ class ICache(val icacheParams: ICacheParams, val staticIdForMetadataUseOnly: Int
     * AMBA privileged, secure will be set as true while others set as false.
     * see [[freechips.rocketchip.amba.AMBAProt]] for more informations.
     */
-  val useVM = p(TileKey).core.useVM
+  val useVM = usingVM: Boolean
+
+  val pBits = paddrBits
+  val vBits = vaddrBits
+  val ppn = ppnBits
+  val vpn = vpnBits
+  val iCacheParams = icacheParams
 
   /** [[TLClientNode]] of I$.
     *
@@ -208,11 +214,11 @@ class ICachePerfEvents extends Bundle {
 }
 
 /** IO from CPU to ICache. */
-class ICacheBundle(val outer: ICache) extends CoreBundle()(outer.p) {
+class ICacheBundle(val outer: ICache) extends Bundle {
   /** first cycle requested from CPU. */
-  val req = Flipped(Decoupled(new ICacheReq))
-  val s1_paddr = Input(UInt(paddrBits.W)) // delayed one cycle w.r.t. req
-  val s2_vaddr = Input(UInt(vaddrBits.W)) // delayed two cycles w.r.t. req
+  val req = Flipped(Decoupled(new ICacheReq(outer.vBits)))
+  val s1_paddr = Input(UInt(outer.pBits.W)) // delayed one cycle w.r.t. req
+  val s2_vaddr = Input(UInt(outer.vBits.W)) // delayed two cycles w.r.t. req
   val s1_kill = Input(Bool()) // delayed one cycle w.r.t. req
   val s2_kill = Input(Bool()) // delayed two cycles; prevents I$ miss emission
   val s2_cacheable = Input(Bool()) // should L2 cache line on a miss?
@@ -228,7 +234,7 @@ class ICacheBundle(val outer: ICache) extends CoreBundle()(outer.p) {
   /** I$ has error, notify to bus.
     * TODO: send to BPU.
     */
-  val errors = new ICacheErrors
+  val errors = new ICacheErrors(outer.pBits, outer.iCacheParams)
 
   /** for performance counting. */
   val perf = Output(new ICachePerfEvents())
diff --git a/diplomatic/src/rocket/RocketTile.scala b/diplomatic/src/rocket/RocketTile.scala
index b3dae9ea9..5603e3dee 100644
--- a/diplomatic/src/rocket/RocketTile.scala
+++ b/diplomatic/src/rocket/RocketTile.scala
@@ -61,7 +61,7 @@ class RocketTile private(
   dtim_adapter.foreach(lm => connectTLSlave(lm.node, lm.node.portParams.head.beatBytes))
 
   val bus_error_unit = rocketParams.beuAddr map { a =>
-    val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
+    val beu = LazyModule(new BusErrorUnit(new L1BusErrors(paddrBits,rocketParams.icache.get), BusErrorUnitParams(a)))
     intOutwardNode := beu.intNode
     connectTLSlave(beu.node, xBytes)
     beu