diff --git a/TrackletGraph.py b/TrackletGraph.py
index 4c6c212..c2b348b 100644
--- a/TrackletGraph.py
+++ b/TrackletGraph.py
@@ -233,7 +233,7 @@ def populate_bitwidths(mem,hls_dir): # FIXME this information should be parsed f
             if barrelPS>-1 or barrel2S>-1: mem.bitwidth = 52
             if disk>-1: mem.bitwidth = 55
         elif mem.mtype == "TrackWord":
-            mem.bitwidth = 104
+            mem.bitwidth = 113
         elif mem.mtype == "BarrelStubWord":
             mem.bitwidth = 46
         elif mem.mtype == "DiskStubWord":
@@ -497,16 +497,8 @@ def split_track_fit_streams(p_dict, m_dict):
                 down_p.upstreams.append(new_mem)
                 down_p.input_port_names.append("trackwordin")
 
-            # Determine the layers/disks from the associated full match
-            # memories.
-            layers = set()
-            if up_p is not None:
-                for up_m in up_p.upstreams:
-                    if up_m.mtype != "FullMatch":
-                        continue
-                    layer = up_m.inst.split("_")[-1][0:2]
-                    assert(layer.startswith("L") or layer.startswith("D"))
-                    layers.add(layer)
+            # We will have all layers for each TrackWord
+            layers = {'L1', 'L2', 'L3', 'L4', 'L5', 'L6', 'D1', 'D2', 'D3', 'D4', 'D5'}
 
             # Replace the old memory with a stub word for each of the
             # layers/disks that can have matches.
diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py
index 1d3df4a..ddc90b0 100644
--- a/WriteVHDLSyntax.py
+++ b/WriteVHDLSyntax.py
@@ -132,7 +132,7 @@ def writeTBMemoryStimulusProcess(initial_proc):
     string_mem += "    -- Process to start first module in chain & generate its BX counter input.\n"
     string_mem += "    -- Also releases reset flag.\n"
     string_mem += "    constant CLK_RESET : natural := 5; -- Any low number OK.\n"
-    string_mem += "    variable CLK_COUNT : natural := 1;\n" if "IR" not in initial_proc else "    variable CLK_COUNT : natural := MAX_ENTRIES - CLK_RESET;\n"
+    string_mem += "    variable CLK_COUNT : natural := 4; -- Magic adjustment (ryd)\n" if "IR" not in initial_proc else "    variable CLK_COUNT : natural := MAX_ENTRIES - CLK_RESET;\n"
     string_mem += "    variable EVENT_COUNT : integer := -1;\n"
     string_mem += "    variable v_line : line; -- Line for debug\n"
     string_mem += "  begin\n\n"
@@ -346,6 +346,15 @@ def writeMemoryUtil(memDict, memInfoDict):
                 tName = "t_"+mtypeB+"_NENTADDRDISK"
                 nentaddrbits = "4"
                 ss += "  subtype "+tName+" is std_logic_vector("+nentaddrbits+" downto 0);\n"
+                #FIXME - hardcoded number
+                tName = "t_"+mtypeB+"_ADDRBINMASK"
+                ss += "  subtype "+tName+" is std_logic_vector(3 downto 0);\n"
+                tName = "t_"+mtypeB+"_ADDRBINMASKDISK"
+                ss += "  subtype "+tName+" is std_logic_vector(4 downto 0);\n"
+                tName = "t_"+mtypeB+"_BINMASK"
+                ss += "  subtype "+tName+" is std_logic_vector(7 downto 0);\n"
+                tName = "t_"+mtypeB+"_BINMASKDISK"
+                ss += "  subtype "+tName+" is std_logic_vector(7 downto 0);\n"
             else:
                 #FIXME
                 tpages = 1
@@ -468,9 +477,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
         merge_portlist = ""
         # Write wires
         if delay > 0:
-            if not memInfo.is_binned:
-                wirelist += "  signal "+mem+"_bx                   : "
-                wirelist += "std_logic_vector(2 downto 0);\n"
+            wirelist += "  signal "+mem+"_bx                   : "
+            wirelist += "std_logic_vector(2 downto 0);\n"
             wirelist += "  signal "+mem+"_start                   : "
             wirelist += "std_logic;\n"
             wirelist += "  signal "+mem+"_wea_delay_0          : "
@@ -519,6 +527,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
                     wirelist += "STD_LOGIC_VECTOR(8 downto 0);\n"
                     wirelist += "  signal "+mem+"_AV_dout_nent        : "
                     wirelist += "t_arr_7b(0 to 31);\n"
+                    wirelist += "  signal "+mem+"_AV_dout_mask        : "
+                    wirelist += "t_arr_4b(0 to 7);\n"
                 #FIXME this is a hack
                 if "AS" in mem and "in" in mem :
                     wirelist += "  signal "+mem+"_V_as        : "
@@ -544,6 +554,18 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
                     wirelist += "t_"+mtypeB+"_DATA_"+str(nmem)+";\n"
                     wirelist += "  signal "+mem+"_V_masktmp : "
                     wirelist += "t_"+mtypeB+"_MASK"+disk+"_"+str(num_pages)+";\n"
+                    wirelist += "  signal "+mem+"_V_addr_binmaskA   : "
+                    wirelist += "t_"+mtypeB+"_ADDRBINMASK"+disk+";\n"
+                    wirelist += "  signal "+mem+"_V_binmaskA   : "
+                    wirelist += "t_"+mtypeB+"_BINMASK"+disk+";\n"
+                    wirelist += "  signal "+mem+"_enb_binmaskA   : "
+                    wirelist += "t_"+mtypeB+"_1b;\n"
+                    wirelist += "  signal "+mem+"_V_addr_binmaskB   : "
+                    wirelist += "t_"+mtypeB+"_ADDRBINMASK"+disk+";\n"
+                    wirelist += "  signal "+mem+"_V_binmaskB   : "
+                    wirelist += "t_"+mtypeB+"_BINMASK"+disk+";\n"
+                    wirelist += "  signal "+mem+"_enb_binmaskB   : "
+                    wirelist += "t_"+mtypeB+"_1b;\n"
                 else:
                     wirelist += "  signal "+mem+"_AV_dout_nent  : "
                     wirelist += "t_"+mtypeB+"_NENT; -- (#page)\n"
@@ -563,7 +585,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
         # Write parameters
         parameterlist += "        RAM_WIDTH       => "+bitwidth+",\n"
         parameterlist += "        NUM_PAGES       => "+str(num_pages)+",\n"
-        if "MPROJ" in mem:
+        if "MPROJ" in mem :
             parameterlist += "        PAGE_LENGTH       => 64,\n"
         if "MPROJ" in mem or "MPAR" in mem:
             parameterlist += "        NUM_TPAGES       => 4,\n"
@@ -572,7 +594,10 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
         parameterlist += "        RAM_PERFORMANCE => \"HIGH_PERFORMANCE\",\n"
         parameterlist += "        NAME            => \""+mem+"\",\n"
         if delay > 0:
-            delay2_parameterlist +="        DELAY           => " + str(delay*2) +",\n"
+            if "in" in mem :
+                delay2_parameterlist +="        DELAY           => " + str(2+delay*2) +",\n"
+            else:
+                delay2_parameterlist +="        DELAY           => " + str(delay*2) +",\n"
             delay_parameterlist +="        DELAY           => " + str(delay) +",\n"
             delay_parameterlist_0 +="        DELAY           => " + str(delay+1) +",\n"
             #enable to use non-default delay value
@@ -639,6 +664,8 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
                 else:
                     delay2_portlist += "        done   => "+memmod.upstreams[0].mtype_short()+"_done,\n"
                     delay2_portlist += "        bx_out   => "+memmod.upstreams[0].mtype_short()+"_bx_out,\n"
+            else:
+                delay2_portlist += "        done   => PC_start,\n"
             delay2_portlist += "        bx       => "+mem+"_bx,\n"
             delay2_portlist += "        start    => "+mem+"_start,\n"
             delay_portlist_0 += "        clk      => clk,\n"
@@ -717,16 +744,14 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
             portlist += "        enb       => "+mem+"_enb,\n"
             portlist += "        addrb     => "+mem+"_V_readaddr,\n"
             portlist += "        doutb     => "+mem+"_V_dout,\n"
-        if ("AS" in mem or "MPAR" in mem) and "in" in mem:
-            portlist += "        sync_nent => PC_start,\n"
-        elif "MPAR" in mem and "in" not in mem:
+        if "MPAR" in mem and "in" not in mem:
             portlist += "        sync_nent => "+mem+"_start,\n"
         elif "AS" in mem and "n1" in mem and split == 1:
             portlist += "        sync_nent => TP_L1L2A_start,\n"
         elif "TPAR" in mem and split == 1:
             portlist += "        sync_nent => TP_done,\n" 
         else:
-            portlist += "        sync_nent => "+sync_signal+",\n"
+            portlist += "        sync_nent => "+mem+"_start,\n"
         if memmod.has_numEntries_out or ("n1" in mem and split == 1):
             if memList[0].is_binned:
                 ncopy = getVMStubNCopy(memmod);
@@ -746,11 +771,18 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
                 portlist += "        enb_nent  => "+mem+"_enb_nent,\n"
                 portlist += "        addr_nent  => "+mem+"_V_addr_nent,\n"
                 portlist += "        dout_nent  => "+mem+"_AV_dout_nent,\n"
-                portlist += "        mask_o    => "+mem+"_V_masktmp,\n"
+                portlist += "        enb_binmaska  => "+mem+"_enb_binmaska,\n"
+                portlist += "        addr_binmaska  => "+mem+"_V_addr_binmaska,\n"
+                portlist += "        binmaska_o  => "+mem+"_V_binmaska,\n"
+                portlist += "        enb_binmaskb  => "+mem+"_enb_binmaskb,\n"
+                portlist += "        addr_binmaskb  => "+mem+"_V_addr_binmaskb,\n"
+                portlist += "        binmaskb_o  => "+mem+"_V_binmaskb,\n"
             else:
                 portlist += "        nent_o    => "+mem+"_AV_dout_nent,\n"
                 if "MPROJ" in mem:
                     portlist += "        mask_o    => "+mem+"_AV_dout_mask,\n"
+                if "MPAR" in mem:
+                    portlist += "        mask_o    => "+mem+"_AV_dout_mask,\n"
         else:
             portlist += "        nent_o    => open,\n"
 
@@ -768,18 +800,6 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
                 else:
                     mem_str += "        dataout"+str(i)+" => "+mem+"_AV_dout("+str(i)+")\n"
             mem_str += "      );\n\n"
-            disk = ""
-            if "VMSME_D" in mem:
-                disk = "DISK"
-            mem_str += "    "+mem+"_maskformat : entity work.vmstub"+str(nbx)+"mask"+disk+"\n"
-            mem_str += "      port map (\n"
-            mem_str += "        datain => "+mem+"_V_masktmp,\n"
-            for i in range(0, nbx) :
-                if i < nbx-1 :
-                    mem_str += "        dataout"+str(i)+" => "+mem+"_AV_dout_mask("+str(i)+"),\n"
-                else:
-                    mem_str += "        dataout"+str(i)+" => "+mem+"_AV_dout_mask("+str(i)+")\n"
-            mem_str += "      );\n\n"
             mem_str += "    "+mem+" : entity work.tf_mem_bin\n"
         else:
             if "MPROJ" in mem:
@@ -791,10 +811,9 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl
         mem_str += "      generic map (\n"+parameterlist.rstrip(",\n")+"\n      )\n"
         mem_str += "      port map (\n"+portlist.rstrip(",\n")+"\n      );\n\n"
         if delay > 0:
-            if not memInfo.is_binned and not "in" in mem and not "AS_" in mem:
-                mem_str += "    "+mem+"_BX_GEN : entity work.CreateStartSignal\n"
-                mem_str += "      generic map (\n"+delay2_parameterlist.rstrip(",\n")+"\n      )\n"
-                mem_str += "      port map (\n"+delay2_portlist.rstrip(",\n")+"\n      );\n\n"
+            mem_str += "    "+mem+"_BX_GEN : entity work.CreateStartSignal\n"
+            mem_str += "      generic map (\n"+delay2_parameterlist.rstrip(",\n")+"\n      )\n"
+            mem_str += "      port map (\n"+delay2_portlist.rstrip(",\n")+"\n      );\n\n"
             mem_str += "    "+mem+"_DELAY : entity work.tf_pipe_delay\n"        
             mem_str += "      generic map (\n"+delay_parameterlist.rstrip(",\n")+"\n      )\n"
             mem_str += "      port map (\n"+delay_portlist.rstrip(",\n")+"\n      );\n\n"
@@ -825,7 +844,7 @@ def writeControlSignals_interface(initial_proc, final_procs, notfinal_procs, del
     string_ctrl_signals += "    "+final_proc_short+"_bx_out : out std_logic_vector(2 downto 0);\n"
     string_ctrl_signals += "    "+final_proc_short+"_bx_out_vld : out std_logic;\n"
     string_ctrl_signals += "    "+final_proc_short+"_done   : out std_logic;\n"
-    if final_proc_short == "FT":
+    if final_proc_short == "TB":
       for final_proc in final_procs:
         string_ctrl_signals += "    "+final_proc+"_last_track   : out std_logic;\n"
         string_ctrl_signals += "    "+final_proc+"_last_track_vld   : out std_logic;\n"
@@ -916,7 +935,6 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict, split, MPARdict = 0)
           string_output_mems += "    "+mem+"_A_enb          : in t_"+mtypeB+"_A1b;\n"
           string_output_mems += "    "+mem+"_AV_readaddr    : in t_"+mtypeB+"_AADDR"+disk+";\n"
           string_output_mems += "    "+mem+"_AV_dout        : out t_"+mtypeB+"_ADATA;\n"
-          string_output_mems += "    "+mem+"_AV_dout_mask        : out t_"+mtypeB+"_MASK"+disk+";\n"
           string_output_mems += "    "+mem+"_enb_nent        : out t_"+mtypeB+"_1b;\n"
           string_output_mems += "    "+mem+"_V_addr_nent        : out t_"+mtypeB+"_NENTADDR"+disk+";\n"
           string_output_mems += "    "+mem+"_AV_dout_nent       : out t_"+mtypeB+"_NENT;\n"
@@ -937,8 +955,6 @@ def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict, split, MPARdict = 0)
               if memInfo.is_binned:
                   string_output_mems += "    "+mem+"_AV_dout_nent : "
                   string_output_mems += "out t_"+mtypeB+"_NENT;\n"
-                  string_output_mems += "    "+mem+"_AV_dout_mask : "
-                  string_output_mems += "out t_"+mtypeB+"_MASK;\n"
               else:
                   string_output_mems += "    "+mem+"_AV_dout_nent  : "
                   string_output_mems += "out t_"+mtypeB+"_NENT;\n"
@@ -1071,7 +1087,7 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi
     string_ctrl_signals += ("  signal "+final_procs[-1].mtype_short()+"_bx_out").ljust(str_len)+": std_logic_vector(2 downto 0) := (others => '1');\n"
     string_ctrl_signals += ("  signal "+final_procs[-1].mtype_short()+"_bx_out_vld").ljust(str_len)+": std_logic := '0';\n"
     string_ctrl_signals += ("  signal "+final_procs[-1].mtype_short()+"_done").ljust(str_len)+": std_logic := '0';\n"
-    if final_procs[-1].mtype_short().startswith("FT"):
+    if final_procs[-1].mtype_short().startswith("TB"):
         for final_proc in final_procs:
             string_ctrl_signals += ("  signal "+final_proc.inst+"_last_track").ljust(str_len)+": std_logic := '0';\n"
             string_ctrl_signals += ("  signal "+final_proc.inst+"_last_track_vld").ljust(str_len)+": std_logic := '0';\n"
@@ -1138,8 +1154,6 @@ def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfi
                     string_ctrl_signals += ("t_"+mtypeB+"_ADATA").ljust(str_len2)+":= (others => (others => '0'));\n"
                     string_ctrl_signals += ("  signal "+mem+"_AAV_dout_nent").ljust(str_len)+": "
                     string_ctrl_signals += ("t_"+mtypeB+"_NENT").ljust(str_len2)+":= (others => '0'); -- (#page)(#bin)\n"
-                    string_ctrl_signals += ("  signal "+mem+"_AV_dout_mask").ljust(str_len)+": "
-                    string_ctrl_signals += ("t_"+mtypeB+"_MASK").ljust(str_len2)+":= (others => (others => '0')); -- (#page)(#bin)\n"
                 elif split == 1 and "TPAR" in mem:
                     seed = mem.split("_")[1][:-1]
                     itc = mem.split("_")[1][-1]
@@ -1219,7 +1233,7 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc
     string_fwblock_inst += ("        " + final_procs[-1].mtype_short() + "_bx_out").ljust(str_len) + "=> " + final_procs[-1].mtype_short() + "_bx_out,\n"
     string_fwblock_inst += ("        " + final_procs[-1].mtype_short() + "_bx_out_vld").ljust(str_len) + "=> " + final_procs[-1].mtype_short() + "_bx_out_vld,\n"
     string_fwblock_inst += ("        " + final_procs[-1].mtype_short() + "_done").ljust(str_len) + "=> " + final_procs[-1].mtype_short() + "_done,\n"
-    if final_procs[-1].mtype_short().startswith("FT"):
+    if final_procs[-1].mtype_short().startswith("TB"):
         for final_proc in final_procs :
             string_fwblock_inst += ("        " + final_proc.inst + "_last_track").ljust(str_len) + "=> " + final_proc.inst + "_last_track,\n"
             string_fwblock_inst += ("        " + final_proc.inst + "_last_track_vld").ljust(str_len) + "=> " + final_proc.inst + "_last_track_vld,\n"
@@ -1271,7 +1285,6 @@ def writeFWBlockInstance(topfunc, memDict, memInfoDict, initial_proc, final_proc
                     string_output += ("        "+mem+"_A_enb").ljust(str_len) + "=> "+mem+"_enb,\n"
                     string_output += ("        "+mem+"_AV_readaddr").ljust(str_len) + "=> "+mem+"_readaddr,\n"
                     string_output += ("        "+mem+"_AV_dout").ljust(str_len) + "=> "+mem+"_dout,\n"
-                    string_output += ("        "+mem+"_AV_dout_mask").ljust(str_len) + "=> open,\n" #FIXME
                     string_output += ("        "+mem+"_enb_nent").ljust(str_len) + "=> open,\n"
                     string_output += ("        "+mem+"_V_addr_nent").ljust(str_len) + "=> open,\n"
                     string_output += ("        "+mem+"_AV_dout_nent").ljust(str_len) + "=> open,\n"
@@ -1350,9 +1363,14 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi
                 string_mem += "        PAGE_LENGTH".ljust(str_len)+"=> 2048,\n"
             else:
                 string_mem += "        PAGE_LENGTH".ljust(str_len)+"=> 1024,\n"
+            if "VMSME" in mem:
+                string_mem += "        CLK_CNT_INIT".ljust(str_len)+"=> -17,\n" #-17 is emperically determined to allign the FileWriter BX with the data stream
         if "MPROJ" in mem :
             string_mem += "        NUM_TPAGES".ljust(str_len)+"=> 4,\n"
             string_mem += "        PAGE_LENGTH".ljust(str_len)+"=> 64,\n"
+            string_mem += "        CLK_CNT_INIT".ljust(str_len)+"=> -17,\n" #-17 is emperically determined to allign the FileWriter BX with the data stream
+        if "FM" in mem :
+            string_mem += "        CLK_CNT_INIT".ljust(str_len)+"=> -17,\n" #-17 is emperically determined to allign the FileWriter BX with the data stream
         string_mem += "        NUM_PAGES".ljust(str_len)+"=> " + str(2**bxbitwidth) + "\n"
         string_mem += "      )\n"
         string_mem += "      port map (\n"
@@ -1360,7 +1378,7 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi
         string_mem += "        ADDR".ljust(str_len)+"=> "+mem+"_writeaddr,\n"
         string_mem += "        DATA".ljust(str_len)+"=> "+mem+"_din,\n"
         string_mem += "        WRITE_EN".ljust(str_len)+"=> "+mem+"_wea,\n"
-        if proc == "VMSMER" :
+        if proc == "VMSMER" or proc == "PC":
             string_mem += "        START".ljust(str_len)+"=> PC_START,\n"
         else:
             string_mem += "        START".ljust(str_len)+"=> "+(proc+"_START,\n" if not proc_up else proc_up+"_DONE,\n")
@@ -1494,7 +1512,8 @@ def writeProcCombination(module, str_ctrl_func, str_ports):
         module_str += "      dout  => MPAR_"+module.inst[3:]+"in_V_tpar,\n"
         module_str += "      valid  => MPAR_"+module.inst[3:]+"in_valid,\n"
         module_str += "      index  => MPAR_"+module.inst[3:]+"in_trackletindex,\n"
-        module_str += "      nent  => MPAR_"+module.inst[3:]+"in_AV_dout_nent\n"
+        module_str += "      nent  => MPAR_"+module.inst[3:]+"in_AV_dout_nent,\n"
+        module_str += "      mask  => MPAR_"+module.inst[3:]+"in_AV_dout_mask\n"
         module_str += "    );\n\n"
 
     if "VMSMER_" in module.inst:
@@ -1513,7 +1532,8 @@ def writeProcCombination(module, str_ctrl_func, str_ports):
         module_str += "      dout  => AS_"+module.inst[7:]+"in_V_as,\n"
         module_str += "      valid  => AS_"+module.inst[7:]+"in_valid,\n"
         module_str += "      index  => AS_"+module.inst[7:]+"in_index(6 downto 0),\n"
-        module_str += "      nent  => AS_"+module.inst[7:]+"in_AV_dout_nent\n"
+        module_str += "      nent  => AS_"+module.inst[7:]+"in_AV_dout_nent,\n"
+        module_str += "      mask  => (others => (others => '1'))\n"
         module_str += "    );\n\n"
 
     module_str += str_ctrl_func
@@ -1552,7 +1572,7 @@ def writeStartSwitchAndInternalBX(module,mem,extraports=False, delay = 0, first_
     if "PC_" in mtype and first_of_type :
 
         int_ctrl_func +=  "  LATCH_PC_VMSMER: entity work.CreateStartSignal\n"
-        startsignal_parameter_list = "        DELAY           => " + str(110) +",\n"
+        startsignal_parameter_list = "        DELAY           => " + str(123) +",\n"
         int_ctrl_func += "      generic map (\n"+startsignal_parameter_list.rstrip(",\n")+"\n      )\n"
 
         int_ctrl_func += "    port map (\n"
@@ -1573,31 +1593,32 @@ def writeStartSwitchAndInternalBX(module,mem,extraports=False, delay = 0, first_
         int_ctrl_wire += "  signal "+mtype_up+"_done : std_logic := '0';\n"
         int_ctrl_wire += "  signal "+mtype_up+"_bx_out : std_logic_vector(2 downto 0);\n"
         int_ctrl_wire += "  signal "+mtype_up+"_bx_out_vld : std_logic;\n"
-    int_ctrl_wire += "  signal "+mtype+"_bx_in : std_logic_vector(2 downto 0);\n"
-    int_ctrl_wire += "  signal "+mtype+"_start : std_logic := '0';\n"
-    int_ctrl_func +=  "  LATCH_"+mtype+": entity work.CreateStartSignal\n"
-    if delay > 0:
-      startsignal_parameter_list = "        DELAY           => " + str(delay*2) +",\n"
-      int_ctrl_func += "      generic map (\n"+startsignal_parameter_list.rstrip(",\n")+"\n      )\n"
-
-    int_ctrl_func += "    port map (\n"
-    int_ctrl_func += "      clk   => clk,\n"
-    int_ctrl_func += "      reset => reset,\n"
-    if "MP_" in mtype :
-        int_ctrl_func += "      done  => PC_done,\n"
-        int_ctrl_func += "      bx_out => PC_bx_out,\n"
-    else:
-        if first_proc:
-            if mtype_up == "VMSMER":
-                mtype_up = "PC"
-            int_ctrl_func += "      done  => "+mtype_up+"_start,\n"
-            int_ctrl_func += "      bx_out => "+mtype_up+"_bx_in,\n"
+    if "VMSMER" not in mtype:
+        int_ctrl_wire += "  signal "+mtype+"_bx_in : std_logic_vector(2 downto 0);\n"
+        int_ctrl_wire += "  signal "+mtype+"_start : std_logic := '0';\n"
+        int_ctrl_func +=  "  LATCH_"+mtype+": entity work.CreateStartSignal\n"
+        if delay > 0:
+            startsignal_parameter_list = "        DELAY           => " + str(delay*2) +",\n"
+            int_ctrl_func += "      generic map (\n"+startsignal_parameter_list.rstrip(",\n")+"\n      )\n"
+
+        int_ctrl_func += "    port map (\n"
+        int_ctrl_func += "      clk   => clk,\n"
+        int_ctrl_func += "      reset => reset,\n"
+        if "MP_" in mtype :
+            int_ctrl_func += "      done  => PC_done,\n"
+            int_ctrl_func += "      bx_out => PC_bx_out,\n"
         else:
-            int_ctrl_func += "      done  => "+mtype_up+"_done,\n"
-            int_ctrl_func += "      bx_out => "+mtype_up+"_bx_out,\n"
-    int_ctrl_func += "      bx => "+mtype+"_bx_in,\n"
-    int_ctrl_func += "      start => "+mtype+"_start\n"
-    int_ctrl_func += "  );\n\n"
+            if first_proc:
+                if mtype_up == "VMSMER":
+                    mtype_up = "PC"
+                int_ctrl_func += "      done  => "+mtype_up+"_start,\n"
+                int_ctrl_func += "      bx_out => "+mtype_up+"_bx_in,\n"
+            else:
+                int_ctrl_func += "      done  => "+mtype_up+"_done,\n"
+                int_ctrl_func += "      bx_out => "+mtype_up+"_bx_out,\n"
+        int_ctrl_func += "      bx => "+mtype+"_bx_in,\n"
+        int_ctrl_func += "      start => "+mtype+"_start\n"
+        int_ctrl_func += "  );\n\n"
 
     return int_ctrl_wire,int_ctrl_func
 
@@ -1643,7 +1664,7 @@ def writeProcBXPort(modName,isInput,isInitial,first_of_type,delay):
         else:
             if first_of_type and not ("VMSMER" in modName or "PC" in modName):
                 bx_str += "      bx_o_V        => "+modName.split("_")[0]+"_bx_out,\n"
-                if ("FT_" in modName) or ("TP_" in modName):
+                if ("TB_" in modName) or ("TP_" in modName):
                   bx_str += "      bx_o_V_ap_vld => "+modName.split("_")[0]+"_bx_out_vld,\n"
                 else:
                   bx_str += "      bx_o_V_ap_vld => open,\n"
@@ -1735,17 +1756,12 @@ def writeProcMemoryRHSPorts(argname,mem,portindex=0, split = 0):
             string_mem_ports += "      "+argname+"_nentries_V_ce0 => "+mem.mtype_short()+"_"+mem.var()+"_enb_nent,\n"
             string_mem_ports += "      "+argname+"_nentries_V_address0 => "+mem.mtype_short()+"_"+mem.var()+"_V_addr_nent,\n"
             string_mem_ports += "      "+argname+"_nentries_V_q0 => "+mem.mtype_short()+"_"+mem.var()+"_AV_dout_nent,\n"
-            for i in range(0,2**mem.bxbitwidth):
-                nrz = 8
-                if mem.var()[0] == "D"  and split == 2:
-                    nrz = 16
-                for j in range(0,nrz):
-                    string_mem_ports += "      "+argname+"_binmask8_"+str(i)+"_V_"+str(j)+"     => ("
-                    for k in range(0,8):
-                        if k != 0 :
-                            string_mem_ports += ", "
-                        string_mem_ports += mem.mtype_short()+"_"+mem.var()+"_AV_dout_mask("+str(i)+")("+str((j+1)*8-k-1)+")"
-                    string_mem_ports += "),\n"
+            string_mem_ports += "      "+argname+"_binmaskA_V_address0 => "+mem.mtype_short()+"_"+mem.var()+"_V_addr_binmaskA,\n"
+            string_mem_ports += "      "+argname+"_binmaskA_V_ce0 => "+mem.mtype_short()+"_"+mem.var()+"_enb_binmaskA,\n"
+            string_mem_ports += "      "+argname+"_binmaskA_V_q0 => "+mem.mtype_short()+"_"+mem.var()+"_V_binmaskA,\n"
+            string_mem_ports += "      "+argname+"_binmaskB_V_address0 => "+mem.mtype_short()+"_"+mem.var()+"_V_addr_binmaskB,\n"
+            string_mem_ports += "      "+argname+"_binmaskB_V_ce0 => "+mem.mtype_short()+"_"+mem.var()+"_enb_binmaskB,\n"
+            string_mem_ports += "      "+argname+"_binmaskB_V_q0 => "+mem.mtype_short()+"_"+mem.var()+"_V_binmaskB,\n"
         else:
             tpage = 1
             if "MPROJ" in mem.mtype_short() :
diff --git a/bodge/TF_D1D2_tb_writer.vhd.bodge b/bodge/TF_D1D2_tb_writer.vhd.bodge
deleted file mode 100644
index bc24144..0000000
--- a/bodge/TF_D1D2_tb_writer.vhd.bodge
+++ /dev/null
@@ -1,16 +0,0 @@
-  -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2.
-  -- (Needed to compare with emData/).
-  writeTF_D1D2_297 : entity work.FileWriterFIFO
-  generic map (
-    FILE_NAME  => FILE_OUT_TF&memory_enum_to_string(D1D2)&outputFileNameEnding,
-    FIFO_WIDTH  => 297
-  )
-  port map (
-    CLK => CLK,
-    DONE => FT_DONE,
-    WRITE_EN => (TW_D1D2_stream_A_write and TW_D1D2_stream_AV_din(103)),
-    FULL_NEG => TW_D1D2_stream_A_full_neg,
-    --DATA => TW_D1D2_stream_AV_din&BW_D1D2_L1_stream_AV_din&BW_D1D2_D3_stream_AV_din&BW_D1D2_D4_stream_AV_din&BW_D1D2_D5_stream_AV_din
-    DATA => TW_D1D2_stream_AV_din&BW_D1D2_L1_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub
-  );
-
diff --git a/bodge/TF_D3D4_tb_writer.vhd.bodge b/bodge/TF_D3D4_tb_writer.vhd.bodge
deleted file mode 100644
index 57b27eb..0000000
--- a/bodge/TF_D3D4_tb_writer.vhd.bodge
+++ /dev/null
@@ -1,15 +0,0 @@
-  -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2.
-  -- (Needed to compare with emData/).
-  writeTF_D3D4_297 : entity work.FileWriterFIFO
-  generic map (
-    FILE_NAME  => FILE_OUT_TF&memory_enum_to_string(D3D4)&outputFileNameEnding,
-    FIFO_WIDTH  => 297
-  )
-  port map (
-    CLK => CLK,
-    DONE => FT_DONE,
-    WRITE_EN => (TW_D3D4_stream_A_write and TW_D3D4_stream_AV_din(103)),
-    FULL_NEG => TW_D3D4_stream_A_full_neg,
-    DATA => TW_D3D4_stream_AV_din&BW_D3D4_L1_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub
-  );
-
diff --git a/bodge/TF_L1D1_tb_writer.vhd.bodge b/bodge/TF_L1D1_tb_writer.vhd.bodge
deleted file mode 100644
index 2072b44..0000000
--- a/bodge/TF_L1D1_tb_writer.vhd.bodge
+++ /dev/null
@@ -1,15 +0,0 @@
-  -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2.
-  -- (Needed to compare with emData/).
-  writeTF_L1D1_300 : entity work.FileWriterFIFO
-  generic map (
-    FILE_NAME  => FILE_OUT_TF&memory_enum_to_string(L1D1)&outputFileNameEnding,
-    FIFO_WIDTH  => 300
-  )
-  port map (
-    CLK => CLK,
-    DONE => FT_DONE,
-    WRITE_EN => (TW_L1D1_stream_A_write and TW_L1D1_stream_AV_din(103)),
-    FULL_NEG => TW_L1D1_stream_A_full_neg,
-    DATA => TW_L1D1_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub
-  );
-
diff --git a/bodge/TF_L1L2_tb_writer.vhd.bodge b/bodge/TF_L1L2_tb_writer.vhd.bodge
deleted file mode 100644
index 0e88c66..0000000
--- a/bodge/TF_L1L2_tb_writer.vhd.bodge
+++ /dev/null
@@ -1,15 +0,0 @@
-  -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2.
-  -- (Needed to compare with emData/).
-  writeTF_L1L2_484 : entity work.FileWriterFIFO
-  generic map (
-    FILE_NAME  => FILE_OUT_TF&"L1L2"&outputFileNameEnding,
-    FIFO_WIDTH  => 484
-  )
-  port map (
-    CLK => CLK,
-    DONE => FT_DONE,
-    WRITE_EN => (TW_L1L2_stream_A_write and TW_L1L2_stream_AV_din(103)),
-    FULL_NEG => TW_L1L2_stream_A_full_neg,
-    DATA => TW_L1L2_stream_AV_din&BW_L1L2_L3_stream_AV_din&BW_L1L2_L4_stream_AV_din&BW_L1L2_L5_stream_AV_din&BW_L1L2_L6_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub
-  );
-
diff --git a/bodge/TF_L2D1_tb_writer.vhd.bodge b/bodge/TF_L2D1_tb_writer.vhd.bodge
deleted file mode 100644
index 5d07e40..0000000
--- a/bodge/TF_L2D1_tb_writer.vhd.bodge
+++ /dev/null
@@ -1,15 +0,0 @@
-  -- A bodge for TrackBuilder to write TF concatenated track+stub data for L1L2.
-  -- (Needed to compare with emData/).
-  writeTF_L2D1_346 : entity work.FileWriterFIFO
-  generic map (
-    FILE_NAME  => FILE_OUT_TF&memory_enum_to_string(L2D1)&outputFileNameEnding,
-    FIFO_WIDTH  => 346
-  )
-  port map (
-    CLK => CLK,
-    DONE => FT_DONE,
-    WRITE_EN => (TW_L2D1_stream_A_write and TW_L2D1_stream_AV_din(103)),
-    FULL_NEG => TW_L2D1_stream_A_full_neg,
-    DATA => TW_L2D1_stream_AV_din&BW_L2D1_L1_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub
-  );
-
diff --git a/bodge/TF_L2L3_tb_writer.vhd.bodge b/bodge/TF_L2L3_tb_writer.vhd.bodge
deleted file mode 100644
index 402b6e1..0000000
--- a/bodge/TF_L2L3_tb_writer.vhd.bodge
+++ /dev/null
@@ -1,15 +0,0 @@
-  -- A bodge for TrackBuilder to write TF concatenated track+stub data for L2L3.
-  -- (Needed to compare with emData/).
-  writeTF_L2L3_438 : entity work.FileWriterFIFO
-  generic map (
-    FILE_NAME  => FILE_OUT_TF&"L2L3"&outputFileNameEnding,
-    FIFO_WIDTH  => 438
-  )
-  port map (
-    CLK => CLK,
-    DONE => FT_DONE,
-    WRITE_EN => (TW_L2L3_stream_A_write and TW_L2L3_stream_AV_din(103)),
-    FULL_NEG => TW_L2L3_stream_A_full_neg,
-    DATA => TW_L2L3_stream_AV_din&BW_L2L3_L1_stream_AV_din&BW_L2L3_L4_stream_AV_din&BW_L2L3_L5_stream_AV_din&emptyDiskStub&emptyDiskStub&emptyDiskStub&emptyDiskStub
-  );
-
diff --git a/bodge/TF_L3L4_tb_writer.vhd.bodge b/bodge/TF_L3L4_tb_writer.vhd.bodge
deleted file mode 100644
index c3b994b..0000000
--- a/bodge/TF_L3L4_tb_writer.vhd.bodge
+++ /dev/null
@@ -1,15 +0,0 @@
-  -- A bodge for TrackBuilder to write TF concatenated track+stub data for L3L4.
-  -- (Needed to compare with emData/).
-  writeTF_L3L4_386 : entity work.FileWriterFIFO
-  generic map (
-    FILE_NAME  => FILE_OUT_TF&"L3L4"&outputFileNameEnding,
-    FIFO_WIDTH  => 386
-  )
-  port map (
-    CLK => CLK,
-    DONE => FT_DONE,
-    WRITE_EN => (TW_L3L4_stream_A_write and TW_L3L4_stream_AV_din(103)),
-    FULL_NEG => TW_L3L4_stream_A_full_neg,
-    DATA => TW_L3L4_stream_AV_din&BW_L3L4_L1_stream_AV_din&BW_L3L4_L2_stream_AV_din&BW_L3L4_L5_stream_AV_din&BW_L3L4_L6_stream_AV_din&emptyDiskStub&emptyDiskStub
-  );
-
diff --git a/bodge/TF_L5L6_tb_writer.vhd.bodge b/bodge/TF_L5L6_tb_writer.vhd.bodge
deleted file mode 100644
index 5196fa0..0000000
--- a/bodge/TF_L5L6_tb_writer.vhd.bodge
+++ /dev/null
@@ -1,15 +0,0 @@
-  -- A bodge for TrackBuilder to write TF concatenated track+stub data for L5L6.
-  -- (Needed to compare with emData/).
-  writeTF_L5L6_288 : entity work.FileWriterFIFO
-  generic map (
-    FILE_NAME  => FILE_OUT_TF&"L5L6"&outputFileNameEnding,
-    FIFO_WIDTH  => 288
-  )
-  port map (
-    CLK => CLK,
-    DONE => FT_DONE,
-    WRITE_EN => (TW_L5L6_stream_A_write and TW_L5L6_stream_AV_din(103)),
-    FULL_NEG => TW_L5L6_stream_A_full_neg,
-    DATA => TW_L5L6_stream_AV_din&BW_L5L6_L1_stream_AV_din&BW_L5L6_L2_stream_AV_din&BW_L5L6_L3_stream_AV_din&BW_L5L6_L4_stream_AV_din
-  );
-
diff --git a/bodge/TF_tb_constants.vhd.bodge b/bodge/TF_tb_constants.vhd.bodge
deleted file mode 100644
index 14c8155..0000000
--- a/bodge/TF_tb_constants.vhd.bodge
+++ /dev/null
@@ -1,6 +0,0 @@
-  -- A bodge for TrackBuilder to write TF concatenated track+stub data.
-  -- (Needed to compare with emData/).
-  constant FILE_OUT_TF          : string := dataOutDir&"TF_";
-  -- Empty field in the output from barrel-only TrackBuilders corresponding to
-  -- disk matches
-  constant emptyDiskStub : std_logic_vector(48 downto 0) := (others => '0');
diff --git a/generator_hdl.py b/generator_hdl.py
index 66ee73b..4ee22fa 100755
--- a/generator_hdl.py
+++ b/generator_hdl.py
@@ -290,16 +290,36 @@ def writeTBMemoryWrites(memDict, memInfoDict, notfinal_procs,split, MPARdict):
 
         if memInfo.isFIFO:
             string_tmp = writeTBMemoryWriteFIFOInstance(mtypeB, memDict, proc)
-            # A bodge for TrackBuilder to write TF concatenated track+stub data.
+            # Code for TrackBuilder to write TF concatenated track+stub data.
             # (Needed to compare with emData/).
-            if mtypeB == 'TW_104':
+            if mtypeB.startswith('TW_'):
                 for m in memDict[mtypeB]:
                     memName = m.inst
                     seed = memName[-4:]
-                    fileTF = open("bodge/TF_" + seed + "_tb_writer.vhd.bodge")
-                    string_tmp += fileTF.read();
-                    fileTF.close()
-
+                    bw_keys = [key for key in memDict if key.startswith('BW_')]
+                    bw_width = memDict[bw_keys[0]][0].bitwidth if len(bw_keys) > 0 else 0
+                    n_bw = len([key for key in memDict[bw_keys[0]] if seed in key.inst]) if len(bw_keys) > 0 else 0
+                    dw_keys = [key for key in memDict if key.startswith('DW_')]
+                    dw_width = memDict[dw_keys[0]][0].bitwidth if len(dw_keys) > 0 else 0
+                    n_dw = len([key for key in memDict[dw_keys[0]] if seed in key.inst]) if len(dw_keys) > 0 else 0
+                    # Calculate total width of track word plus stub words
+                    total_width = str(m.bitwidth + n_bw * bw_width + n_dw * dw_width)
+
+                    string_tmp += "-- Code for TrackBuilder to write TF concatenated track+stub data.\n";
+                    string_tmp += "-- (Needed to compare with emData/).\n";
+                    string_tmp += "writeTF_"+seed+"_" + total_width + " : entity work.FileWriterFIFO\n";
+                    string_tmp += "generic map (\n";
+                    string_tmp += "  FILE_NAME  => FILE_OUT_TF&\""+seed+"\"&outputFileNameEnding,\n";
+                    string_tmp += "  FIFO_WIDTH  => " + total_width + "\n";
+                    string_tmp += ")\n";
+                    string_tmp += "port map (\n";
+                    string_tmp += "  CLK => CLK,\n"
+                    string_tmp += "  DONE => TB_DONE,\n";
+                    string_tmp += "  WRITE_EN => (TW_"+seed+"_stream_A_write and TW_"+seed+"_stream_AV_din("+str(m.bitwidth-1)+")),\n";
+                    string_tmp += "  FULL_NEG => TW_"+seed+"_stream_A_full_neg,\n";
+                    string_tmp += "  DATA => TW_"+seed+"_stream_AV_din&BW_"+seed+"_L1_stream_AV_din&BW_"+seed+"_L2_stream_AV_din&BW_"+seed+"_L3_stream_AV_din&BW_"+seed+"_L4_stream_AV_din&BW_"+seed+"_L5_stream_AV_din&BW_"+seed+"_L6_stream_AV_din&DW_"+seed+"_D1_stream_AV_din&DW_"+seed+"_D2_stream_AV_din&DW_"+seed+"_D3_stream_AV_din&DW_"+seed+"_D4_stream_AV_din&DW_"+seed+"_D5_stream_AV_din\n";
+                    string_tmp += ");\n";
+                    
         if memInfo.is_final:
             if memInfo.isFIFO:
               string_final += string_tmp
@@ -355,12 +375,9 @@ def writeTestBench(tbfunc, topfunc, process_list, memDict, memInfoDict, memPrint
     string_header += writeTBOpener(tbfunc)
 
     string_constants = writeTBConstants(memDict, memInfoDict, notfinal_procs+[final_procs[-1].mtype_short()], memPrintsDir, sector, split)
-    # A bodge for TrackBuilder to write TF concatenated track+stub data.
-    # (Needed to compare with emData/).
-    if 'TW_104' in memInfoDict.keys():
-      fileTF = open("bodge/TF_tb_constants.vhd.bodge")
-      string_constants += fileTF.read();
-
+    if len([key for key in memInfoDict if key.startswith('TW_')]) > 0:
+        string_constants += 'constant FILE_OUT_TF          : string := dataOutDir&"TF_";';
+        
     string_ctrl_signals = writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfinal_procs,split, MPARdict)
 
     string_begin = writeTBEntityBegin()