From d431ebc2edc847fd7c7fa0cc724c58bdab87938b Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Thu, 24 Apr 2025 14:29:21 -0400 Subject: [PATCH 1/2] Small change to pick correct TP for reduced FPGA1 project - old code assummed TP_L1LA --- WriteVHDLSyntax.py | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index ddc90b0..75362e9 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -439,6 +439,18 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl first_merge_streamer = True + first_tp="" + + for memmod in memList: + nmem = 0 + mem=memmod.inst + if "L1L2" in mem: + first_tp = "TP_L1L2A" + + #If we did not find L1L2 assume L5L^ for reduced project + if first_tp == "" : + first_tp = "TP_L5L6A" + for memmod in memList: nmem = 0 @@ -747,7 +759,7 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl if "MPAR" in mem and "in" not in mem: portlist += " sync_nent => "+mem+"_start,\n" elif "AS" in mem and "n1" in mem and split == 1: - portlist += " sync_nent => TP_L1L2A_start,\n" + portlist += " sync_nent => "+first_tp+"_start,\n" elif "TPAR" in mem and split == 1: portlist += " sync_nent => TP_done,\n" else: From 3a6495b17cadae8d5b09190025d353ab4d73e1f4 Mon Sep 17 00:00:00 2001 From: Anders Ryd Date: Wed, 4 Jun 2025 15:39:08 -0400 Subject: [PATCH 2/2] Fix typos --- WriteVHDLSyntax.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/WriteVHDLSyntax.py b/WriteVHDLSyntax.py index 75362e9..b650670 100644 --- a/WriteVHDLSyntax.py +++ b/WriteVHDLSyntax.py @@ -442,12 +442,11 @@ def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, spl first_tp="" for memmod in memList: - nmem = 0 mem=memmod.inst if "L1L2" in mem: first_tp = "TP_L1L2A" - #If we did not find L1L2 assume L5L^ for reduced project + #If we did not find L1L2 assume L5L6 for reduced project if first_tp == "" : first_tp = "TP_L5L6A"