How AFOCL's pocl almaif driver slices tasks and schedules them when processing NDRange ? #2
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soccercheng
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In the future, it might make sense to scale up the FPGA utilization by having multiple HLS'ed components exist in parallel which are fed work-groups to execute by the firmware. Scaling up by simple vectorization gets quite difficult with hundreds of elements (FPGA gets congested, or is not able to meet the timing) |
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Hi AFOCL Team
I've been trying to add my first OpenCL kernel (written in OpenCL C), and I have the following questions.
~Sting
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