From b26adf4061b4c23681fe5cf589cea5cbaebfe4a3 Mon Sep 17 00:00:00 2001 From: d0p1 Date: Tue, 31 May 2022 11:07:00 +0200 Subject: [PATCH 1/5] trying to be less x86 specific --- src/SUMMARY.md | 6 +++ "src/drivers/cartes-r\303\251seaux/E1000.md" | 7 +++ .../drivers/cartes-r\303\251seaux/RTL8139.md" | 5 +++ src/drivers/communication-serie/UART8250.md | 45 +++++++++++++++++++ 4 files changed, 63 insertions(+) create mode 100644 "src/drivers/cartes-r\303\251seaux/E1000.md" create mode 100644 "src/drivers/cartes-r\303\251seaux/RTL8139.md" create mode 100644 src/drivers/communication-serie/UART8250.md diff --git a/src/SUMMARY.md b/src/SUMMARY.md index 07a5370..d667360 100644 --- a/src/SUMMARY.md +++ b/src/SUMMARY.md @@ -32,3 +32,9 @@ - [Multitâche](x86_64/premiers-pas/06-multitache.md) - [Tache utilisateur](x86_64/premiers-pas/06-tache-utilisateur.md) - [Epilogue](x86_64/premiers-pas/06-epilogue.md) +- [drivers]() + - [cartes réseaux]() + - [e1000](drivers/cartes-réseaux/E1000.md) + - [RTL8139](drivers/cartes-réseaux/RTL8139.md) + - [communication série]() + - [UART8250](drivers/communication-serie/UART8250.md) diff --git "a/src/drivers/cartes-r\303\251seaux/E1000.md" "b/src/drivers/cartes-r\303\251seaux/E1000.md" new file mode 100644 index 0000000..e95cd63 --- /dev/null +++ "b/src/drivers/cartes-r\303\251seaux/E1000.md" @@ -0,0 +1,7 @@ +# E1000 + +# Références + +- [Intel i217 datasheet](https://www.mouser.com/datasheet/2/612/i217-ethernet-controller-datasheet-257741.pdf) +- [Intel 82540EM datasheet](https://www.intel.com/content/dam/doc/manual/pci-pci-x-family-gbe-controllers-software-dev-manual.pdf) + diff --git "a/src/drivers/cartes-r\303\251seaux/RTL8139.md" "b/src/drivers/cartes-r\303\251seaux/RTL8139.md" new file mode 100644 index 0000000..617ef79 --- /dev/null +++ "b/src/drivers/cartes-r\303\251seaux/RTL8139.md" @@ -0,0 +1,5 @@ +# RTL8139 + +# Référence + +- [RTL8139D Datasheet](http://realtek.info/pdf/rtl8139d.pdf) \ No newline at end of file diff --git a/src/drivers/communication-serie/UART8250.md b/src/drivers/communication-serie/UART8250.md new file mode 100644 index 0000000..697d85d --- /dev/null +++ b/src/drivers/communication-serie/UART8250.md @@ -0,0 +1,45 @@ +# UART8250 / UART16750 + +
+ +[![NS 8250B](https://upload.wikimedia.org/wikipedia/commons/c/ce/UART_chip_NS_8250B.jpg)](https://commons.wikimedia.org/wiki/File:UART_chip_NS_8250B.jpg) + +
+ +## Les registres + +| Offset | Nom | Ecriture | Lecture | +| -----------------|-----------------------------------------|-----------|---------| +| 0x0 (DLAB == 0) | Transmit Holding Register (THR) | ✔️ | ❌ | +| 0x0 (DLAB == 0) | Receive Buffer Register (RBR) | ❌ | ✔️ | +| 0x1 (DLAB == 0) | Interrupt Enable Register (IER) | ✔️ | ✔️ | +| 0x2 | Interrupt Identification Register (IIR) | ❌ | ✔️ | +| 0x3 | Line Control Register (LCR) | ✔️ | ✔️ | +| 0x4 | Modem Control Register (MCR) | ✔️ | ✔️ | +| 0x5 | Line Status Register (LSR) | ✔️ | ✔️ | +| 0x6 | Modem Status Register (MSR) | ✔️ | ✔️ | +| 0x7 | Scratch Register (SCR) | ✔️ | ✔️ | +| 0x0 (DLAB == 1) | Divisor Latch LSB (DLL) | ✔️ | ✔️ | +| 0x1 (DLAB == 1) | Divisor Latch MSB (DLH) | ✔️ | ✔️ | + +### Transmit Holding Register (THR) + +Tout ce qui sera ecrit sur ce registre sera transmis en liaison série. + +### Receive Buffer Register (RBR) + + + +## Interrupt Enable Register (IER) + +| 7-4 | 3 | 2 | 1 | 0 | +|----------|--------------|----------------------|-----------|-------------------------| +| reserved | MODEM Status | Receiver Line Status | THR Empty | Received Data Available | + +## Interrupt Identification Register (IIR) + + + +## Références + +- [Datasheet](https://web.archive.org/web/20160503070506/http://archive.pcjs.org/pubs/pc/datasheets/8250A-UART.pdf) \ No newline at end of file From 24b0d5b3ecf15b163c74542b8bd908007badd9ce Mon Sep 17 00:00:00 2001 From: d0p1 Date: Tue, 31 May 2022 12:50:49 +0200 Subject: [PATCH 2/5] =?UTF-8?q?drivers=20->=20p=C3=A9riph=C3=A9riques?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/SUMMARY.md | 8 ++++---- .../cartes-r\303\251seaux/E1000.md" | 0 .../cartes-r\303\251seaux/RTL8139.md" | 0 .../communication-serie/UART8250.md" | 0 4 files changed, 4 insertions(+), 4 deletions(-) rename "src/drivers/cartes-r\303\251seaux/E1000.md" => "src/p\303\251riph\303\251riques/cartes-r\303\251seaux/E1000.md" (100%) rename "src/drivers/cartes-r\303\251seaux/RTL8139.md" => "src/p\303\251riph\303\251riques/cartes-r\303\251seaux/RTL8139.md" (100%) rename src/drivers/communication-serie/UART8250.md => "src/p\303\251riph\303\251riques/communication-serie/UART8250.md" (100%) diff --git a/src/SUMMARY.md b/src/SUMMARY.md index d667360..67c8b98 100644 --- a/src/SUMMARY.md +++ b/src/SUMMARY.md @@ -32,9 +32,9 @@ - [Multitâche](x86_64/premiers-pas/06-multitache.md) - [Tache utilisateur](x86_64/premiers-pas/06-tache-utilisateur.md) - [Epilogue](x86_64/premiers-pas/06-epilogue.md) -- [drivers]() +- [périphériques]() - [cartes réseaux]() - - [e1000](drivers/cartes-réseaux/E1000.md) - - [RTL8139](drivers/cartes-réseaux/RTL8139.md) + - [e1000](périphériques/cartes-réseaux/E1000.md) + - [RTL8139](périphériques/cartes-réseaux/RTL8139.md) - [communication série]() - - [UART8250](drivers/communication-serie/UART8250.md) + - [UART8250](périphériques/communication-serie/UART8250.md) diff --git "a/src/drivers/cartes-r\303\251seaux/E1000.md" "b/src/p\303\251riph\303\251riques/cartes-r\303\251seaux/E1000.md" similarity index 100% rename from "src/drivers/cartes-r\303\251seaux/E1000.md" rename to "src/p\303\251riph\303\251riques/cartes-r\303\251seaux/E1000.md" diff --git "a/src/drivers/cartes-r\303\251seaux/RTL8139.md" "b/src/p\303\251riph\303\251riques/cartes-r\303\251seaux/RTL8139.md" similarity index 100% rename from "src/drivers/cartes-r\303\251seaux/RTL8139.md" rename to "src/p\303\251riph\303\251riques/cartes-r\303\251seaux/RTL8139.md" diff --git a/src/drivers/communication-serie/UART8250.md "b/src/p\303\251riph\303\251riques/communication-serie/UART8250.md" similarity index 100% rename from src/drivers/communication-serie/UART8250.md rename to "src/p\303\251riph\303\251riques/communication-serie/UART8250.md" From cc35d484cb21136ad56492a49a59c502973f7d57 Mon Sep 17 00:00:00 2001 From: d0p1 Date: Tue, 31 May 2022 13:41:57 +0200 Subject: [PATCH 3/5] wip uart8250 --- .../communication-serie/UART8250.md" | 69 +++++++++++++++++-- 1 file changed, 63 insertions(+), 6 deletions(-) diff --git "a/src/p\303\251riph\303\251riques/communication-serie/UART8250.md" "b/src/p\303\251riph\303\251riques/communication-serie/UART8250.md" index 697d85d..ad1980c 100644 --- "a/src/p\303\251riph\303\251riques/communication-serie/UART8250.md" +++ "b/src/p\303\251riph\303\251riques/communication-serie/UART8250.md" @@ -24,21 +24,78 @@ ### Transmit Holding Register (THR) -Tout ce qui sera ecrit sur ce registre sera transmis en liaison série. +Tout ce qui sera ecrit sur ce registre sera transmis par l'UART. ### Receive Buffer Register (RBR) +Tout ce qui est reçu par l'UART sur la laison série sera accessible sur ce registre. +### Interrupt Enable Register (IER) -## Interrupt Enable Register (IER) +| 7-4 | 3 | 2 | 1 | 0 | +|---------|--------------|----------------------|-----------|-------------------------| +| reservé | MODEM Status | Receiver Line Status | THR Empty | Received Data Available | -| 7-4 | 3 | 2 | 1 | 0 | -|----------|--------------|----------------------|-----------|-------------------------| -| reserved | MODEM Status | Receiver Line Status | THR Empty | Received Data Available | +- **__Received Data Available__**: Si le bit est à 1 alors une interruption sera généré à la réception d'un charactère. +- **__THR Empty__**: si le bit est à 1 alors une interruption sera généré quand il sera possible d'écrire à nouveau dans le registre **THR** -## Interrupt Identification Register (IIR) +### Interrupt Identification Register (IIR) +### Line Control Register (LCR) +### Modem Control Register (MCR) + +### Line Status Register (LSR) + +### Modem Status Register (MSR) + +### Scratch Register (SCR) + +### Divisor Latch LSB (DLL) & Divisor Latch MSB (DLH) + +| Baud Rate | 1.8432Mhz | 3.072 MHz | 8.0 MHz | +|-----------|-----------|-----------|---------| +| 50 | 2304 | 3840 | 10000 | +| 75 | 1536 | 2560 | 6667 | +| 110 | 1047 | 1745 | 4545 | +| 134.5 | 857 | 1428 | 3717 | +| 150 | 768 | 1280 | 3333 | +| 300 | 384 | 640 | 1667 | +| 600 | 192 | 320 | 833 | +| 1200 | 96 | 160 | 417 | +| 1800 | 64 | 107 | 277 | +| 2000 | 58 | 96 | 250 | +| 2400 | 48 | 80 | 208 | +| 3600 | 32 | 53 | 139 | +| 4800 | 24 | 40 | 104 | +| 7200 | 16 | 27 | 69 | +| 9600 | 12 | 20 | 52 | +| 19200 | 6 | 10 | 26 | +| 38400 | 3 | 5 | 13 | +| 56000 | 2 | - | 9 | +| 128000 | - | - | 4 | + +Pour l'IBM PC la clock est de 1.8432Mhz + +## Exemple (en pseudo C) + +Partons du principe que nous avont `uart8250_write` permetant d'ecrire une valeur dans un registre et `uart8250_read` permetant de lire la valeur d'un registre. + +### Initialisation de l'UART + +```c + /* on desactive les interuptions en metant IER à zero */ + uart8250_write(IER, 0x0); + + /* DLAB à 1 */ + uart8250_write(LCR, (1 << 7)); + + /* 9600 baud donc un diviseur de 12 (voir le tableau) */ + uart8250_write(DLH, 0x0); + uart8250_write(DLL, 0xC); + + /* TODO */ +``` ## Références From 5b51f422f8de0a8b6b166276f8e62b8f299d6b9b Mon Sep 17 00:00:00 2001 From: d0p1 Date: Tue, 31 May 2022 14:30:59 +0200 Subject: [PATCH 4/5] fifo register (not available on UART8250) --- .../communication-serie/UART8250.md" | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git "a/src/p\303\251riph\303\251riques/communication-serie/UART8250.md" "b/src/p\303\251riph\303\251riques/communication-serie/UART8250.md" index ad1980c..73d6e91 100644 --- "a/src/p\303\251riph\303\251riques/communication-serie/UART8250.md" +++ "b/src/p\303\251riph\303\251riques/communication-serie/UART8250.md" @@ -1,4 +1,4 @@ -# UART8250 / UART16750 +# UART8250 / UART16550
@@ -13,6 +13,7 @@ | 0x0 (DLAB == 0) | Transmit Holding Register (THR) | ✔️ | ❌ | | 0x0 (DLAB == 0) | Receive Buffer Register (RBR) | ❌ | ✔️ | | 0x1 (DLAB == 0) | Interrupt Enable Register (IER) | ✔️ | ✔️ | +| 0x2 (⚠️UART16550 seulement) | FIFO Control Register (FCR) | ✔️ | ❌ | | 0x2 | Interrupt Identification Register (IIR) | ❌ | ✔️ | | 0x3 | Line Control Register (LCR) | ✔️ | ✔️ | | 0x4 | Modem Control Register (MCR) | ✔️ | ✔️ | @@ -99,4 +100,5 @@ Partons du principe que nous avont `uart8250_write` permetant d'ecrire une valeu ## Références -- [Datasheet](https://web.archive.org/web/20160503070506/http://archive.pcjs.org/pubs/pc/datasheets/8250A-UART.pdf) \ No newline at end of file +- [8250A UART datasheet](https://web.archive.org/web/20160503070506/http://archive.pcjs.org/pubs/pc/datasheets/8250A-UART.pdf) +- [PC16550D UART datasheet](https://web.archive.org/web/20180826215135/http://www.ti.com/lit/ds/symlink/pc16550d.pdf) \ No newline at end of file From ddeeb8d6922e777bf4bad726119be702814580a1 Mon Sep 17 00:00:00 2001 From: d0p1 Date: Mon, 7 Nov 2022 10:36:43 +0100 Subject: [PATCH 5/5] uart8250: add IIR and LCR --- .../communication-serie/UART8250.md" | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git "a/src/p\303\251riph\303\251riques/communication-serie/UART8250.md" "b/src/p\303\251riph\303\251riques/communication-serie/UART8250.md" index 73d6e91..4b555c6 100644 --- "a/src/p\303\251riph\303\251riques/communication-serie/UART8250.md" +++ "b/src/p\303\251riph\303\251riques/communication-serie/UART8250.md" @@ -13,7 +13,7 @@ | 0x0 (DLAB == 0) | Transmit Holding Register (THR) | ✔️ | ❌ | | 0x0 (DLAB == 0) | Receive Buffer Register (RBR) | ❌ | ✔️ | | 0x1 (DLAB == 0) | Interrupt Enable Register (IER) | ✔️ | ✔️ | -| 0x2 (⚠️UART16550 seulement) | FIFO Control Register (FCR) | ✔️ | ❌ | +| 0x2 (⚠️UART16550 seulement) | FIFO Control Register (FCR) | ✔️ | ❌ | | 0x2 | Interrupt Identification Register (IIR) | ❌ | ✔️ | | 0x3 | Line Control Register (LCR) | ✔️ | ✔️ | | 0x4 | Modem Control Register (MCR) | ✔️ | ✔️ | @@ -42,8 +42,16 @@ Tout ce qui est reçu par l'UART sur la laison série sera accessible sur ce reg ### Interrupt Identification Register (IIR) +| 7-3 | 2-1 | 0 | +|---------|--------------|-------------------| +| reservé | Interrupt ID | Interrupt pending | + ### Line Control Register (LCR) +| 7 | 6 | 5 | 4 | 3 | 2 | 1-0 | +|------|-----------|--------------|--------------------|---------------|-----------|-----------------| +| DLAB | Set Break | Stick parity | Even Parity Select | Parity enable | Stop Bits | Word length | + ### Modem Control Register (MCR) ### Line Status Register (LSR)