From 5d1c20fc5f5e327489930eab205e7d3424b72474 Mon Sep 17 00:00:00 2001 From: Concode0 Date: Mon, 8 Dec 2025 12:47:05 +0900 Subject: [PATCH] fix(bmi270): correct interrupt pin configuration logic --- components/bmi270/include/bmi270.hpp | 29 +++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/components/bmi270/include/bmi270.hpp b/components/bmi270/include/bmi270.hpp index 675991247..6ce6255a3 100644 --- a/components/bmi270/include/bmi270.hpp +++ b/components/bmi270/include/bmi270.hpp @@ -433,17 +433,28 @@ class Bmi270 : public espp::BasePeripheral(config.active_level) << 1) | static_cast(config.output_type); - - if (config.pin == InterruptPin::INT1) { - write_u8_to_register(static_cast(Register::INT1_IO_CTRL), int_io_ctrl, ec); - } else { - write_u8_to_register(static_cast(Register::INT2_IO_CTRL), int_io_ctrl, ec); + // Configure interrupt pin electrical behavior (Output Enable | Output Type | Active Level) + // Bit 3 is Output Enable, which must be set to 1 for the pin to drive the line. + uint8_t int_io_ctrl = (1 << 3) | + (static_cast(config.output_type) << 2) | + (static_cast(config.active_level) << 1); + + auto pin_reg = (config.pin == InterruptPin::INT1) ? Register::INT1_IO_CTRL : Register::INT2_IO_CTRL; + write_u8_to_register(static_cast(pin_reg), int_io_ctrl, ec); + if (ec) return false; + + // Map interrupt features to pins + uint8_t int_map_data = 0; + if (config.enable_data_ready) { + // Map Data Ready interrupt to the selected pin + // Bit 2: Data Ready -> INT1, Bit 6: Data Ready -> INT2 + int_map_data |= (config.pin == InterruptPin::INT1) ? (1 << 2) : (1 << 6); } - return !ec; + write_u8_to_register(static_cast(Register::INT_MAP_DATA), int_map_data, ec); + if (ec) return false; + + return true; } protected: