$prsim() is passed a space-padded string from plusarg, needs to be stripped

[fangism]

Consider the following Verilog (used for cosimulation) that takes a file name from a plusarg:

  initial begin
    reg [128:0] prs_obj;
    if (!$value$plusargs("PRSIM_OBJ=%s", prs_obj)) begin
      prs_obj = "Missing required +PRSIM_OBJ= arg.";  // causes fatal error below
    end
    $prsim(prs_obj);
    ...
end

Passing the plusarg +PRSIM_OBJ=foo.haco-c to cosimulation gives:

Error opening object file " foo.haco-c".

(Note the leading space.)
If we used instead:

    string prs_obj;

then it works. However, string is a SystemVerilog type. It would be nice if this worked with plain Verilog. Enabling SystemVerilog string is the workaround.

The correct patch to fix this would be to call strip_spaces() in vpi-prsim.cc in the prsim_file() function.