From d518a2148cd2b27eaaf29cce05baf7afa603fcde Mon Sep 17 00:00:00 2001 From: occheung Date: Wed, 21 May 2025 15:25:21 +0800 Subject: [PATCH] add iob attribute --- migen/build/lattice/icestorm.py | 5 ++++- migen/build/xilinx/vivado.py | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/migen/build/lattice/icestorm.py b/migen/build/lattice/icestorm.py index 1508fb850..100727536 100644 --- a/migen/build/lattice/icestorm.py +++ b/migen/build/lattice/icestorm.py @@ -84,7 +84,10 @@ class LatticeIceStormToolchain: "ars_false_path": None, # user-defined attribute # ice40 does not have a shift register primitive. - "no_shreg_extract": None + "no_shreg_extract": None, + + # ice40 I/O registers must be declared by PIN_TYPE of SB_IO + "iob": None } special_overrides = common.lattice_ice40_special_overrides diff --git a/migen/build/xilinx/vivado.py b/migen/build/xilinx/vivado.py index 709053c4e..618c7f4cb 100644 --- a/migen/build/xilinx/vivado.py +++ b/migen/build/xilinx/vivado.py @@ -75,6 +75,7 @@ class XilinxVivadoToolchain: "keep": ("dont_touch", "true"), "no_retiming": ("dont_touch", "true"), "async_reg": ("async_reg", "true"), + "iob": ("iob", "true"), "mr_ff": ("mr_ff", "true"), # user-defined attribute "ars_ff1": ("ars_ff1", "true"), # user-defined attribute "ars_ff2": ("ars_ff2", "true"), # user-defined attribute