diff --git a/champsim_config.json b/champsim_config.json index fcc4ba8ea6..775c282262 100644 --- a/champsim_config.json +++ b/champsim_config.json @@ -159,7 +159,8 @@ }, "physical_memory": { - "model": "integrated", + "model": "ramulator", + "config": "ramulator.yaml", "frequency": 3200, "channels": 1, "ranks": 2, diff --git a/dram_controller/ramulator/dram_controller.cc b/dram_controller/ramulator/dram_controller.cc index 461cf944a8..f28d2cd941 100644 --- a/dram_controller/ramulator/dram_controller.cc +++ b/dram_controller/ramulator/dram_controller.cc @@ -622,3 +622,4 @@ void MEMORY_CONTROLLER::print_deadlock() { } // LCOV_EXCL_STOP + diff --git a/hammer_test_0_0.hp b/hammer_test_0_0.hp new file mode 100644 index 0000000000..f675cfe132 --- /dev/null +++ b/hammer_test_0_0.hp @@ -0,0 +1 @@ +0 214 diff --git a/hammer_test_0_0.hr b/hammer_test_0_0.hr new file mode 100644 index 0000000000..9fd31fc066 --- /dev/null +++ b/hammer_test_0_0.hr @@ -0,0 +1 @@ +0 296 diff --git a/hammer_test_0_0.hw b/hammer_test_0_0.hw new file mode 100644 index 0000000000..e69de29bb2 diff --git a/hammer_test_0_0.hwb b/hammer_test_0_0.hwb new file mode 100644 index 0000000000..e69de29bb2 diff --git a/hammer_test_0_0.log b/hammer_test_0_0.log new file mode 100644 index 0000000000..41b5ba68eb --- /dev/null +++ b/hammer_test_0_0.log @@ -0,0 +1,157 @@ +ROW-HAMMER STATISTICS +#################################################################################################### +Row Hammers (READ INSTIGATED): 510 + Normal: 296 Prefetch: 214 +Row Hammers (WRITE INSTIGATED): 0 + Normal: 0 Prefetch: 0 Writeback: 0 +Row Hammers (REFRESH INSTIGATED): 0 +Total Row Hammers: 510 +#################################################################################################### +Channels: 1 +Ranks: 1 +Banks: 16 +Rows: 32768 +Columns: 1024 +Address Space Used: 0.0247955% +#################################################################################################### +Refreshes: 0 +Rows Per Refresh: 4 +Refresh Cycles: 0 +#################################################################################################### +Victim Reads: 0 +Victim Writes: 0 +Lost Hammers: 0 + To Refresh: 0 To Access: 0 +#################################################################################################### +Stats by Row + Channel: 0x0 Rank: 0x0 Bank: 0xf Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 8 (2:6:0) Limit: Access Highest Single-Cycle Hammers(2243)/(Normal:Prefetch:Writeback): 8 (2:6:0) Lost Hammers/(Refresh:Access): 8 (0:8) + Channel: 0x0 Rank: 0x0 Bank: 0xf Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 8 (2:6:0) Limit: Access Highest Single-Cycle Hammers(2243)/(Normal:Prefetch:Writeback): 8 (2:6:0) Lost Hammers/(Refresh:Access): 8 (0:8) + Channel: 0x0 Rank: 0x0 Bank: 0x7 Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 7 (1:6:0) Limit: Access Highest Single-Cycle Hammers(2995)/(Normal:Prefetch:Writeback): 7 (1:6:0) Lost Hammers/(Refresh:Access): 7 (0:7) + Channel: 0x0 Rank: 0x0 Bank: 0x5 Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 7 (1:6:0) Limit: Access Highest Single-Cycle Hammers(2694)/(Normal:Prefetch:Writeback): 7 (1:6:0) Lost Hammers/(Refresh:Access): 7 (0:7) + Channel: 0x0 Rank: 0x0 Bank: 0x7 Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 7 (1:6:0) Limit: Access Highest Single-Cycle Hammers(2995)/(Normal:Prefetch:Writeback): 7 (1:6:0) Lost Hammers/(Refresh:Access): 7 (0:7) + Channel: 0x0 Rank: 0x0 Bank: 0x0 Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 7 (5:2:0) Limit: Access Highest Single-Cycle Hammers(2679)/(Normal:Prefetch:Writeback): 7 (5:2:0) Lost Hammers/(Refresh:Access): 7 (0:7) + Channel: 0x0 Rank: 0x0 Bank: 0x0 Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 7 (5:2:0) Limit: Access Highest Single-Cycle Hammers(2679)/(Normal:Prefetch:Writeback): 7 (5:2:0) Lost Hammers/(Refresh:Access): 7 (0:7) + Channel: 0x0 Rank: 0x0 Bank: 0x5 Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 7 (1:6:0) Limit: Access Highest Single-Cycle Hammers(2694)/(Normal:Prefetch:Writeback): 7 (1:6:0) Lost Hammers/(Refresh:Access): 7 (0:7) + Channel: 0x0 Rank: 0x0 Bank: 0x2 Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (1:5:0) Limit: Access Highest Single-Cycle Hammers(3037)/(Normal:Prefetch:Writeback): 6 (1:5:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0x4 Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (2:4:0) Limit: Access Highest Single-Cycle Hammers(2197)/(Normal:Prefetch:Writeback): 6 (2:4:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0xb Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (2:4:0) Limit: Access Highest Single-Cycle Hammers(2982)/(Normal:Prefetch:Writeback): 6 (2:4:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0xb Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (4:2:0) Limit: Access Highest Single-Cycle Hammers(4001)/(Normal:Prefetch:Writeback): 6 (4:2:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0x8 Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (1:5:0) Limit: Access Highest Single-Cycle Hammers(2235)/(Normal:Prefetch:Writeback): 6 (1:5:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0x3 Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (6:0:0) Limit: Access Highest Single-Cycle Hammers(1576)/(Normal:Prefetch:Writeback): 6 (6:0:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0x3 Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (6:0:0) Limit: Access Highest Single-Cycle Hammers(1576)/(Normal:Prefetch:Writeback): 6 (6:0:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0x8 Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (1:5:0) Limit: Access Highest Single-Cycle Hammers(2235)/(Normal:Prefetch:Writeback): 6 (1:5:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0xb Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (4:2:0) Limit: Access Highest Single-Cycle Hammers(4001)/(Normal:Prefetch:Writeback): 6 (4:2:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0x4 Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (2:4:0) Limit: Access Highest Single-Cycle Hammers(2197)/(Normal:Prefetch:Writeback): 6 (2:4:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0x7 Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (5:1:0) Limit: Access Highest Single-Cycle Hammers(2649)/(Normal:Prefetch:Writeback): 6 (5:1:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0x2 Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (1:5:0) Limit: Access Highest Single-Cycle Hammers(3037)/(Normal:Prefetch:Writeback): 6 (1:5:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0x0 Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (2:4:0) Limit: Access Highest Single-Cycle Hammers(2176)/(Normal:Prefetch:Writeback): 6 (2:4:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0x7 Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (5:1:0) Limit: Access Highest Single-Cycle Hammers(2649)/(Normal:Prefetch:Writeback): 6 (5:1:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0xd Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (1:5:0) Limit: Access Highest Single-Cycle Hammers(1869)/(Normal:Prefetch:Writeback): 6 (1:5:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0xd Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (1:5:0) Limit: Access Highest Single-Cycle Hammers(1869)/(Normal:Prefetch:Writeback): 6 (1:5:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0x0 Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (2:4:0) Limit: Access Highest Single-Cycle Hammers(2176)/(Normal:Prefetch:Writeback): 6 (2:4:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0xb Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 6 (2:4:0) Limit: Access Highest Single-Cycle Hammers(2982)/(Normal:Prefetch:Writeback): 6 (2:4:0) Lost Hammers/(Refresh:Access): 6 (0:6) + Channel: 0x0 Rank: 0x0 Bank: 0x0 Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (5:0:0) Limit: Access Highest Single-Cycle Hammers(2751)/(Normal:Prefetch:Writeback): 5 (5:0:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0xd Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (4:1:0) Limit: Access Highest Single-Cycle Hammers(2105)/(Normal:Prefetch:Writeback): 5 (4:1:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0xd Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (4:1:0) Limit: Access Highest Single-Cycle Hammers(2105)/(Normal:Prefetch:Writeback): 5 (4:1:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x7 Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (3:2:0) Limit: Access Highest Single-Cycle Hammers(1656)/(Normal:Prefetch:Writeback): 5 (3:2:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x7 Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (3:2:0) Limit: Access Highest Single-Cycle Hammers(1656)/(Normal:Prefetch:Writeback): 5 (3:2:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x6 Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (1:4:0) Limit: Access Highest Single-Cycle Hammers(2927)/(Normal:Prefetch:Writeback): 5 (1:4:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x0 Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (5:0:0) Limit: Access Highest Single-Cycle Hammers(2751)/(Normal:Prefetch:Writeback): 5 (5:0:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x6 Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (1:4:0) Limit: Access Highest Single-Cycle Hammers(2927)/(Normal:Prefetch:Writeback): 5 (1:4:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x5 Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (5:0:0) Limit: Access Highest Single-Cycle Hammers(1618)/(Normal:Prefetch:Writeback): 5 (5:0:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x5 Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (5:0:0) Limit: Access Highest Single-Cycle Hammers(1618)/(Normal:Prefetch:Writeback): 5 (5:0:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0xe Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (1:4:0) Limit: Access Highest Single-Cycle Hammers(2931)/(Normal:Prefetch:Writeback): 5 (1:4:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0xf Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (5:0:0) Limit: Access Highest Single-Cycle Hammers(2656)/(Normal:Prefetch:Writeback): 5 (5:0:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0xf Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (5:0:0) Limit: Access Highest Single-Cycle Hammers(2656)/(Normal:Prefetch:Writeback): 5 (5:0:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x1 Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (2:3:0) Limit: Access Highest Single-Cycle Hammers(2935)/(Normal:Prefetch:Writeback): 5 (2:3:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x1 Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (2:3:0) Limit: Access Highest Single-Cycle Hammers(2935)/(Normal:Prefetch:Writeback): 5 (2:3:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x2 Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (4:1:0) Limit: Access Highest Single-Cycle Hammers(1826)/(Normal:Prefetch:Writeback): 5 (4:1:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x2 Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (4:1:0) Limit: Access Highest Single-Cycle Hammers(1826)/(Normal:Prefetch:Writeback): 5 (4:1:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x9 Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (0:5:0) Limit: Access Highest Single-Cycle Hammers(2948)/(Normal:Prefetch:Writeback): 5 (0:5:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x9 Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (0:5:0) Limit: Access Highest Single-Cycle Hammers(2948)/(Normal:Prefetch:Writeback): 5 (0:5:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x2 Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (4:1:0) Limit: Access Highest Single-Cycle Hammers(2201)/(Normal:Prefetch:Writeback): 5 (4:1:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x2 Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (4:1:0) Limit: Access Highest Single-Cycle Hammers(2201)/(Normal:Prefetch:Writeback): 5 (4:1:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x8 Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (4:1:0) Limit: Access Highest Single-Cycle Hammers(2690)/(Normal:Prefetch:Writeback): 5 (4:1:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0x8 Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (4:1:0) Limit: Access Highest Single-Cycle Hammers(2690)/(Normal:Prefetch:Writeback): 5 (4:1:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0xe Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 5 (1:4:0) Limit: Access Highest Single-Cycle Hammers(2931)/(Normal:Prefetch:Writeback): 5 (1:4:0) Lost Hammers/(Refresh:Access): 5 (0:5) + Channel: 0x0 Rank: 0x0 Bank: 0xb Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (4:0:0) Limit: Access Highest Single-Cycle Hammers(1648)/(Normal:Prefetch:Writeback): 4 (4:0:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x9 Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (4:0:0) Limit: Access Highest Single-Cycle Hammers(1614)/(Normal:Prefetch:Writeback): 4 (4:0:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x9 Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (4:0:0) Limit: Access Highest Single-Cycle Hammers(1614)/(Normal:Prefetch:Writeback): 4 (4:0:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0xb Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (4:0:0) Limit: Access Highest Single-Cycle Hammers(1648)/(Normal:Prefetch:Writeback): 4 (4:0:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0xa Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (0:4:0) Limit: Access Highest Single-Cycle Hammers(3050)/(Normal:Prefetch:Writeback): 4 (0:4:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0xa Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (0:4:0) Limit: Access Highest Single-Cycle Hammers(3050)/(Normal:Prefetch:Writeback): 4 (0:4:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0xc Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (0:4:0) Limit: Access Highest Single-Cycle Hammers(3033)/(Normal:Prefetch:Writeback): 4 (0:4:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x6 Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (3:1:0) Limit: Access Highest Single-Cycle Hammers(2205)/(Normal:Prefetch:Writeback): 4 (3:1:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x0 Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (3:1:0) Limit: Access Highest Single-Cycle Hammers(1865)/(Normal:Prefetch:Writeback): 4 (3:1:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x0 Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (3:1:0) Limit: Access Highest Single-Cycle Hammers(1865)/(Normal:Prefetch:Writeback): 4 (3:1:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x3 Row: 0x47 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (0:4:0) Limit: Access Highest Single-Cycle Hammers(2969)/(Normal:Prefetch:Writeback): 4 (0:4:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x3 Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (0:4:0) Limit: Access Highest Single-Cycle Hammers(2969)/(Normal:Prefetch:Writeback): 4 (0:4:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x3 Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (3:1:0) Limit: Access Highest Single-Cycle Hammers(2239)/(Normal:Prefetch:Writeback): 4 (3:1:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x3 Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (3:1:0) Limit: Access Highest Single-Cycle Hammers(2239)/(Normal:Prefetch:Writeback): 4 (3:1:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x4 Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (4:0:0) Limit: Access Highest Single-Cycle Hammers(2269)/(Normal:Prefetch:Writeback): 4 (4:0:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x4 Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (4:0:0) Limit: Access Highest Single-Cycle Hammers(2269)/(Normal:Prefetch:Writeback): 4 (4:0:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0xd Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (2:2:0) Limit: Access Highest Single-Cycle Hammers(1622)/(Normal:Prefetch:Writeback): 4 (2:2:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x5 Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (3:1:0) Limit: Access Highest Single-Cycle Hammers(2855)/(Normal:Prefetch:Writeback): 4 (3:1:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x5 Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (3:1:0) Limit: Access Highest Single-Cycle Hammers(2855)/(Normal:Prefetch:Writeback): 4 (3:1:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0xc Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (4:0:0) Limit: Access Highest Single-Cycle Hammers(1652)/(Normal:Prefetch:Writeback): 4 (4:0:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0xc Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (4:0:0) Limit: Access Highest Single-Cycle Hammers(1652)/(Normal:Prefetch:Writeback): 4 (4:0:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0xd Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (2:2:0) Limit: Access Highest Single-Cycle Hammers(1622)/(Normal:Prefetch:Writeback): 4 (2:2:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0xc Row: 0x49 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (0:4:0) Limit: Access Highest Single-Cycle Hammers(3033)/(Normal:Prefetch:Writeback): 4 (0:4:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x6 Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 4 (3:1:0) Limit: Access Highest Single-Cycle Hammers(2205)/(Normal:Prefetch:Writeback): 4 (3:1:0) Lost Hammers/(Refresh:Access): 4 (0:4) + Channel: 0x0 Rank: 0x0 Bank: 0x8 Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (2:1:0) Limit: Access Highest Single-Cycle Hammers(3173)/(Normal:Prefetch:Writeback): 3 (2:1:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0xa Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (2:1:0) Limit: Access Highest Single-Cycle Hammers(5558)/(Normal:Prefetch:Writeback): 3 (2:1:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0xa Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (2:1:0) Limit: Access Highest Single-Cycle Hammers(5558)/(Normal:Prefetch:Writeback): 3 (2:1:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0xf Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (2:1:0) Limit: Access Highest Single-Cycle Hammers(1644)/(Normal:Prefetch:Writeback): 3 (2:1:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0xf Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (2:1:0) Limit: Access Highest Single-Cycle Hammers(1644)/(Normal:Prefetch:Writeback): 3 (2:1:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0xf Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (3:0:0) Limit: Access Highest Single-Cycle Hammers(2914)/(Normal:Prefetch:Writeback): 3 (3:0:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0xf Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (3:0:0) Limit: Access Highest Single-Cycle Hammers(2914)/(Normal:Prefetch:Writeback): 3 (3:0:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0xe Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (1:2:0) Limit: Access Highest Single-Cycle Hammers(3662)/(Normal:Prefetch:Writeback): 3 (1:2:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0xe Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (1:2:0) Limit: Access Highest Single-Cycle Hammers(3662)/(Normal:Prefetch:Writeback): 3 (1:2:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x8 Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (2:1:0) Limit: Access Highest Single-Cycle Hammers(3173)/(Normal:Prefetch:Writeback): 3 (2:1:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x5 Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (3:0:0) Limit: Access Highest Single-Cycle Hammers(2290)/(Normal:Prefetch:Writeback): 3 (3:0:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x5 Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (3:0:0) Limit: Access Highest Single-Cycle Hammers(2290)/(Normal:Prefetch:Writeback): 3 (3:0:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x4 Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (3:0:0) Limit: Access Highest Single-Cycle Hammers(2034)/(Normal:Prefetch:Writeback): 3 (3:0:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x4 Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (3:0:0) Limit: Access Highest Single-Cycle Hammers(2034)/(Normal:Prefetch:Writeback): 3 (3:0:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x3 Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (2:1:0) Limit: Access Highest Single-Cycle Hammers(1906)/(Normal:Prefetch:Writeback): 3 (2:1:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x8 Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (3:0:0) Limit: Access Highest Single-Cycle Hammers(1808)/(Normal:Prefetch:Writeback): 3 (3:0:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x8 Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (3:0:0) Limit: Access Highest Single-Cycle Hammers(1808)/(Normal:Prefetch:Writeback): 3 (3:0:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x9 Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (2:1:0) Limit: Access Highest Single-Cycle Hammers(1914)/(Normal:Prefetch:Writeback): 3 (2:1:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x9 Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (2:1:0) Limit: Access Highest Single-Cycle Hammers(1914)/(Normal:Prefetch:Writeback): 3 (2:1:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x3 Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (2:1:0) Limit: Access Highest Single-Cycle Hammers(1906)/(Normal:Prefetch:Writeback): 3 (2:1:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x1 Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (0:3:0) Limit: Access Highest Single-Cycle Hammers(4582)/(Normal:Prefetch:Writeback): 3 (0:3:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x1 Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 3 (0:3:0) Limit: Access Highest Single-Cycle Hammers(4582)/(Normal:Prefetch:Writeback): 3 (0:3:0) Lost Hammers/(Refresh:Access): 3 (0:3) + Channel: 0x0 Rank: 0x0 Bank: 0x1 Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (1:1:0) Limit: Access Highest Single-Cycle Hammers(4423)/(Normal:Prefetch:Writeback): 2 (1:1:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xd Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(2303)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0x1 Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (1:1:0) Limit: Access Highest Single-Cycle Hammers(4423)/(Normal:Prefetch:Writeback): 2 (1:1:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xe Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(1588)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xe Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(1588)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xe Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (1:1:0) Limit: Access Highest Single-Cycle Hammers(2277)/(Normal:Prefetch:Writeback): 2 (1:1:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xe Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (1:1:0) Limit: Access Highest Single-Cycle Hammers(2277)/(Normal:Prefetch:Writeback): 2 (1:1:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0x4 Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(1821)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0x4 Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(1821)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0x1 Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(1610)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0x1 Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(1610)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0x7 Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(2383)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xa Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(5970)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xa Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(5970)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0x9 Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (0:2:0) Limit: Access Highest Single-Cycle Hammers(4594)/(Normal:Prefetch:Writeback): 2 (0:2:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xb Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(2307)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xb Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(2307)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0x9 Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (0:2:0) Limit: Access Highest Single-Cycle Hammers(4594)/(Normal:Prefetch:Writeback): 2 (0:2:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xc Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(2214)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xc Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(2214)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0x6 Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (1:1:0) Limit: Access Highest Single-Cycle Hammers(4091)/(Normal:Prefetch:Writeback): 2 (1:1:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0x7 Row: 0x3f Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(2383)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0x6 Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(1584)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0x6 Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(1584)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xc Row: 0x57 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (1:1:0) Limit: Access Highest Single-Cycle Hammers(2897)/(Normal:Prefetch:Writeback): 2 (1:1:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xc Row: 0x59 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (1:1:0) Limit: Access Highest Single-Cycle Hammers(2897)/(Normal:Prefetch:Writeback): 2 (1:1:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xd Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (2:0:0) Limit: Access Highest Single-Cycle Hammers(2303)/(Normal:Prefetch:Writeback): 2 (2:0:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0x6 Row: 0x41 Lifetime Hammers/(Normal:Prefetch:Writeback): 2 (1:1:0) Limit: Access Highest Single-Cycle Hammers(4091)/(Normal:Prefetch:Writeback): 2 (1:1:0) Lost Hammers/(Refresh:Access): 2 (0:2) + Channel: 0x0 Rank: 0x0 Bank: 0xf Row: 0x61 Lifetime Hammers/(Normal:Prefetch:Writeback): 1 (0:1:0) Limit: Access Highest Single-Cycle Hammers(7675)/(Normal:Prefetch:Writeback): 1 (0:1:0) Lost Hammers/(Refresh:Access): 1 (0:1) + Channel: 0x0 Rank: 0x0 Bank: 0xf Row: 0x5f Lifetime Hammers/(Normal:Prefetch:Writeback): 1 (0:1:0) Limit: Access Highest Single-Cycle Hammers(7675)/(Normal:Prefetch:Writeback): 1 (0:1:0) Lost Hammers/(Refresh:Access): 1 (0:1) + Channel: 0x0 Rank: 0x0 Bank: 0x2 Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 1 (1:0:0) Limit: Access Highest Single-Cycle Hammers(1898)/(Normal:Prefetch:Writeback): 1 (1:0:0) Lost Hammers/(Refresh:Access): 1 (0:1) + Channel: 0x0 Rank: 0x0 Bank: 0x2 Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 1 (1:0:0) Limit: Access Highest Single-Cycle Hammers(1898)/(Normal:Prefetch:Writeback): 1 (1:0:0) Lost Hammers/(Refresh:Access): 1 (0:1) + Channel: 0x0 Rank: 0x0 Bank: 0xa Row: 0x51 Lifetime Hammers/(Normal:Prefetch:Writeback): 1 (1:0:0) Limit: Access Highest Single-Cycle Hammers(1580)/(Normal:Prefetch:Writeback): 1 (1:0:0) Lost Hammers/(Refresh:Access): 1 (0:1) + Channel: 0x0 Rank: 0x0 Bank: 0xa Row: 0x4f Lifetime Hammers/(Normal:Prefetch:Writeback): 1 (1:0:0) Limit: Access Highest Single-Cycle Hammers(1580)/(Normal:Prefetch:Writeback): 1 (1:0:0) Lost Hammers/(Refresh:Access): 1 (0:1) +#################################################################################################### diff --git a/inc/vmem.h b/inc/vmem.h index c3aa77d69e..e27c1ebe9a 100644 --- a/inc/vmem.h +++ b/inc/vmem.h @@ -123,4 +123,4 @@ class VirtualMemory std::pair get_pte_pa(uint32_t cpu_num, champsim::page_number vaddr, std::size_t level); }; -#endif +#endif \ No newline at end of file diff --git a/power_consumption_rates_PBPI.txt b/power_consumption_rates_PBPI.txt new file mode 100644 index 0000000000..dc9a1994e7 --- /dev/null +++ b/power_consumption_rates_PBPI.txt @@ -0,0 +1,311 @@ +Rate for instruction 0: 83.3333% +Rate for instruction 1: 50% +Rate for instruction 2: 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a/power_consumption_rates_rasl.txt b/power_consumption_rates_rasl.txt new file mode 100644 index 0000000000..8da6378d89 --- /dev/null +++ b/power_consumption_rates_rasl.txt @@ -0,0 +1,4 @@ +Rate for instruction 0: 34.6154% +Rate for instruction 1: 25% +Rate for instruction 2: 19.2308% +Rate for instruction 3: 19.2308% diff --git a/ramulator.yaml b/ramulator.yaml index 1ee4371410..a395471ac6 100755 --- a/ramulator.yaml +++ b/ramulator.yaml @@ -27,7 +27,14 @@ MemorySystem: impl: FRFCFS RefreshManager: impl: AllBank - plugins: + plugins: + - ControllerPlugin: {impl: ChampSimStats} + - ControllerPlugin: {impl: HammerCounter, + output_file: hammer_test, + cycles_per_heartbeat: 1000000, + histogram_period: 100e-6, + refresh_period: 64e-3, + target_cycle: 0} AddrMapper: - impl: RoRaCoBaBgCh + impl: RASL diff --git a/ramulator2ext/src/addr_mapper/impl/champsim_mappers.cpp b/ramulator2ext/src/addr_mapper/impl/champsim_mappers.cpp index baeb191ced..bf614a945c 100644 --- a/ramulator2ext/src/addr_mapper/impl/champsim_mappers.cpp +++ b/ramulator2ext/src/addr_mapper/impl/champsim_mappers.cpp @@ -1,4 +1,6 @@ #include +#include +#include #include "base/base.h" #include "dram/dram.h" @@ -54,17 +56,26 @@ namespace Ramulator{ Addr_t addr = req.addr >> m_tx_offset; //channel req.addr_vec[m_dram->m_levels("channel")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("channel")]); + std::cout << "The channel : " << req.addr_vec[m_dram->m_levels("channel")] << std::endl; //bank group + //std::cout << "The bankgroup before: " << req.addr_vec[m_dram->m_levels("bankgroup")] << std::endl; if(m_dram->m_organization.count.size() > 5) req.addr_vec[m_dram->m_levels("bankgroup")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("bankgroup")]); + std::cout << "The bankgroup: " << req.addr_vec[m_dram->m_levels("bankgroup")] << std::endl; + //bank req.addr_vec[m_dram->m_levels("bank")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("bank")]); + std::cout << "The bank: " << req.addr_vec[m_dram->m_levels("bank")] << std::endl; //column req.addr_vec[m_dram->m_levels("column")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("column")]); + std::cout << "The column: " << req.addr_vec[m_dram->m_levels("column")] << std::endl; //rank req.addr_vec[m_dram->m_levels("rank")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("rank")]); + std::cout << "The rank: " << req.addr_vec[m_dram->m_levels("rank")] << std::endl; //row req.addr_vec[m_dram->m_levels("row")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("row")]); + std::cout << "The row: " << req.addr_vec[m_dram->m_levels("row")] << std::endl; + std::cout << std::endl; } }; @@ -82,6 +93,12 @@ namespace Ramulator{ int m_col_bits_idx = -1; int m_row_bits_idx = -1; + // store the previous address vector + std::vector m_prev_addr_vec; + + // make a vector to store power consumption rates + std::vector power_consumption_rates; + void init() override { }; void setup(IFrontEnd* frontend, IMemorySystem* memory_system) { m_dram = memory_system->get_ifce(); @@ -92,6 +109,7 @@ namespace Ramulator{ m_addr_bits.resize(m_num_levels); for (size_t level = 0; level < m_addr_bits.size(); level++) { m_addr_bits[level] = calc_log2(count[level]); + //std::cout << "This is the number of bits in level [" << level << "]: " << m_addr_bits[level] << std::endl; } // Last (Column) address have the granularity of the prefetch size @@ -109,42 +127,318 @@ namespace Ramulator{ // Assume column is always the last level m_col_bits_idx = m_num_levels - 1; - } + //tot power + std::vector tot_power; + + // initialize the previous address vector with the same size + m_prev_addr_vec.assign(m_num_levels, 0); + } + + // initialize bit counter + int bit_counter = 0; + int num_bits_pc = 0; void apply(Request& req) override { req.addr_vec.resize(m_num_levels, -1); + // initialize xor result to hold power consumption for each level + Addr_t xor_result_power = 0; + + // initialize power_cons to hold the bit changes for each level + std::vector power_vector; + + //retrieve the number of bits for the level currently in + int num_bits = m_addr_bits.size(); + Addr_t col1_bits = 12 - m_tx_offset - m_addr_bits[m_dram->m_levels("bankgroup")] - m_addr_bits[m_dram->m_levels("bank")] - m_addr_bits[m_dram->m_levels("channel")]; + //std::cout << "The number of col1_bits [" << col1_bits << "]." << std::endl; Addr_t col2_bits = m_addr_bits[m_dram->m_levels("column")] - col1_bits; + //std::cout << "The number of col2_bits [" << col2_bits << "]." << std::endl; Addr_t addr = req.addr >> m_tx_offset; + //std::cout << "The address is: " << addr << std::endl; Addr_t xor_bits = req.addr >> 17; + //std::cout << "The xor_bits being used: " << xor_bits << std::endl; //channel req.addr_vec[m_dram->m_levels("channel")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("channel")]); + //std::cout << "The channel address is: " << req.addr_vec[m_dram->m_levels("channel")] << std::endl; //col 1 req.addr_vec[m_dram->m_levels("column")] = slice_lower_bits(addr, col1_bits); + //std::cout << "The column address is: " << req.addr_vec[m_dram->m_levels("column")] << std::endl; //bank group and bank if(m_dram->m_organization.count.size() > 5) { int bankgroup_val = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("bankgroup")]) ^ xor_bits; req.addr_vec[m_dram->m_levels("bankgroup")] = slice_lower_bits(bankgroup_val, m_addr_bits[m_dram->m_levels("bankgroup")]); + //std::cout << "After count > 5, bankgroup size is: " << req.addr_vec[m_dram->m_levels("bankgroup")] << std::endl; int bank_val = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("bank")]) ^ (xor_bits >> m_addr_bits[m_dram->m_levels("bankgroup")]); req.addr_vec[m_dram->m_levels("bank")] = slice_lower_bits(bank_val,m_addr_bits[m_dram->m_levels("bank")]); + //std::cout << "After count > 5, bank size is: " << req.addr_vec[m_dram->m_levels("bank")] << std::endl; } else { int bank_val = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("bank")]) ^ xor_bits; req.addr_vec[m_dram->m_levels("bank")] = slice_lower_bits(bank_val, m_addr_bits[m_dram->m_levels("bank")]); + //std::cout << "The bankgroup size is: " << req.addr_vec[m_dram->m_levels("bank")] << std::endl; } //col 2 req.addr_vec[m_dram->m_levels("column")] += slice_lower_bits(addr, col2_bits) << col1_bits; + //std::cout << "The column bits is: " << req.addr_vec[m_dram->m_levels("column")] << std::endl; //rank req.addr_vec[m_dram->m_levels("rank")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("rank")]); + //std::cout << "The rank bits is: " << req.addr_vec[m_dram->m_levels("rank")] << std::endl; //row req.addr_vec[m_dram->m_levels("row")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("row")]); + //std::cout << "The row address is: " << req.addr_vec[m_dram->m_levels("row")] << std::endl; + //std::cout << std::endl; + + // calculate bit changes for power consumption + for (size_t i = 0; i < m_num_levels; ++i) { + // uncomment for analysis [NOT FOR LONG RUNS] + //std::cout << "The current address for level [" << i << "]: " << req.addr_vec[i] << std::endl; + //std::cout << "The prev address for level [" << i << "]: " << m_prev_addr_vec[i] << std::endl; + xor_result_power |= (req.addr_vec[i] ^ m_prev_addr_vec[i]); + //std::cout << "The xor result: " << xor_result_power << std::endl; + } + //std::cout << std::endl; + // store xor_result into power_vector + power_vector.push_back(xor_result_power); + + + // power consumption ----------------------------------------------------------------------------- + + // convert to binary + std::bitset<64> binary_representation(xor_result_power); + + // count the number of 1s in the xor result + int bit_transitions = std::bitset<64>(xor_result_power).count(); + + //update the total bit counter for transistions and total bits + bit_counter += bit_transitions; + num_bits_pc += m_addr_bits.size(); + + // Cast to float for proper decimal division + double power_consumption_rate = (static_cast(bit_counter) / static_cast(num_bits_pc)) * 100; + + // uncomment this for analysis [NOT FOR LONGER RUNS] + //std::cout << "The power consumption rate: " << std::dec << power_consumption_rate << "%" << std::endl << std::endl; + power_consumption_rates.push_back(power_consumption_rate); + + m_prev_addr_vec.assign(req.addr_vec.begin(), req.addr_vec.end()); + + writePowerConsumptionRatesToFile("power_consumption_rates_PBPI.txt"); + } + + void writePowerConsumptionRatesToFile(const std::string& filename) const { + std::ofstream outFile(filename); // Open the file for writing + + if (outFile.is_open()) { + for (size_t i = 0; i < power_consumption_rates.size(); ++i) { + outFile << "Cumulative Power Consumption: " << power_consumption_rates[i] << "%" << std::endl; + } + outFile.close(); // Close the file + } else { + std::cerr << "Unable to open file " << filename << std::endl; + } + } + + }; + /****************************************This is where I will apply my method RASL - Yanez Saucedo*******************************************/ + class RASL final : public IAddrMapper, public Implementation { + RAMULATOR_REGISTER_IMPLEMENTATION(IAddrMapper, RASL, "RASL", "Applies a RASL Mapping to the address. Yanez's Scheme."); + // We will try to increase randomization without using too much power + + public: + IDRAM* m_dram = nullptr; + + int m_num_levels = -1; // How many levels in the hierarchy? + std::vector m_addr_bits; // How many address bits for each level in the hierarchy? + + Addr_t m_tx_offset = -1; + + int m_col_bits_idx = -1; + int m_row_bits_idx = -1; + + // store the previous address vector + std::vector m_prev_addr_vec; + + // make a vector to store power consumption rates + std::vector power_consumption_rates; + + void init() override { }; + void setup(IFrontEnd* frontend, IMemorySystem* memory_system) { + m_dram = memory_system->get_ifce(); + + // Populate m_addr_bits vector with the number of address bits for each level in the hierachy + const auto& count = m_dram->m_organization.count; + + // count the num of levels in our hierarchy + m_num_levels = count.size(); + //std::cout << "The number of levels in our hierarchy: " << m_num_levels << std::endl; + + m_addr_bits.resize(m_num_levels); + for (size_t level = 0; level < m_addr_bits.size(); level++) { + m_addr_bits[level] = calc_log2(count[level]); + //std::cout << "This is the number of bits in [" << level << "]: " << m_addr_bits[level] << std::endl; + } + + // Last (Column) address have the granularity of the prefetch size + m_addr_bits[m_num_levels - 1] -= calc_log2(m_dram->m_internal_prefetch_size); + + int tx_bytes = m_dram->m_internal_prefetch_size * m_dram->m_channel_width / 8; + m_tx_offset = calc_log2(tx_bytes); + + // Determine where are the row and col bits + try { + m_row_bits_idx = m_dram->m_levels("row"); + } catch (const std::out_of_range& r) { + throw std::runtime_error(fmt::format("Organization \"row\" not found in the spec, cannot use linear mapping!")); + } + + // Assume column is always the last level + m_col_bits_idx = m_num_levels - 1; + + //tot power + std::vector tot_power; + + // initialize the previous address vector with the same size + m_prev_addr_vec.assign(m_num_levels, 0); } + + // initialize bit counter + int bit_counter = 0; + int num_bits_pc = 0; + void apply(Request& req) override { + // initialize addr_vec and resize to match the number of levels in the DRAM hierarchy + req.addr_vec.resize(m_num_levels, -1); + + //shift the original address to the right by offset bits. + Addr_t addr = req.addr >> m_tx_offset; + + //channel + req.addr_vec[m_dram->m_levels("channel")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("channel")]); + //std::cout << "This is the current address of the channel: 0x" << std::hex << req.addr_vec[m_dram->m_levels("channel")] << std::endl; + + //bank group + if(m_dram->m_organization.count.size() > 5) + req.addr_vec[m_dram->m_levels("bankgroup")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("bankgroup")]); + //std::cout << "This is the current address of the bankgroup: 0x" << std::hex << req.addr_vec[m_dram->m_levels("bankgroup")] << std::endl; + + //bank + req.addr_vec[m_dram->m_levels("bank")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("bank")]); + //std::cout << "This is the current address of the bank: 0x" << std::hex << req.addr_vec[m_dram->m_levels("bank")] << std::endl; + + //column + req.addr_vec[m_dram->m_levels("column")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("column")]); + //std::cout << "This is the current address of the column: 0x" << std::hex << req.addr_vec[m_dram->m_levels("column")] << std::endl; + + //rank + req.addr_vec[m_dram->m_levels("rank")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("rank")]); + //std::cout << "This is the current address of the rank: 0x" << std::hex << req.addr_vec[m_dram->m_levels("rank")] << std::endl; + + //row + req.addr_vec[m_dram->m_levels("row")] = slice_lower_bits(addr, m_addr_bits[m_dram->m_levels("row")]); + //std::cout << "This is the current address of the row: 0x" << std::hex << req.addr_vec[m_dram->m_levels("row")] << std::endl; + + //std::cout << std::endl; + + // initialize xor result to hold power consumption for each level + Addr_t xor_result_power = 0; + + // initialize power_cons to hold the bit changes for each level + std::vector power_vector; + + // Generate random address bits for each level (iterate each level) + for(size_t level = 0; level < m_num_levels; level++){ + + //retrieve the number of bits for the level currently in + int num_bits = m_addr_bits[level]; + + //initialize rasl_addr to hold the randomized address bits for current level + Addr_t rasl_addr = 0; + + // loop each bit of the address level currently in to extract + for(int bit = 0;bit < num_bits; bit++){ + //extract the bit at 'bit position, then shift addr right by that 'bit' + // bitwise 1 is to isolate the single bit at that position + Addr_t extracted_bit = (req.addr_vec[level] >> bit) & 1; + //place the extracted bit in a new, shuffled position + //add 3 bits to the current bit position and check if new position is within available bits for current level + int new_position = (bit + 3) % num_bits; + //place the extracted bit in rasl_addr. Shift the extracted bit left by new_position and bitwise OR with + //rasl_addr to combine with previous bits + rasl_addr |= (extracted_bit << new_position); + } + // power consumption result for each level + // uncomment this for analysis [NOT FOR LONGER RUNS] + //std::cout << "This is the previous address for level [" << level << "] : " << m_prev_addr_vec[level] << std::endl; + //std::cout << "This is the current address for level [" << level << "] : " << rasl_addr << std::endl; + xor_result_power = m_prev_addr_vec[level] ^ rasl_addr; + //std::cout << "This is the xor result of level [" << level << "] : " << xor_result_power << std::endl; + //std::cout << std::endl; + + // store xor_result into power_vector + power_vector.push_back(xor_result_power); + + //store the result of RASL to the corresponding level + req.addr_vec[level] = rasl_addr; + + //prepare 'addr' for the next level by shifting out the bits we've just proccessed + addr >> num_bits; + + // update m_prev_addr_vec with current RASL for next comparison + m_prev_addr_vec[level] = req.addr_vec[level]; + + // power consumption ----------------------------------------------------------------------------- + int bit_one_counter = 0; + + // convert to binary + std::bitset<64> binary_representation(xor_result_power); + + // check if binary representation is correct + std::string binary_str = binary_representation.to_string().substr(64-num_bits); + + // count the total number of 1 bits + for (char bit : binary_str){ + if (bit == '1'){ + bit_one_counter += 1; + } + } + + bit_counter = bit_one_counter + bit_counter; + num_bits_pc = num_bits + num_bits_pc; + + } + // Cast to float for proper decimal division + double power_consumption_rate = (static_cast(bit_counter) / static_cast(num_bits_pc)) * 100; + + // uncomment this for analysis [NOT FOR LONGER RUNS] + //std::cout << "The power consumption rate: " << std::dec << power_consumption_rate << "%" << std::endl << std::endl; + power_consumption_rates.push_back(power_consumption_rate); + + // using this when not using the text file + for (size_t p = 0; p < power_consumption_rates.size(); ++p) + { + std::cout << "power consumption = " << power_consumption_rates[p] << "%" << std::endl; + } + + //writePowerConsumptionRatesToFile("power_consumption_rates_rasl.txt"); + } + + void writePowerConsumptionRatesToFile(const std::string& filename) const { + std::ofstream outFile(filename); // Open the file for writing + + if (outFile.is_open()) { + for (size_t i = 0; i < power_consumption_rates.size(); ++i) { + outFile << "Cumulative Power Consumption: " << power_consumption_rates[i] << "%" << std::endl; + } + outFile.close(); // Close the file + } else { + std::cerr << "Unable to open file " << filename << std::endl; + } + } }; } \ No newline at end of file diff --git a/src/vmem.cc b/src/vmem.cc index 48f7748f35..5532848dcb 100644 --- a/src/vmem.cc +++ b/src/vmem.cc @@ -159,4 +159,4 @@ std::pair VirtualMemory::g } return {paddr, penalty}; -} \ No newline at end of file +}