From 655927b5a3983d94839a23e7baca3eb8abe5551a Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Wed, 26 Oct 2022 21:54:24 +0000 Subject: [PATCH 1/8] Remove GitHub workflows Signed-off-by: Hoa Nguyen --- .github/workflows/RISCV-build.yml | 24 ------------------------ 1 file changed, 24 deletions(-) delete mode 100644 .github/workflows/RISCV-build.yml diff --git a/.github/workflows/RISCV-build.yml b/.github/workflows/RISCV-build.yml deleted file mode 100644 index de0a3f0171..0000000000 --- a/.github/workflows/RISCV-build.yml +++ /dev/null @@ -1,24 +0,0 @@ -name: RISCV/gem5.opt build CI - -on: - push: - branches: [ "rvv-cpu" ] - pull_request: - branches: [ "rvv-cpu" ] - -jobs: - build: - runs-on: self-hosted - - steps: - - name: Install dependencies - run: | - apt-get update - apt-get install -y build-essential git-core m4 scons zlib1g zlib1g-dev libprotobuf-dev protobuf-compiler libprotoc-dev libgoogle-perftools-dev swig python-dev python - apt-get clean - - - uses: actions/checkout@v3 - - - name: RISCV/gem5.opt build - run: | - /usr/bin/env python3 $(which scons) build/RISCV/gem5.opt -j32 From 55c789e56132cbd6897f96a4c0063e8b41f56f42 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Wed, 9 Nov 2022 21:32:57 +0000 Subject: [PATCH 2/8] arch-riscv: Make vlen and elen parameters Change-Id: I741aed8b982adab58523564f28aedcc0f970eaa3 Signed-off-by: Hoa Nguyen --- src/arch/riscv/RiscvISA.py | 12 ++++++++++++ src/arch/riscv/isa.cc | 11 ++++++++++- src/arch/riscv/isa.hh | 7 +++++++ src/arch/riscv/regs/vector.hh | 1 + 4 files changed, 30 insertions(+), 1 deletion(-) diff --git a/src/arch/riscv/RiscvISA.py b/src/arch/riscv/RiscvISA.py index a54dcfd2a1..61b5f120dd 100644 --- a/src/arch/riscv/RiscvISA.py +++ b/src/arch/riscv/RiscvISA.py @@ -39,8 +39,20 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.objects.BaseISA import BaseISA +from m5.params import Param class RiscvISA(BaseISA): type = 'RiscvISA' cxx_class = 'gem5::RiscvISA::ISA' cxx_header = "arch/riscv/isa.hh" + + vlen = Param.Int( + 1024, + "VLEN: The number of bits in a single vector register, VLEN>=ELEN, " + "which must be a power of 2, and must be no greater than 65536." + ) + elen = Param.Int( + 64, + "ELEN: The maximum size in bits of a vector element that any operation" + " can produce or consume, ELEN>=8, which must be a power of 2." + ) diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc index aacf0f392b..c754e5bf44 100644 --- a/src/arch/riscv/isa.cc +++ b/src/arch/riscv/isa.cc @@ -211,7 +211,7 @@ RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs); } // anonymous namespace -ISA::ISA(const Params &p) : BaseISA(p) +ISA::ISA(const Params &p) : BaseISA(p), vlen(p.vlen), elen(p.elen) { _regClasses.push_back(&intRegClass); _regClasses.push_back(&floatRegClass); @@ -223,6 +223,15 @@ ISA::ISA(const Params &p) : BaseISA(p) miscRegFile.resize(NUM_MISCREGS); clear(); + + fatal_if(vlen > MaxVlenInBits, "RISC-V VLEN greater than %d not supported." + " Found VLEN of %d.", + MaxVlenInBits, vlen); + fatal_if(elen > vlen, "ELEN (%d) must be less than or equal to VLEN (%d).", + elen, vlen); + fatal_if(!isPowerOf2(vlen), "VLEN (%d) must be a power of 2.", vlen); + fatal_if(!isPowerOf2(elen), "ELEN (%d) must be a power of 2.", elen); + fatal_if(elen > 64, "ELEN > 64 is not supported."); } bool ISA::inUserMode() const diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh index 3123914597..e4fd8d2f6d 100644 --- a/src/arch/riscv/isa.hh +++ b/src/arch/riscv/isa.hh @@ -75,6 +75,10 @@ enum class VPUStatus class ISA : public BaseISA { + private: + int vlen; + int elen; + protected: std::vector miscRegFile; @@ -97,6 +101,9 @@ class ISA : public BaseISA void setMiscRegNoEffect(int misc_reg, RegVal val); void setMiscReg(int misc_reg, RegVal val); + int getVlen() const { return vlen; } + int getElen() const { return elen; } + RegId flattenRegId(const RegId ®Id) const { return regId; } int flattenIntIndex(int reg) const { return reg; } int flattenFloatIndex(int reg) const { return reg; } diff --git a/src/arch/riscv/regs/vector.hh b/src/arch/riscv/regs/vector.hh index bb7e3c13b2..a4d5e77656 100644 --- a/src/arch/riscv/regs/vector.hh +++ b/src/arch/riscv/regs/vector.hh @@ -46,6 +46,7 @@ namespace gem5 namespace RiscvISA { +const unsigned MaxVlenInBits = 65536; constexpr unsigned NumVecElemPerVecReg = 4; using VecElem = uint64_t; constexpr size_t VLENB = NumVecElemPerVecReg * sizeof(VecElem); From b061650493901143ccf60585ef87e46687e2949a Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Thu, 10 Nov 2022 23:23:14 +0000 Subject: [PATCH 3/8] arch-riscv: Add vtype and vl to riscv pcstate Change-Id: If8765b27674be86d444fc6d275484e3f94c20282 Signed-off-by: Hoa Nguyen --- src/arch/riscv/pcstate.hh | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/src/arch/riscv/pcstate.hh b/src/arch/riscv/pcstate.hh index 0125507f96..de5aff0fc2 100644 --- a/src/arch/riscv/pcstate.hh +++ b/src/arch/riscv/pcstate.hh @@ -43,6 +43,7 @@ #define __ARCH_RISCV_PCSTATE_HH__ #include "arch/generic/pcstate.hh" +#include "arch/riscv/regs/vector.hh" namespace gem5 { @@ -55,6 +56,8 @@ class PCState : public GenericISA::UPCState<4> private: bool _compressed = false; bool _rv32 = false; + VTYPE _vtype = 0; + uint32_t _vl = 0; public: using GenericISA::UPCState<4>::UPCState; @@ -65,9 +68,11 @@ class PCState : public GenericISA::UPCState<4> update(const PCStateBase &other) override { Base::update(other); - auto &pcstate = other.as(); + auto &pcstate = other.as(); _compressed = pcstate._compressed; _rv32 = pcstate._rv32; + _vtype = pcstate._vtype; + _vl = pcstate._vl; } void compressed(bool c) { _compressed = c; } @@ -76,6 +81,12 @@ class PCState : public GenericISA::UPCState<4> void rv32(bool val) { _rv32 = val; } bool rv32() const { return _rv32; } + void vl(uint32_t val) { _vl = val; } + uint32_t vl() const { return _vl; } + + void vtype(RiscvISA::VTYPE val) { _vtype = val; } + RiscvISA::VTYPE vtype() const { return _vtype; } + bool branching() const override { @@ -85,6 +96,16 @@ class PCState : public GenericISA::UPCState<4> return npc() != pc() + 4 || nupc() != upc() + 1; } } + + bool + equals(const PCStateBase &_other) const override + { + auto &other = _other.as(); + return _pc == other._pc \ + && _upc == other._upc \ + && _vl == other._vl \ + && _vtype == other._vtype; + } }; } // namespace RiscvISA From 44400ccd15b725a47eb5562edecd64b493285609 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Fri, 11 Nov 2022 01:19:16 +0000 Subject: [PATCH 4/8] arch-riscv: Extend vl to 16 bits Per RVV spec 1.0, VLMAX = 2**16 Change-Id: I27d93ac602ca750648348419fe7923f459f18191 Signed-off-by: Hoa Nguyen --- src/arch/riscv/types.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/types.hh b/src/arch/riscv/types.hh index d3a8392915..fb7aab8f02 100644 --- a/src/arch/riscv/types.hh +++ b/src/arch/riscv/types.hh @@ -59,7 +59,7 @@ typedef uint32_t MachInst; BitUnion64(ExtMachInst) Bitfield<63> compressed; // More bits for vector extension - Bitfield<52, 41> vl; + Bitfield<56, 41> vl; Bitfield<40> vill; SubBitUnion(vtype8, 39, 32) // exclude vill Bitfield<39> vma; From 8d946c742ea093445e406e518a7e6b485e0f2a75 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Fri, 11 Nov 2022 04:44:09 +0000 Subject: [PATCH 5/8] arch-riscv: speculatively get vl and vtype from PCState Change-Id: I23d0c0629c71e432e89dcb330e043fc638ca6905 Signed-off-by: Hoa Nguyen --- src/arch/riscv/decoder.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc index ae692acf73..8944ca4c57 100644 --- a/src/arch/riscv/decoder.cc +++ b/src/arch/riscv/decoder.cc @@ -91,9 +91,6 @@ Decoder::moreBytes(const PCStateBase &pc, Addr fetchPC) } } if (instDone) { - emi.vl = this->machVl; - emi.vtype8 = this->machVtype & 0xff; - emi.vill = this->machVtype.vill; if (vconf(emi)) { this->vConfigDone = false; // set true when vconfig inst execute } @@ -120,7 +117,7 @@ Decoder::decode(PCStateBase &_next_pc) return nullptr; instDone = false; - auto &next_pc = _next_pc.as(); + auto &next_pc = _next_pc.as(); if (compressed(emi)) { next_pc.npc(next_pc.instAddr() + sizeof(machInst) / 2); @@ -130,6 +127,11 @@ Decoder::decode(PCStateBase &_next_pc) next_pc.compressed(false); } + emi.vl = next_pc.vl(); + VTYPE vtype = next_pc.vtype(); + emi.vtype8 = vtype.vtype8; + emi.vill = vtype.vill; + return decode(emi, next_pc.instAddr()); } From 3013eb0c5738bdc588d4d830cf33351d562176a7 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Fri, 11 Nov 2022 04:49:47 +0000 Subject: [PATCH 6/8] arch-riscv: Change the nature of vsetvl* family of insts - The vsetvl* insts, apart from the spec, also update the vl and vtype stored in the next pc PCState. - The vsetvl* insts are marked as control instructions and behave like a branch instruction. Upon the execution stage, the values of vl and vtype will be updated, and the updated values will be compared to the initial values. If they are different, the pipeline will be flushed. The next instruction will get the PCState from this instruction, so it will have the updated vl and vtype. Change-Id: I8d988fd8ca833021908694bd1713cb3963bdfa3c Signed-off-by: Hoa Nguyen --- src/arch/riscv/isa/decoder.isa | 6 ++++-- src/arch/riscv/isa/formats/vector_conf.isa | 11 +++++++++-- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index f819a5d925..0e71667846 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -3797,7 +3797,8 @@ decode QUADRANT default Unknown::unknown() { uint64_t requested_vtype = zimm11; Rd_ud = 0; - }}, VectorConfigOp); + }}, VectorConfigOp, IsControl, IsIndirectControl, + IsUncondControl); 0x1: decode BIT30 { 0x0: vsetvl({{ uint64_t rd_bits = RD; @@ -3806,7 +3807,8 @@ decode QUADRANT default Unknown::unknown() { uint64_t requested_vtype = Rs2_ud; Rd_ud = 0; - }}, VectorConfigOp); + }}, VectorConfigOp, IsControl, IsIndirectControl, + IsUncondControl); 0x1: vsetivli({{ uint64_t rd_bits = RD; uint64_t rs1_bits = -1; diff --git a/src/arch/riscv/isa/formats/vector_conf.isa b/src/arch/riscv/isa/formats/vector_conf.isa index 31a489ef39..7796335a34 100644 --- a/src/arch/riscv/isa/formats/vector_conf.isa +++ b/src/arch/riscv/isa/formats/vector_conf.isa @@ -86,11 +86,18 @@ def template VConfExecute {{ xc->setMiscReg(MISCREG_VL, new_vl); - tc->getDecoderPtr()->as().setVlAndVtype(new_vl, new_vtype); + //tc->getDecoderPtr()->as().setVlAndVtype(new_vl, new_vtype); + RiscvISA::PCState newPCState; + set(newPCState, xc->pcState()); + newPCState.vtype(new_vtype); + newPCState.vl(new_vl); + xc->pcState(newPCState); + + xc->tcBase()->pcState(newPCState); Rd = new_vl; %(op_wb)s; return NoFault; } -}}; \ No newline at end of file +}}; From d4f24e432a653e4478ca263c198e39339ae41779 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Fri, 11 Nov 2022 09:52:27 +0000 Subject: [PATCH 7/8] arch-riscv,cpu: remove fetch stalls Change-Id: I8d8101fb3522beaa22cb928ef3458dfaa3d86271 Signed-off-by: Hoa Nguyen --- src/arch/generic/decoder.hh | 10 ---------- src/arch/riscv/decoder.cc | 23 ----------------------- src/arch/riscv/decoder.hh | 3 --- src/cpu/minor/fetch2.cc | 5 +---- src/cpu/o3/fetch.cc | 6 +----- 5 files changed, 2 insertions(+), 45 deletions(-) diff --git a/src/arch/generic/decoder.hh b/src/arch/generic/decoder.hh index e7d361e6cf..afba1a3e7c 100644 --- a/src/arch/generic/decoder.hh +++ b/src/arch/generic/decoder.hh @@ -48,7 +48,6 @@ class InstDecoder : public SimObject bool instDone = false; bool outOfBytes = true; - bool stall = false; public: template @@ -155,15 +154,6 @@ class InstDecoder : public SimObject * decoder isn't ready (see instReady()). */ virtual StaticInstPtr decode(PCStateBase &pc) = 0; - - /** - * Has decoder been stalled? - * - * This method can be used to check if decoder has been stalled for - * some reason. If so, no more instructions can be fetch from decoder. - * - */ - bool isStalled() { return this->stall; } }; } // namespace gem5 diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc index 8944ca4c57..26270ea920 100644 --- a/src/arch/riscv/decoder.cc +++ b/src/arch/riscv/decoder.cc @@ -44,7 +44,6 @@ void Decoder::reset() { aligned = true; mid = false; - vConfigDone = true; machInst = 0; emi = 0; } @@ -52,14 +51,6 @@ void Decoder::reset() void Decoder::moreBytes(const PCStateBase &pc, Addr fetchPC) { - if (GEM5_UNLIKELY(!this->vConfigDone)) { - DPRINTF(Decode, "Waiting for vset*vl* to be executed\n"); - instDone = false; - outOfBytes = false; - stall = true; - return; - } - stall = false; // The MSB of the upper and lower halves of a machine instruction. constexpr size_t max_bit = sizeof(machInst) * 8 - 1; @@ -90,11 +81,6 @@ Decoder::moreBytes(const PCStateBase &pc, Addr fetchPC) instDone = compressed(emi); } } - if (instDone) { - if (vconf(emi)) { - this->vConfigDone = false; // set true when vconfig inst execute - } - } } StaticInstPtr @@ -135,14 +121,5 @@ Decoder::decode(PCStateBase &_next_pc) return decode(emi, next_pc.instAddr()); } -void -Decoder::setVlAndVtype(uint32_t vl, VTYPE vtype) -{ - this->machVtype = vtype; - this->machVl = vl; - - this->vConfigDone = true; -} - } // namespace RiscvISA } // namespace gem5 diff --git a/src/arch/riscv/decoder.hh b/src/arch/riscv/decoder.hh index c6167814bc..f17dfdbc08 100644 --- a/src/arch/riscv/decoder.hh +++ b/src/arch/riscv/decoder.hh @@ -52,7 +52,6 @@ class Decoder : public InstDecoder private: bool aligned; bool mid; - bool vConfigDone; protected: //The extended machine instruction being generated ExtMachInst emi; @@ -90,8 +89,6 @@ class Decoder : public InstDecoder void moreBytes(const PCStateBase &pc, Addr fetchPC) override; StaticInstPtr decode(PCStateBase &nextPC) override; - - void setVlAndVtype(uint32_t vl, VTYPE vtype); }; } // namespace RiscvISA diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc index dfac3cb76f..fc7338ffed 100644 --- a/src/cpu/minor/fetch2.cc +++ b/src/cpu/minor/fetch2.cc @@ -303,7 +303,6 @@ Fetch2::evaluate() unsigned int output_index = 0; - bool fetch2_stall = false; /* Pack instructions into the output while we can. This may involve * using more than one input line. Note that lineWidth will be 0 * for faulting lines */ @@ -311,8 +310,7 @@ Fetch2::evaluate() (line_in->isFault() || fetch_info.inputIndex < line_in->lineWidth) && /* More input */ output_index < outputWidth && /* More output to fill */ - prediction.isBubble() && /* No predicted branch */ - !fetch2_stall) + prediction.isBubble() && /* No predicted branch */) { ThreadContext *thread = cpu.getContext(line_in->id.threadId); InstDecoder *decoder = thread->getDecoderPtr(); @@ -388,7 +386,6 @@ Fetch2::evaluate() line_in->lineBaseAddr + fetch_info.inputIndex); DPRINTF(Fetch, "Offering MachInst to decoder addr: 0x%x\n", line_in->lineBaseAddr + fetch_info.inputIndex); - fetch2_stall = decoder->isStalled(); } /* Maybe make the above a loop to accomodate ISAs with diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc index 72743ff92d..49060b718d 100644 --- a/src/cpu/o3/fetch.cc +++ b/src/cpu/o3/fetch.cc @@ -1199,13 +1199,10 @@ Fetch::fetch(bool &status_change) auto *dec_ptr = decoder[tid]; const Addr pc_mask = dec_ptr->pcMask(); - auto fetchStall = false; - - // Loop through instruction memory from the cache. // Keep issuing while fetchWidth is available and branch is not // predicted taken while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize - && !predictedBranch && !quiesce && !fetchStall) { + && !predictedBranch && !quiesce) { // We need to process more memory if we aren't going to get a // StaticInst from the rom, the current macroop, or what's already // in the decoder. @@ -1253,7 +1250,6 @@ Fetch::fetch(bool &status_change) pcOffset = 0; } } else { - fetchStall = dec_ptr->isStalled(); // We need more bytes for this instruction so blkOffset and // pcOffset will be updated break; From 3db9ddb6c33a2ca0b0d25abddb43fab78d546730 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Sat, 12 Nov 2022 03:54:04 +0000 Subject: [PATCH 8/8] arch-riscv: Remove a change that added a blank line Change-Id: I14172a4cf517f3f81d9cf3928c7db32f49644b20 Signed-off-by: Hoa Nguyen --- src/arch/riscv/fp_inst.hh | 1 - 1 file changed, 1 deletion(-) diff --git a/src/arch/riscv/fp_inst.hh b/src/arch/riscv/fp_inst.hh index 0c59879b72..604c0169f0 100644 --- a/src/arch/riscv/fp_inst.hh +++ b/src/arch/riscv/fp_inst.hh @@ -40,5 +40,4 @@ return std::make_shared("RM fault", machInst);\ softfloat_roundingMode = rm; \ - #endif // __ARCH_RISCV_FP_INST_HH__