diff --git a/Bender.local b/Bender.local index c9fd587..a7bab39 100644 --- a/Bender.local +++ b/Bender.local @@ -1,6 +1,5 @@ overrides: fpnew : { git: "https://github.com/pulp-platform/cvfpu.git" , rev: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 } - hci : { git: "https://github.com/pulp-platform/hci.git" , rev: 5a48a854573fca5bbabc1cfd4110fa4530a50ed7 } cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: 37a82d337ba60129c333d104c29e816d0698b53b } cv32e40x : { git: "https://github.com/pulp-platform/cv32e40x.git" , rev: a90101211048ba1a16cedbe4db963ab6e12569d7 } axi : { git: "https://github.com/pulp-platform/axi.git" , version: 0.39.5 } diff --git a/Bender.yml b/Bender.yml index 51a1585..0f4c977 100644 --- a/Bender.yml +++ b/Bender.yml @@ -24,13 +24,13 @@ package: - "Luca Balboni (luca.balboni10@studio.unibo.it)" dependencies: - redmule : { git: "https://github.com/pulp-platform/redmule.git" , rev: 9a1aa14be0b23f0ade84bab57e7e434397ac9876 } # branch: vi/scale_up + redmule : { git: "https://github.com/pulp-platform/redmule.git" , rev: 1eb90a872e813716c505d4cc9a0fcaf7dd3d131c } # branch: fc/ooo-mux cv32e40x : { git: "https://github.com/pulp-platform/cv32e40x.git" , rev: a90101211048ba1a16cedbe4db963ab6e12569d7 } # branch: vi/redmule_scaleup cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: 37a82d337ba60129c333d104c29e816d0698b53b } idma : { git: "https://github.com/pulp-platform/iDMA.git" , rev: a6b190c7991331432afa9a2899d032bc1b176830 } # branch: vi/redmule_scaleup hwpe-stream : { git: "https://github.com/pulp-platform/hwpe-stream.git" , version: 1.6 } - hwpe-ctrl : { git: "https://github.com/pulp-platform/hwpe-ctrl.git" , rev: c35d5b0886ab549fb9144c3c14a4682112330e21 } # branch: yt/reqrsp - hci : { git: "https://github.com/pulp-platform/hci.git" , rev: 5a48a854573fca5bbabc1cfd4110fa4530a50ed7 } # branch: vi/redmule_scaleup + hwpe-ctrl : { git: "https://github.com/pulp-platform/hwpe-ctrl.git" , version: 3.0.0 } + hci : { git: "https://github.com/pulp-platform/hci.git" , version: 2.3.0 } cluster_icache : { git: "https://github.com/pulp-platform/cluster_icache.git" , rev: 917ecbf908bdaa22c5713bbcff277d142506bb16 } # branch: michaero/astral fpnew : { git: "https://github.com/pulp-platform/cvfpu.git" , rev: "pulp-v0.1.3" } fpu_ss : { git: "https://github.com/pulp-platform/fpu_ss.git" , rev: 8e2eff774d9d38a1e17a46bd56a0936dac9522f0 } # branch: vi/bender_manifest @@ -83,6 +83,7 @@ sources: - hw/tile/fractal_sync_xif_inst_decoder.sv - hw/tile/obi_slave_fsync.sv - hw/tile/core_data_demux_eu_direct.sv + - hw/tile/magia_redmule_wrap.sv - hw/tile/magia_tile.sv # MAGIA DV - target/sim/src/tile/magia_tile_tb_pkg.sv @@ -132,6 +133,7 @@ sources: - hw/tile/fractal_sync_xif_inst_decoder.sv - hw/tile/obi_slave_fsync.sv - hw/tile/core_data_demux_eu_direct.sv + - hw/tile/magia_redmule_wrap.sv - hw/tile/magia_tile.sv # MAGIA - hw/mesh/magia.sv @@ -180,6 +182,7 @@ sources: - hw/tile/fractal_sync_xif_inst_decoder.sv - hw/tile/obi_slave_fsync.sv - hw/tile/core_data_demux_eu_direct.sv + - hw/tile/magia_redmule_wrap.sv - hw/tile/magia_tile.sv # MAGIA - hw/mesh/noc/floo_axi_mesh_2x2_noc.sv diff --git a/Makefile b/Makefile index be433dc..dbeb6b6 100644 --- a/Makefile +++ b/Makefile @@ -30,9 +30,11 @@ BUILD_DIR ?= sim/work ifneq (,$(wildcard /etc/iis.version)) QUESTA ?= questa-2025.1 BENDER ?= bender + BASE_PYTHON ?= python else QUESTA ?= BENDER ?= ./bender + BASE_PYTHON ?= python3 endif BENDER_DIR ?= . ISA ?= riscv @@ -60,7 +62,7 @@ compile_script_synth ?= scripts/synth_compile.tcl compile_flag ?= -suppress 2583 -suppress 13314 -suppress 3009 questa_compile_flag += -t 1ns -suppress 3009 -questa_opt_flag += -suppress 3009 -debugdb +acc=npr +questa_opt_flag += -suppress 3009 -debugdb +acc questa_opt_fast_flag += -suppress 3009 questa_run_flag += -t 1ns -debugDB -suppress 3009 questa_run_fast_flag += -t 1ns -suppress 3009 @@ -128,7 +130,7 @@ VSIM_LIBS=work $(STIM_INSTR) $(STIM_DATA): $(BIN) objcopy --srec-len 1 --output-target=srec $(BIN) $(BIN).s19 && \ scripts/parse_s19.pl $(BIN).s19 > $(BIN).txt && \ - python scripts/s19tomem.py $(BIN).txt $(STIM_INSTR) $(STIM_DATA) + $(BASE_PYTHON) scripts/s19tomem.py $(BIN).txt $(STIM_INSTR) $(STIM_DATA) cd $(TEST_DIR)/$(test) && \ ln -sfn $(ROOT_DIR)/$(INI_PATH) $(VSIM_INI) && \ ln -sfn $(ROOT_DIR)/$(WORK_PATH) $(VSIM_LIBS) @@ -159,9 +161,6 @@ IDMA_ADD_IDS ?= rw_axi_rw_obi # Parameters used for FlooNoC FLOONOC_ROOT ?= $(shell $(BENDER) path floo_noc) -# Setup python3 venv and install dependencies -BASE_PYTHON ?= python - .PHONY: python_venv python_deps python_venv: @@ -318,7 +317,7 @@ objdump: $(OBJDUMP) -d -l -s $(BIN) > $(ODUMP) itb: - python scripts/objdump2itb.py $(ODUMP) > $(ITB) + $(BASE_PYTHON) scripts/objdump2itb.py $(ODUMP) > $(ITB) OP ?= gemm fp_fmt ?= FP16 @@ -367,7 +366,7 @@ hw-all: hw-clean hw-lib hw-compile hw-opt # Nonfree components MAGIA_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/magia-nonfree MAGIA_NONFREE_DIR ?= nonfree -MAGIA_NONFREE_COMMIT ?= main +MAGIA_NONFREE_COMMIT ?= v0.1 .PHONY: magia-nonfree-init MAGIA_NONFREE_DEPS ?= 1 diff --git a/hw/tile/converters/hci2obi.sv b/hw/tile/converters/hci2obi.sv index e123446..a25c554 100644 --- a/hw/tile/converters/hci2obi.sv +++ b/hw/tile/converters/hci2obi.sv @@ -30,10 +30,10 @@ module hci2obi_rsp #( assign obi_rsp_o.gnt = hci_rsp_i.gnt; assign obi_rsp_o.rvalid = hci_rsp_i.r_valid; assign obi_rsp_o.r.rdata = hci_rsp_i.r_data; - assign obi_rsp_o.r.rid = '0; - assign obi_rsp_o.r.err = 1'b0; - assign obi_rsp_o.r.r_optional.ruser = 'b0; + assign obi_rsp_o.r.rid = hci_rsp_i.r_id; + assign obi_rsp_o.r.err = hci_rsp_i.r_opc; + assign obi_rsp_o.r.r_optional.ruser = '0; assign obi_rsp_o.r.r_optional.exokay = 1'b0; - assign obi_rsp_o.r.r_optional.rchk = 'b0; + assign obi_rsp_o.r.r_optional.rchk = '0; endmodule: hci2obi_rsp diff --git a/hw/tile/converters/obi2hci.sv b/hw/tile/converters/obi2hci.sv index 5bd1f0b..f7b265f 100644 --- a/hw/tile/converters/obi2hci.sv +++ b/hw/tile/converters/obi2hci.sv @@ -21,19 +21,22 @@ module obi2hci_req #( parameter type obi_req_t = logic, - parameter type hic_req_t = logic + parameter type hci_req_t = logic )( input obi_req_t obi_req_i, - output hic_req_t hci_req_o + output hci_req_t hci_req_o ); - assign hci_req_o.req = obi_req_i.req; - assign hci_req_o.add = obi_req_i.a.addr; - assign hci_req_o.wen = ~obi_req_i.a.we; - assign hci_req_o.data = obi_req_i.a.wdata; - assign hci_req_o.be = obi_req_i.a.be; - assign hci_req_o.boffs = '0; - assign hci_req_o.lrdy = 1'b1; - assign hci_req_o.user = '0; + assign hci_req_o.req = obi_req_i.req; + assign hci_req_o.add = obi_req_i.a.addr; + assign hci_req_o.wen = ~obi_req_i.a.we; + assign hci_req_o.data = obi_req_i.a.wdata; + assign hci_req_o.be = obi_req_i.a.be; + assign hci_req_o.user = '0; + assign hci_req_o.id = '0; + assign hci_req_o.ecc = '0; + assign hci_req_o.ereq = '0; + assign hci_req_o.r_ready = 1'b1; + assign hci_req_o.r_eready = '1; endmodule: obi2hci_req diff --git a/hw/tile/l1_spm.sv b/hw/tile/l1_spm.sv index 9dc6b5b..95de2e7 100644 --- a/hw/tile/l1_spm.sv +++ b/hw/tile/l1_spm.sv @@ -26,9 +26,9 @@ module l1_spm #( parameter int unsigned ID_W = 1, // ID width parameter SIM_INIT = "ones" // Simulation initialization value )( - input logic clk_i, - input logic rst_ni, - hci_mem_intf.slave tcdm_slave[N_BANK] // Memory interface + input logic clk_i, + input logic rst_ni, + hci_core_intf.target tcdm_slave[N_BANK] // Memory interface ); for (genvar i = 0; i < N_BANK; i++) begin: gen_tcdm_bank @@ -37,9 +37,12 @@ module l1_spm #( assign rsp_id_d = tcdm_slave[i].id; assign tcdm_slave[i].r_id = rsp_id_q; - always_ff @(posedge clk_i, negedge rst_ni) begin: rsp_id_register - if (~rst_ni) rsp_id_q <= '0; - else rsp_id_q <= rsp_id_d; + always_ff @(posedge clk_i or negedge rst_ni) + begin + if (~rst_ni) + rsp_id_q <= '0; + else + rsp_id_q <= rsp_id_d; end tc_sram #( @@ -64,7 +67,13 @@ module l1_spm #( .rdata_o ( tcdm_slave[i].r_data ) ); - assign tcdm_slave[i].gnt = 1'b1; + assign tcdm_slave[i].gnt = 1'b1; + assign tcdm_slave[i].r_valid = '1; + assign tcdm_slave[i].r_user = '0; + assign tcdm_slave[i].r_opc = 1'b0; + assign tcdm_slave[i].r_ecc = '0; + assign tcdm_slave[i].egnt = '0; + assign tcdm_slave[i].r_evalid = '0; end endmodule: l1_spm \ No newline at end of file diff --git a/hw/tile/magia_redmule_wrap.sv b/hw/tile/magia_redmule_wrap.sv new file mode 100644 index 0000000..557f8cf --- /dev/null +++ b/hw/tile/magia_redmule_wrap.sv @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2024 ETH Zurich and University of Bologna + * + * Licensed under the Solderpad Hardware License, Version 0.51 + * (the "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: SHL-0.51 + * + * Authors: Francesco Conti + * + * MAGIA RedMulE Wrapper + * + * This wrapper wraps redmule_top to expose struct-based HCI and HWPE-ctrl + * interfaces instead of the interface-based ports used by redmule_top. + */ + +`include "hci_helpers.svh" + +module magia_redmule_wrap + import fpnew_pkg::*; + import redmule_pkg::*; + import hci_package::*; + import hwpe_ctrl_package::*; + import hwpe_stream_package::*; + import magia_tile_pkg::*; + import magia_pkg::*; +#( + parameter int unsigned DataW = magia_tile_pkg::REDMULE_DW, + parameter fp_format_e FpFormat = FP16, + parameter int unsigned Height = 16, + parameter int unsigned Width = 24, // fixme: possibly decrease to 16 + parameter int unsigned NumPipeRegs = 1, + parameter pipe_config_t PipeConfig = DISTRIBUTED, + parameter int unsigned EccChunkSize = 32, + parameter bit LatchBuffers = 0, + parameter fpnew_pkg::fmt_logic_t FpFmtConfig = 6'b001101, + parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = 4'b1000, + parameter ctrl_intf_e CtrlIntfConfig = XIF, + parameter logic [6:0] McnfigOpCode = 7'b0001011, + parameter logic [6:0] MarithOpCode = 7'b0001011, + parameter logic [6:0] MopcntOpCode = 7'b0001011, + parameter logic [2:0] McnfigFunct3 = 3'b000, + parameter logic [2:0] MarithFunct3 = 3'b001, + parameter logic [2:0] MopcntFunct3 = 3'b010, + parameter logic [1:0] McnfigFunct2 = 2'b00, + parameter logic [1:0] MarithFunct2 = 2'b00, + parameter logic [1:0] MopcntFunct2 = 2'b00, + parameter int unsigned XifNumHarts = 1, + parameter int unsigned XifIdWidth = 1, + parameter int unsigned XifIssueRegisterSplit = 0, + parameter type x_issue_req_t = logic, + parameter type x_issue_resp_t = logic, + parameter type x_register_t = logic, + parameter type x_commit_t = logic, + parameter type x_result_t = logic, + parameter type redmule_data_req_t = magia_tile_pkg::redmule_data_req_t, + parameter type redmule_data_rsp_t = magia_tile_pkg::redmule_data_rsp_t, + parameter type redmule_ctrl_req_t = magia_tile_pkg::redmule_ctrl_req_t, + parameter type redmule_ctrl_rsp_t = magia_tile_pkg::redmule_ctrl_rsp_t, + parameter hci_size_parameter_t `HCI_SIZE_PARAM(tcdm) = '{ + DW: DataW, + AW: magia_pkg::ADDR_W, + BW: hci_package::DEFAULT_BW, + UW: magia_tile_pkg::REDMULE_UW, + IW: hci_package::DEFAULT_IW, + EW: hci_package::DEFAULT_EW, + EHW: hci_package::DEFAULT_EHW + } +)( + input logic clk_i, + input logic rst_ni, + input logic test_mode_i, + output logic busy_o, + output logic evt_o, + // XIF ports (unused if CtrlIntfConfig = HWPE_TARGET) + input x_issue_req_t x_issue_req_i, + output x_issue_resp_t x_issue_resp_o, + input logic x_issue_valid_i, + output logic x_issue_ready_o, + input x_register_t x_register_i, + input logic x_register_valid_i, + output logic x_register_ready_o, + input x_commit_t x_commit_i, + input logic x_commit_valid_i, + output x_result_t x_result_o, + output logic x_result_valid_o, + input logic x_result_ready_i, + // Struct-based HCI data ports + output redmule_data_req_t data_req_o, + input redmule_data_rsp_t data_rsp_i, + // Struct-based HWPE-ctrl ports + input redmule_ctrl_req_t ctrl_req_i, + output redmule_ctrl_rsp_t ctrl_rsp_o +); + + localparam hci_size_parameter_t `HCI_SIZE_PARAM(tcdm_filtered) = `HCI_SIZE_PARAM(tcdm); + + // Internal interface instances for HCI + `HCI_INTF(tcdm, clk_i); + `HCI_INTF(tcdm_filtered, clk_i); + + // Internal interface instance for HWPE-ctrl + hwpe_ctrl_intf_periph #( + .ID_WIDTH ( hci_package::DEFAULT_IW ) + ) target ( + .clk ( clk_i ) + ); + + // Internal interface instances for HWPE streams (dummy, unused) + hwpe_stream_intf_stream w_stream_i ( + .clk ( clk_i ) + ); + hwpe_stream_intf_stream x_stream_i ( + .clk ( clk_i ) + ); + hwpe_stream_intf_stream w_stream_o ( + .clk ( clk_i ) + ); + hwpe_stream_intf_stream x_stream_o ( + .clk ( clk_i ) + ); + + // Tie off dummy HWPE stream inputs + assign w_stream_i.valid = '0; + assign w_stream_i.data = '0; + assign w_stream_i.strb = '0; + assign x_stream_i.valid = '0; + assign x_stream_i.data = '0; + assign x_stream_i.strb = '0; + + // Tie off dummy HWPE stream outputs + assign w_stream_o.ready = '1; + assign x_stream_o.ready = '1; + + // Filter r_id from tcdm interface + hci_core_r_id_filter #( + .`HCI_SIZE_PARAM(tcdm_target) ( `HCI_SIZE_PARAM(tcdm) ) + ) i_tcdm_r_id_filter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( 1'b0 ), + .enable_i ( 1'b1 ), + .tcdm_target ( tcdm ), + .tcdm_initiator ( tcdm_filtered ) + ); + + // Convert struct-based ports to interface-based ports for HCI + `HCI_ASSIGN_FROM_INTF(tcdm_filtered, data_req_o, data_rsp_i); + + // Convert struct-based ports to interface-based ports for HWPE-ctrl + assign target.req = ctrl_req_i.req; + assign target.add = ctrl_req_i.add; + assign target.wen = ctrl_req_i.wen; + assign target.be = ctrl_req_i.be; + assign target.data = ctrl_req_i.data; + assign target.id = ctrl_req_i.id; + assign ctrl_rsp_o.gnt = target.gnt; + assign ctrl_rsp_o.r_data = target.r_data; + assign ctrl_rsp_o.r_valid = target.r_valid; + assign ctrl_rsp_o.r_id = target.r_id; + + // Instantiate redmule_top with interface-based ports + redmule_top #( + .DataW ( DataW ), + .FpFormat ( FpFormat ), + .Height ( Height ), + .Width ( Width ), + .NumPipeRegs ( NumPipeRegs ), + .PipeConfig ( PipeConfig ), + .EccChunkSize ( EccChunkSize ), + .LatchBuffers ( LatchBuffers ), + .FpFmtConfig ( FpFmtConfig ), + .IntFmtConfig ( IntFmtConfig ), + .CtrlIntfConfig ( CtrlIntfConfig ), + .McnfigOpCode ( McnfigOpCode ), + .MarithOpCode ( MarithOpCode ), + .MopcntOpCode ( MopcntOpCode ), + .McnfigFunct3 ( McnfigFunct3 ), + .MarithFunct3 ( MarithFunct3 ), + .MopcntFunct3 ( MopcntFunct3 ), + .McnfigFunct2 ( McnfigFunct2 ), + .MarithFunct2 ( MarithFunct2 ), + .MopcntFunct2 ( MopcntFunct2 ), + .XifNumHarts ( XifNumHarts ), + .XifIdWidth ( XifIdWidth ), + .XifIssueRegisterSplit ( XifIssueRegisterSplit), + .x_issue_req_t ( x_issue_req_t ), + .x_issue_resp_t ( x_issue_resp_t ), + .x_register_t ( x_register_t ), + .x_commit_t ( x_commit_t ), + .x_result_t ( x_result_t ), + .`HCI_SIZE_PARAM(tcdm) ( `HCI_SIZE_PARAM(tcdm)) + ) i_redmule_top ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_mode_i ( test_mode_i ), + .busy_o ( busy_o ), + .evt_o ( evt_o ), + .w_stream_i ( w_stream_i ), + .x_stream_i ( x_stream_i ), + .w_stream_o ( w_stream_o ), + .x_stream_o ( x_stream_o ), + .x_issue_req_i ( x_issue_req_i ), + .x_issue_resp_o ( x_issue_resp_o ), + .x_issue_valid_i ( x_issue_valid_i ), + .x_issue_ready_o ( x_issue_ready_o ), + .x_register_i ( x_register_i ), + .x_register_valid_i ( x_register_valid_i ), + .x_register_ready_o ( x_register_ready_o ), + .x_commit_i ( x_commit_i ), + .x_commit_valid_i ( x_commit_valid_i ), + .x_result_o ( x_result_o ), + .x_result_valid_o ( x_result_valid_o ), + .x_result_ready_i ( x_result_ready_i ), + .sync_o ( ), + .sync_i ( 1'b0 ), + .tcdm ( tcdm ), + .target ( target ) + ); + +endmodule diff --git a/hw/tile/magia_tile.sv b/hw/tile/magia_tile.sv index 9ed4b0b..a9fcbf2 100644 --- a/hw/tile/magia_tile.sv +++ b/hw/tile/magia_tile.sv @@ -21,7 +21,7 @@ */ `include "axi/assign.svh" - `include "hci/assign.svh" + `include "hci_helpers.svh" module magia_tile import magia_tile_pkg::*; @@ -409,11 +409,7 @@ module magia_tile assign fsync_clear = 1'b0; - assign xif_coproc_rules[magia_tile_pkg::XIF_REDMULE_IDX] = '{sign_list: '{ {{redmule_pkg::MCNFIG, 3'h0}}, - {{redmule_pkg::MARITH, 3'h0}}, {{redmule_pkg::MARITH, 3'h1}}, - {{redmule_pkg::MARITH, 3'h2}}, {{redmule_pkg::MARITH, 3'h3}}, - {{redmule_pkg::MARITH, 3'h4}}, {{redmule_pkg::MARITH, 3'h5}}, - {{redmule_pkg::MARITH, 3'h6}}, {{redmule_pkg::MARITH, 3'h7}} }}; + assign xif_coproc_rules[magia_tile_pkg::XIF_REDMULE_IDX] = '0; // current version of XIF-RedMulE not (yet) supported assign xif_coproc_rules[magia_tile_pkg::XIF_IDMA_IDX] = '{sign_list: '{ {{magia_tile_pkg::CONF_OPCODE, magia_tile_pkg::CONF_FUNC3}}, {{magia_tile_pkg::SET_OPCODE, magia_tile_pkg::SET_AL_FUNC3}}, {{magia_tile_pkg::SET_OPCODE, magia_tile_pkg::SET_SR2_FUNC3}}, @@ -424,6 +420,7 @@ module magia_tile {{magia_tile_pkg::SET_OPCODE, magia_tile_pkg::SET_S_FUNC3}}, {{magia_tile_pkg::SET_OPCODE, magia_tile_pkg::SET_S_FUNC3}} }}; assign xif_coproc_rules[magia_tile_pkg::XIF_FSYNC_IDX] = '{sign_list: '{ default: {magia_tile_pkg::FSYNC_OPCODE, magia_tile_pkg::FSYNC_FUNC3} }}; + assign redmule_evt[0][1] = 1'b0; `ifdef CV32E40X assign irq[magia_tile_pkg::IRQ_IDX_REDMULE_EVT_0] = 1'b0; /* redmule_evt[0][0]; */ // Event Unit manages these interrupts // Only 1 core supported @@ -502,7 +499,7 @@ module magia_tile obi2hci_req #( .obi_req_t ( magia_tile_pkg::core_obi_data_req_t ), - .hic_req_t ( magia_tile_pkg::core_hci_data_req_t ) + .hci_req_t ( magia_tile_pkg::core_hci_data_req_t ) ) i_core_data_obi2hci_req ( .obi_req_i ( core_l1_data_amo_req ), .hci_req_o ( core_l1_data_req ) @@ -554,7 +551,7 @@ module magia_tile obi2hci_req #( .obi_req_t ( magia_tile_pkg::idma_obi_req_t ), - .hic_req_t ( magia_tile_pkg::idma_hci_req_t ) + .hci_req_t ( magia_tile_pkg::idma_hci_req_t ) ) i_idma_obi2hci_req ( .obi_req_i ( idma_obi_read_req ), .hci_req_o ( idma_hci_read_req ) @@ -570,7 +567,7 @@ module magia_tile obi2hci_req #( .obi_req_t ( magia_tile_pkg::idma_obi_req_t ), - .hic_req_t ( magia_tile_pkg::idma_hci_req_t ) + .hci_req_t ( magia_tile_pkg::idma_hci_req_t ) ) i_idma_obi2hci_write_req ( .obi_req_i ( idma_obi_write_req ), .hci_req_o ( idma_hci_write_req ) @@ -698,51 +695,60 @@ module magia_tile /** Interface Definitions Beginning **/ /*******************************************************/ - hci_mem_intf #( - .AW ( magia_tile_pkg::AWM ), - .DW ( magia_tile_pkg::DW_LIC ), - .BW ( magia_tile_pkg::BW_LIC ), - .IW ( magia_tile_pkg::IW ), - .UW ( magia_tile_pkg::UW_LIC ) - ) hci_tcdm_sram_if[N_MEM_BANKS-1:0] ( - .clk ( sys_clk ) - ); + localparam hci_package::hci_size_parameter_t `HCI_SIZE_PARAM(hci_tcdm_sram_if) = '{ + DW: magia_tile_pkg::DW_LIC, + AW: magia_tile_pkg::AWM, + BW: hci_package::DEFAULT_BW, + UW: magia_tile_pkg::UW_LIC, + IW: magia_tile_pkg::IW, + EW: hci_package::DEFAULT_EW, + EHW: hci_package::DEFAULT_EHW + }; + `HCI_INTF_ARRAY(hci_tcdm_sram_if, sys_clk, 0:N_MEM_BANKS-1); - hci_core_intf #( - .DW ( magia_tile_pkg::DW_LIC ), - .AW ( magia_tile_pkg::AWC ), - .OW ( magia_tile_pkg::AWC ), - .UW ( magia_tile_pkg::UW_LIC ) - ) hci_core_if[magia_tile_pkg::N_CORE-1:0] ( - .clk( sys_clk ) - ); - - hci_core_intf #( - .DW ( magia_tile_pkg::REDMULE_DW ), - .AW ( magia_tile_pkg::AWH ), - .OW ( magia_tile_pkg::OWH ), - .UW ( magia_tile_pkg::REDMULE_UW ) - ) hci_redmule_if[magia_tile_pkg::N_HWPE-1:0] ( - .clk( sys_clk ) - ); - - hci_core_intf #( - .DW ( magia_tile_pkg::DW_LIC ), - .AW ( magia_tile_pkg::AWC ), - .OW ( magia_tile_pkg::AWC ), - .UW ( magia_tile_pkg::UW_LIC ) - ) hci_dma_if[magia_tile_pkg::N_DMA-1:0] ( - .clk( sys_clk ) - ); - - hci_core_intf #( - .DW ( magia_tile_pkg::DW_LIC ), - .AW ( magia_tile_pkg::AWC ), - .OW ( magia_tile_pkg::AWC ), - .UW ( magia_tile_pkg::UW_LIC ) - ) hci_ext_if[magia_tile_pkg::N_EXT-1:0] ( - .clk( sys_clk ) - ); + localparam hci_package::hci_size_parameter_t `HCI_SIZE_PARAM(hci_core_if) = '{ + DW: magia_tile_pkg::DW_LIC, + AW: magia_tile_pkg::AWC, + BW: hci_package::DEFAULT_BW, + UW: magia_tile_pkg::UW_LIC, + IW: hci_package::DEFAULT_IW, + EW: hci_package::DEFAULT_EW, + EHW: hci_package::DEFAULT_EHW + }; + `HCI_INTF_ARRAY(hci_core_if, sys_clk, 0:magia_tile_pkg::N_CORE-1); + + localparam hci_package::hci_size_parameter_t `HCI_SIZE_PARAM(hci_redmule_if) = '{ + DW: magia_tile_pkg::REDMULE_DW, + AW: magia_tile_pkg::AWH, + BW: hci_package::DEFAULT_BW, + UW: magia_tile_pkg::REDMULE_UW, + IW: hci_package::DEFAULT_IW, + EW: hci_package::DEFAULT_EW, + EHW: hci_package::DEFAULT_EHW + }; + `HCI_INTF_ARRAY(hci_redmule_if, sys_clk, 0:magia_tile_pkg::N_HWPE-1); + + localparam hci_package::hci_size_parameter_t `HCI_SIZE_PARAM(hci_dma_if) = '{ + DW: magia_tile_pkg::DW_LIC, + AW: magia_tile_pkg::AWC, + BW: hci_package::DEFAULT_BW, + UW: magia_tile_pkg::UW_LIC, + IW: hci_package::DEFAULT_IW, + EW: hci_package::DEFAULT_EW, + EHW: hci_package::DEFAULT_EHW + }; + `HCI_INTF_ARRAY(hci_dma_if, sys_clk, 0:magia_tile_pkg::N_DMA-1); + + localparam hci_package::hci_size_parameter_t `HCI_SIZE_PARAM(hci_ext_if) = '{ + DW: magia_tile_pkg::DW_LIC, + AW: magia_tile_pkg::AWC, + BW: hci_package::DEFAULT_BW, + UW: magia_tile_pkg::UW_LIC, + IW: hci_package::DEFAULT_IW, + EW: hci_package::DEFAULT_EW, + EHW: hci_package::DEFAULT_EHW + }; + `HCI_INTF_ARRAY(hci_ext_if, sys_clk, 0:magia_tile_pkg::N_EXT-1); cv32e40x_if_xif xif_redmule_if (); @@ -796,35 +802,47 @@ module magia_tile /** RedMulE Beginning **/ /*******************************************************/ - redmule_top #( - .ID_WIDTH ( magia_tile_pkg::REDMULE_ID_W ), - .N_CORES ( magia_tile_pkg::N_CORE ), - .DW ( magia_tile_pkg::REDMULE_DW ), - .UW ( magia_tile_pkg::REDMULE_UW ), + magia_redmule_wrap #( `ifdef CV32E40X - .X_EXT ( magia_tile_pkg::X_EXT_EN ), + .CtrlIntfConfig ( redmule_pkg::XIF ), `else - .X_EXT ( 1'b0 ), // RedMulE does not implement the eXtension Interface (X) - using HWPE-CTRL mode + .CtrlIntfConfig ( redmule_pkg::HWPE_TARGET ), `endif - .SysInstWidth ( magia_pkg::INSTR_W ), - .SysDataWidth ( magia_pkg::DATA_W ), - .redmule_data_req_t ( magia_tile_pkg::redmule_data_req_t ), - .redmule_data_rsp_t ( magia_tile_pkg::redmule_data_rsp_t ), - .redmule_ctrl_req_t ( magia_tile_pkg::redmule_ctrl_req_t ), - .redmule_ctrl_rsp_t ( magia_tile_pkg::redmule_ctrl_rsp_t ) - ) i_redmule_top ( + .XifIdWidth ( magia_tile_pkg::X_ID_W ) + ) i_redmule_wrap ( .clk_i ( sys_clk ), .rst_ni ( rst_ni ), - .test_mode_i , + .test_mode_i ( test_mode_i ), .busy_o ( redmule_busy ), - .evt_o ( redmule_evt ), + .evt_o ( redmule_evt[0][0] ), `ifdef CV32E40X - .xif_issue_if_i ( xif_coproc_if.coproc_issue[magia_tile_pkg::XIF_REDMULE_IDX] ), - .xif_result_if_o ( xif_redmule_if.coproc_result ), - .xif_compressed_if_i ( xif_redmule_if.coproc_compressed ), - .xif_mem_if_o ( xif_redmule_if.coproc_mem ), + .x_issue_req_i ( xif_coproc_if.coproc_issue[magia_tile_pkg::XIF_REDMULE_IDX].issue_req ), + .x_issue_resp_o ( xif_coproc_if.coproc_issue[magia_tile_pkg::XIF_REDMULE_IDX].issue_resp ), + .x_issue_valid_i ( xif_coproc_if.coproc_issue[magia_tile_pkg::XIF_REDMULE_IDX].issue_valid ), + .x_issue_ready_o ( xif_coproc_if.coproc_issue[magia_tile_pkg::XIF_REDMULE_IDX].issue_ready ), + .x_register_i ( xif_coproc_if.coproc_issue[magia_tile_pkg::XIF_REDMULE_IDX].register ), + .x_register_valid_i ( xif_coproc_if.coproc_issue[magia_tile_pkg::XIF_REDMULE_IDX].register_valid ), + .x_register_ready_o ( xif_coproc_if.coproc_issue[magia_tile_pkg::XIF_REDMULE_IDX].register_ready ), + .x_commit_i ( xif_coproc_if.coproc_commit[magia_tile_pkg::XIF_REDMULE_IDX].commit ), + .x_commit_valid_i ( xif_coproc_if.coproc_commit[magia_tile_pkg::XIF_REDMULE_IDX].commit_valid ), + .x_result_o ( xif_redmule_if.coproc_result.result ), + .x_result_valid_o ( xif_redmule_if.coproc_result.result_valid ), + .x_result_ready_i ( xif_redmule_if.coproc_result.result_ready ), +`else + .x_issue_req_i ( ), // Not used in HWPE mode + .x_issue_resp_o ( ), // Not used in HWPE mode + .x_issue_valid_i ( 1'b0 ), // Not used in HWPE mode + .x_issue_ready_o ( ), // Not used in HWPE mode + .x_register_i ( ), // Not used in HWPE mode + .x_register_valid_i ( 1'b0 ), // Not used in HWPE mode + .x_register_ready_o ( ), // Not used in HWPE mode + .x_commit_i ( ), // Not used in HWPE mode + .x_commit_valid_i ( 1'b0 ), // Not used in HWPE mode + .x_result_o ( ), // Not used in HWPE mode + .x_result_valid_o ( ), // Not used in HWPE mode + .x_result_ready_i ( 1'b0 ), // Not used in HWPE mode `endif .data_req_o ( redmule_data_req ), @@ -1158,27 +1176,18 @@ module magia_tile /*******************************************************/ hci_interconnect #( - .N_HWPE ( magia_tile_pkg::N_HWPE ), - .N_CORE ( magia_tile_pkg::N_CORE ), - .N_DMA ( magia_tile_pkg::N_DMA ), - .N_EXT ( magia_tile_pkg::N_EXT ), - .N_MEM ( N_MEM_BANKS ), - .AWC ( magia_tile_pkg::AWC ), - .AWM ( magia_tile_pkg::AWM ), - .DW_LIC ( magia_tile_pkg::DW_LIC ), - .BW_LIC ( magia_tile_pkg::BW_LIC ), - .UW_LIC ( magia_tile_pkg::UW_LIC ), - .DW_SIC ( ), - .TS_BIT ( magia_tile_pkg::TS_BIT ), - .IW ( magia_tile_pkg::IW ), - .EXPFIFO ( magia_tile_pkg::EXPFIFO ), - .DWH ( magia_tile_pkg::DWH ), - .AWH ( magia_tile_pkg::AWH ), - .BWH ( magia_tile_pkg::BWH ), - .WWH ( magia_tile_pkg::WWH ), - .OWH ( magia_tile_pkg::OWH ), - .UWH ( magia_tile_pkg::UWH ), - .SEL_LIC ( magia_tile_pkg::SEL_LIC ) + .N_HWPE ( magia_tile_pkg::N_HWPE ), + .N_CORE ( magia_tile_pkg::N_CORE ), + .N_DMA ( magia_tile_pkg::N_DMA ), + .N_EXT ( magia_tile_pkg::N_EXT ), + .N_MEM ( N_MEM_BANKS ), + .TS_BIT ( magia_tile_pkg::TS_BIT ), + .IW ( magia_tile_pkg::IW ), + .EXPFIFO ( magia_tile_pkg::EXPFIFO ), + .SEL_LIC ( magia_tile_pkg::SEL_LIC ), + .`HCI_SIZE_PARAM(cores) ( `HCI_SIZE_PARAM(hci_core_if) ), + .`HCI_SIZE_PARAM(mems) ( `HCI_SIZE_PARAM(hci_tcdm_sram_if) ), + .`HCI_SIZE_PARAM(hwpe) ( `HCI_SIZE_PARAM(hci_redmule_if) ) ) i_local_interconnect ( .clk_i ( sys_clk ), .rst_ni ( rst_ni ), @@ -1190,7 +1199,7 @@ module magia_tile .dma ( hci_dma_if ), .ext ( hci_ext_if ), .mems ( hci_tcdm_sram_if ), - .hwpe ( hci_redmule_if[0] ) + .hwpe ( hci_redmule_if ) ); /*******************************************************/ diff --git a/hw/tile/magia_tile_pkg.sv b/hw/tile/magia_tile_pkg.sv index d3955b3..4f06773 100644 --- a/hw/tile/magia_tile_pkg.sv +++ b/hw/tile/magia_tile_pkg.sv @@ -22,16 +22,14 @@ package magia_tile_pkg; - `include "hci/typedef.svh" - `include "hwpe-ctrl/typedef.svh" + `include "hci_helpers.svh" + `include "hwpe_ctrl_helpers.svh" `include "obi/typedef.svh" `include "axi/typedef.svh" `include "register_interface/typedef.svh" `include "idma/typedef.svh" `include "fractal_sync/typedef.svh" - `include "hci/assign.svh" - `include "../include/alias.svh" // IRQ constraints @@ -97,7 +95,7 @@ package magia_tile_pkg; parameter int unsigned TS_BIT = 21; // TEST_SET_BIT (for Log Interconnect) parameter int unsigned IW = N_HWPE+N_CORE+N_DMA+N_EXT; // ID Width HCI parameter int unsigned EXPFIFO = 0; // FIFO Depth for HWPE Interconnect - parameter int unsigned DWH = 544; // Data Width for HWPE Interconnect: RedMulE Hx(P+1)xBits + Bank width = 8x(3+1)x16+32 + parameter int unsigned DWH = 544; // Data Width for HWPE Interconnect: RedMulE Hx(P+1)xBits + Bank width for misaligned access = 8x(3+1)x16+32 parameter int unsigned AWH = magia_pkg::ADDR_W; // Address Width for HWPE Interconnect parameter int unsigned BWH = magia_pkg::BYTE_W; // Byte Width for HWPE Interconnect parameter int unsigned WWH = DWH; // Word Width for HWPE Interconnect @@ -153,7 +151,7 @@ package magia_tile_pkg; parameter int unsigned EVENT_UNIT_IRQ_WIDTH = 5; // Width of Event Unit IRQ ID signals (supports up to 32 different event types) // Parameters used by RedMulE - parameter int unsigned REDMULE_DW = DWH; // RedMulE Data Width + parameter int unsigned REDMULE_DW = DWH-32; // RedMulE Data Width parameter int unsigned REDMULE_ID_W = magia_pkg::ID_W + magia_pkg::ID_W_OFFSET; // RedMulE ID Width parameter int unsigned REDMULE_UW = UWH; // RedMulE User Width @@ -493,8 +491,8 @@ package magia_tile_pkg; `HWPE_CTRL_TYPEDEF_REQ_T(redmule_ctrl_req_t, logic[AWC-1:0], logic[DWH-1:0], logic[SWH-1:0], logic[IW-1:0]) `HWPE_CTRL_TYPEDEF_RSP_T(redmule_ctrl_rsp_t, logic[DWH-1:0], logic[IW-1:0]) - `HCI_TYPEDEF_REQ_T(redmule_data_req_t, logic[AWC-1:0], logic[DWH-1:0], logic[SWH-1:0], logic signed[WDH-1:0][AWH:0], logic[UWH-1:0]) - `HCI_TYPEDEF_RSP_T(redmule_data_rsp_t, logic[DWH-1:0], logic[UWH-1:0]) + `HCI_TYPEDEF_REQ_T(redmule_data_req_t, logic[AWC-1:0], logic[DWH-1:0], logic[SWH-1:0], logic[UWH-1:0], logic[0:0], logic[0:0], logic[0:0]) + `HCI_TYPEDEF_RSP_T(redmule_data_rsp_t, logic[DWH-1:0], logic[UWH-1:0], logic[0:0], logic[0:0], logic[0:0]) localparam obi_pkg::obi_optional_cfg_t obi_amo_optional_cfg = obi_pkg::obi_all_optional_config(AUSER_WIDTH, WUSER_WIDTH, RUSER_WIDTH, MID_WIDTH, ACHK_WIDTH, RCHK_WIDTH); localparam obi_pkg::obi_cfg_t obi_amo_cfg = obi_pkg::obi_default_cfg(magia_pkg::ADDR_W, magia_pkg::DATA_W, OBI_ID_WIDTH, obi_amo_optional_cfg); @@ -514,8 +512,8 @@ package magia_tile_pkg; `OBI_TYPEDEF_DEFAULT_REQ_T(core_obi_instr_req_t, core_instr_obi_a_chan_t) `OBI_TYPEDEF_RSP_T(core_obi_instr_rsp_t, core_instr_obi_r_chan_t) - `HCI_TYPEDEF_REQ_T(core_hci_data_req_t, logic[AWC-1:0], logic[DW_LIC-1:0], logic[SW_LIC-1:0], logic signed[WD_LIC-1:0][AWH:0], logic[UWH-1:0]) - `HCI_TYPEDEF_RSP_T(core_hci_data_rsp_t, logic[DW_LIC-1:0], logic[UWH-1:0]) + `HCI_TYPEDEF_REQ_T(core_hci_data_req_t, logic[AWC-1:0], logic[DW_LIC-1:0], logic[SW_LIC-1:0], logic[UWH-1:0], logic[0:0], logic[0:0], logic[0:0]) + `HCI_TYPEDEF_RSP_T(core_hci_data_rsp_t, logic[DW_LIC-1:0], logic[UWH-1:0], logic[0:0], logic[0:0], logic[0:0]) `AXI_TYPEDEF_ALL_CT(core_axi_data, core_axi_data_req_t, core_axi_data_rsp_t, logic[magia_pkg::ADDR_W-1:0], logic[AXI_ID_W-1:0], logic[magia_pkg::DATA_W-1:0], logic[magia_pkg::STRB_W-1:0], logic[AXI_U_W-1:0]) `AXI_TYPEDEF_ALL_CT(core_axi_instr, core_axi_instr_req_t, core_axi_instr_rsp_t, logic[magia_pkg::ADDR_W-1:0], logic[AXI_ID_W-1:0], logic[magia_pkg::DATA_W-1:0], logic[magia_pkg::STRB_W-1:0], logic[AXI_U_W-1:0]) @@ -563,8 +561,8 @@ package magia_tile_pkg; `AXI_ALIAS(core_axi_data, axi_xbar_slv, core_axi_data_req_t, axi_xbar_slv_req_t, core_axi_data_rsp_t, axi_xbar_slv_rsp_t) `AXI_ALIAS(core_axi_data, axi_xbar_mst, core_axi_data_req_t, axi_xbar_mst_req_t, core_axi_data_rsp_t, axi_xbar_mst_rsp_t) - `HCI_TYPEDEF_REQ_T(idma_hci_req_t, logic[AWC-1:0], logic[DW_LIC-1:0], logic[SW_LIC-1:0], logic signed[WD_LIC-1:0][AWH:0], logic[UWH-1:0]) - `HCI_TYPEDEF_RSP_T(idma_hci_rsp_t, logic[DW_LIC-1:0], logic[UWH-1:0]) + `HCI_TYPEDEF_REQ_T(idma_hci_req_t, logic[AWC-1:0], logic[DW_LIC-1:0], logic[SW_LIC-1:0], logic[UWH-1:0], logic[0:0], logic[0:0], logic[0:0]) + `HCI_TYPEDEF_RSP_T(idma_hci_rsp_t, logic[DW_LIC-1:0], logic[UWH-1:0], logic[0:0], logic[0:0], logic[0:0]) localparam axi_pkg::xbar_cfg_t axi_xbar_cfg = '{ NoSlvPorts : AxiXbarNoSlvPorts, diff --git a/sw/tests/eu_tests/event_unit_test.c b/sw/tests/eu_tests/event_unit_test.c index c93a34a..2518aac 100644 --- a/sw/tests/eu_tests/event_unit_test.c +++ b/sw/tests/eu_tests/event_unit_test.c @@ -117,7 +117,7 @@ int main(void) { ; redmule_cfg((unsigned int)X_BASE_1, (unsigned int)W_BASE_1, (unsigned int)Y_BASE_1, - M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16); + M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16, (uint8_t)Float16); // Launch IDMA operations printf("Launching IDMA operations...\n"); diff --git a/sw/tests/eu_tests/mesh_test_event_unit.c b/sw/tests/eu_tests/mesh_test_event_unit.c index aecc049..2bb26e6 100644 --- a/sw/tests/eu_tests/mesh_test_event_unit.c +++ b/sw/tests/eu_tests/mesh_test_event_unit.c @@ -190,7 +190,7 @@ int main(void) { redmule_cfg((unsigned int)(X_BASE + get_hartid()*L1_TILE_OFFSET), (unsigned int)(W_BASE + get_hartid()*L1_TILE_OFFSET), (unsigned int)(Y_BASE + get_hartid()*L1_TILE_OFFSET), - M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16); + M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16, (uint8_t)Float16); hwpe_trigger_job(); diff --git a/sw/tests/eu_tests/redmule_test_event_unit.c b/sw/tests/eu_tests/redmule_test_event_unit.c index 5efe2d0..bb290a5 100644 --- a/sw/tests/eu_tests/redmule_test_event_unit.c +++ b/sw/tests/eu_tests/redmule_test_event_unit.c @@ -97,7 +97,7 @@ int main(void) { ; redmule_cfg((unsigned int)X_BASE, (unsigned int)W_BASE, (unsigned int)Y_BASE, - M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16); + M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16, (uint8_t)Float16); // Initialize Event Unit for RedMulE eu_redmule_init(); diff --git a/sw/tests/eu_tests/tile_test_event_unit.c b/sw/tests/eu_tests/tile_test_event_unit.c index f71a4e7..a6e54f1 100644 --- a/sw/tests/eu_tests/tile_test_event_unit.c +++ b/sw/tests/eu_tests/tile_test_event_unit.c @@ -188,7 +188,7 @@ int main(void) { ; redmule_cfg((unsigned int)X_BASE, (unsigned int)W_BASE, (unsigned int)Y_BASE, - M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16); + M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16, (uint8_t)Float16); // Initialize Event Unit for RedMulE eu_redmule_init(); diff --git a/sw/tests/mm_tests/mesh_test_mm.c b/sw/tests/mm_tests/mesh_test_mm.c index 919bf95..484765d 100644 --- a/sw/tests/mm_tests/mesh_test_mm.c +++ b/sw/tests/mm_tests/mesh_test_mm.c @@ -160,7 +160,7 @@ int main(void) { redmule_cfg((unsigned int)(X_BASE + get_hartid()*L1_TILE_OFFSET), (unsigned int)(W_BASE + get_hartid()*L1_TILE_OFFSET), (unsigned int)(Y_BASE + get_hartid()*L1_TILE_OFFSET), - M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16); + M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16, (uint8_t)Float16); hwpe_trigger_job(); diff --git a/sw/tests/mm_tests/redmule.h b/sw/tests/mm_tests/redmule.h new file mode 100644 index 0000000..e51bb36 --- /dev/null +++ b/sw/tests/mm_tests/redmule.h @@ -0,0 +1,178 @@ +// Generated by PeakRDL-cheader - A free and open-source header generator +// https://github.com/SystemRDL/PeakRDL-cheader + +#ifndef REDMULE_H +#define REDMULE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +// Reg - redmule_regif::hwpe_commit_trigger +#define REDMULE_REGIF__HWPE_COMMIT_TRIGGER__COMMIT_TRIGGER_bm 0x3 +#define REDMULE_REGIF__HWPE_COMMIT_TRIGGER__COMMIT_TRIGGER_bp 0 +#define REDMULE_REGIF__HWPE_COMMIT_TRIGGER__COMMIT_TRIGGER_bw 2 +#define REDMULE_REGIF__HWPE_COMMIT_TRIGGER__COMMIT_TRIGGER_reset 0x0 +#define REDMULE_REGIF__HWPE_COMMIT_TRIGGER__R0_bm 0xfffffffc +#define REDMULE_REGIF__HWPE_COMMIT_TRIGGER__R0_bp 2 +#define REDMULE_REGIF__HWPE_COMMIT_TRIGGER__R0_bw 30 +#define REDMULE_REGIF__HWPE_COMMIT_TRIGGER__R0_reset 0x0 + +// Reg - redmule_regif::hwpe_acquire +#define REDMULE_REGIF__HWPE_ACQUIRE__ACQUIRE_bm 0xffffffff +#define REDMULE_REGIF__HWPE_ACQUIRE__ACQUIRE_bp 0 +#define REDMULE_REGIF__HWPE_ACQUIRE__ACQUIRE_bw 32 +#define REDMULE_REGIF__HWPE_ACQUIRE__ACQUIRE_reset 0x0 + +// Reg - redmule_regif::hwpe_reserved +#define REDMULE_REGIF__HWPE_RESERVED__RESERVED_bm 0xffffffff +#define REDMULE_REGIF__HWPE_RESERVED__RESERVED_bp 0 +#define REDMULE_REGIF__HWPE_RESERVED__RESERVED_bw 32 +#define REDMULE_REGIF__HWPE_RESERVED__RESERVED_reset 0x0 + +// Reg - redmule_regif::hwpe_status +#define REDMULE_REGIF__HWPE_STATUS__STATUS0_bm 0xffffffff +#define REDMULE_REGIF__HWPE_STATUS__STATUS0_bp 0 +#define REDMULE_REGIF__HWPE_STATUS__STATUS0_bw 32 +#define REDMULE_REGIF__HWPE_STATUS__STATUS0_reset 0x0 + +// Reg - redmule_regif::hwpe_running_job +#define REDMULE_REGIF__HWPE_RUNNING_JOB__RUNNING_JOB_bm 0xff +#define REDMULE_REGIF__HWPE_RUNNING_JOB__RUNNING_JOB_bp 0 +#define REDMULE_REGIF__HWPE_RUNNING_JOB__RUNNING_JOB_bw 8 +#define REDMULE_REGIF__HWPE_RUNNING_JOB__RUNNING_JOB_reset 0x0 +#define REDMULE_REGIF__HWPE_RUNNING_JOB__R0_bm 0xffffff00 +#define REDMULE_REGIF__HWPE_RUNNING_JOB__R0_bp 8 +#define REDMULE_REGIF__HWPE_RUNNING_JOB__R0_bw 24 +#define REDMULE_REGIF__HWPE_RUNNING_JOB__R0_reset 0x0 + +// Reg - redmule_regif::hwpe_soft_clear +#define REDMULE_REGIF__HWPE_SOFT_CLEAR__SOFT_CLEAR_bm 0x3 +#define REDMULE_REGIF__HWPE_SOFT_CLEAR__SOFT_CLEAR_bp 0 +#define REDMULE_REGIF__HWPE_SOFT_CLEAR__SOFT_CLEAR_bw 2 +#define REDMULE_REGIF__HWPE_SOFT_CLEAR__SOFT_CLEAR_reset 0x0 +#define REDMULE_REGIF__HWPE_SOFT_CLEAR__R0_bm 0xfffffffc +#define REDMULE_REGIF__HWPE_SOFT_CLEAR__R0_bp 2 +#define REDMULE_REGIF__HWPE_SOFT_CLEAR__R0_bw 30 +#define REDMULE_REGIF__HWPE_SOFT_CLEAR__R0_reset 0x0 + +// Regfile - redmule_regif::hwpe_ctrl_mandatory +typedef struct __attribute__ ((__packed__)) { + uint32_t commit_trigger; + uint32_t acquire; + uint32_t reserved0; + uint32_t status; + uint32_t running_job; + uint32_t soft_clear; + uint32_t reserved1; + uint32_t reserved2; +} redmule_regif__hwpe_ctrl_mandatory_t; + +// Reg - redmule_regif::mcnfig0 +#define REDMULE_REGIF__MCNFIG0__M_SIZE_bm 0xffff +#define REDMULE_REGIF__MCNFIG0__M_SIZE_bp 0 +#define REDMULE_REGIF__MCNFIG0__M_SIZE_bw 16 +#define REDMULE_REGIF__MCNFIG0__M_SIZE_reset 0x0 +#define REDMULE_REGIF__MCNFIG0__K_SIZE_bm 0xffff0000 +#define REDMULE_REGIF__MCNFIG0__K_SIZE_bp 16 +#define REDMULE_REGIF__MCNFIG0__K_SIZE_bw 16 +#define REDMULE_REGIF__MCNFIG0__K_SIZE_reset 0x0 + +// Reg - redmule_regif::mcnfig1 +#define REDMULE_REGIF__MCNFIG1__N_SIZE_bm 0xffff +#define REDMULE_REGIF__MCNFIG1__N_SIZE_bp 0 +#define REDMULE_REGIF__MCNFIG1__N_SIZE_bw 16 +#define REDMULE_REGIF__MCNFIG1__N_SIZE_reset 0x0 +#define REDMULE_REGIF__MCNFIG1__RECEIVE_X_bm 0x10000 +#define REDMULE_REGIF__MCNFIG1__RECEIVE_X_bp 16 +#define REDMULE_REGIF__MCNFIG1__RECEIVE_X_bw 1 +#define REDMULE_REGIF__MCNFIG1__RECEIVE_X_reset 0x0 +#define REDMULE_REGIF__MCNFIG1__SEND_X_bm 0x20000 +#define REDMULE_REGIF__MCNFIG1__SEND_X_bp 17 +#define REDMULE_REGIF__MCNFIG1__SEND_X_bw 1 +#define REDMULE_REGIF__MCNFIG1__SEND_X_reset 0x0 +#define REDMULE_REGIF__MCNFIG1__RECEIVE_W_bm 0x40000 +#define REDMULE_REGIF__MCNFIG1__RECEIVE_W_bp 18 +#define REDMULE_REGIF__MCNFIG1__RECEIVE_W_bw 1 +#define REDMULE_REGIF__MCNFIG1__RECEIVE_W_reset 0x0 +#define REDMULE_REGIF__MCNFIG1__SEND_W_bm 0x80000 +#define REDMULE_REGIF__MCNFIG1__SEND_W_bp 19 +#define REDMULE_REGIF__MCNFIG1__SEND_W_bw 1 +#define REDMULE_REGIF__MCNFIG1__SEND_W_reset 0x0 +#define REDMULE_REGIF__MCNFIG1__GEMM_OPS_bm 0x700000 +#define REDMULE_REGIF__MCNFIG1__GEMM_OPS_bp 20 +#define REDMULE_REGIF__MCNFIG1__GEMM_OPS_bw 3 +#define REDMULE_REGIF__MCNFIG1__GEMM_OPS_reset 0x0 +#define REDMULE_REGIF__MCNFIG1__GEMM_INPUT_FMT_bm 0x1800000 +#define REDMULE_REGIF__MCNFIG1__GEMM_INPUT_FMT_bp 23 +#define REDMULE_REGIF__MCNFIG1__GEMM_INPUT_FMT_bw 2 +#define REDMULE_REGIF__MCNFIG1__GEMM_INPUT_FMT_reset 0x0 +#define REDMULE_REGIF__MCNFIG1__GEMM_OUTPUT_FMT_bm 0x6000000 +#define REDMULE_REGIF__MCNFIG1__GEMM_OUTPUT_FMT_bp 25 +#define REDMULE_REGIF__MCNFIG1__GEMM_OUTPUT_FMT_bw 2 +#define REDMULE_REGIF__MCNFIG1__GEMM_OUTPUT_FMT_reset 0x0 + +// Reg - redmule_regif::mcnfig2 +#define REDMULE_REGIF__MCNFIG2__Y_OFFS_bm 0xffffffff +#define REDMULE_REGIF__MCNFIG2__Y_OFFS_bp 0 +#define REDMULE_REGIF__MCNFIG2__Y_OFFS_bw 32 +#define REDMULE_REGIF__MCNFIG2__Y_OFFS_reset 0x0 + +// Reg - redmule_regif::marith0 +#define REDMULE_REGIF__MARITH0__X_ADDR_bm 0xffffffff +#define REDMULE_REGIF__MARITH0__X_ADDR_bp 0 +#define REDMULE_REGIF__MARITH0__X_ADDR_bw 32 +#define REDMULE_REGIF__MARITH0__X_ADDR_reset 0x0 + +// Reg - redmule_regif::marith1 +#define REDMULE_REGIF__MARITH1__W_ADDR_bm 0xffffffff +#define REDMULE_REGIF__MARITH1__W_ADDR_bp 0 +#define REDMULE_REGIF__MARITH1__W_ADDR_bw 32 +#define REDMULE_REGIF__MARITH1__W_ADDR_reset 0x0 + +// Reg - redmule_regif::marith2 +#define REDMULE_REGIF__MARITH2__Z_ADDR_bm 0xffffffff +#define REDMULE_REGIF__MARITH2__Z_ADDR_bp 0 +#define REDMULE_REGIF__MARITH2__Z_ADDR_bw 32 +#define REDMULE_REGIF__MARITH2__Z_ADDR_reset 0x0 + +// Reg - redmule_regif::mopcnt +#define REDMULE_REGIF__MOPCNT__OP_ID_CNT_bm 0xffffffff +#define REDMULE_REGIF__MOPCNT__OP_ID_CNT_bp 0 +#define REDMULE_REGIF__MOPCNT__OP_ID_CNT_bw 32 +#define REDMULE_REGIF__MOPCNT__OP_ID_CNT_reset 0x0 + +// Regfile - redmule_regif::hwpe_ctrl_job_dep +typedef struct __attribute__ ((__packed__)) { + uint32_t mcnfig0; + uint32_t mcnfig1; + uint32_t mcnfig2; + uint32_t marith0; + uint32_t marith1; + uint32_t marith2; + uint32_t mopcnt; +} redmule_regif__hwpe_ctrl_job_dep_t; + +// Regfile - redmule_regif::hwpe_ctrl_job_indep +typedef struct __attribute__ ((__packed__)) { + uint32_t reserved; +} redmule_regif__hwpe_ctrl_job_indep_t; + +// Addrmap - redmule_regif +typedef struct __attribute__ ((__packed__)) { + redmule_regif__hwpe_ctrl_mandatory_t hwpe_ctrl; + redmule_regif__hwpe_ctrl_job_dep_t hwpe_job_dep; + redmule_regif__hwpe_ctrl_job_indep_t hwpe_job_indep; +} redmule_regif_t; + + +static_assert(sizeof(redmule_regif_t) == 0x40, "Packing error"); + +#ifdef __cplusplus +} +#endif + +#endif /* REDMULE_H */ diff --git a/sw/tests/mm_tests/redmule_test_mm.c b/sw/tests/mm_tests/redmule_test_mm.c index eea3abf..cabc859 100644 --- a/sw/tests/mm_tests/redmule_test_mm.c +++ b/sw/tests/mm_tests/redmule_test_mm.c @@ -95,7 +95,7 @@ int main(void) { ; redmule_cfg((unsigned int)X_BASE, (unsigned int)W_BASE, (unsigned int)Y_BASE, - M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16); + M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16, (uint8_t)Float16); // Wait for end of computation printf("Testing matrix multiplication with RedMulE...\n"); diff --git a/sw/tests/mm_tests/tile_test_mm.c b/sw/tests/mm_tests/tile_test_mm.c index a79e92d..a38d7ad 100644 --- a/sw/tests/mm_tests/tile_test_mm.c +++ b/sw/tests/mm_tests/tile_test_mm.c @@ -161,7 +161,7 @@ int main(void) { ; redmule_cfg((unsigned int)X_BASE, (unsigned int)W_BASE, (unsigned int)Y_BASE, - M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16); + M_SIZE, N_SIZE, K_SIZE, (uint8_t)gemm_ops, (uint8_t)Float16, (uint8_t)Float16); printf("Testing matrix multiplication with RedMulE...\n"); hwpe_trigger_job(); diff --git a/sw/utils/redmule_mm_utils.h b/sw/utils/redmule_mm_utils.h index b39468c..c08a728 100644 --- a/sw/utils/redmule_mm_utils.h +++ b/sw/utils/redmule_mm_utils.h @@ -43,12 +43,13 @@ #define REDMULE_SOFT_CLEAR 0x14 /* RedMulE configuration registers */ -#define REDMULE_REG_X_PTR 0x40 -#define REDMULE_REG_W_PTR 0x44 -#define REDMULE_REG_Z_PTR 0x48 -#define REDMULE_MCFG0_PTR 0x4C -#define REDMULE_MCFG1_PTR 0x50 -#define REDMULE_ARITH_PTR 0x54 +#define REDMULE_REG_MCNFIG0 0x20 +#define REDMULE_REG_MCNFIG1 0x24 +#define REDMULE_REG_MCNFIG2 0x28 +#define REDMULE_REG_MARITH0 0x2c +#define REDMULE_REG_MARITH1 0x30 +#define REDMULE_REG_MARITH2 0x34 +#define REDMULE_REG_MOPCNT 0x38 /* Operations and formats */ #define gemm_ops 0x1 @@ -59,24 +60,21 @@ /* HWPE Register Access Functions */ static inline void redmule_x_add_set(unsigned int value) { - HWPE_WRITE(value, REDMULE_REG_OFFS + REDMULE_REG_X_PTR); + HWPE_WRITE(value, REDMULE_REG_OFFS + REDMULE_REG_MARITH0); } static inline void redmule_w_add_set(unsigned int value) { - HWPE_WRITE(value, REDMULE_REG_OFFS + REDMULE_REG_W_PTR); + HWPE_WRITE(value, REDMULE_REG_OFFS + REDMULE_REG_MARITH1); } static inline void redmule_z_add_set(unsigned int value) { - HWPE_WRITE(value, REDMULE_REG_OFFS + REDMULE_REG_Z_PTR); + HWPE_WRITE(value, REDMULE_REG_OFFS + REDMULE_REG_MARITH2); } -static inline void redmule_mcfg_set(uint32_t mcfg0, uint32_t mcfg1) { - HWPE_WRITE(mcfg0, REDMULE_REG_OFFS + REDMULE_MCFG0_PTR); - HWPE_WRITE(mcfg1, REDMULE_REG_OFFS + REDMULE_MCFG1_PTR); -} - -static inline void redmule_arith_set(uint32_t arith) { - HWPE_WRITE(arith, REDMULE_REG_OFFS + REDMULE_ARITH_PTR); +static inline void redmule_mcfg_set(uint32_t mcfg0, uint32_t mcfg1, uint32_t mcfg2) { + HWPE_WRITE(mcfg0, REDMULE_REG_OFFS + REDMULE_REG_MCNFIG0); + HWPE_WRITE(mcfg1, REDMULE_REG_OFFS + REDMULE_REG_MCNFIG1); + HWPE_WRITE(mcfg2, REDMULE_REG_OFFS + REDMULE_REG_MCNFIG2); } static inline void hwpe_trigger_job() { @@ -129,18 +127,26 @@ static inline void hwpe_wait_for_completion() { } /* RedMulE Configuration Function */ -static inline void redmule_cfg(unsigned int x, unsigned int w, unsigned int z, uint16_t m_size, uint16_t n_size, - uint16_t k_size, uint8_t gemm_op, uint8_t gemm_fmt) { - - uint32_t mcfg_reg0 = (k_size << 16) | (m_size << 0); - uint32_t mcfg_reg1 = n_size << 0; - uint32_t arith_reg = (gemm_op << 10) | (gemm_fmt << 7); +static inline void redmule_cfg( + unsigned int x, + unsigned int w, + unsigned int z, + uint16_t m_size, + uint16_t n_size, + uint16_t k_size, + uint8_t gemm_op, + uint8_t gemm_fmt_in, + uint8_t gemm_fmt_out +) { + + uint32_t mcfg0 = (k_size << 16) | (m_size << 0); + uint32_t mcfg1 = (gemm_fmt_out << 25) | (gemm_fmt_in << 23) | (gemm_op << 20) | (n_size << 0); + uint32_t mcfg2 = 0; redmule_x_add_set((unsigned int)x); redmule_w_add_set((unsigned int)w); redmule_z_add_set((unsigned int)z); - redmule_mcfg_set((unsigned int)mcfg_reg0, (unsigned int)mcfg_reg1); - redmule_arith_set((unsigned int)arith_reg); + redmule_mcfg_set(mcfg0, mcfg1, mcfg2); } #endif /* REDMULE_MM_UTILS_H */ \ No newline at end of file