From 6284bb78418b1611dc11a78c65889716c01645b7 Mon Sep 17 00:00:00 2001 From: Victor Isachi Date: Fri, 17 Oct 2025 11:37:58 +0200 Subject: [PATCH 1/6] Communication Rework: (i) updated the NoC splitting it into narrow 32bti and wide 256bit; (ii) Updated iDMA making it 256bit and connecting it to wide NoC directly; (iii) updated local interconnect implementing a custom network of routers and arbiters; (iv) Updated the verification environment accordingly --- Bender.yml | 32 +- hw/mesh/magia.sv | 328 ++++++---- hw/mesh/magia_pkg.sv | 5 +- hw/mesh/noc/floo_axi_mesh_2x2_noc.sv | 99 --- ...6_noc.sv => floo_axi_nw_mesh_16x16_noc.sv} | 55 +- hw/mesh/noc/floo_axi_nw_mesh_2x2_noc.sv | 120 ++++ ...2_noc.sv => floo_axi_nw_mesh_32x32_noc.sv} | 55 +- ...4x4_noc.sv => floo_axi_nw_mesh_4x4_noc.sv} | 55 +- ...8x8_noc.sv => floo_axi_nw_mesh_8x8_noc.sv} | 55 +- hw/mesh/noc/magia_noc_pkg.sv | 86 ++- .../floonoc_axi_mesh_16x16_config.yml | 33 +- .../floonoc_axi_mesh_2x2_config.yml | 33 +- .../floonoc_axi_mesh_32x32_config.yml | 33 +- .../floonoc_axi_mesh_4x4_config.yml | 33 +- .../floonoc_axi_mesh_8x8_config.yml | 33 +- hw/tile/local_interconnect.sv | 283 ++++++++ hw/tile/magia_tile.sv | 602 ++++++++++++------ hw/tile/magia_tile_pkg.sv | 143 ++--- target/sim/src/mesh/magia_fixture.sv | 15 +- target/sim/src/mesh/magia_l2_mem_wrapper.sv | 184 ++++-- target/sim/src/mesh/magia_vip.sv | 15 +- target/sim/src/tile/floo_axi_mesh_1x2_pkg.sv | 97 --- .../sim/src/tile/floo_axi_nw_mesh_1x2_pkg.sv | 118 ++++ target/sim/src/tile/magia_tile_fixture.sv | 16 + target/sim/src/tile/magia_tile_vip.sv | 26 +- 25 files changed, 1714 insertions(+), 840 deletions(-) delete mode 100644 hw/mesh/noc/floo_axi_mesh_2x2_noc.sv rename hw/mesh/noc/{floo_axi_mesh_16x16_noc.sv => floo_axi_nw_mesh_16x16_noc.sv} (93%) create mode 100644 hw/mesh/noc/floo_axi_nw_mesh_2x2_noc.sv rename hw/mesh/noc/{floo_axi_mesh_32x32_noc.sv => floo_axi_nw_mesh_32x32_noc.sv} (98%) rename hw/mesh/noc/{floo_axi_mesh_4x4_noc.sv => floo_axi_nw_mesh_4x4_noc.sv} (58%) rename hw/mesh/noc/{floo_axi_mesh_8x8_noc.sv => floo_axi_nw_mesh_8x8_noc.sv} (80%) create mode 100644 hw/tile/local_interconnect.sv delete mode 100644 target/sim/src/tile/floo_axi_mesh_1x2_pkg.sv create mode 100644 target/sim/src/tile/floo_axi_nw_mesh_1x2_pkg.sv diff --git a/Bender.yml b/Bender.yml index b96784d..a37a3f8 100644 --- a/Bender.yml +++ b/Bender.yml @@ -27,7 +27,7 @@ dependencies: redmule : { git: "https://github.com/pulp-platform/redmule.git" , rev: 944d4a4d45fe05147cfbf7f872af677578f3b15c } # branch: fc/ooo-mux cv32e40x : { git: "https://github.com/pulp-platform/cv32e40x.git" , rev: a90101211048ba1a16cedbe4db963ab6e12569d7 } # branch: vi/redmule_scaleup cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: 37a82d337ba60129c333d104c29e816d0698b53b } - idma : { git: "https://github.com/pulp-platform/iDMA.git" , rev: a6b190c7991331432afa9a2899d032bc1b176830 } # branch: vi/redmule_scaleup + idma : { git: "https://github.com/pulp-platform/iDMA.git" , rev: a6b190c7991331432afa9a2899d032bc1b176830 } hwpe-stream : { git: "https://github.com/pulp-platform/hwpe-stream.git" , version: 1.6 } hwpe-ctrl : { git: "https://github.com/pulp-platform/hwpe-ctrl.git" , version: 3.0.0 } hci : { git: "https://github.com/pulp-platform/hci.git" , version: 2.3.0 } @@ -41,7 +41,7 @@ dependencies: common_cells : { git: "https://github.com/pulp-platform/common_cells.git" , version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 } fractal_sync : { git: "https://github.com/VictorIsachi/fractal_sync" , rev: fdb619f40f99d769cfceb20ac2117ff8d99e98a3 } # branch: main - floo_noc : { git: "https://github.com/pulp-platform/FlooNoC.git" , rev: f4a36265cda8b56faee45692afb20ddfffba6dee } # branch: main + floo_noc : { git: "https://github.com/pulp-platform/FlooNoC.git" , version: 0.6.1 } event_unit_flex : { git: "https://github.com/pulp-platform/event_unit_flex.git" , rev: 763c3b9977970f656326c70a96debfb2ac0f85b2 } export_include_dirs: @@ -54,7 +54,7 @@ sources: CORE_TRACES: ~ files: # NoC - - target/sim/src/tile/floo_axi_mesh_1x2_pkg.sv + - target/sim/src/tile/floo_axi_nw_mesh_1x2_pkg.sv # MAGIA Packages - hw/mesh/magia_pkg.sv - hw/tile/magia_tile_pkg.sv @@ -74,6 +74,8 @@ sources: - hw/tile/magia_event_unit.sv - hw/tile/obi_demux_addr.sv - hw/tile/l1_spm.sv + - hw/tile/local_interconnect.sv + - hw/tile/idma_xif_inst_decoder.sv - hw/tile/xif_inst_dispatcher.sv - hw/tile/idma_xif_inst_decoder.sv - hw/tile/idma_ctrl.sv @@ -99,11 +101,11 @@ sources: CORE_TRACES: ~ files: # NoC - - hw/mesh/noc/floo_axi_mesh_2x2_noc.sv - - hw/mesh/noc/floo_axi_mesh_4x4_noc.sv - - hw/mesh/noc/floo_axi_mesh_8x8_noc.sv - - hw/mesh/noc/floo_axi_mesh_16x16_noc.sv - - hw/mesh/noc/floo_axi_mesh_32x32_noc.sv + - hw/mesh/noc/floo_axi_nw_mesh_2x2_noc.sv + - hw/mesh/noc/floo_axi_nw_mesh_4x4_noc.sv + - hw/mesh/noc/floo_axi_nw_mesh_8x8_noc.sv + - hw/mesh/noc/floo_axi_nw_mesh_16x16_noc.sv + - hw/mesh/noc/floo_axi_nw_mesh_32x32_noc.sv # MAGIA Packages - hw/mesh/magia_pkg.sv - hw/tile/magia_tile_pkg.sv @@ -124,6 +126,8 @@ sources: - hw/tile/magia_event_unit.sv - hw/tile/obi_demux_addr.sv - hw/tile/l1_spm.sv + - hw/tile/local_interconnect.sv + - hw/tile/idma_xif_inst_decoder.sv - hw/tile/xif_inst_dispatcher.sv - hw/tile/idma_xif_inst_decoder.sv - hw/tile/idma_ctrl.sv @@ -173,6 +177,8 @@ sources: - hw/tile/magia_event_unit.sv - hw/tile/obi_demux_addr.sv - hw/tile/l1_spm.sv + - hw/tile/local_interconnect.sv + - hw/tile/idma_xif_inst_decoder.sv - hw/tile/xif_inst_dispatcher.sv - hw/tile/idma_xif_inst_decoder.sv - hw/tile/idma_ctrl.sv @@ -185,11 +191,11 @@ sources: - hw/tile/magia_redmule_wrap.sv - hw/tile/magia_tile.sv # MAGIA - - hw/mesh/noc/floo_axi_mesh_2x2_noc.sv - - hw/mesh/noc/floo_axi_mesh_4x4_noc.sv - - hw/mesh/noc/floo_axi_mesh_8x8_noc.sv - - hw/mesh/noc/floo_axi_mesh_16x16_noc.sv - - hw/mesh/noc/floo_axi_mesh_32x32_noc.sv + - hw/mesh/noc/floo_axi_nw_mesh_2x2_noc.sv + - hw/mesh/noc/floo_axi_nw_mesh_4x4_noc.sv + - hw/mesh/noc/floo_axi_nw_mesh_8x8_noc.sv + - hw/mesh/noc/floo_axi_nw_mesh_16x16_noc.sv + - hw/mesh/noc/floo_axi_nw_mesh_32x32_noc.sv - hw/mesh/magia.sv # Tech - pd/sourcecode/tc_sram.sv diff --git a/hw/mesh/magia.sv b/hw/mesh/magia.sv index 7dac58b..cf9df1e 100644 --- a/hw/mesh/magia.sv +++ b/hw/mesh/magia.sv @@ -67,10 +67,13 @@ module magia input logic wu_wfe_i, // Only west-side L2 - output floo_req_t [N_TILES_Y-1:0] l2_noc_req_o, - input floo_rsp_t [N_TILES_Y-1:0] l2_noc_rsp_i, - input floo_req_t [N_TILES_Y-1:0] l2_noc_req_i, - output floo_rsp_t [N_TILES_Y-1:0] l2_noc_rsp_o + output floo_req_t [N_TILES_Y-1:0] l2_noc_req_o, + input floo_rsp_t [N_TILES_Y-1:0] l2_noc_rsp_i, + input floo_req_t [N_TILES_Y-1:0] l2_noc_req_i, + output floo_rsp_t [N_TILES_Y-1:0] l2_noc_rsp_o, + + input floo_wide_t [N_TILES_Y-1:0] l2_noc_wide_i, + output floo_wide_t [N_TILES_Y-1:0] l2_noc_wide_o ); /*******************************************************/ @@ -80,14 +83,18 @@ module magia logic[31:0] mhartid[N_TILES]; // FlooNoC buses - floo_req_t [N_TILES-1:0] tile_south_req_in, tile_south_req_out; - floo_rsp_t [N_TILES-1:0] tile_south_rsp_in, tile_south_rsp_out; - floo_req_t [N_TILES-1:0] tile_east_req_in, tile_east_req_out; - floo_rsp_t [N_TILES-1:0] tile_east_rsp_in, tile_east_rsp_out; - floo_req_t [N_TILES-1:0] tile_north_req_in, tile_north_req_out; - floo_rsp_t [N_TILES-1:0] tile_north_rsp_in, tile_north_rsp_out; - floo_req_t [N_TILES-1:0] tile_west_req_in, tile_west_req_out; - floo_rsp_t [N_TILES-1:0] tile_west_rsp_in, tile_west_rsp_out; + floo_req_t [N_TILES-1:0] tile_south_req_in, tile_south_req_out; + floo_rsp_t [N_TILES-1:0] tile_south_rsp_in, tile_south_rsp_out; + floo_wide_t [N_TILES-1:0] tile_south_wide_in, tile_south_wide_out; + floo_req_t [N_TILES-1:0] tile_east_req_in, tile_east_req_out; + floo_rsp_t [N_TILES-1:0] tile_east_rsp_in, tile_east_rsp_out; + floo_wide_t [N_TILES-1:0] tile_east_wide_in, tile_east_wide_out; + floo_req_t [N_TILES-1:0] tile_north_req_in, tile_north_req_out; + floo_rsp_t [N_TILES-1:0] tile_north_rsp_in, tile_north_rsp_out; + floo_wide_t [N_TILES-1:0] tile_north_wide_in, tile_north_wide_out; + floo_req_t [N_TILES-1:0] tile_west_req_in, tile_west_req_out; + floo_rsp_t [N_TILES-1:0] tile_west_rsp_in, tile_west_rsp_out; + floo_wide_t [N_TILES-1:0] tile_west_wide_in, tile_west_wide_out; magia_tile_pkg::ht_tile_fsync_req_t ht_tile_fsync_req[N_TILES][1]; // Single link CU-FSync interface magia_tile_pkg::ht_tile_fsync_rsp_t ht_tile_fsync_rsp[N_TILES][1]; // Single link CU-FSync interface @@ -168,60 +175,68 @@ module magia .CORE_M ( ), .ERROR_CAP ( ) ) i_magia_tile ( - .clk_i , - .rst_ni , - .test_mode_i , - .tile_enable_i , - - .noc_south_req_o ( tile_south_req_out[i*N_TILES_X+j]), - .noc_south_rsp_i ( tile_south_rsp_in[i*N_TILES_X+j] ), - .noc_east_req_o ( tile_east_req_out[i*N_TILES_X+j] ), - .noc_east_rsp_i ( tile_east_rsp_in[i*N_TILES_X+j] ), - .noc_north_req_o ( tile_north_req_out[i*N_TILES_X+j]), - .noc_north_rsp_i ( tile_north_rsp_in[i*N_TILES_X+j] ), - .noc_west_req_o ( tile_west_req_out[i*N_TILES_X+j] ), - .noc_west_rsp_i ( tile_west_rsp_in[i*N_TILES_X+j] ), - - .noc_south_req_i ( tile_south_req_in[i*N_TILES_X+j] ), - .noc_south_rsp_o ( tile_south_rsp_out[i*N_TILES_X+j]), - .noc_east_req_i ( tile_east_req_in[i*N_TILES_X+j] ), - .noc_east_rsp_o ( tile_east_rsp_out[i*N_TILES_X+j] ), - .noc_north_req_i ( tile_north_req_in[i*N_TILES_X+j] ), - .noc_north_rsp_o ( tile_north_rsp_out[i*N_TILES_X+j]), - .noc_west_req_i ( tile_west_req_in[i*N_TILES_X+j] ), - .noc_west_rsp_o ( tile_west_rsp_out[i*N_TILES_X+j] ), - - .x_id_i ( j ), - .y_id_i ( i ), + .clk_i , + .rst_ni , + .test_mode_i , + .tile_enable_i , + + .noc_south_req_o ( tile_south_req_out[i*N_TILES_X+j] ), + .noc_south_rsp_i ( tile_south_rsp_in[i*N_TILES_X+j] ), + .noc_south_wide_o ( tile_south_wide_out[i*N_TILES_X+j] ), + .noc_east_req_o ( tile_east_req_out[i*N_TILES_X+j] ), + .noc_east_rsp_i ( tile_east_rsp_in[i*N_TILES_X+j] ), + .noc_east_wide_o ( tile_east_wide_out[i*N_TILES_X+j] ), + .noc_north_req_o ( tile_north_req_out[i*N_TILES_X+j] ), + .noc_north_rsp_i ( tile_north_rsp_in[i*N_TILES_X+j] ), + .noc_north_wide_o ( tile_north_wide_out[i*N_TILES_X+j] ), + .noc_west_req_o ( tile_west_req_out[i*N_TILES_X+j] ), + .noc_west_rsp_i ( tile_west_rsp_in[i*N_TILES_X+j] ), + .noc_west_wide_o ( tile_west_wide_out[i*N_TILES_X+j] ), + + .noc_south_req_i ( tile_south_req_in[i*N_TILES_X+j] ), + .noc_south_rsp_o ( tile_south_rsp_out[i*N_TILES_X+j] ), + .noc_south_wide_i ( tile_south_wide_in[i*N_TILES_X+j] ), + .noc_east_req_i ( tile_east_req_in[i*N_TILES_X+j] ), + .noc_east_rsp_o ( tile_east_rsp_out[i*N_TILES_X+j] ), + .noc_east_wide_i ( tile_east_wide_in[i*N_TILES_X+j] ), + .noc_north_req_i ( tile_north_req_in[i*N_TILES_X+j] ), + .noc_north_rsp_o ( tile_north_rsp_out[i*N_TILES_X+j] ), + .noc_north_wide_i ( tile_north_wide_in[i*N_TILES_X+j] ), + .noc_west_req_i ( tile_west_req_in[i*N_TILES_X+j] ), + .noc_west_rsp_o ( tile_west_rsp_out[i*N_TILES_X+j] ), + .noc_west_wide_i ( tile_west_wide_in[i*N_TILES_X+j] ), + + .x_id_i ( j ), + .y_id_i ( i ), - .ht_fsync_if_o ( ht_fsync_if[i*N_TILES_X+j] ), - .hn_fsync_if_o ( hn_fsync_if[i*N_TILES_X+j] ), - .vt_fsync_if_o ( vt_fsync_if[i*N_TILES_X+j] ), - .vn_fsync_if_o ( vn_fsync_if[i*N_TILES_X+j] ), + .ht_fsync_if_o ( ht_fsync_if[i*N_TILES_X+j] ), + .hn_fsync_if_o ( hn_fsync_if[i*N_TILES_X+j] ), + .vt_fsync_if_o ( vt_fsync_if[i*N_TILES_X+j] ), + .vn_fsync_if_o ( vn_fsync_if[i*N_TILES_X+j] ), - .scan_cg_en_i , + .scan_cg_en_i , - .boot_addr_i , - .mtvec_addr_i , - .dm_halt_addr_i , - .dm_exception_addr_i , - .mhartid_i ( mhartid[i*N_TILES_X+j] ), - .mimpid_patch_i , + .boot_addr_i , + .mtvec_addr_i , + .dm_halt_addr_i , + .dm_exception_addr_i , + .mhartid_i ( mhartid[i*N_TILES_X+j] ), + .mimpid_patch_i , - .mcycle_o ( mcycle_o[i*N_TILES_X+j] ), - .time_i , + .mcycle_o ( mcycle_o[i*N_TILES_X+j] ), + .time_i , - .irq_i ( irq_i[i*N_TILES_X+j] ), + .irq_i ( irq_i[i*N_TILES_X+j] ), - .debug_req_i , - .debug_havereset_o ( debug_havereset_o[i*N_TILES_X+j] ), - .debug_running_o ( debug_running_o[i*N_TILES_X+j] ), - .debug_halted_o ( debug_halted_o[i*N_TILES_X+j] ), - .debug_pc_valid_o ( debug_pc_valid_o[i*N_TILES_X+j] ), - .debug_pc_o ( debug_pc_o[i*N_TILES_X+j] ), + .debug_req_i , + .debug_havereset_o ( debug_havereset_o[i*N_TILES_X+j] ), + .debug_running_o ( debug_running_o[i*N_TILES_X+j] ), + .debug_halted_o ( debug_halted_o[i*N_TILES_X+j] ), + .debug_pc_valid_o ( debug_pc_valid_o[i*N_TILES_X+j] ), + .debug_pc_o ( debug_pc_o[i*N_TILES_X+j] ), - .fetch_enable_i , - .core_sleep_o ( core_sleep_o[i*N_TILES_X+j] ), + .fetch_enable_i , + .core_sleep_o ( core_sleep_o[i*N_TILES_X+j] ), .wu_wfe_i ); `ifdef CORE_TRACES @@ -234,95 +249,134 @@ module magia if (i == 0) begin if (j == 0) begin // T-L corner - assign tile_north_req_in[i*N_TILES_X+j] = '0; - assign tile_north_rsp_in[i*N_TILES_X+j] = '0; - assign tile_west_req_in[i*N_TILES_X+j] = l2_noc_req_i[i]; - assign l2_noc_rsp_o[i] = tile_west_rsp_out[i*N_TILES_X+j]; - assign l2_noc_req_o[i] = tile_west_req_out[i*N_TILES_X+j]; - assign tile_west_rsp_in[i*N_TILES_X+j] = l2_noc_rsp_i[i]; - assign tile_south_req_in[i*N_TILES_X+j] = tile_north_req_out[(i+1)*N_TILES_X+j]; - assign tile_south_rsp_in[i*N_TILES_X+j] = tile_north_rsp_out[(i+1)*N_TILES_X+j]; - assign tile_east_req_in[i*N_TILES_X+j] = tile_west_req_out[i*N_TILES_X+j+1]; - assign tile_east_rsp_in[i*N_TILES_X+j] = tile_west_rsp_out[i*N_TILES_X+j+1]; + assign tile_north_req_in[i*N_TILES_X+j] = '0; + assign tile_north_rsp_in[i*N_TILES_X+j] = '0; + assign tile_north_wide_in[i*N_TILES_X+j] = '0; + assign tile_west_req_in[i*N_TILES_X+j] = l2_noc_req_i[i]; + assign tile_west_rsp_in[i*N_TILES_X+j] = l2_noc_rsp_i[i]; + assign tile_west_wide_in[i*N_TILES_X+j] = l2_noc_wide_i[i]; + assign l2_noc_rsp_o[i] = tile_west_rsp_out[i*N_TILES_X+j]; + assign l2_noc_req_o[i] = tile_west_req_out[i*N_TILES_X+j]; + assign l2_noc_wide_o[i] = tile_west_wide_out[i*N_TILES_X+j]; + assign tile_south_req_in[i*N_TILES_X+j] = tile_north_req_out[(i+1)*N_TILES_X+j]; + assign tile_south_rsp_in[i*N_TILES_X+j] = tile_north_rsp_out[(i+1)*N_TILES_X+j]; + assign tile_south_wide_in[i*N_TILES_X+j] = tile_north_wide_out[(i+1)*N_TILES_X+j]; + assign tile_east_req_in[i*N_TILES_X+j] = tile_west_req_out[i*N_TILES_X+j+1]; + assign tile_east_rsp_in[i*N_TILES_X+j] = tile_west_rsp_out[i*N_TILES_X+j+1]; + assign tile_east_wide_in[i*N_TILES_X+j] = tile_west_wide_out[i*N_TILES_X+j+1]; end else if (j == N_TILES_X-1) begin // T-R corner - assign tile_north_req_in[i*N_TILES_X+j] = '0; - assign tile_north_rsp_in[i*N_TILES_X+j] = '0; - assign tile_west_req_in[i*N_TILES_X+j] = tile_east_req_out[i*N_TILES_X+j-1]; - assign tile_west_rsp_in[i*N_TILES_X+j] = tile_east_rsp_out[i*N_TILES_X+j-1]; - assign tile_south_req_in[i*N_TILES_X+j] = tile_north_req_out[(i+1)*N_TILES_X+j]; - assign tile_south_rsp_in[i*N_TILES_X+j] = tile_north_rsp_out[(i+1)*N_TILES_X+j]; - assign tile_east_req_in[i*N_TILES_X+j] = '0; - assign tile_east_rsp_in[i*N_TILES_X+j] = '0; + assign tile_north_req_in[i*N_TILES_X+j] = '0; + assign tile_north_rsp_in[i*N_TILES_X+j] = '0; + assign tile_north_wide_in[i*N_TILES_X+j] = '0; + assign tile_west_req_in[i*N_TILES_X+j] = tile_east_req_out[i*N_TILES_X+j-1]; + assign tile_west_rsp_in[i*N_TILES_X+j] = tile_east_rsp_out[i*N_TILES_X+j-1]; + assign tile_west_wide_in[i*N_TILES_X+j] = tile_east_wide_out[i*N_TILES_X+j-1]; + assign tile_south_req_in[i*N_TILES_X+j] = tile_north_req_out[(i+1)*N_TILES_X+j]; + assign tile_south_rsp_in[i*N_TILES_X+j] = tile_north_rsp_out[(i+1)*N_TILES_X+j]; + assign tile_south_wide_in[i*N_TILES_X+j] = tile_north_wide_out[(i+1)*N_TILES_X+j]; + assign tile_east_req_in[i*N_TILES_X+j] = '0; + assign tile_east_rsp_in[i*N_TILES_X+j] = '0; + assign tile_east_wide_in[i*N_TILES_X+j] = '0; end else if ((j > 0) && (j < (N_TILES_X-1))) begin // First row without corners - assign tile_north_req_in[i*N_TILES_X+j] = '0; - assign tile_north_rsp_in[i*N_TILES_X+j] = '0; - assign tile_west_req_in[i*N_TILES_X+j] = tile_east_req_out[i*N_TILES_X+j-1]; - assign tile_west_rsp_in[i*N_TILES_X+j] = tile_east_rsp_out[i*N_TILES_X+j-1]; - assign tile_south_req_in[i*N_TILES_X+j] = tile_north_req_out[(i+1)*N_TILES_X+j]; - assign tile_south_rsp_in[i*N_TILES_X+j] = tile_north_rsp_out[(i+1)*N_TILES_X+j]; - assign tile_east_req_in[i*N_TILES_X+j] = tile_west_req_out[i*N_TILES_X+j+1]; - assign tile_east_rsp_in[i*N_TILES_X+j] = tile_west_rsp_out[i*N_TILES_X+j+1]; + assign tile_north_req_in[i*N_TILES_X+j] = '0; + assign tile_north_rsp_in[i*N_TILES_X+j] = '0; + assign tile_north_wide_in[i*N_TILES_X+j] = '0; + assign tile_west_req_in[i*N_TILES_X+j] = tile_east_req_out[i*N_TILES_X+j-1]; + assign tile_west_rsp_in[i*N_TILES_X+j] = tile_east_rsp_out[i*N_TILES_X+j-1]; + assign tile_west_wide_in[i*N_TILES_X+j] = tile_east_wide_out[i*N_TILES_X+j-1]; + assign tile_south_req_in[i*N_TILES_X+j] = tile_north_req_out[(i+1)*N_TILES_X+j]; + assign tile_south_rsp_in[i*N_TILES_X+j] = tile_north_rsp_out[(i+1)*N_TILES_X+j]; + assign tile_south_wide_in[i*N_TILES_X+j] = tile_north_wide_out[(i+1)*N_TILES_X+j]; + assign tile_east_req_in[i*N_TILES_X+j] = tile_west_req_out[i*N_TILES_X+j+1]; + assign tile_east_rsp_in[i*N_TILES_X+j] = tile_west_rsp_out[i*N_TILES_X+j+1]; + assign tile_east_wide_in[i*N_TILES_X+j] = tile_west_wide_out[i*N_TILES_X+j+1]; end end else if (i == N_TILES_Y-1) begin if (j == 0) begin // B-L corner - assign tile_north_req_in[i*N_TILES_X+j] = tile_south_req_out[(i-1)*N_TILES_X+j]; - assign tile_north_rsp_in[i*N_TILES_X+j] = tile_south_rsp_out[(i-1)*N_TILES_X+j]; - assign tile_west_req_in[i*N_TILES_X+j] = l2_noc_req_i[i]; - assign l2_noc_rsp_o[i] = tile_west_rsp_out[i*N_TILES_X+j]; - assign l2_noc_req_o[i] = tile_west_req_out[i*N_TILES_X+j]; - assign tile_west_rsp_in[i*N_TILES_X+j] = l2_noc_rsp_i[i]; - assign tile_south_req_in[i*N_TILES_X+j] = '0; - assign tile_south_rsp_in[i*N_TILES_X+j] = '0; - assign tile_east_req_in[i*N_TILES_X+j] = tile_west_req_out[i*N_TILES_X+j+1]; - assign tile_east_rsp_in[i*N_TILES_X+j] = tile_west_rsp_out[i*N_TILES_X+j+1]; + assign tile_north_req_in[i*N_TILES_X+j] = tile_south_req_out[(i-1)*N_TILES_X+j]; + assign tile_north_rsp_in[i*N_TILES_X+j] = tile_south_rsp_out[(i-1)*N_TILES_X+j]; + assign tile_north_wide_in[i*N_TILES_X+j] = tile_south_wide_out[(i-1)*N_TILES_X+j]; + assign tile_west_req_in[i*N_TILES_X+j] = l2_noc_req_i[i]; + assign tile_west_rsp_in[i*N_TILES_X+j] = l2_noc_rsp_i[i]; + assign tile_west_wide_in[i*N_TILES_X+j] = l2_noc_wide_i[i]; + assign l2_noc_rsp_o[i] = tile_west_rsp_out[i*N_TILES_X+j]; + assign l2_noc_req_o[i] = tile_west_req_out[i*N_TILES_X+j]; + assign l2_noc_wide_o[i] = tile_west_wide_out[i*N_TILES_X+j]; + assign tile_south_req_in[i*N_TILES_X+j] = '0; + assign tile_south_rsp_in[i*N_TILES_X+j] = '0; + assign tile_south_wide_in[i*N_TILES_X+j] = '0; + assign tile_east_req_in[i*N_TILES_X+j] = tile_west_req_out[i*N_TILES_X+j+1]; + assign tile_east_rsp_in[i*N_TILES_X+j] = tile_west_rsp_out[i*N_TILES_X+j+1]; + assign tile_east_wide_in[i*N_TILES_X+j] = tile_west_wide_out[i*N_TILES_X+j+1]; end else if (j == N_TILES_X-1) begin // B-R corner - assign tile_north_req_in[i*N_TILES_X+j] = tile_south_req_out[(i-1)*N_TILES_X+j]; - assign tile_north_rsp_in[i*N_TILES_X+j] = tile_south_rsp_out[(i-1)*N_TILES_X+j]; - assign tile_west_req_in[i*N_TILES_X+j] = tile_east_req_out[i*N_TILES_X+j-1]; - assign tile_west_rsp_in[i*N_TILES_X+j] = tile_east_rsp_out[i*N_TILES_X+j-1]; - assign tile_south_req_in[i*N_TILES_X+j] = '0; - assign tile_south_rsp_in[i*N_TILES_X+j] = '0; - assign tile_east_req_in[i*N_TILES_X+j] = '0; - assign tile_east_rsp_in[i*N_TILES_X+j] = '0; + assign tile_north_req_in[i*N_TILES_X+j] = tile_south_req_out[(i-1)*N_TILES_X+j]; + assign tile_north_rsp_in[i*N_TILES_X+j] = tile_south_rsp_out[(i-1)*N_TILES_X+j]; + assign tile_north_wide_in[i*N_TILES_X+j] = tile_south_wide_out[(i-1)*N_TILES_X+j]; + assign tile_west_req_in[i*N_TILES_X+j] = tile_east_req_out[i*N_TILES_X+j-1]; + assign tile_west_rsp_in[i*N_TILES_X+j] = tile_east_rsp_out[i*N_TILES_X+j-1]; + assign tile_west_wide_in[i*N_TILES_X+j] = tile_east_wide_out[i*N_TILES_X+j-1]; + assign tile_south_req_in[i*N_TILES_X+j] = '0; + assign tile_south_rsp_in[i*N_TILES_X+j] = '0; + assign tile_south_wide_in[i*N_TILES_X+j] = '0; + assign tile_east_req_in[i*N_TILES_X+j] = '0; + assign tile_east_rsp_in[i*N_TILES_X+j] = '0; + assign tile_east_wide_in[i*N_TILES_X+j] = '0; end else if ((j > 0) && (j < (N_TILES_X-1))) begin // Last row without corners - assign tile_north_req_in[i*N_TILES_X+j] = tile_south_req_out[(i-1)*N_TILES_X+j]; - assign tile_north_rsp_in[i*N_TILES_X+j] = tile_south_rsp_out[(i-1)*N_TILES_X+j]; - assign tile_west_req_in[i*N_TILES_X+j] = tile_east_req_out[i*N_TILES_X+j-1]; - assign tile_west_rsp_in[i*N_TILES_X+j] = tile_east_rsp_out[i*N_TILES_X+j-1]; - assign tile_south_req_in[i*N_TILES_X+j] = '0; - assign tile_south_rsp_in[i*N_TILES_X+j] = '0; - assign tile_east_req_in[i*N_TILES_X+j] = tile_west_req_out[i*N_TILES_X+j+1]; - assign tile_east_rsp_in[i*N_TILES_X+j] = tile_west_rsp_out[i*N_TILES_X+j+1]; + assign tile_north_req_in[i*N_TILES_X+j] = tile_south_req_out[(i-1)*N_TILES_X+j]; + assign tile_north_rsp_in[i*N_TILES_X+j] = tile_south_rsp_out[(i-1)*N_TILES_X+j]; + assign tile_north_wide_in[i*N_TILES_X+j] = tile_south_wide_out[(i-1)*N_TILES_X+j]; + assign tile_west_req_in[i*N_TILES_X+j] = tile_east_req_out[i*N_TILES_X+j-1]; + assign tile_west_rsp_in[i*N_TILES_X+j] = tile_east_rsp_out[i*N_TILES_X+j-1]; + assign tile_west_wide_in[i*N_TILES_X+j] = tile_east_wide_out[i*N_TILES_X+j-1]; + assign tile_south_req_in[i*N_TILES_X+j] = '0; + assign tile_south_rsp_in[i*N_TILES_X+j] = '0; + assign tile_south_wide_in[i*N_TILES_X+j] = '0; + assign tile_east_req_in[i*N_TILES_X+j] = tile_west_req_out[i*N_TILES_X+j+1]; + assign tile_east_rsp_in[i*N_TILES_X+j] = tile_west_rsp_out[i*N_TILES_X+j+1]; + assign tile_east_wide_in[i*N_TILES_X+j] = tile_west_wide_out[i*N_TILES_X+j+1]; end end else if (j == 0 && i != 0 && i != N_TILES_Y-1) begin // First column - assign tile_north_req_in[i*N_TILES_X+j] = tile_south_req_out[(i-1)*N_TILES_X+j]; - assign tile_north_rsp_in[i*N_TILES_X+j] = tile_south_rsp_out[(i-1)*N_TILES_X+j]; - assign tile_west_req_in[i*N_TILES_X+j] = l2_noc_req_i[i]; - assign l2_noc_rsp_o[i] = tile_west_rsp_out[i*N_TILES_X+j]; - assign l2_noc_req_o[i] = tile_west_req_out[i*N_TILES_X+j]; - assign tile_west_rsp_in[i*N_TILES_X+j] = l2_noc_rsp_i[i]; - assign tile_south_req_in[i*N_TILES_X+j] = tile_north_req_out[(i+1)*N_TILES_X+j]; - assign tile_south_rsp_in[i*N_TILES_X+j] = tile_north_rsp_out[(i+1)*N_TILES_X+j]; - assign tile_east_req_in[i*N_TILES_X+j] = tile_west_req_out[i*N_TILES_X+j+1]; - assign tile_east_rsp_in[i*N_TILES_X+j] = tile_west_rsp_out[i*N_TILES_X+j+1]; + assign tile_north_req_in[i*N_TILES_X+j] = tile_south_req_out[(i-1)*N_TILES_X+j]; + assign tile_north_rsp_in[i*N_TILES_X+j] = tile_south_rsp_out[(i-1)*N_TILES_X+j]; + assign tile_north_wide_in[i*N_TILES_X+j] = tile_south_wide_out[(i-1)*N_TILES_X+j]; + assign tile_west_req_in[i*N_TILES_X+j] = l2_noc_req_i[i]; + assign tile_west_rsp_in[i*N_TILES_X+j] = l2_noc_rsp_i[i]; + assign tile_west_wide_in[i*N_TILES_X+j] = l2_noc_wide_i[i]; + assign l2_noc_rsp_o[i] = tile_west_rsp_out[i*N_TILES_X+j]; + assign l2_noc_req_o[i] = tile_west_req_out[i*N_TILES_X+j]; + assign l2_noc_wide_o[i] = tile_west_wide_out[i*N_TILES_X+j]; + assign tile_south_req_in[i*N_TILES_X+j] = tile_north_req_out[(i+1)*N_TILES_X+j]; + assign tile_south_rsp_in[i*N_TILES_X+j] = tile_north_rsp_out[(i+1)*N_TILES_X+j]; + assign tile_south_wide_in[i*N_TILES_X+j] = tile_north_wide_out[(i+1)*N_TILES_X+j]; + assign tile_east_req_in[i*N_TILES_X+j] = tile_west_req_out[i*N_TILES_X+j+1]; + assign tile_east_rsp_in[i*N_TILES_X+j] = tile_west_rsp_out[i*N_TILES_X+j+1]; + assign tile_east_wide_in[i*N_TILES_X+j] = tile_west_wide_out[i*N_TILES_X+j+1]; end else if (j == N_TILES_X-1 && i != 0 && i != N_TILES_Y-1) begin // Last column - assign tile_north_req_in[i*N_TILES_X+j] = tile_south_req_out[(i-1)*N_TILES_X+j]; - assign tile_north_rsp_in[i*N_TILES_X+j] = tile_south_rsp_out[(i-1)*N_TILES_X+j]; - assign tile_west_req_in[i*N_TILES_X+j] = tile_east_req_out[i*N_TILES_X+j-1]; - assign tile_west_rsp_in[i*N_TILES_X+j] = tile_east_rsp_out[i*N_TILES_X+j-1]; - assign tile_south_req_in[i*N_TILES_X+j] = tile_north_req_out[(i+1)*N_TILES_X+j]; - assign tile_south_rsp_in[i*N_TILES_X+j] = tile_north_rsp_out[(i+1)*N_TILES_X+j]; - assign tile_east_req_in[i*N_TILES_X+j] = '0; - assign tile_east_rsp_in[i*N_TILES_X+j] = '0; + assign tile_north_req_in[i*N_TILES_X+j] = tile_south_req_out[(i-1)*N_TILES_X+j]; + assign tile_north_rsp_in[i*N_TILES_X+j] = tile_south_rsp_out[(i-1)*N_TILES_X+j]; + assign tile_north_wide_in[i*N_TILES_X+j] = tile_south_wide_out[(i-1)*N_TILES_X+j]; + assign tile_west_req_in[i*N_TILES_X+j] = tile_east_req_out[i*N_TILES_X+j-1]; + assign tile_west_rsp_in[i*N_TILES_X+j] = tile_east_rsp_out[i*N_TILES_X+j-1]; + assign tile_west_wide_in[i*N_TILES_X+j] = tile_east_wide_out[i*N_TILES_X+j-1]; + assign tile_south_req_in[i*N_TILES_X+j] = tile_north_req_out[(i+1)*N_TILES_X+j]; + assign tile_south_rsp_in[i*N_TILES_X+j] = tile_north_rsp_out[(i+1)*N_TILES_X+j]; + assign tile_south_wide_in[i*N_TILES_X+j] = tile_north_wide_out[(i+1)*N_TILES_X+j]; + assign tile_east_req_in[i*N_TILES_X+j] = '0; + assign tile_east_rsp_in[i*N_TILES_X+j] = '0; + assign tile_east_wide_in[i*N_TILES_X+j] = '0; end else begin // Central tiles - assign tile_north_req_in[i*N_TILES_X+j] = tile_south_req_out[(i-1)*N_TILES_X+j]; - assign tile_north_rsp_in[i*N_TILES_X+j] = tile_south_rsp_out[(i-1)*N_TILES_X+j]; - assign tile_west_req_in[i*N_TILES_X+j] = tile_east_req_out[i*N_TILES_X+j-1]; - assign tile_west_rsp_in[i*N_TILES_X+j] = tile_east_rsp_out[i*N_TILES_X+j-1]; - assign tile_south_req_in[i*N_TILES_X+j] = tile_north_req_out[(i+1)*N_TILES_X+j]; - assign tile_south_rsp_in[i*N_TILES_X+j] = tile_north_rsp_out[(i+1)*N_TILES_X+j]; - assign tile_east_req_in[i*N_TILES_X+j] = tile_west_req_out[i*N_TILES_X+j+1]; - assign tile_east_rsp_in[i*N_TILES_X+j] = tile_west_rsp_out[i*N_TILES_X+j+1]; + assign tile_north_req_in[i*N_TILES_X+j] = tile_south_req_out[(i-1)*N_TILES_X+j]; + assign tile_north_rsp_in[i*N_TILES_X+j] = tile_south_rsp_out[(i-1)*N_TILES_X+j]; + assign tile_north_wide_in[i*N_TILES_X+j] = tile_south_wide_out[(i-1)*N_TILES_X+j]; + assign tile_west_req_in[i*N_TILES_X+j] = tile_east_req_out[i*N_TILES_X+j-1]; + assign tile_west_rsp_in[i*N_TILES_X+j] = tile_east_rsp_out[i*N_TILES_X+j-1]; + assign tile_west_wide_in[i*N_TILES_X+j] = tile_east_wide_out[i*N_TILES_X+j-1]; + assign tile_south_req_in[i*N_TILES_X+j] = tile_north_req_out[(i+1)*N_TILES_X+j]; + assign tile_south_rsp_in[i*N_TILES_X+j] = tile_north_rsp_out[(i+1)*N_TILES_X+j]; + assign tile_south_wide_in[i*N_TILES_X+j] = tile_north_wide_out[(i+1)*N_TILES_X+j]; + assign tile_east_req_in[i*N_TILES_X+j] = tile_west_req_out[i*N_TILES_X+j+1]; + assign tile_east_rsp_in[i*N_TILES_X+j] = tile_west_rsp_out[i*N_TILES_X+j+1]; + assign tile_east_wide_in[i*N_TILES_X+j] = tile_west_wide_out[i*N_TILES_X+j+1]; end end end diff --git a/hw/mesh/magia_pkg.sv b/hw/mesh/magia_pkg.sv index 88852a9..4b62bc6 100644 --- a/hw/mesh/magia_pkg.sv +++ b/hw/mesh/magia_pkg.sv @@ -32,6 +32,8 @@ package magia_pkg; localparam int unsigned INSTR_W = 32; // System-wide instruction Width localparam int unsigned BYTE_W = 8; // System-wide byte Width localparam int unsigned STRB_W = DATA_W/BYTE_W; // System-wide strobe Width + localparam int unsigned WIDE_DATA_W = 256; // System-wide wide communication channel Width + localparam int unsigned WIDE_STRB_W = WIDE_DATA_W/BYTE_W; // System-wide wide communication strobe Width localparam int unsigned N_MEM_BANKS = 32; // Number of TCDM banks (1 extra bank for missaligned accesses) localparam int unsigned N_WORDS_BANK = 8192; // Number of words per TCDM bank localparam int unsigned N_TILES_Y = 4; // Number of Tile rowns @@ -68,7 +70,8 @@ package magia_pkg; `AXI_ALIAS(noc_axi_data, axi_xbar_mst, noc_axi_data_req_t, axi_xbar_mst_req_t, noc_axi_data_rsp_t, axi_xbar_mst_rsp_t) `AXI_ALIAS(noc_axi_data, axi_default, noc_axi_data_req_t, axi_default_req_t, noc_axi_data_rsp_t, axi_default_rsp_t) - `AXI_TYPEDEF_ALL_CT(axi_l2, axi_l2_req_t, axi_l2_rsp_t, logic[ADDR_W-1:0], logic[L2_ID_W-1:0], logic[DATA_W-1:0], logic[STRB_W-1:0], logic[L2_U_W-1:0]) + `AXI_TYPEDEF_ALL_CT(axi_narrow_l2, axi_narrow_l2_req_t, axi_narrow_l2_rsp_t, logic[ADDR_W-1:0], logic[L2_ID_W-1:0], logic[DATA_W-1:0], logic[STRB_W-1:0], logic[L2_U_W-1:0]) + `AXI_TYPEDEF_ALL_CT(axi_wide_l2, axi_wide_l2_req_t, axi_wide_l2_rsp_t, logic[ADDR_W-1:0], logic[L2_ID_W-1:0], logic[WIDE_DATA_W-1:0], logic[WIDE_STRB_W-1:0], logic[L2_U_W-1:0]) `FSYNC_TYPEDEF_ALL(h_root_fsync, logic[ROOT_FSYNC_AGGR_W-1:0], logic[ROOT_FSYNC_LVL_W-1:0], logic[ROOT_FSYNC_ID_W-1:0]) `FSYNC_TYPEDEF_ALL(v_root_fsync, logic[ROOT_FSYNC_AGGR_W-1:0], logic[ROOT_FSYNC_LVL_W-1:0], logic[ROOT_FSYNC_ID_W-1:0]) diff --git a/hw/mesh/noc/floo_axi_mesh_2x2_noc.sv b/hw/mesh/noc/floo_axi_mesh_2x2_noc.sv deleted file mode 100644 index a1a73f3..0000000 --- a/hw/mesh/noc/floo_axi_mesh_2x2_noc.sv +++ /dev/null @@ -1,99 +0,0 @@ -// Copyright 2025 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// AUTOMATICALLY GENERATED! DO NOT EDIT! - -`include "axi/typedef.svh" -`include "floo_noc/typedef.svh" - -package floo_axi_mesh_2x2_noc_pkg; - - import floo_pkg::*; - - ///////////////////// - // Address Map // - ///////////////////// - - typedef enum logic[2:0] { - MagiaTileX0Y0 = 0, - MagiaTileX0Y1 = 1, - MagiaTileX1Y0 = 2, - MagiaTileX1Y1 = 3, - L20 = 4, - L21 = 5, - NumEndpoints = 6} ep_id_e; - - - - typedef logic[0:0] rob_idx_t; -typedef logic[0:0] port_id_t; -typedef logic[1:0] x_bits_t; -typedef logic[0:0] y_bits_t; -typedef struct packed { - x_bits_t x; - y_bits_t y; - port_id_t port_id; -} id_t; - -typedef logic route_t; - - - localparam int unsigned SamNumRules = 6; - -typedef struct packed { - id_t idx; - logic [31:0] start_addr; - logic [31:0] end_addr; -} sam_rule_t; - -localparam sam_rule_t[SamNumRules-1:0] Sam = '{ -'{idx: '{x: 0, y: 1, port_id: 0}, start_addr: 32'he0000000, end_addr: 32'h100000000},// L2_1_sam_idx -'{idx: '{x: 0, y: 0, port_id: 0}, start_addr: 32'hc0000000, end_addr: 32'he0000000},// L2_0_sam_idx -'{idx: '{x: 2, y: 1, port_id: 0}, start_addr: 32'h00300000, end_addr: 32'h00400000},// magia_tile_x1_y1_sam_idx -'{idx: '{x: 1, y: 1, port_id: 0}, start_addr: 32'h00200000, end_addr: 32'h00300000},// magia_tile_x0_y1_sam_idx -'{idx: '{x: 2, y: 0, port_id: 0}, start_addr: 32'h00100000, end_addr: 32'h00200000},// magia_tile_x1_y0_sam_idx -'{idx: '{x: 1, y: 0, port_id: 0}, start_addr: 32'h00000000, end_addr: 32'h00100000} // magia_tile_x0_y0_sam_idx - -}; - - - - localparam route_cfg_t RouteCfg = '{ RouteAlgo: XYRouting, - UseIdTable: 1'b1, - XYAddrOffsetX: 32, - XYAddrOffsetY: 34, - IdAddrOffset: 0, - NumSamRules: 6, - NumRoutes: 0}; - - - typedef logic[31:0] axi_data_mst_addr_t; -typedef logic[31:0] axi_data_mst_data_t; -typedef logic[3:0] axi_data_mst_strb_t; -typedef logic[1:0] axi_data_mst_id_t; -typedef logic[0:0] axi_data_mst_user_t; -`AXI_TYPEDEF_ALL_CT(axi_data_mst, axi_data_mst_req_t, axi_data_mst_rsp_t, axi_data_mst_addr_t, axi_data_mst_id_t, axi_data_mst_data_t, axi_data_mst_strb_t, axi_data_mst_user_t) - - - typedef logic[31:0] axi_data_slv_addr_t; -typedef logic[31:0] axi_data_slv_data_t; -typedef logic[3:0] axi_data_slv_strb_t; -typedef logic[3:0] axi_data_slv_id_t; -typedef logic[0:0] axi_data_slv_user_t; -`AXI_TYPEDEF_ALL_CT(axi_data_slv, axi_data_slv_req_t, axi_data_slv_rsp_t, axi_data_slv_addr_t, axi_data_slv_id_t, axi_data_slv_data_t, axi_data_slv_strb_t, axi_data_slv_user_t) - - - - `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, axi_ch_e, rob_idx_t) - localparam axi_cfg_t AxiCfg = '{ AddrWidth: 32, - DataWidth: 32, - UserWidth: 1, - InIdWidth: 4, - OutIdWidth: 2}; -`FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi_data_slv, AxiCfg, hdr_t) - -`FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, req, rsp) - - -endpackage diff --git a/hw/mesh/noc/floo_axi_mesh_16x16_noc.sv b/hw/mesh/noc/floo_axi_nw_mesh_16x16_noc.sv similarity index 93% rename from hw/mesh/noc/floo_axi_mesh_16x16_noc.sv rename to hw/mesh/noc/floo_axi_nw_mesh_16x16_noc.sv index 22c3f43..c28a32d 100644 --- a/hw/mesh/noc/floo_axi_mesh_16x16_noc.sv +++ b/hw/mesh/noc/floo_axi_nw_mesh_16x16_noc.sv @@ -7,7 +7,7 @@ `include "axi/typedef.svh" `include "floo_noc/typedef.svh" -package floo_axi_mesh_16x16_noc_pkg; +package floo_axi_nw_mesh_16x16_noc_pkg; import floo_pkg::*; @@ -600,32 +600,53 @@ localparam sam_rule_t[SamNumRules-1:0] Sam = '{ NumRoutes: 0}; - typedef logic[31:0] axi_data_mst_addr_t; -typedef logic[31:0] axi_data_mst_data_t; -typedef logic[3:0] axi_data_mst_strb_t; -typedef logic[1:0] axi_data_mst_id_t; -typedef logic[0:0] axi_data_mst_user_t; -`AXI_TYPEDEF_ALL_CT(axi_data_mst, axi_data_mst_req_t, axi_data_mst_rsp_t, axi_data_mst_addr_t, axi_data_mst_id_t, axi_data_mst_data_t, axi_data_mst_strb_t, axi_data_mst_user_t) + typedef logic[31:0] axi_narrow_data_mst_addr_t; +typedef logic[31:0] axi_narrow_data_mst_data_t; +typedef logic[3:0] axi_narrow_data_mst_strb_t; +typedef logic[1:0] axi_narrow_data_mst_id_t; +typedef logic[0:0] axi_narrow_data_mst_user_t; +`AXI_TYPEDEF_ALL_CT(axi_narrow_data_mst, axi_narrow_data_mst_req_t, axi_narrow_data_mst_rsp_t, axi_narrow_data_mst_addr_t, axi_narrow_data_mst_id_t, axi_narrow_data_mst_data_t, axi_narrow_data_mst_strb_t, axi_narrow_data_mst_user_t) - typedef logic[31:0] axi_data_slv_addr_t; -typedef logic[31:0] axi_data_slv_data_t; -typedef logic[3:0] axi_data_slv_strb_t; -typedef logic[3:0] axi_data_slv_id_t; -typedef logic[0:0] axi_data_slv_user_t; -`AXI_TYPEDEF_ALL_CT(axi_data_slv, axi_data_slv_req_t, axi_data_slv_rsp_t, axi_data_slv_addr_t, axi_data_slv_id_t, axi_data_slv_data_t, axi_data_slv_strb_t, axi_data_slv_user_t) + typedef logic[31:0] axi_narrow_data_slv_addr_t; +typedef logic[31:0] axi_narrow_data_slv_data_t; +typedef logic[3:0] axi_narrow_data_slv_strb_t; +typedef logic[3:0] axi_narrow_data_slv_id_t; +typedef logic[0:0] axi_narrow_data_slv_user_t; +`AXI_TYPEDEF_ALL_CT(axi_narrow_data_slv, axi_narrow_data_slv_req_t, axi_narrow_data_slv_rsp_t, axi_narrow_data_slv_addr_t, axi_narrow_data_slv_id_t, axi_narrow_data_slv_data_t, axi_narrow_data_slv_strb_t, axi_narrow_data_slv_user_t) + typedef logic[31:0] axi_wide_data_mst_addr_t; +typedef logic[255:0] axi_wide_data_mst_data_t; +typedef logic[31:0] axi_wide_data_mst_strb_t; +typedef logic[1:0] axi_wide_data_mst_id_t; +typedef logic[0:0] axi_wide_data_mst_user_t; +`AXI_TYPEDEF_ALL_CT(axi_wide_data_mst, axi_wide_data_mst_req_t, axi_wide_data_mst_rsp_t, axi_wide_data_mst_addr_t, axi_wide_data_mst_id_t, axi_wide_data_mst_data_t, axi_wide_data_mst_strb_t, axi_wide_data_mst_user_t) - `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, axi_ch_e, rob_idx_t) - localparam axi_cfg_t AxiCfg = '{ AddrWidth: 32, + + typedef logic[31:0] axi_wide_data_slv_addr_t; +typedef logic[255:0] axi_wide_data_slv_data_t; +typedef logic[31:0] axi_wide_data_slv_strb_t; +typedef logic[1:0] axi_wide_data_slv_id_t; +typedef logic[0:0] axi_wide_data_slv_user_t; +`AXI_TYPEDEF_ALL_CT(axi_wide_data_slv, axi_wide_data_slv_req_t, axi_wide_data_slv_rsp_t, axi_wide_data_slv_addr_t, axi_wide_data_slv_id_t, axi_wide_data_slv_data_t, axi_wide_data_slv_strb_t, axi_wide_data_slv_user_t) + + + + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, nw_ch_e, rob_idx_t) + localparam axi_cfg_t AxiCfgN = '{ AddrWidth: 32, DataWidth: 32, UserWidth: 1, InIdWidth: 4, OutIdWidth: 2}; -`FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi_data_slv, AxiCfg, hdr_t) +localparam axi_cfg_t AxiCfgW = '{ AddrWidth: 32, + DataWidth: 256, + UserWidth: 1, + InIdWidth: 2, + OutIdWidth: 2}; +`FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_data_slv, axi_wide_data_slv, AxiCfgN, AxiCfgW, hdr_t) -`FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, req, rsp) +`FLOO_TYPEDEF_NW_LINK_ALL(req, rsp, wide, req, rsp, wide) endpackage diff --git a/hw/mesh/noc/floo_axi_nw_mesh_2x2_noc.sv b/hw/mesh/noc/floo_axi_nw_mesh_2x2_noc.sv new file mode 100644 index 0000000..6ccb4a7 --- /dev/null +++ b/hw/mesh/noc/floo_axi_nw_mesh_2x2_noc.sv @@ -0,0 +1,120 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// AUTOMATICALLY GENERATED! DO NOT EDIT! + +`include "axi/typedef.svh" +`include "floo_noc/typedef.svh" + +package floo_axi_nw_mesh_2x2_noc_pkg; + + import floo_pkg::*; + + ///////////////////// + // Address Map // + ///////////////////// + + typedef enum logic[2:0] { + MagiaTileX0Y0 = 0, + MagiaTileX0Y1 = 1, + MagiaTileX1Y0 = 2, + MagiaTileX1Y1 = 3, + L20 = 4, + L21 = 5, + NumEndpoints = 6} ep_id_e; + + + + typedef logic[0:0] rob_idx_t; +typedef logic[0:0] port_id_t; +typedef logic[1:0] x_bits_t; +typedef logic[0:0] y_bits_t; +typedef struct packed { + x_bits_t x; + y_bits_t y; + port_id_t port_id; +} id_t; + +typedef logic route_t; + + + localparam int unsigned SamNumRules = 6; + +typedef struct packed { + id_t idx; + logic [31:0] start_addr; + logic [31:0] end_addr; +} sam_rule_t; + +localparam sam_rule_t[SamNumRules-1:0] Sam = '{ +'{idx: '{x: 0, y: 1, port_id: 0}, start_addr: 32'he0000000, end_addr: 32'h100000000},// L2_1_sam_idx +'{idx: '{x: 0, y: 0, port_id: 0}, start_addr: 32'hc0000000, end_addr: 32'he0000000},// L2_0_sam_idx +'{idx: '{x: 2, y: 1, port_id: 0}, start_addr: 32'h00300000, end_addr: 32'h00400000},// magia_tile_x1_y1_sam_idx +'{idx: '{x: 1, y: 1, port_id: 0}, start_addr: 32'h00200000, end_addr: 32'h00300000},// magia_tile_x0_y1_sam_idx +'{idx: '{x: 2, y: 0, port_id: 0}, start_addr: 32'h00100000, end_addr: 32'h00200000},// magia_tile_x1_y0_sam_idx +'{idx: '{x: 1, y: 0, port_id: 0}, start_addr: 32'h00000000, end_addr: 32'h00100000} // magia_tile_x0_y0_sam_idx + +}; + + + + localparam route_cfg_t RouteCfg = '{ RouteAlgo: XYRouting, + UseIdTable: 1'b1, + XYAddrOffsetX: 32, + XYAddrOffsetY: 34, + IdAddrOffset: 0, + NumSamRules: 6, + NumRoutes: 0}; + + + typedef logic[31:0] axi_narrow_data_mst_addr_t; +typedef logic[31:0] axi_narrow_data_mst_data_t; +typedef logic[3:0] axi_narrow_data_mst_strb_t; +typedef logic[1:0] axi_narrow_data_mst_id_t; +typedef logic[0:0] axi_narrow_data_mst_user_t; +`AXI_TYPEDEF_ALL_CT(axi_narrow_data_mst, axi_narrow_data_mst_req_t, axi_narrow_data_mst_rsp_t, axi_narrow_data_mst_addr_t, axi_narrow_data_mst_id_t, axi_narrow_data_mst_data_t, axi_narrow_data_mst_strb_t, axi_narrow_data_mst_user_t) + + + typedef logic[31:0] axi_narrow_data_slv_addr_t; +typedef logic[31:0] axi_narrow_data_slv_data_t; +typedef logic[3:0] axi_narrow_data_slv_strb_t; +typedef logic[3:0] axi_narrow_data_slv_id_t; +typedef logic[0:0] axi_narrow_data_slv_user_t; +`AXI_TYPEDEF_ALL_CT(axi_narrow_data_slv, axi_narrow_data_slv_req_t, axi_narrow_data_slv_rsp_t, axi_narrow_data_slv_addr_t, axi_narrow_data_slv_id_t, axi_narrow_data_slv_data_t, axi_narrow_data_slv_strb_t, axi_narrow_data_slv_user_t) + + + typedef logic[31:0] axi_wide_data_mst_addr_t; +typedef logic[255:0] axi_wide_data_mst_data_t; +typedef logic[31:0] axi_wide_data_mst_strb_t; +typedef logic[1:0] axi_wide_data_mst_id_t; +typedef logic[0:0] axi_wide_data_mst_user_t; +`AXI_TYPEDEF_ALL_CT(axi_wide_data_mst, axi_wide_data_mst_req_t, axi_wide_data_mst_rsp_t, axi_wide_data_mst_addr_t, axi_wide_data_mst_id_t, axi_wide_data_mst_data_t, axi_wide_data_mst_strb_t, axi_wide_data_mst_user_t) + + + typedef logic[31:0] axi_wide_data_slv_addr_t; +typedef logic[255:0] axi_wide_data_slv_data_t; +typedef logic[31:0] axi_wide_data_slv_strb_t; +typedef logic[1:0] axi_wide_data_slv_id_t; +typedef logic[0:0] axi_wide_data_slv_user_t; +`AXI_TYPEDEF_ALL_CT(axi_wide_data_slv, axi_wide_data_slv_req_t, axi_wide_data_slv_rsp_t, axi_wide_data_slv_addr_t, axi_wide_data_slv_id_t, axi_wide_data_slv_data_t, axi_wide_data_slv_strb_t, axi_wide_data_slv_user_t) + + + + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, nw_ch_e, rob_idx_t) + localparam axi_cfg_t AxiCfgN = '{ AddrWidth: 32, + DataWidth: 32, + UserWidth: 1, + InIdWidth: 4, + OutIdWidth: 2}; +localparam axi_cfg_t AxiCfgW = '{ AddrWidth: 32, + DataWidth: 256, + UserWidth: 1, + InIdWidth: 2, + OutIdWidth: 2}; +`FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_data_slv, axi_wide_data_slv, AxiCfgN, AxiCfgW, hdr_t) + +`FLOO_TYPEDEF_NW_LINK_ALL(req, rsp, wide, req, rsp, wide) + + +endpackage diff --git a/hw/mesh/noc/floo_axi_mesh_32x32_noc.sv b/hw/mesh/noc/floo_axi_nw_mesh_32x32_noc.sv similarity index 98% rename from hw/mesh/noc/floo_axi_mesh_32x32_noc.sv rename to hw/mesh/noc/floo_axi_nw_mesh_32x32_noc.sv index 05e14d1..05a6266 100644 --- a/hw/mesh/noc/floo_axi_mesh_32x32_noc.sv +++ b/hw/mesh/noc/floo_axi_nw_mesh_32x32_noc.sv @@ -7,7 +7,7 @@ `include "axi/typedef.svh" `include "floo_noc/typedef.svh" -package floo_axi_mesh_32x32_noc_pkg; +package floo_axi_nw_mesh_32x32_noc_pkg; import floo_pkg::*; @@ -2168,32 +2168,53 @@ localparam sam_rule_t[SamNumRules-1:0] Sam = '{ NumRoutes: 0}; - typedef logic[31:0] axi_data_mst_addr_t; -typedef logic[31:0] axi_data_mst_data_t; -typedef logic[3:0] axi_data_mst_strb_t; -typedef logic[1:0] axi_data_mst_id_t; -typedef logic[0:0] axi_data_mst_user_t; -`AXI_TYPEDEF_ALL_CT(axi_data_mst, axi_data_mst_req_t, axi_data_mst_rsp_t, axi_data_mst_addr_t, axi_data_mst_id_t, axi_data_mst_data_t, axi_data_mst_strb_t, axi_data_mst_user_t) + typedef logic[31:0] axi_narrow_data_mst_addr_t; +typedef logic[31:0] axi_narrow_data_mst_data_t; +typedef logic[3:0] axi_narrow_data_mst_strb_t; +typedef logic[1:0] axi_narrow_data_mst_id_t; +typedef logic[0:0] axi_narrow_data_mst_user_t; +`AXI_TYPEDEF_ALL_CT(axi_narrow_data_mst, axi_narrow_data_mst_req_t, axi_narrow_data_mst_rsp_t, axi_narrow_data_mst_addr_t, axi_narrow_data_mst_id_t, axi_narrow_data_mst_data_t, axi_narrow_data_mst_strb_t, axi_narrow_data_mst_user_t) - typedef logic[31:0] axi_data_slv_addr_t; -typedef logic[31:0] axi_data_slv_data_t; -typedef logic[3:0] axi_data_slv_strb_t; -typedef logic[3:0] axi_data_slv_id_t; -typedef logic[0:0] axi_data_slv_user_t; -`AXI_TYPEDEF_ALL_CT(axi_data_slv, axi_data_slv_req_t, axi_data_slv_rsp_t, axi_data_slv_addr_t, axi_data_slv_id_t, axi_data_slv_data_t, axi_data_slv_strb_t, axi_data_slv_user_t) + typedef logic[31:0] axi_narrow_data_slv_addr_t; +typedef logic[31:0] axi_narrow_data_slv_data_t; +typedef logic[3:0] axi_narrow_data_slv_strb_t; +typedef logic[3:0] axi_narrow_data_slv_id_t; +typedef logic[0:0] axi_narrow_data_slv_user_t; +`AXI_TYPEDEF_ALL_CT(axi_narrow_data_slv, axi_narrow_data_slv_req_t, axi_narrow_data_slv_rsp_t, axi_narrow_data_slv_addr_t, axi_narrow_data_slv_id_t, axi_narrow_data_slv_data_t, axi_narrow_data_slv_strb_t, axi_narrow_data_slv_user_t) + typedef logic[31:0] axi_wide_data_mst_addr_t; +typedef logic[255:0] axi_wide_data_mst_data_t; +typedef logic[31:0] axi_wide_data_mst_strb_t; +typedef logic[1:0] axi_wide_data_mst_id_t; +typedef logic[0:0] axi_wide_data_mst_user_t; +`AXI_TYPEDEF_ALL_CT(axi_wide_data_mst, axi_wide_data_mst_req_t, axi_wide_data_mst_rsp_t, axi_wide_data_mst_addr_t, axi_wide_data_mst_id_t, axi_wide_data_mst_data_t, axi_wide_data_mst_strb_t, axi_wide_data_mst_user_t) - `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, axi_ch_e, rob_idx_t) - localparam axi_cfg_t AxiCfg = '{ AddrWidth: 32, + + typedef logic[31:0] axi_wide_data_slv_addr_t; +typedef logic[255:0] axi_wide_data_slv_data_t; +typedef logic[31:0] axi_wide_data_slv_strb_t; +typedef logic[1:0] axi_wide_data_slv_id_t; +typedef logic[0:0] axi_wide_data_slv_user_t; +`AXI_TYPEDEF_ALL_CT(axi_wide_data_slv, axi_wide_data_slv_req_t, axi_wide_data_slv_rsp_t, axi_wide_data_slv_addr_t, axi_wide_data_slv_id_t, axi_wide_data_slv_data_t, axi_wide_data_slv_strb_t, axi_wide_data_slv_user_t) + + + + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, nw_ch_e, rob_idx_t) + localparam axi_cfg_t AxiCfgN = '{ AddrWidth: 32, DataWidth: 32, UserWidth: 1, InIdWidth: 4, OutIdWidth: 2}; -`FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi_data_slv, AxiCfg, hdr_t) +localparam axi_cfg_t AxiCfgW = '{ AddrWidth: 32, + DataWidth: 256, + UserWidth: 1, + InIdWidth: 2, + OutIdWidth: 2}; +`FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_data_slv, axi_wide_data_slv, AxiCfgN, AxiCfgW, hdr_t) -`FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, req, rsp) +`FLOO_TYPEDEF_NW_LINK_ALL(req, rsp, wide, req, rsp, wide) endpackage diff --git a/hw/mesh/noc/floo_axi_mesh_4x4_noc.sv b/hw/mesh/noc/floo_axi_nw_mesh_4x4_noc.sv similarity index 58% rename from hw/mesh/noc/floo_axi_mesh_4x4_noc.sv rename to hw/mesh/noc/floo_axi_nw_mesh_4x4_noc.sv index 38b4156..56e6929 100644 --- a/hw/mesh/noc/floo_axi_mesh_4x4_noc.sv +++ b/hw/mesh/noc/floo_axi_nw_mesh_4x4_noc.sv @@ -7,7 +7,7 @@ `include "axi/typedef.svh" `include "floo_noc/typedef.svh" -package floo_axi_mesh_4x4_noc_pkg; +package floo_axi_nw_mesh_4x4_noc_pkg; import floo_pkg::*; @@ -96,32 +96,53 @@ localparam sam_rule_t[SamNumRules-1:0] Sam = '{ NumRoutes: 0}; - typedef logic[31:0] axi_data_mst_addr_t; -typedef logic[31:0] axi_data_mst_data_t; -typedef logic[3:0] axi_data_mst_strb_t; -typedef logic[1:0] axi_data_mst_id_t; -typedef logic[0:0] axi_data_mst_user_t; -`AXI_TYPEDEF_ALL_CT(axi_data_mst, axi_data_mst_req_t, axi_data_mst_rsp_t, axi_data_mst_addr_t, axi_data_mst_id_t, axi_data_mst_data_t, axi_data_mst_strb_t, axi_data_mst_user_t) + typedef logic[31:0] axi_narrow_data_mst_addr_t; +typedef logic[31:0] axi_narrow_data_mst_data_t; +typedef logic[3:0] axi_narrow_data_mst_strb_t; +typedef logic[1:0] axi_narrow_data_mst_id_t; +typedef logic[0:0] axi_narrow_data_mst_user_t; +`AXI_TYPEDEF_ALL_CT(axi_narrow_data_mst, axi_narrow_data_mst_req_t, axi_narrow_data_mst_rsp_t, axi_narrow_data_mst_addr_t, axi_narrow_data_mst_id_t, axi_narrow_data_mst_data_t, axi_narrow_data_mst_strb_t, axi_narrow_data_mst_user_t) - typedef logic[31:0] axi_data_slv_addr_t; -typedef logic[31:0] axi_data_slv_data_t; -typedef logic[3:0] axi_data_slv_strb_t; -typedef logic[3:0] axi_data_slv_id_t; -typedef logic[0:0] axi_data_slv_user_t; -`AXI_TYPEDEF_ALL_CT(axi_data_slv, axi_data_slv_req_t, axi_data_slv_rsp_t, axi_data_slv_addr_t, axi_data_slv_id_t, axi_data_slv_data_t, axi_data_slv_strb_t, axi_data_slv_user_t) + typedef logic[31:0] axi_narrow_data_slv_addr_t; +typedef logic[31:0] axi_narrow_data_slv_data_t; +typedef logic[3:0] axi_narrow_data_slv_strb_t; +typedef logic[3:0] axi_narrow_data_slv_id_t; +typedef logic[0:0] axi_narrow_data_slv_user_t; +`AXI_TYPEDEF_ALL_CT(axi_narrow_data_slv, axi_narrow_data_slv_req_t, axi_narrow_data_slv_rsp_t, axi_narrow_data_slv_addr_t, axi_narrow_data_slv_id_t, axi_narrow_data_slv_data_t, axi_narrow_data_slv_strb_t, axi_narrow_data_slv_user_t) + typedef logic[31:0] axi_wide_data_mst_addr_t; +typedef logic[255:0] axi_wide_data_mst_data_t; +typedef logic[31:0] axi_wide_data_mst_strb_t; +typedef logic[1:0] axi_wide_data_mst_id_t; +typedef logic[0:0] axi_wide_data_mst_user_t; +`AXI_TYPEDEF_ALL_CT(axi_wide_data_mst, axi_wide_data_mst_req_t, axi_wide_data_mst_rsp_t, axi_wide_data_mst_addr_t, axi_wide_data_mst_id_t, axi_wide_data_mst_data_t, axi_wide_data_mst_strb_t, axi_wide_data_mst_user_t) - `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, axi_ch_e, rob_idx_t) - localparam axi_cfg_t AxiCfg = '{ AddrWidth: 32, + + typedef logic[31:0] axi_wide_data_slv_addr_t; +typedef logic[255:0] axi_wide_data_slv_data_t; +typedef logic[31:0] axi_wide_data_slv_strb_t; +typedef logic[1:0] axi_wide_data_slv_id_t; +typedef logic[0:0] axi_wide_data_slv_user_t; +`AXI_TYPEDEF_ALL_CT(axi_wide_data_slv, axi_wide_data_slv_req_t, axi_wide_data_slv_rsp_t, axi_wide_data_slv_addr_t, axi_wide_data_slv_id_t, axi_wide_data_slv_data_t, axi_wide_data_slv_strb_t, axi_wide_data_slv_user_t) + + + + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, nw_ch_e, rob_idx_t) + localparam axi_cfg_t AxiCfgN = '{ AddrWidth: 32, DataWidth: 32, UserWidth: 1, InIdWidth: 4, OutIdWidth: 2}; -`FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi_data_slv, AxiCfg, hdr_t) +localparam axi_cfg_t AxiCfgW = '{ AddrWidth: 32, + DataWidth: 256, + UserWidth: 1, + InIdWidth: 2, + OutIdWidth: 2}; +`FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_data_slv, axi_wide_data_slv, AxiCfgN, AxiCfgW, hdr_t) -`FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, req, rsp) +`FLOO_TYPEDEF_NW_LINK_ALL(req, rsp, wide, req, rsp, wide) endpackage diff --git a/hw/mesh/noc/floo_axi_mesh_8x8_noc.sv b/hw/mesh/noc/floo_axi_nw_mesh_8x8_noc.sv similarity index 80% rename from hw/mesh/noc/floo_axi_mesh_8x8_noc.sv rename to hw/mesh/noc/floo_axi_nw_mesh_8x8_noc.sv index 90483b5..67e35dc 100644 --- a/hw/mesh/noc/floo_axi_mesh_8x8_noc.sv +++ b/hw/mesh/noc/floo_axi_nw_mesh_8x8_noc.sv @@ -7,7 +7,7 @@ `include "axi/typedef.svh" `include "floo_noc/typedef.svh" -package floo_axi_mesh_8x8_noc_pkg; +package floo_axi_nw_mesh_8x8_noc_pkg; import floo_pkg::*; @@ -200,32 +200,53 @@ localparam sam_rule_t[SamNumRules-1:0] Sam = '{ NumRoutes: 0}; - typedef logic[31:0] axi_data_mst_addr_t; -typedef logic[31:0] axi_data_mst_data_t; -typedef logic[3:0] axi_data_mst_strb_t; -typedef logic[1:0] axi_data_mst_id_t; -typedef logic[0:0] axi_data_mst_user_t; -`AXI_TYPEDEF_ALL_CT(axi_data_mst, axi_data_mst_req_t, axi_data_mst_rsp_t, axi_data_mst_addr_t, axi_data_mst_id_t, axi_data_mst_data_t, axi_data_mst_strb_t, axi_data_mst_user_t) + typedef logic[31:0] axi_narrow_data_mst_addr_t; +typedef logic[31:0] axi_narrow_data_mst_data_t; +typedef logic[3:0] axi_narrow_data_mst_strb_t; +typedef logic[1:0] axi_narrow_data_mst_id_t; +typedef logic[0:0] axi_narrow_data_mst_user_t; +`AXI_TYPEDEF_ALL_CT(axi_narrow_data_mst, axi_narrow_data_mst_req_t, axi_narrow_data_mst_rsp_t, axi_narrow_data_mst_addr_t, axi_narrow_data_mst_id_t, axi_narrow_data_mst_data_t, axi_narrow_data_mst_strb_t, axi_narrow_data_mst_user_t) - typedef logic[31:0] axi_data_slv_addr_t; -typedef logic[31:0] axi_data_slv_data_t; -typedef logic[3:0] axi_data_slv_strb_t; -typedef logic[3:0] axi_data_slv_id_t; -typedef logic[0:0] axi_data_slv_user_t; -`AXI_TYPEDEF_ALL_CT(axi_data_slv, axi_data_slv_req_t, axi_data_slv_rsp_t, axi_data_slv_addr_t, axi_data_slv_id_t, axi_data_slv_data_t, axi_data_slv_strb_t, axi_data_slv_user_t) + typedef logic[31:0] axi_narrow_data_slv_addr_t; +typedef logic[31:0] axi_narrow_data_slv_data_t; +typedef logic[3:0] axi_narrow_data_slv_strb_t; +typedef logic[3:0] axi_narrow_data_slv_id_t; +typedef logic[0:0] axi_narrow_data_slv_user_t; +`AXI_TYPEDEF_ALL_CT(axi_narrow_data_slv, axi_narrow_data_slv_req_t, axi_narrow_data_slv_rsp_t, axi_narrow_data_slv_addr_t, axi_narrow_data_slv_id_t, axi_narrow_data_slv_data_t, axi_narrow_data_slv_strb_t, axi_narrow_data_slv_user_t) + typedef logic[31:0] axi_wide_data_mst_addr_t; +typedef logic[255:0] axi_wide_data_mst_data_t; +typedef logic[31:0] axi_wide_data_mst_strb_t; +typedef logic[1:0] axi_wide_data_mst_id_t; +typedef logic[0:0] axi_wide_data_mst_user_t; +`AXI_TYPEDEF_ALL_CT(axi_wide_data_mst, axi_wide_data_mst_req_t, axi_wide_data_mst_rsp_t, axi_wide_data_mst_addr_t, axi_wide_data_mst_id_t, axi_wide_data_mst_data_t, axi_wide_data_mst_strb_t, axi_wide_data_mst_user_t) - `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, axi_ch_e, rob_idx_t) - localparam axi_cfg_t AxiCfg = '{ AddrWidth: 32, + + typedef logic[31:0] axi_wide_data_slv_addr_t; +typedef logic[255:0] axi_wide_data_slv_data_t; +typedef logic[31:0] axi_wide_data_slv_strb_t; +typedef logic[1:0] axi_wide_data_slv_id_t; +typedef logic[0:0] axi_wide_data_slv_user_t; +`AXI_TYPEDEF_ALL_CT(axi_wide_data_slv, axi_wide_data_slv_req_t, axi_wide_data_slv_rsp_t, axi_wide_data_slv_addr_t, axi_wide_data_slv_id_t, axi_wide_data_slv_data_t, axi_wide_data_slv_strb_t, axi_wide_data_slv_user_t) + + + + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, nw_ch_e, rob_idx_t) + localparam axi_cfg_t AxiCfgN = '{ AddrWidth: 32, DataWidth: 32, UserWidth: 1, InIdWidth: 4, OutIdWidth: 2}; -`FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi_data_slv, AxiCfg, hdr_t) +localparam axi_cfg_t AxiCfgW = '{ AddrWidth: 32, + DataWidth: 256, + UserWidth: 1, + InIdWidth: 2, + OutIdWidth: 2}; +`FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_data_slv, axi_wide_data_slv, AxiCfgN, AxiCfgW, hdr_t) -`FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, req, rsp) +`FLOO_TYPEDEF_NW_LINK_ALL(req, rsp, wide, req, rsp, wide) endpackage diff --git a/hw/mesh/noc/magia_noc_pkg.sv b/hw/mesh/noc/magia_noc_pkg.sv index 1cfae0a..30a04b4 100644 --- a/hw/mesh/noc/magia_noc_pkg.sv +++ b/hw/mesh/noc/magia_noc_pkg.sv @@ -15,6 +15,7 @@ * SPDX-License-Identifier: SHL-0.51 * * Authors: Alessandro Nadalini + * Victor Isachi * * MAGIA NoC Package */ @@ -56,19 +57,19 @@ package magia_noc_pkg; case (num_tiles) 32'd4: begin - Sam = floo_axi_mesh_2x2_noc_pkg::Sam; + Sam = floo_axi_nw_mesh_2x2_noc_pkg::Sam; end 32'd16: begin - Sam = floo_axi_mesh_4x4_noc_pkg::Sam; + Sam = floo_axi_nw_mesh_4x4_noc_pkg::Sam; end 32'd64: begin - Sam = floo_axi_mesh_8x8_noc_pkg::Sam; + Sam = floo_axi_nw_mesh_8x8_noc_pkg::Sam; end 32'd256: begin - Sam = floo_axi_mesh_16x16_noc_pkg::Sam; + Sam = floo_axi_nw_mesh_16x16_noc_pkg::Sam; end 32'd1024: begin - Sam = floo_axi_mesh_32x32_noc_pkg::Sam; + Sam = floo_axi_nw_mesh_32x32_noc_pkg::Sam; end endcase @@ -84,19 +85,19 @@ package magia_noc_pkg; case (num_tiles) 32'd4: begin - RouteCfg = floo_axi_mesh_2x2_noc_pkg::RouteCfg; + RouteCfg = floo_axi_nw_mesh_2x2_noc_pkg::RouteCfg; end 32'd16: begin - RouteCfg = floo_axi_mesh_4x4_noc_pkg::RouteCfg; + RouteCfg = floo_axi_nw_mesh_4x4_noc_pkg::RouteCfg; end 32'd64: begin - RouteCfg = floo_axi_mesh_8x8_noc_pkg::RouteCfg; + RouteCfg = floo_axi_nw_mesh_8x8_noc_pkg::RouteCfg; end 32'd256: begin - RouteCfg = floo_axi_mesh_16x16_noc_pkg::RouteCfg; + RouteCfg = floo_axi_nw_mesh_16x16_noc_pkg::RouteCfg; end 32'd1024: begin - RouteCfg = floo_axi_mesh_32x32_noc_pkg::RouteCfg; + RouteCfg = floo_axi_nw_mesh_32x32_noc_pkg::RouteCfg; end endcase @@ -106,31 +107,52 @@ package magia_noc_pkg; // Actual declaration of RouteCfg localparam route_cfg_t RouteCfg = gen_route_config(N_TILES); - typedef logic[ADDR_W-1:0] axi_data_mst_addr_t; - typedef logic[DATA_W-1:0] axi_data_mst_data_t; - typedef logic[STRB_W-1:0] axi_data_mst_strb_t; - typedef logic[L2_ID_W-1:0] axi_data_mst_id_t; - typedef logic[L2_U_W-1:0] axi_data_mst_user_t; - `AXI_TYPEDEF_ALL_CT(axi_data_mst, axi_data_mst_req_t, axi_data_mst_rsp_t, axi_data_mst_addr_t, axi_data_mst_id_t, axi_data_mst_data_t, axi_data_mst_strb_t, axi_data_mst_user_t) - - typedef logic[ADDR_W-1:0] axi_data_slv_addr_t; - typedef logic[DATA_W-1:0] axi_data_slv_data_t; - typedef logic[STRB_W-1:0] axi_data_slv_strb_t; - typedef logic[AXI_NOC_ID_W-1:0] axi_data_slv_id_t; - typedef logic[AXI_NOC_U_W-1:0] axi_data_slv_user_t; - `AXI_TYPEDEF_ALL_CT(axi_data_slv, axi_data_slv_req_t, axi_data_slv_rsp_t, axi_data_slv_addr_t, axi_data_slv_id_t, axi_data_slv_data_t, axi_data_slv_strb_t, axi_data_slv_user_t) - - `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, axi_ch_e, rob_idx_t) - localparam axi_cfg_t AxiCfg = '{ - AddrWidth: ADDR_W, - DataWidth: DATA_W, - UserWidth: AXI_U_W, - InIdWidth: AXI_NOC_ID_W, + typedef logic[ADDR_W-1:0] axi_narrow_data_mst_addr_t; + typedef logic[DATA_W-1:0] axi_narrow_data_mst_data_t; + typedef logic[STRB_W-1:0] axi_narrow_data_mst_strb_t; + typedef logic[L2_ID_W-1:0] axi_narrow_data_mst_id_t; + typedef logic[L2_U_W-1:0] axi_narrow_data_mst_user_t; + `AXI_TYPEDEF_ALL_CT(axi_narrow_data_mst, axi_narrow_data_mst_req_t, axi_narrow_data_mst_rsp_t, axi_narrow_data_mst_addr_t, axi_narrow_data_mst_id_t, axi_narrow_data_mst_data_t, axi_narrow_data_mst_strb_t, axi_narrow_data_mst_user_t) + + typedef logic[ADDR_W-1:0] axi_narrow_data_slv_addr_t; + typedef logic[DATA_W-1:0] axi_narrow_data_slv_data_t; + typedef logic[STRB_W-1:0] axi_narrow_data_slv_strb_t; + typedef logic[AXI_NOC_ID_W-1:0] axi_narrow_data_slv_id_t; + typedef logic[AXI_NOC_U_W-1:0] axi_narrow_data_slv_user_t; + `AXI_TYPEDEF_ALL_CT(axi_narrow_data_slv, axi_narrow_data_slv_req_t, axi_narrow_data_slv_rsp_t, axi_narrow_data_slv_addr_t, axi_narrow_data_slv_id_t, axi_narrow_data_slv_data_t, axi_narrow_data_slv_strb_t, axi_narrow_data_slv_user_t) + + typedef logic[ADDR_W-1:0] axi_wide_data_mst_addr_t; + typedef logic[WIDE_DATA_W-1:0] axi_wide_data_mst_data_t; + typedef logic[WIDE_STRB_W-1:0] axi_wide_data_mst_strb_t; + typedef logic[iDMA_AxiIdWidth-1:0] axi_wide_data_mst_id_t; + typedef logic[iDMA_UserWidth-1:0] axi_wide_data_mst_user_t; + `AXI_TYPEDEF_ALL_CT(axi_wide_data_mst, axi_wide_data_mst_req_t, axi_wide_data_mst_rsp_t, axi_wide_data_mst_addr_t, axi_wide_data_mst_id_t, axi_wide_data_mst_data_t, axi_wide_data_mst_strb_t, axi_wide_data_mst_user_t) + + typedef logic[ADDR_W-1:0] axi_wide_data_slv_addr_t; + typedef logic[WIDE_DATA_W-1:0] axi_wide_data_slv_data_t; + typedef logic[WIDE_STRB_W-1:0] axi_wide_data_slv_strb_t; + typedef logic[iDMA_AxiIdWidth-1:0] axi_wide_data_slv_id_t; + typedef logic[iDMA_UserWidth-1:0] axi_wide_data_slv_user_t; + `AXI_TYPEDEF_ALL_CT(axi_wide_data_slv, axi_wide_data_slv_req_t, axi_wide_data_slv_rsp_t, axi_wide_data_slv_addr_t, axi_wide_data_slv_id_t, axi_wide_data_slv_data_t, axi_wide_data_slv_strb_t, axi_wide_data_slv_user_t) + + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, nw_ch_e, rob_idx_t) + localparam axi_cfg_t AxiCfgN = '{ + AddrWidth: ADDR_W, + DataWidth: DATA_W, + UserWidth: AXI_U_W, + InIdWidth: AXI_NOC_ID_W, OutIdWidth: L2_ID_W }; + localparam axi_cfg_t AxiCfgW = '{ + AddrWidth: ADDR_W, + DataWidth: WIDE_DATA_W, + UserWidth: iDMA_UserWidth, + InIdWidth: iDMA_AxiIdWidth, + OutIdWidth: iDMA_AxiIdWidth + }; - `FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi_data_slv, AxiCfg, hdr_t) + `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_data_slv, axi_wide_data_slv, AxiCfgN, AxiCfgW, hdr_t) - `FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, req, rsp) + `FLOO_TYPEDEF_NW_LINK_ALL(req, rsp, wide, req, rsp, wide) endpackage \ No newline at end of file diff --git a/hw/mesh/noc_configs/floonoc_axi_mesh_16x16_config.yml b/hw/mesh/noc_configs/floonoc_axi_mesh_16x16_config.yml index b85ac94..f3939c6 100644 --- a/hw/mesh/noc_configs/floonoc_axi_mesh_16x16_config.yml +++ b/hw/mesh/noc_configs/floonoc_axi_mesh_16x16_config.yml @@ -1,24 +1,40 @@ -name: axi_mesh_16x16 +name: axi_nw_mesh_16x16 description: "Configuration file for a 16x16 MAGIA Mesh NoC" -network_type: "axi" +network_type: "narrow-wide" routing: route_algo: "XY" use_id_table: true protocols: - - name: "data_mst" + - name: "narrow_data_mst" + type: "narrow" protocol: "AXI4" data_width: 32 addr_width: 32 id_width: 2 user_width: 1 - - name: "data_slv" + - name: "narrow_data_slv" + type: "narrow" protocol: "AXI4" data_width: 32 addr_width: 32 id_width: 4 user_width: 1 + - name: "wide_data_mst" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 + - name: "wide_data_slv" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 endpoints: - name: "magia_tile" @@ -27,16 +43,19 @@ endpoints: base: 0x0000_0000 size: 0x0010_0000 mgr_port_protocol: - - "data_slv" + - "narrow_data_slv" + - "wide_data_slv" sbr_port_protocol: - - "data_mst" + - "narrow_data_mst" + - "wide_data_mst" - name: "L2" array: [16] addr_range: base: 0xC000_0000 size: 0x0400_0000 sbr_port_protocol: - - "data_mst" + - "narrow_data_mst" + - "wide_data_mst" routers: - name: "router" diff --git a/hw/mesh/noc_configs/floonoc_axi_mesh_2x2_config.yml b/hw/mesh/noc_configs/floonoc_axi_mesh_2x2_config.yml index 69c4628..d0af44c 100644 --- a/hw/mesh/noc_configs/floonoc_axi_mesh_2x2_config.yml +++ b/hw/mesh/noc_configs/floonoc_axi_mesh_2x2_config.yml @@ -1,24 +1,40 @@ -name: axi_mesh_2x2 +name: axi_nw_mesh_2x2 description: "Configuration file for a 2x2 MAGIA Mesh NoC" -network_type: "axi" +network_type: "narrow-wide" routing: route_algo: "XY" use_id_table: true protocols: - - name: "data_mst" + - name: "narrow_data_mst" + type: "narrow" protocol: "AXI4" data_width: 32 addr_width: 32 id_width: 2 user_width: 1 - - name: "data_slv" + - name: "narrow_data_slv" + type: "narrow" protocol: "AXI4" data_width: 32 addr_width: 32 id_width: 4 user_width: 1 + - name: "wide_data_mst" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 + - name: "wide_data_slv" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 endpoints: - name: "magia_tile" @@ -27,16 +43,19 @@ endpoints: base: 0x0000_0000 size: 0x0010_0000 mgr_port_protocol: - - "data_slv" + - "narrow_data_slv" + - "wide_data_slv" sbr_port_protocol: - - "data_mst" + - "narrow_data_mst" + - "wide_data_mst" - name: "L2" array: [2] addr_range: base: 0xC000_0000 size: 0x2000_0000 sbr_port_protocol: - - "data_mst" + - "narrow_data_mst" + - "wide_data_mst" routers: - name: "router" diff --git a/hw/mesh/noc_configs/floonoc_axi_mesh_32x32_config.yml b/hw/mesh/noc_configs/floonoc_axi_mesh_32x32_config.yml index 44efa46..5f7f416 100644 --- a/hw/mesh/noc_configs/floonoc_axi_mesh_32x32_config.yml +++ b/hw/mesh/noc_configs/floonoc_axi_mesh_32x32_config.yml @@ -1,24 +1,40 @@ -name: axi_mesh_32x32 +name: axi_nw_mesh_32x32 description: "Configuration file for a 32x32 MAGIA Mesh NoC" -network_type: "axi" +network_type: "narrow-wide" routing: route_algo: "XY" use_id_table: true protocols: - - name: "data_mst" + - name: "narrow_data_mst" + type: "narrow" protocol: "AXI4" data_width: 32 addr_width: 32 id_width: 2 user_width: 1 - - name: "data_slv" + - name: "narrow_data_slv" + type: "narrow" protocol: "AXI4" data_width: 32 addr_width: 32 id_width: 4 user_width: 1 + - name: "wide_data_mst" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 + - name: "wide_data_slv" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 endpoints: - name: "magia_tile" @@ -27,16 +43,19 @@ endpoints: base: 0x0000_0000 size: 0x0010_0000 mgr_port_protocol: - - "data_slv" + - "narrow_data_slv" + - "wide_data_slv" sbr_port_protocol: - - "data_mst" + - "narrow_data_mst" + - "wide_data_mst" - name: "L2" array: [32] addr_range: base: 0xC000_0000 size: 0x0200_0000 sbr_port_protocol: - - "data_mst" + - "narrow_data_mst" + - "wide_data_mst" routers: - name: "router" diff --git a/hw/mesh/noc_configs/floonoc_axi_mesh_4x4_config.yml b/hw/mesh/noc_configs/floonoc_axi_mesh_4x4_config.yml index b13e59c..b1f4deb 100644 --- a/hw/mesh/noc_configs/floonoc_axi_mesh_4x4_config.yml +++ b/hw/mesh/noc_configs/floonoc_axi_mesh_4x4_config.yml @@ -1,24 +1,40 @@ -name: axi_mesh_4x4 +name: axi_nw_mesh_4x4 description: "Configuration file for a 4x4 MAGIA Mesh NoC" -network_type: "axi" +network_type: "narrow-wide" routing: route_algo: "XY" use_id_table: true protocols: - - name: "data_mst" + - name: "narrow_data_mst" + type: "narrow" protocol: "AXI4" data_width: 32 addr_width: 32 id_width: 2 user_width: 1 - - name: "data_slv" + - name: "narrow_data_slv" + type: "narrow" protocol: "AXI4" data_width: 32 addr_width: 32 id_width: 4 user_width: 1 + - name: "wide_data_mst" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 + - name: "wide_data_slv" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 endpoints: - name: "magia_tile" @@ -27,16 +43,19 @@ endpoints: base: 0x0000_0000 size: 0x0010_0000 mgr_port_protocol: - - "data_slv" + - "narrow_data_slv" + - "wide_data_slv" sbr_port_protocol: - - "data_mst" + - "narrow_data_mst" + - "wide_data_mst" - name: "L2" array: [4] addr_range: base: 0xC000_0000 size: 0x1000_0000 sbr_port_protocol: - - "data_mst" + - "narrow_data_mst" + - "wide_data_mst" routers: - name: "router" diff --git a/hw/mesh/noc_configs/floonoc_axi_mesh_8x8_config.yml b/hw/mesh/noc_configs/floonoc_axi_mesh_8x8_config.yml index 945921d..c62a00c 100644 --- a/hw/mesh/noc_configs/floonoc_axi_mesh_8x8_config.yml +++ b/hw/mesh/noc_configs/floonoc_axi_mesh_8x8_config.yml @@ -1,24 +1,40 @@ -name: axi_mesh_8x8 +name: axi_nw_mesh_8x8 description: "Configuration file for a 8x8 MAGIA Mesh NoC" -network_type: "axi" +network_type: "narrow-wide" routing: route_algo: "XY" use_id_table: true protocols: - - name: "data_mst" + - name: "narrow_data_mst" + type: "narrow" protocol: "AXI4" data_width: 32 addr_width: 32 id_width: 2 user_width: 1 - - name: "data_slv" + - name: "narrow_data_slv" + type: "narrow" protocol: "AXI4" data_width: 32 addr_width: 32 id_width: 4 user_width: 1 + - name: "wide_data_mst" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 + - name: "wide_data_slv" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 endpoints: - name: "magia_tile" @@ -27,16 +43,19 @@ endpoints: base: 0x0000_0000 size: 0x0010_0000 mgr_port_protocol: - - "data_slv" + - "narrow_data_slv" + - "wide_data_slv" sbr_port_protocol: - - "data_mst" + - "narrow_data_mst" + - "wide_data_mst" - name: "L2" array: [8] addr_range: base: 0xC000_0000 size: 0x0800_0000 sbr_port_protocol: - - "data_mst" + - "narrow_data_mst" + - "wide_data_mst" routers: - name: "router" diff --git a/hw/tile/local_interconnect.sv b/hw/tile/local_interconnect.sv new file mode 100644 index 0000000..84e94bd --- /dev/null +++ b/hw/tile/local_interconnect.sv @@ -0,0 +1,283 @@ +/* + * Copyright (C) 2023-2024 ETH Zurich and University of Bologna + * + * Licensed under the Solderpad Hardware License, Version 0.51 + * (the "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: SHL-0.51 + * + * Authors: Victor Isachi + * + * MAGIA Tile Local Interconnect + */ + +`include "hci_helpers.svh" + +module local_interconnect + import hci_package::*; + import magia_tile_pkg::*; + import magia_pkg::*; +#( + parameter int unsigned N_HWPE = magia_tile_pkg::N_HWPE, + parameter int unsigned N_DMA = magia_tile_pkg::N_DMA, + parameter int unsigned N_CORE = magia_tile_pkg::N_CORE, + parameter int unsigned N_MEM = magia_pkg::N_MEM_BANKS, + parameter int unsigned EXPFIFO = magia_tile_pkg::EXPFIFO, + parameter int unsigned FILTER_WRITE_R_VALID[0:N_HWPE-1] = '{default: 0}, + parameter int unsigned MEM_DATA_W = magia_tile_pkg::MEM_DATA_W, + parameter int unsigned MEM_ADDR_W = magia_tile_pkg::MEM_ADDR_W, + parameter int unsigned MEM_BYTE_W = magia_tile_pkg::MEM_BYTE_W, + parameter int unsigned MEM_USER_W = magia_tile_pkg::MEM_USER_W, + parameter int unsigned MEM_ID_W = magia_tile_pkg::MEM_ID_W, + parameter hci_size_parameter_t `HCI_SIZE_PARAM(hwpe) = magia_tile_pkg::HCI_SIZE_HWPE, + parameter hci_size_parameter_t `HCI_SIZE_PARAM(dma) = magia_tile_pkg::HCI_SIZE_DMA, + parameter hci_size_parameter_t `HCI_SIZE_PARAM(core) = magia_tile_pkg::HCI_SIZE_CORE, + parameter hci_size_parameter_t `HCI_SIZE_PARAM(mem) = magia_tile_pkg::HCI_SIZE_MEM +) ( + input logic clk_i, + input logic rst_ni, + + input logic clear_i, + input hci_package::hci_interconnect_ctrl_t ctrl_i, + + hci_core_intf.target hwpe[N_HWPE], + hci_core_intf.target dma [N_DMA], + hci_core_intf.target core[N_CORE], + hci_core_intf.initiator mem [N_MEM] +); + +/*******************************************************/ +/** Parameter and Interface Definitions Beginning **/ +/*******************************************************/ + + localparam hci_size_parameter_t `HCI_SIZE_PARAM(hwpe_mem) = '{ + DW: MEM_DATA_W, + AW: MEM_ADDR_W, + BW: MEM_BYTE_W, + UW: MEM_USER_W, + IW: MEM_ID_W, + EW: hci_package::DEFAULT_EW, + EHW: hci_package::DEFAULT_EHW + }; + `HCI_INTF_ARRAY(hwpe_mem, clk_i, 0:N_HWPE*N_MEM-1); + + localparam hci_size_parameter_t `HCI_SIZE_PARAM(hwpe_mem_muxed) = '{ + DW: MEM_DATA_W, + AW: MEM_ADDR_W, + BW: MEM_BYTE_W, + UW: MEM_USER_W, + IW: MEM_ID_W, + EW: hci_package::DEFAULT_EW, + EHW: hci_package::DEFAULT_EHW + }; + `HCI_INTF_ARRAY(hwpe_mem_muxed, clk_i, 0:N_MEM-1); + + localparam hci_size_parameter_t `HCI_SIZE_PARAM(dma_mem) = '{ + DW: MEM_DATA_W, + AW: MEM_ADDR_W, + BW: MEM_BYTE_W, + UW: MEM_USER_W, + IW: MEM_ID_W, + EW: hci_package::DEFAULT_EW, + EHW: hci_package::DEFAULT_EHW + }; + `HCI_INTF_ARRAY(dma_mem, clk_i, 0:N_DMA*N_MEM-1); + + localparam hci_size_parameter_t `HCI_SIZE_PARAM(dma_mem_muxed) = '{ + DW: MEM_DATA_W, + AW: MEM_ADDR_W, + BW: MEM_BYTE_W, + UW: MEM_USER_W, + IW: MEM_ID_W, + EW: hci_package::DEFAULT_EW, + EHW: hci_package::DEFAULT_EHW + }; + `HCI_INTF_ARRAY(dma_mem_muxed, clk_i, 0:N_MEM-1); + + localparam hci_size_parameter_t `HCI_SIZE_PARAM(hwpe_dma_mem_muxed) = '{ + DW: MEM_DATA_W, + AW: MEM_ADDR_W, + BW: MEM_BYTE_W, + UW: MEM_USER_W, + IW: MEM_ID_W, + EW: hci_package::DEFAULT_EW, + EHW: hci_package::DEFAULT_EHW + }; + `HCI_INTF_ARRAY(hwpe_dma_mem_muxed, clk_i, 0:N_MEM-1); + + localparam hci_size_parameter_t `HCI_SIZE_PARAM(core_mem) = '{ + DW: MEM_DATA_W, + AW: MEM_ADDR_W, + BW: MEM_BYTE_W, + UW: MEM_USER_W, + IW: MEM_ID_W, + EW: hci_package::DEFAULT_EW, + EHW: hci_package::DEFAULT_EHW + }; + `HCI_INTF_ARRAY(core_mem, clk_i, 0:N_CORE*N_MEM-1); + + localparam hci_size_parameter_t `HCI_SIZE_PARAM(core_mem_muxed) = '{ + DW: MEM_DATA_W, + AW: MEM_ADDR_W, + BW: MEM_BYTE_W, + UW: MEM_USER_W, + IW: MEM_ID_W, + EW: hci_package::DEFAULT_EW, + EHW: hci_package::DEFAULT_EHW + }; + `HCI_INTF_ARRAY(core_mem_muxed, clk_i, 0:N_MEM-1); + +/*******************************************************/ +/** Parameter and Interface Definitions End **/ +/*******************************************************/ +/** HWPE Routing and Arbitration Beginning **/ +/*******************************************************/ + + for(genvar i = 0; i < N_HWPE; i++) begin : gen_hwpe_req2mem + hci_router #( + .FIFO_DEPTH ( EXPFIFO ), + .NB_OUT_CHAN ( N_MEM ), + .FILTER_WRITE_R_VALID ( FILTER_WRITE_R_VALID[i] ), + .`HCI_SIZE_PARAM(in) ( `HCI_SIZE_PARAM(hwpe) ), + .`HCI_SIZE_PARAM(out) ( `HCI_SIZE_PARAM(hwpe_mem) ) + ) i_hwpe_router ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear_i ), + .in ( hwpe[i] ), + .out ( hwpe_mem[i*N_MEM:(i+1)*N_MEM-1] ) + ); + end + + hci_arbiter_tree #( + .NB_REQUESTS ( N_HWPE ), + .NB_CHAN ( N_MEM ), + .`HCI_SIZE_PARAM(out) ( `HCI_SIZE_PARAM(hwpe_mem_muxed) ) + ) i_hwpe_wide_port_arbiter_tree ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear_i ), + .ctrl_i ( ctrl_i ), + .in ( hwpe_mem ), + .out ( hwpe_mem_muxed ) + ); + +/*******************************************************/ +/** HWPE Routing and Arbitration End **/ +/*******************************************************/ +/** DMA Routing and Arbitration Beginning **/ +/*******************************************************/ + + for(genvar i = 0; i < N_DMA; i++) begin : gen_dma_req2mem + hci_router #( + .FIFO_DEPTH ( EXPFIFO ), + .NB_OUT_CHAN ( N_MEM ), + .FILTER_WRITE_R_VALID ( FILTER_WRITE_R_VALID[i] ), + .`HCI_SIZE_PARAM(in) ( `HCI_SIZE_PARAM(dma) ), + .`HCI_SIZE_PARAM(out) ( `HCI_SIZE_PARAM(dma_mem) ) + ) i_dma_router ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear_i ), + .in ( dma[i] ), + .out ( dma_mem[i*N_MEM:(i+1)*N_MEM-1] ) + ); + end + + hci_arbiter_tree #( + .NB_REQUESTS ( N_DMA ), + .NB_CHAN ( N_MEM ), + .`HCI_SIZE_PARAM(out) ( `HCI_SIZE_PARAM(dma_mem_muxed) ) + ) i_dma_wide_port_arbiter_tree ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear_i ), + .ctrl_i ( ctrl_i ), + .in ( dma_mem ), + .out ( dma_mem_muxed ) + ); + +/*******************************************************/ +/** DMA Routing and Arbitration End **/ +/*******************************************************/ +/** HWPE and DMA Arbitration Beginning **/ +/*******************************************************/ + + hci_arbiter #( + .NB_CHAN ( N_MEM ) + ) i_hwpe_vs_dma_arbiter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear_i ), + .ctrl_i ( ctrl_i ), + .in_high ( hwpe_mem_muxed ), + .in_low ( dma_mem_muxed ), + .out ( hwpe_dma_mem_muxed ) + ); + +/*******************************************************/ +/** HWPE and DMA Arbitration End **/ +/*******************************************************/ +/** Core Routing and Arbitration Beginning **/ +/*******************************************************/ + + for(genvar i = 0; i < N_CORE; i++) begin : gen_core_req2mem + hci_router #( + .FIFO_DEPTH ( EXPFIFO ), + .NB_OUT_CHAN ( N_MEM ), + .FILTER_WRITE_R_VALID ( FILTER_WRITE_R_VALID[i] ), + .`HCI_SIZE_PARAM(in) ( `HCI_SIZE_PARAM(core) ), + .`HCI_SIZE_PARAM(out) ( `HCI_SIZE_PARAM(core_mem) ) + ) i_core_router ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear_i ), + .in ( core[i] ), + .out ( core_mem[i*N_MEM:(i+1)*N_MEM-1] ) + ); + end + + hci_arbiter_tree #( + .NB_REQUESTS ( N_CORE ), + .NB_CHAN ( N_MEM ), + .`HCI_SIZE_PARAM(out) ( `HCI_SIZE_PARAM(core_mem_muxed) ) + ) i_core_wide_port_arbiter_tree ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear_i ), + .ctrl_i ( ctrl_i ), + .in ( core_mem ), + .out ( core_mem_muxed ) + ); + +/*******************************************************/ +/** Core Routing and Arbitration End **/ +/*******************************************************/ +/** HWPE/DMA and Core Arbitration Beginning **/ +/*******************************************************/ + + hci_arbiter #( + .NB_CHAN ( N_MEM ) + ) i_wide_vs_narrow_arbiter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear_i ), + .ctrl_i ( ctrl_i ), + .in_high ( hwpe_dma_mem_muxed ), + .in_low ( core_mem_muxed ), + .out ( mem ) + ); + +/*******************************************************/ +/** HWPE/DMA and Core Arbitration End **/ +/*******************************************************/ + +endmodule: local_interconnect diff --git a/hw/tile/magia_tile.sv b/hw/tile/magia_tile.sv index a9fcbf2..1a9e4fe 100644 --- a/hw/tile/magia_tile.sv +++ b/hw/tile/magia_tile.sv @@ -22,6 +22,7 @@ `include "axi/assign.svh" `include "hci_helpers.svh" + `include "hwpe_ctrl_helpers.svh" module magia_tile import magia_tile_pkg::*; @@ -40,7 +41,7 @@ module magia_tile `ifndef TARGET_STANDALONE_TILE import magia_noc_pkg::*; `else - import floo_axi_mesh_1x2_noc_pkg::*; + import floo_axi_nw_mesh_1x2_noc_pkg::*; `endif #( // Parameters used by hci_interconnect and l1_spm @@ -64,23 +65,31 @@ module magia_tile // NoC input and output links input floo_req_t noc_south_req_i, output floo_rsp_t noc_south_rsp_o, + input floo_wide_t noc_south_wide_i, output floo_req_t noc_south_req_o, input floo_rsp_t noc_south_rsp_i, + output floo_wide_t noc_south_wide_o, input floo_req_t noc_east_req_i, output floo_rsp_t noc_east_rsp_o, + input floo_wide_t noc_east_wide_i, output floo_req_t noc_east_req_o, input floo_rsp_t noc_east_rsp_i, + output floo_wide_t noc_east_wide_o, input floo_req_t noc_north_req_i, output floo_rsp_t noc_north_rsp_o, + input floo_wide_t noc_north_wide_i, output floo_req_t noc_north_req_o, input floo_rsp_t noc_north_rsp_i, + output floo_wide_t noc_north_wide_o, input floo_req_t noc_west_req_i, output floo_rsp_t noc_west_rsp_o, + input floo_wide_t noc_west_wide_i, output floo_req_t noc_west_req_o, input floo_rsp_t noc_west_rsp_i, + output floo_wide_t noc_west_wide_o, // Tile spatial IDs input logic [31:0] x_id_i, @@ -181,35 +190,53 @@ module magia_tile magia_tile_pkg::core_axi_instr_req_t core_l2_instr_req; magia_tile_pkg::core_axi_instr_rsp_t core_l2_instr_rsp; - magia_tile_pkg::idma_axi_req_t idma_axi_read_req; - magia_tile_pkg::idma_axi_rsp_t idma_axi_read_rsp; + magia_tile_pkg::idma_axi_req_t idma_axi_read_req_out; + magia_tile_pkg::idma_axi_rsp_t idma_axi_read_rsp_out; - magia_tile_pkg::idma_axi_req_t idma_axi_write_req; - magia_tile_pkg::idma_axi_rsp_t idma_axi_write_rsp; + magia_tile_pkg::idma_axi_req_t idma_axi_write_req_out; + magia_tile_pkg::idma_axi_rsp_t idma_axi_write_rsp_out; - magia_tile_pkg::idma_axi_req_t idma_axi_req; - magia_tile_pkg::idma_axi_rsp_t idma_axi_rsp; + magia_tile_pkg::idma_axi_req_t idma_axi_req_out; + magia_tile_pkg::idma_axi_rsp_t idma_axi_rsp_out; - magia_tile_pkg::idma_obi_req_t idma_obi_read_req; - magia_tile_pkg::idma_obi_rsp_t idma_obi_read_rsp; + magia_tile_pkg::idma_axi_req_t idma_axi_read_req_in; + magia_tile_pkg::idma_axi_rsp_t idma_axi_read_rsp_in; - magia_tile_pkg::idma_obi_req_t idma_obi_write_req; - magia_tile_pkg::idma_obi_rsp_t idma_obi_write_rsp; + magia_tile_pkg::idma_axi_req_t idma_axi_write_req_in; + magia_tile_pkg::idma_axi_rsp_t idma_axi_write_rsp_in; - magia_tile_pkg::idma_hci_req_t idma_hci_read_req; - magia_tile_pkg::idma_hci_rsp_t idma_hci_read_rsp; + magia_tile_pkg::idma_axi_req_t idma_axi_req_in; + magia_tile_pkg::idma_axi_rsp_t idma_axi_rsp_in; - magia_tile_pkg::idma_hci_req_t idma_hci_write_req; - magia_tile_pkg::idma_hci_rsp_t idma_hci_write_rsp; + magia_tile_pkg::idma_obi_req_t idma_obi_read_req_out; + magia_tile_pkg::idma_obi_rsp_t idma_obi_read_rsp_out; - magia_tile_pkg::axi_xbar_slv_req_t[magia_tile_pkg::AxiXbarNoSlvPorts-1:0] axi_xbar_data_in_req; // Index 3 -> ext, Index 2 -> iDMA, Index 1 -> Core Data, Index 0 -> Core Instruction - magia_tile_pkg::axi_xbar_slv_rsp_t[magia_tile_pkg::AxiXbarNoSlvPorts-1:0] axi_xbar_data_in_rsp; // Index 3 -> ext, Index 2 -> iDMA, Index 1 -> Core Data, Index 0 -> Core Instruction + magia_tile_pkg::idma_obi_req_t idma_obi_write_req_out; + magia_tile_pkg::idma_obi_rsp_t idma_obi_write_rsp_out; - magia_pkg::axi_xbar_mst_req_t[magia_tile_pkg::AxiXbarNoMstPorts-1:0] axi_xbar_mst_req; - magia_pkg::axi_xbar_mst_rsp_t[magia_tile_pkg::AxiXbarNoMstPorts-1:0] axi_xbar_mst_rsp; - - magia_pkg::axi_xbar_mst_req_t axi_xbar_data_out_req; - magia_pkg::axi_xbar_mst_rsp_t axi_xbar_data_out_rsp; + magia_tile_pkg::idma_obi_req_t idma_obi_read_req_in; + magia_tile_pkg::idma_obi_rsp_t idma_obi_read_rsp_in; + + magia_tile_pkg::idma_obi_req_t idma_obi_write_req_in; + magia_tile_pkg::idma_obi_rsp_t idma_obi_write_rsp_in; + + magia_tile_pkg::idma_hci_req_t idma_hci_read_req_out; + magia_tile_pkg::idma_hci_rsp_t idma_hci_read_rsp_out; + + magia_tile_pkg::idma_hci_req_t idma_hci_write_req_out; + magia_tile_pkg::idma_hci_rsp_t idma_hci_write_rsp_out; + + magia_tile_pkg::idma_hci_req_t idma_hci_read_req_in; + magia_tile_pkg::idma_hci_rsp_t idma_hci_read_rsp_in; + + magia_tile_pkg::idma_hci_req_t idma_hci_write_req_in; + magia_tile_pkg::idma_hci_rsp_t idma_hci_write_rsp_in; + + magia_tile_pkg::axi_xbar_slv_req_t[magia_tile_pkg::AxiXbarNoSlvPorts-1:0] axi_xbar_slv_req; // Index 2 -> ext, Index 1 -> Core Data, Index 0 -> Core Instruction + magia_tile_pkg::axi_xbar_slv_rsp_t[magia_tile_pkg::AxiXbarNoSlvPorts-1:0] axi_xbar_slv_rsp; // Index 2 -> ext, Index 1 -> Core Data, Index 0 -> Core Instruction + + magia_pkg::axi_xbar_mst_req_t[magia_tile_pkg::AxiXbarNoMstPorts-1:0] axi_xbar_mst_req; // Index 1 -> ext, Index 0 -> OBI XBAR + magia_pkg::axi_xbar_mst_rsp_t[magia_tile_pkg::AxiXbarNoMstPorts-1:0] axi_xbar_mst_rsp; // Index 1 -> ext, Index 0 -> OBI XBAR logic[magia_tile_pkg::axi_xbar_cfg.NoSlvPorts-1:0] en_default_mst_port; @@ -291,13 +318,14 @@ module magia_tile logic [0:0][31:0] other_events_array; // FlooNoC connections between NI and router - floo_req_t [4:0] floo_router_req_in; - floo_rsp_t [4:0] floo_router_rsp_in; - floo_req_t [4:0] floo_router_req_out; - floo_rsp_t [4:0] floo_router_rsp_out; - - id_t floo_id; - + id_t floo_id; + floo_req_t [4:0] floo_router_req_in; + floo_rsp_t [4:0] floo_router_rsp_in; + floo_wide_t [4:0] floo_router_wide_in; + floo_req_t [4:0] floo_router_req_out; + floo_rsp_t [4:0] floo_router_rsp_out; + floo_wide_t [4:0] floo_router_wide_out; + logic x_compressed_valid; logic x_compressed_ready; fpu_ss_pkg::x_compressed_req_t x_compressed_req; @@ -368,12 +396,10 @@ module magia_tile assign obi_xbar_en_default_idx = '1; // Routing to the AXI Xbar all requests with an address outside the range of the internal L1 and the external L2 assign obi_xbar_default_idx = '0; - assign axi_xbar_data_in_req[magia_tile_pkg::AXI_IDMA_IDX] = idma_axi_req; - assign idma_axi_rsp = axi_xbar_data_in_rsp[magia_tile_pkg::AXI_IDMA_IDX]; - assign axi_xbar_data_in_req[magia_tile_pkg::AXI_CORE_DATA_IDX] = core_l2_data_req; - assign core_l2_data_rsp = axi_xbar_data_in_rsp[magia_tile_pkg::AXI_CORE_DATA_IDX]; - assign axi_xbar_data_in_req[magia_tile_pkg::AXI_CORE_INSTR_IDX] = core_l2_instr_req; - assign core_l2_instr_rsp = axi_xbar_data_in_rsp[magia_tile_pkg::AXI_CORE_INSTR_IDX]; + assign axi_xbar_slv_req[magia_tile_pkg::AXI_SLV_CORE_DATA_IDX] = core_l2_data_req; + assign core_l2_data_rsp = axi_xbar_slv_rsp[magia_tile_pkg::AXI_SLV_CORE_DATA_IDX]; + assign axi_xbar_slv_req[magia_tile_pkg::AXI_SLV_CORE_INSTR_IDX] = core_l2_instr_req; + assign core_l2_instr_rsp = axi_xbar_slv_rsp[magia_tile_pkg::AXI_SLV_CORE_INSTR_IDX]; assign obi_xbar_slv_req[magia_tile_pkg::OBI_CORE_IDX] = core_obi_data_req; assign core_obi_data_rsp = obi_xbar_slv_rsp[magia_tile_pkg::OBI_CORE_IDX]; @@ -398,6 +424,8 @@ module magia_tile assign en_default_mst_port = '1; + assign floo_id = '{x: (x_id_i+1), y: y_id_i, port_id: 0}; + assign hci_clear = 1'b0; assign hci_ctrl = '0; @@ -478,8 +506,6 @@ module magia_tile assign irq[2:0] = '0; // Clear IRQs 0-2 `endif - assign floo_id = '{x: (x_id_i+1), y: y_id_i, port_id: 0}; - /*******************************************************/ /** Hardwired Signals End **/ /*******************************************************/ @@ -552,79 +578,203 @@ module magia_tile obi2hci_req #( .obi_req_t ( magia_tile_pkg::idma_obi_req_t ), .hci_req_t ( magia_tile_pkg::idma_hci_req_t ) - ) i_idma_obi2hci_req ( - .obi_req_i ( idma_obi_read_req ), - .hci_req_o ( idma_hci_read_req ) + ) i_idma_out_obi2hci_req ( + .obi_req_i ( idma_obi_read_req_out ), + .hci_req_o ( idma_hci_read_req_out ) + ); + + hci2obi_rsp #( + .hci_rsp_t ( magia_tile_pkg::idma_hci_rsp_t ), + .obi_rsp_t ( magia_tile_pkg::idma_obi_rsp_t ) + ) i_idma_out_hci2obi_rsp ( + .hci_rsp_i ( idma_hci_read_rsp_out ), + .obi_rsp_o ( idma_obi_read_rsp_out ) + ); + + obi2hci_req #( + .obi_req_t ( magia_tile_pkg::idma_obi_req_t ), + .hci_req_t ( magia_tile_pkg::idma_hci_req_t ) + ) i_idma_out_obi2hci_write_req ( + .obi_req_i ( idma_obi_write_req_out ), + .hci_req_o ( idma_hci_write_req_out ) + ); + + hci2obi_rsp #( + .hci_rsp_t ( magia_tile_pkg::idma_hci_rsp_t ), + .obi_rsp_t ( magia_tile_pkg::idma_obi_rsp_t ) + ) i_idma_out_hci2obi_write_rsp ( + .hci_rsp_i ( idma_hci_write_rsp_out ), + .obi_rsp_o ( idma_obi_write_rsp_out ) + ); + + obi2hci_req #( + .obi_req_t ( magia_tile_pkg::idma_obi_req_t ), + .hci_req_t ( magia_tile_pkg::idma_hci_req_t ) + ) i_idma_in_obi2hci_req ( + .obi_req_i ( idma_obi_read_req_in ), + .hci_req_o ( idma_hci_read_req_in ) ); hci2obi_rsp #( .hci_rsp_t ( magia_tile_pkg::idma_hci_rsp_t ), .obi_rsp_t ( magia_tile_pkg::idma_obi_rsp_t ) - ) i_idma_hci2obi_rsp ( - .hci_rsp_i ( idma_hci_read_rsp ), - .obi_rsp_o ( idma_obi_read_rsp ) + ) i_idma_in_hci2obi_rsp ( + .hci_rsp_i ( idma_hci_read_rsp_in ), + .obi_rsp_o ( idma_obi_read_rsp_in ) ); obi2hci_req #( .obi_req_t ( magia_tile_pkg::idma_obi_req_t ), .hci_req_t ( magia_tile_pkg::idma_hci_req_t ) - ) i_idma_obi2hci_write_req ( - .obi_req_i ( idma_obi_write_req ), - .hci_req_o ( idma_hci_write_req ) + ) i_idma_in_obi2hci_write_req ( + .obi_req_i ( idma_obi_write_req_in ), + .hci_req_o ( idma_hci_write_req_in ) ); hci2obi_rsp #( .hci_rsp_t ( magia_tile_pkg::idma_hci_rsp_t ), .obi_rsp_t ( magia_tile_pkg::idma_obi_rsp_t ) - ) i_idma_hci2obi_write_rsp ( - .hci_rsp_i ( idma_hci_write_rsp ), - .obi_rsp_o ( idma_obi_write_rsp ) + ) i_idma_in_hci2obi_write_rsp ( + .hci_rsp_i ( idma_hci_write_rsp_in ), + .obi_rsp_o ( idma_obi_write_rsp_in ) ); axi_to_obi #( - .ObiCfg ( magia_tile_pkg::obi_amo_cfg ), - .obi_req_t ( magia_tile_pkg::core_obi_data_req_t ), - .obi_rsp_t ( magia_tile_pkg::core_obi_data_rsp_t ), - .obi_a_chan_t ( magia_tile_pkg::core_data_obi_a_chan_t ), - .obi_r_chan_t ( magia_tile_pkg::core_data_obi_r_chan_t ), - .AxiAddrWidth ( magia_pkg::ADDR_W ), - .AxiDataWidth ( magia_pkg::DATA_W ), - .AxiIdWidth ( magia_pkg::AXI_NOC_ID_W ), - .AxiUserWidth ( magia_pkg::AXI_NOC_U_W ), - .MaxTrans ( 1 ), - .axi_req_t ( magia_pkg::axi_xbar_mst_req_t ), - .axi_rsp_t ( magia_pkg::axi_xbar_mst_rsp_t ) + .ObiCfg ( magia_tile_pkg::obi_amo_cfg ), + .obi_req_t ( magia_tile_pkg::core_obi_data_req_t ), + .obi_rsp_t ( magia_tile_pkg::core_obi_data_rsp_t ), + .obi_a_chan_t ( magia_tile_pkg::core_data_obi_a_chan_t ), + .obi_r_chan_t ( magia_tile_pkg::core_data_obi_r_chan_t ), + .AxiAddrWidth ( magia_pkg::ADDR_W ), + .AxiDataWidth ( magia_pkg::DATA_W ), + .AxiIdWidth ( magia_pkg::AXI_NOC_ID_W ), + .AxiUserWidth ( magia_pkg::AXI_NOC_U_W ), + .MaxTrans ( 8 ), + .axi_req_t ( magia_pkg::axi_xbar_mst_req_t ), + .axi_rsp_t ( magia_pkg::axi_xbar_mst_rsp_t ) ) i_ext_data_axi2obi ( - .clk_i ( sys_clk ), - .rst_ni ( rst_ni ), - .testmode_i ( test_mode_i ), - .axi_req_i ( axi_xbar_mst_req[magia_tile_pkg::OBI_EXT_IDX] ), - .axi_rsp_o ( axi_xbar_mst_rsp[magia_tile_pkg::OBI_EXT_IDX] ), - .obi_req_o ( ext_obi_data_req ), - .obi_rsp_i ( ext_obi_data_rsp ), - .req_aw_id_o ( ), - .req_aw_user_o ( ), - .req_w_user_o ( ), - .req_write_aid_i ( axi2obi_req_write_aid ), - .req_write_auser_i ( axi2obi_req_write_auser ), - .req_write_wuser_i ( axi2obi_req_write_wuser ), - .req_ar_id_o ( ), - .req_ar_user_o ( ), - .req_read_aid_i ( axi2obi_req_read_aid ), - .req_read_auser_i ( axi2obi_req_read_auser ), - .rsp_write_aw_user_o ( ), - .rsp_write_w_user_o ( ), - .rsp_write_bank_strb_o ( ), - .rsp_write_rid_o ( ), - .rsp_write_ruser_o ( ), - .rsp_write_last_o ( ), - .rsp_write_hs_o ( ), - .rsp_b_user_i ( axi2obi_rsp_b_user ), - .rsp_read_ar_user_o ( ), - .rsp_read_size_enable_o ( ), - .rsp_read_rid_o ( ), - .rsp_read_ruser_o ( ), - .rsp_r_user_i ( axi2obi_rsp_r_user ) + .clk_i ( sys_clk ), + .rst_ni ( rst_ni ), + .testmode_i ( test_mode_i ), + .axi_req_i ( axi_xbar_mst_req[magia_tile_pkg::AXI_MST_OBI_IDX] ), + .axi_rsp_o ( axi_xbar_mst_rsp[magia_tile_pkg::AXI_MST_OBI_IDX] ), + .obi_req_o ( ext_obi_data_req ), + .obi_rsp_i ( ext_obi_data_rsp ), + .req_aw_id_o ( ), + .req_aw_user_o ( ), + .req_w_user_o ( ), + .req_write_aid_i ( axi2obi_req_write_aid ), + .req_write_auser_i ( axi2obi_req_write_auser ), + .req_write_wuser_i ( axi2obi_req_write_wuser ), + .req_ar_id_o ( ), + .req_ar_user_o ( ), + .req_read_aid_i ( axi2obi_req_read_aid ), + .req_read_auser_i ( axi2obi_req_read_auser ), + .rsp_write_aw_user_o ( ), + .rsp_write_w_user_o ( ), + .rsp_write_bank_strb_o ( ), + .rsp_write_rid_o ( ), + .rsp_write_ruser_o ( ), + .rsp_write_last_o ( ), + .rsp_write_hs_o ( ), + .rsp_b_user_i ( axi2obi_rsp_b_user ), + .rsp_read_ar_user_o ( ), + .rsp_read_size_enable_o ( ), + .rsp_read_rid_o ( ), + .rsp_read_ruser_o ( ), + .rsp_r_user_i ( axi2obi_rsp_r_user ) + ); + + axi_to_obi #( + .ObiCfg ( magia_tile_pkg::obi_idma_cfg ), + .obi_req_t ( magia_tile_pkg::idma_obi_req_t ), + .obi_rsp_t ( magia_tile_pkg::idma_obi_rsp_t ), + .obi_a_chan_t ( magia_tile_pkg::idma_obi_a_chan_t ), + .obi_r_chan_t ( magia_tile_pkg::idma_obi_r_chan_t ), + .AxiAddrWidth ( iDMA_AddrWidth ), + .AxiDataWidth ( iDMA_DataWidth ), + .AxiIdWidth ( iDMA_AxiIdWidth ), + .AxiUserWidth ( iDMA_UserWidth ), + .MaxTrans ( 8 ), + .axi_req_t ( magia_tile_pkg::idma_axi_req_t ), + .axi_rsp_t ( magia_tile_pkg::idma_axi_rsp_t ) + ) i_idma_read_in_axi2obi ( + .clk_i ( sys_clk ), + .rst_ni ( rst_ni ), + .testmode_i ( test_mode_i ), + .axi_req_i ( idma_axi_read_req_in ), + .axi_rsp_o ( idma_axi_read_rsp_in ), + .obi_req_o ( idma_obi_read_req_in ), + .obi_rsp_i ( idma_obi_read_rsp_in ), + .req_aw_id_o ( ), + .req_aw_user_o ( ), + .req_w_user_o ( ), + .req_write_aid_i ( '0 ), + .req_write_auser_i ( '0 ), + .req_write_wuser_i ( '0 ), + .req_ar_id_o ( ), + .req_ar_user_o ( ), + .req_read_aid_i ( '0 ), + .req_read_auser_i ( '0 ), + .rsp_write_aw_user_o ( ), + .rsp_write_w_user_o ( ), + .rsp_write_bank_strb_o ( ), + .rsp_write_rid_o ( ), + .rsp_write_ruser_o ( ), + .rsp_write_last_o ( ), + .rsp_write_hs_o ( ), + .rsp_b_user_i ( '0 ), + .rsp_read_ar_user_o ( ), + .rsp_read_size_enable_o ( ), + .rsp_read_rid_o ( ), + .rsp_read_ruser_o ( ), + .rsp_r_user_i ( '0 ) + ); + + axi_to_obi #( + .ObiCfg ( magia_tile_pkg::obi_idma_cfg ), + .obi_req_t ( magia_tile_pkg::idma_obi_req_t ), + .obi_rsp_t ( magia_tile_pkg::idma_obi_rsp_t ), + .obi_a_chan_t ( magia_tile_pkg::idma_obi_a_chan_t ), + .obi_r_chan_t ( magia_tile_pkg::idma_obi_r_chan_t ), + .AxiAddrWidth ( iDMA_AddrWidth ), + .AxiDataWidth ( iDMA_DataWidth ), + .AxiIdWidth ( iDMA_AxiIdWidth ), + .AxiUserWidth ( iDMA_UserWidth ), + .MaxTrans ( 8 ), + .axi_req_t ( magia_tile_pkg::idma_axi_req_t ), + .axi_rsp_t ( magia_tile_pkg::idma_axi_rsp_t ) + ) i_idma_write_in_axi2obi ( + .clk_i ( sys_clk ), + .rst_ni ( rst_ni ), + .testmode_i ( test_mode_i ), + .axi_req_i ( idma_axi_write_req_in ), + .axi_rsp_o ( idma_axi_write_rsp_in ), + .obi_req_o ( idma_obi_write_req_in ), + .obi_rsp_i ( idma_obi_write_rsp_in ), + .req_aw_id_o ( ), + .req_aw_user_o ( ), + .req_w_user_o ( ), + .req_write_aid_i ( '0 ), + .req_write_auser_i ( '0 ), + .req_write_wuser_i ( '0 ), + .req_ar_id_o ( ), + .req_ar_user_o ( ), + .req_read_aid_i ( '0 ), + .req_read_auser_i ( '0 ), + .rsp_write_aw_user_o ( ), + .rsp_write_w_user_o ( ), + .rsp_write_bank_strb_o ( ), + .rsp_write_rid_o ( ), + .rsp_write_ruser_o ( ), + .rsp_write_last_o ( ), + .rsp_write_hs_o ( ), + .rsp_b_user_i ( '0 ), + .rsp_read_ar_user_o ( ), + .rsp_read_size_enable_o ( ), + .rsp_read_rid_o ( ), + .rsp_read_ruser_o ( ), + .rsp_r_user_i ( '0 ) ); `ifndef CV32E40X @@ -709,9 +859,9 @@ module magia_tile localparam hci_package::hci_size_parameter_t `HCI_SIZE_PARAM(hci_core_if) = '{ DW: magia_tile_pkg::DW_LIC, AW: magia_tile_pkg::AWC, - BW: hci_package::DEFAULT_BW, + BW: magia_pkg::BYTE_W, UW: magia_tile_pkg::UW_LIC, - IW: hci_package::DEFAULT_IW, + IW: magia_tile_pkg::IW, EW: hci_package::DEFAULT_EW, EHW: hci_package::DEFAULT_EHW }; @@ -722,18 +872,18 @@ module magia_tile AW: magia_tile_pkg::AWH, BW: hci_package::DEFAULT_BW, UW: magia_tile_pkg::REDMULE_UW, - IW: hci_package::DEFAULT_IW, + IW: magia_tile_pkg::IW, EW: hci_package::DEFAULT_EW, EHW: hci_package::DEFAULT_EHW }; `HCI_INTF_ARRAY(hci_redmule_if, sys_clk, 0:magia_tile_pkg::N_HWPE-1); localparam hci_package::hci_size_parameter_t `HCI_SIZE_PARAM(hci_dma_if) = '{ - DW: magia_tile_pkg::DW_LIC, - AW: magia_tile_pkg::AWC, + DW: magia_tile_pkg::iDMA_DataWidth, + AW: magia_tile_pkg::iDMA_AddrWidth, BW: hci_package::DEFAULT_BW, - UW: magia_tile_pkg::UW_LIC, - IW: hci_package::DEFAULT_IW, + UW: magia_tile_pkg::iDMA_UserWidth, + IW: magia_tile_pkg::IW, EW: hci_package::DEFAULT_EW, EHW: hci_package::DEFAULT_EHW }; @@ -788,13 +938,12 @@ module magia_tile /** Interface Assignments Beginning **/ /*******************************************************/ - `HCI_ASSIGN_TO_INTF(hci_core_if[0], core_l1_data_req, core_l1_data_rsp) // Only 1 core supported - `HCI_ASSIGN_TO_INTF(hci_redmule_if[0], redmule_data_req, redmule_data_rsp) // Only 1 RedMulE supported - `HCI_ASSIGN_TO_INTF(hci_dma_if[magia_tile_pkg::HCI_DMA_CH_READ_IDX], idma_hci_read_req, idma_hci_read_rsp) // iDMA HCI read channel - `HCI_ASSIGN_TO_INTF(hci_dma_if[magia_tile_pkg::HCI_DMA_CH_WRITE_IDX], idma_hci_write_req, idma_hci_write_rsp) // iDMA HCI write channel - - `AXI_ASSIGN_REQ_STRUCT(axi_xbar_data_out_req, axi_xbar_mst_req[magia_tile_pkg::OBI_CORE_IDX]) - `AXI_ASSIGN_RESP_STRUCT(axi_xbar_mst_rsp[magia_tile_pkg::OBI_CORE_IDX], axi_xbar_data_out_rsp) + `HCI_ASSIGN_TO_INTF(hci_core_if[0], core_l1_data_req, core_l1_data_rsp) // Only 1 core supported + `HCI_ASSIGN_TO_INTF(hci_redmule_if[0], redmule_data_req, redmule_data_rsp) // Only 1 RedMulE supported + `HCI_ASSIGN_TO_INTF(hci_dma_if[magia_tile_pkg::HCI_DMA_OUT_CH_READ_IDX], idma_hci_read_req_out, idma_hci_read_rsp_out) // iDMA out HCI read channel + `HCI_ASSIGN_TO_INTF(hci_dma_if[magia_tile_pkg::HCI_DMA_OUT_CH_WRITE_IDX], idma_hci_write_req_out, idma_hci_write_rsp_out) // iDMA out HCI write channel + `HCI_ASSIGN_TO_INTF(hci_dma_if[magia_tile_pkg::HCI_DMA_IN_CH_READ_IDX], idma_hci_read_req_in, idma_hci_read_rsp_in) // iDMA in HCI read channel + `HCI_ASSIGN_TO_INTF(hci_dma_if[magia_tile_pkg::HCI_DMA_IN_CH_WRITE_IDX], idma_hci_write_req_in, idma_hci_write_rsp_in) // iDMA in HCI write channel /*******************************************************/ /** Interface Assignments End **/ @@ -844,7 +993,6 @@ module magia_tile .x_result_valid_o ( ), // Not used in HWPE mode .x_result_ready_i ( 1'b0 ), // Not used in HWPE mode `endif - .data_req_o ( redmule_data_req ), .data_rsp_i ( redmule_data_rsp ), @@ -852,6 +1000,7 @@ module magia_tile .ctrl_rsp_o ( redmule_ctrl_rsp ) ); + /*******************************************************/ /** RedMulE End **/ /*******************************************************/ @@ -1175,31 +1324,33 @@ module magia_tile /** Local Interconnect (HCI) Beginning **/ /*******************************************************/ - hci_interconnect #( - .N_HWPE ( magia_tile_pkg::N_HWPE ), - .N_CORE ( magia_tile_pkg::N_CORE ), - .N_DMA ( magia_tile_pkg::N_DMA ), - .N_EXT ( magia_tile_pkg::N_EXT ), - .N_MEM ( N_MEM_BANKS ), - .TS_BIT ( magia_tile_pkg::TS_BIT ), - .IW ( magia_tile_pkg::IW ), - .EXPFIFO ( magia_tile_pkg::EXPFIFO ), - .SEL_LIC ( magia_tile_pkg::SEL_LIC ), - .`HCI_SIZE_PARAM(cores) ( `HCI_SIZE_PARAM(hci_core_if) ), - .`HCI_SIZE_PARAM(mems) ( `HCI_SIZE_PARAM(hci_tcdm_sram_if) ), - .`HCI_SIZE_PARAM(hwpe) ( `HCI_SIZE_PARAM(hci_redmule_if) ) + local_interconnect #( + .N_HWPE ( magia_tile_pkg::N_HWPE ), + .N_DMA ( magia_tile_pkg::N_DMA ), + .N_CORE ( magia_tile_pkg::N_CORE ), + .N_MEM ( N_MEM_BANKS ), + .EXPFIFO ( magia_tile_pkg::EXPFIFO ), + .FILTER_WRITE_R_VALID ( /*DO NOT OVERWRITE*/ ), + .MEM_DATA_W ( magia_tile_pkg::DW_LIC ), + .MEM_ADDR_W ( magia_tile_pkg::AWM ), + .MEM_BYTE_W ( magia_tile_pkg::BW_LIC ), + .MEM_USER_W ( magia_tile_pkg::UW_LIC ), + .MEM_ID_W ( magia_tile_pkg::IW ), + .HCI_SIZE_hwpe (`HCI_SIZE_PARAM(hci_redmule_if) ), + .HCI_SIZE_dma (`HCI_SIZE_PARAM(hci_dma_if) ), + .HCI_SIZE_core (`HCI_SIZE_PARAM(hci_core_if) ), + .HCI_SIZE_mem (`HCI_SIZE_PARAM(hci_tcdm_sram_if)) ) i_local_interconnect ( - .clk_i ( sys_clk ), - .rst_ni ( rst_ni ), - .clear_i ( hci_clear ), + .clk_i ( sys_clk ), + .rst_ni ( rst_ni ), - .ctrl_i ( hci_ctrl ), + .clear_i ( hci_clear ), + .ctrl_i ( hci_ctrl ), - .cores ( hci_core_if ), - .dma ( hci_dma_if ), - .ext ( hci_ext_if ), - .mems ( hci_tcdm_sram_if ), - .hwpe ( hci_redmule_if ) + .hwpe ( hci_redmule_if ), + .dma ( hci_dma_if ), + .core ( hci_core_if ), + .mem ( hci_tcdm_sram_if ) ); /*******************************************************/ @@ -1265,17 +1416,17 @@ module magia_tile .xif_issue_if_i ( xif_coproc_if.coproc_issue[magia_tile_pkg::XIF_IDMA_IDX] ), - .axi_read_req_o ( idma_axi_read_req ), - .axi_read_rsp_i ( idma_axi_read_rsp ), + .axi_read_req_o ( idma_axi_read_req_out ), + .axi_read_rsp_i ( idma_axi_read_rsp_out ), - .axi_write_req_o ( idma_axi_write_req ), - .axi_write_rsp_i ( idma_axi_write_rsp ), + .axi_write_req_o ( idma_axi_write_req_out ), + .axi_write_rsp_i ( idma_axi_write_rsp_out ), - .obi_read_req_o ( idma_obi_read_req ), - .obi_read_rsp_i ( idma_obi_read_rsp ), + .obi_read_req_o ( idma_obi_read_req_out ), + .obi_read_rsp_i ( idma_obi_read_rsp_out ), - .obi_write_req_o ( idma_obi_write_req ), - .obi_write_rsp_i ( idma_obi_write_rsp ), + .obi_write_req_o ( idma_obi_write_req_out ), + .obi_write_rsp_i ( idma_obi_write_rsp_out ), .axi2obi_start_o ( idma_axi2obi_start ), .axi2obi_busy_o ( idma_axi2obi_busy ), @@ -1309,16 +1460,16 @@ module magia_tile .obi_rsp_o ( core_mem_data_rsp[magia_tile_pkg::OBI_XBAR_IDMA_IDX] ), // AXI Master Interfaces (to L2 memory) - .axi_read_req_o ( idma_axi_read_req ), - .axi_read_rsp_i ( idma_axi_read_rsp ), - .axi_write_req_o ( idma_axi_write_req ), - .axi_write_rsp_i ( idma_axi_write_rsp ), + .axi_read_req_o ( idma_axi_read_req_out ), + .axi_read_rsp_i ( idma_axi_read_rsp_out ), + .axi_write_req_o ( idma_axi_write_req_out ), + .axi_write_rsp_i ( idma_axi_write_rsp_out ), // OBI Master Interfaces (to L1 memory) - .obi_read_req_o ( idma_obi_read_req ), - .obi_read_rsp_i ( idma_obi_read_rsp ), - .obi_write_req_o ( idma_obi_write_req ), - .obi_write_rsp_i ( idma_obi_write_rsp ), + .obi_read_req_o ( idma_obi_read_req_out ), + .obi_read_rsp_i ( idma_obi_read_rsp_out ), + .obi_write_req_o ( idma_obi_write_req_out ), + .obi_write_rsp_i ( idma_obi_write_rsp_out ), // Serialized IRQ outputs .irq_a2o_busy_o ( idma_axi2obi_busy ), @@ -1336,14 +1487,14 @@ module magia_tile .axi_req_t ( magia_tile_pkg::idma_axi_req_t ), .axi_resp_t ( magia_tile_pkg::idma_axi_rsp_t ) ) i_axi_rw_join ( - .clk_i ( sys_clk ), - .rst_ni ( rst_ni ), - .slv_read_req_i ( idma_axi_read_req ), - .slv_read_resp_o ( idma_axi_read_rsp ), - .slv_write_req_i ( idma_axi_write_req ), - .slv_write_resp_o ( idma_axi_write_rsp ), - .mst_req_o ( idma_axi_req ), - .mst_resp_i ( idma_axi_rsp ) + .clk_i ( sys_clk ), + .rst_ni ( rst_ni ), + .slv_read_req_i ( idma_axi_read_req_out ), + .slv_read_resp_o ( idma_axi_read_rsp_out ), + .slv_write_req_i ( idma_axi_write_req_out ), + .slv_write_resp_o ( idma_axi_write_rsp_out ), + .mst_req_o ( idma_axi_req_out ), + .mst_resp_i ( idma_axi_rsp_out ) ); /*******************************************************/ @@ -1417,16 +1568,16 @@ module magia_tile .mst_resp_t ( magia_pkg::axi_xbar_mst_rsp_t ), .rule_t ( axi_pkg::xbar_rule_32_t ) ) i_axi_xbar ( - .clk_i ( sys_clk ), - .rst_ni ( rst_ni ), - .test_i ( test_mode_i ), - .slv_ports_req_i ( axi_xbar_data_in_req ), - .slv_ports_resp_o ( axi_xbar_data_in_rsp ), - .mst_ports_req_o ( axi_xbar_mst_req ), - .mst_ports_resp_i ( axi_xbar_mst_rsp ), - .addr_map_i ( axi_xbar_rule ), - .en_default_mst_port_i ( en_default_mst_port ), - .default_mst_port_i ( '0 ) + .clk_i ( sys_clk ), + .rst_ni ( rst_ni ), + .test_i ( test_mode_i ), + .slv_ports_req_i ( axi_xbar_slv_req ), + .slv_ports_resp_o ( axi_xbar_slv_rsp ), + .mst_ports_req_o ( axi_xbar_mst_req ), + .mst_ports_resp_i ( axi_xbar_mst_rsp ), + .addr_map_i ( axi_xbar_rule ), + .en_default_mst_port_i ( en_default_mst_port ), + .default_mst_port_i ( '0 ) ); /*******************************************************/ @@ -1435,40 +1586,9 @@ module magia_tile /** FlooNoC Modules Beginning **/ /*******************************************************/ - floo_axi_chimney #( - .AxiCfg ( AxiCfg ), - .ChimneyCfg ( set_ports(ChimneyDefaultCfg, 1'b1, 1'b1) ), - .RouteCfg ( RouteCfg ), - .id_t ( id_t ), - .rob_idx_t ( rob_idx_t ), - .hdr_t ( hdr_t ), - .sam_rule_t ( sam_rule_t ), - .Sam ( Sam ), - .axi_in_req_t ( axi_data_slv_req_t ), - .axi_in_rsp_t ( axi_data_slv_rsp_t ), - .axi_out_req_t ( axi_data_mst_req_t ), - .axi_out_rsp_t ( axi_data_mst_rsp_t ), - .floo_req_t ( floo_req_t ), - .floo_rsp_t ( floo_rsp_t ) - ) i_magia_tile_ni ( - .clk_i ( sys_clk ), - .rst_ni ( rst_ni ), - .test_enable_i ( test_mode_i ), - .sram_cfg_i ( '0 ), - .axi_in_req_i ( axi_xbar_data_out_req ), - .axi_in_rsp_o ( axi_xbar_data_out_rsp ), - .axi_out_req_o ( axi_xbar_data_in_req[magia_tile_pkg::AXI_EXT_IDX] ), - .axi_out_rsp_i ( axi_xbar_data_in_rsp[magia_tile_pkg::AXI_EXT_IDX] ), - .id_i ( floo_id ), - .route_table_i ( '0 ), - .floo_req_o ( floo_router_req_in[4] ), - .floo_rsp_i ( floo_router_rsp_out[4] ), - .floo_req_i ( floo_router_req_out[4] ), - .floo_rsp_o ( floo_router_rsp_in[4] ) - ); - - floo_axi_router #( - .AxiCfg ( AxiCfg ), + floo_nw_router #( + .AxiCfgN ( AxiCfgN ), + .AxiCfgW ( AxiCfgW ), .RouteAlgo ( XYRouting ), .NumRoutes ( 5 ), .NumInputs ( 5 ), @@ -1478,44 +1598,114 @@ module magia_tile .id_t ( id_t ), .hdr_t ( hdr_t ), .floo_req_t ( floo_req_t ), - .floo_rsp_t ( floo_rsp_t ) + .floo_rsp_t ( floo_rsp_t ), + .floo_wide_t ( floo_wide_t ) ) i_magia_tile_router ( - .clk_i ( sys_clk ), - .rst_ni ( rst_ni ), - .test_enable_i ( test_mode_i ), - .id_i ( floo_id ), - .id_route_map_i ( '0 ), - .floo_req_i ( floo_router_req_in ), - .floo_rsp_o ( floo_router_rsp_out ), - .floo_req_o ( floo_router_req_out ), - .floo_rsp_i ( floo_router_rsp_in ) + .clk_i ( sys_clk ), + .rst_ni ( rst_ni ), + .test_enable_i ( test_mode_i ), + .id_i ( floo_id ), + .id_route_map_i ( '0 ), + .floo_req_i ( floo_router_req_in ), + .floo_rsp_o ( floo_router_rsp_out ), + .floo_req_o ( floo_router_req_out ), + .floo_rsp_i ( floo_router_rsp_in ), + .floo_wide_i ( floo_router_wide_in ), + .floo_wide_o ( floo_router_wide_out ) ); // Output requests assign noc_south_req_o = floo_router_req_out[0]; assign floo_router_rsp_in[0] = noc_south_rsp_i; + assign noc_south_wide_o = floo_router_wide_out[0]; assign noc_east_req_o = floo_router_req_out[1]; assign floo_router_rsp_in[1] = noc_east_rsp_i; + assign noc_east_wide_o = floo_router_wide_out[1]; assign noc_north_req_o = floo_router_req_out[2]; assign floo_router_rsp_in[2] = noc_north_rsp_i; + assign noc_north_wide_o = floo_router_wide_out[2]; assign noc_west_req_o = floo_router_req_out[3]; assign floo_router_rsp_in[3] = noc_west_rsp_i; + assign noc_west_wide_o = floo_router_wide_out[3]; // Input requests assign floo_router_req_in[0] = noc_south_req_i; assign noc_south_rsp_o = floo_router_rsp_out[0]; + assign floo_router_wide_in[0] = noc_south_wide_i; assign floo_router_req_in[1] = noc_east_req_i; assign noc_east_rsp_o = floo_router_rsp_out[1]; + assign floo_router_wide_in[1] = noc_east_wide_i; assign floo_router_req_in[2] = noc_north_req_i; assign noc_north_rsp_o = floo_router_rsp_out[2]; + assign floo_router_wide_in[2] = noc_north_wide_i; assign floo_router_req_in[3] = noc_west_req_i; assign noc_west_rsp_o = floo_router_rsp_out[3]; + assign floo_router_wide_in[3] = noc_west_wide_i; + + floo_nw_chimney #( + .AxiCfgN ( AxiCfgN ), + .AxiCfgW ( AxiCfgW ), + .ChimneyCfgN ( set_ports(ChimneyDefaultCfg, 1'b1, 1'b1) ), + .ChimneyCfgW ( set_ports(ChimneyDefaultCfg, 1'b1, 1'b1) ), + .RouteCfg ( RouteCfg ), + .id_t ( id_t ), + .rob_idx_t ( rob_idx_t ), + .hdr_t ( hdr_t ), + .sam_rule_t ( sam_rule_t ), + .Sam ( Sam ), + .axi_narrow_in_req_t ( axi_narrow_data_slv_req_t ), + .axi_narrow_in_rsp_t ( axi_narrow_data_slv_rsp_t ), + .axi_narrow_out_req_t ( axi_narrow_data_mst_req_t ), + .axi_narrow_out_rsp_t ( axi_narrow_data_mst_rsp_t ), + .axi_wide_in_req_t ( axi_wide_data_slv_req_t ), + .axi_wide_in_rsp_t ( axi_wide_data_slv_rsp_t ), + .axi_wide_out_req_t ( axi_wide_data_mst_req_t ), + .axi_wide_out_rsp_t ( axi_wide_data_mst_rsp_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ), + .floo_wide_t ( floo_wide_t ) + ) i_magia_tile_ni ( + .clk_i ( sys_clk ), + .rst_ni ( rst_ni ), + .test_enable_i ( test_mode_i ), + .sram_cfg_i ( '0 ), + .axi_narrow_in_req_i ( axi_xbar_mst_req[magia_tile_pkg::AXI_MST_EXT_IDX] ), + .axi_narrow_in_rsp_o ( axi_xbar_mst_rsp[magia_tile_pkg::AXI_MST_EXT_IDX] ), + .axi_narrow_out_req_o ( axi_xbar_slv_req[magia_tile_pkg::AXI_SLV_EXT_IDX] ), + .axi_narrow_out_rsp_i ( axi_xbar_slv_rsp[magia_tile_pkg::AXI_SLV_EXT_IDX] ), + .axi_wide_in_req_i ( idma_axi_req_out ), + .axi_wide_in_rsp_o ( idma_axi_rsp_out ), + .axi_wide_out_req_o ( idma_axi_req_in ), + .axi_wide_out_rsp_i ( idma_axi_rsp_in ), + .id_i ( floo_id ), + .route_table_i ( '0 ), + .floo_req_o ( floo_router_req_in[4] ), + .floo_rsp_i ( floo_router_rsp_out[4] ), + .floo_wide_o ( floo_router_wide_in[4] ), + .floo_req_i ( floo_router_req_out[4] ), + .floo_rsp_o ( floo_router_rsp_in[4] ), + .floo_wide_i ( floo_router_wide_out[4] ) + ); + + axi_rw_split #( + .axi_req_t ( magia_tile_pkg::idma_axi_req_t ), + .axi_resp_t ( magia_tile_pkg::idma_axi_rsp_t ) + ) i_axi_rw_split ( + .clk_i ( sys_clk ), + .rst_ni ( rst_ni ), + .slv_req_i ( idma_axi_req_in ), + .slv_resp_o ( idma_axi_rsp_in ), + .mst_read_req_o ( idma_axi_read_req_in ), + .mst_read_resp_i ( idma_axi_read_rsp_in ), + .mst_write_req_o ( idma_axi_write_req_in ), + .mst_write_resp_i ( idma_axi_write_rsp_in ) + ); /*******************************************************/ /** FlooNoC Modules End **/ diff --git a/hw/tile/magia_tile_pkg.sv b/hw/tile/magia_tile_pkg.sv index 4f06773..aee6c3c 100644 --- a/hw/tile/magia_tile_pkg.sv +++ b/hw/tile/magia_tile_pkg.sv @@ -75,13 +75,23 @@ package magia_tile_pkg; localparam logic [magia_pkg::ADDR_W-1:0] L2_SIZE = 32'h4000_0000; localparam logic [magia_pkg::ADDR_W-1:0] L2_ADDR_END = L2_ADDR_START + L2_SIZE; + // Parameters used by AXI + parameter int unsigned AXI_DATA_ID_W = 2; // Width of the AXI Data ID (2 bits: Core, iDMA, I$, ext) + parameter int unsigned AXI_INSTR_ID_W = 1; // Width of the AXI Instruction ID (0 bits: direct Core - I$ connection) + parameter int unsigned AXI_ID_W = 2; // Width of the AXI Unified Communication Channel ID + parameter int unsigned AXI_DATA_U_W = magia_pkg::USR_W; // Width of the AXI Data User + parameter int unsigned AXI_INSTR_U_W = magia_pkg::USR_W; // Width of the AXI Instruction User + parameter int unsigned AXI_U_W = magia_pkg::USR_W; // Width of the AXI Unified Communication Channel User + // Parameters used by the HCI parameter int unsigned N_HWPE = 1; // Number of HWPEs attached to the port parameter int unsigned N_CORE = 1; // Number of Core ports - parameter int unsigned N_DMA = 2; // Number of DMA ports (1 for the read channel and 1 for the write channel) - typedef enum logic{ - HCI_DMA_CH_READ_IDX = 1'b0, - HCI_DMA_CH_WRITE_IDX = 1'b1 + parameter int unsigned N_DMA = 4; // Number of DMA ports (1 out read channel, 1 out write channel, 1 in read channel and 1 in write channel) + typedef enum logic[1:0]{ + HCI_DMA_OUT_CH_READ_IDX = 2'b00, + HCI_DMA_OUT_CH_WRITE_IDX = 2'b01, + HCI_DMA_IN_CH_READ_IDX = 2'b10, + HCI_DMA_IN_CH_WRITE_IDX = 2'b11 } hci_idma_ch_idx_e; // Index of the HCI DMA read and write channels parameter int unsigned N_EXT = 0; // Number of External ports - LEAVE TO 0 UNLESS YOU KNOW WHAT YOU ARE DOING parameter int unsigned AWC = magia_pkg::ADDR_W; // Address width core (slave ports) @@ -105,6 +115,12 @@ package magia_tile_pkg; localparam int unsigned SWH = DWH/BWH; // Strobe Width for HWPE Interconnect localparam int unsigned WDH = DWH/WWH; // Number of words per data for HWPE Interconnect + // Parameters used by RedMulE + parameter int unsigned REDMULE_DW = DWH - 32; // RedMulE Data Width: Hx(P+1)xBits + Bank width = 8x(1+1)x16+32 + parameter int unsigned REDMULE_UW = UWH; // RedMulE User Width + parameter int unsigned REDMULE_ID_W = magia_pkg::ID_W + + magia_pkg::ID_W_OFFSET; // RedMulE ID Width + // Parameters used by the cv32e40x core parameter bit X_EXT_EN = 1; // Enable eXtension Interface (X) support, see eXtension Interface parameter int unsigned X_ID_W = 4; // Identification width for the eXtension interface @@ -150,53 +166,15 @@ package magia_tile_pkg; // Parameters used by Event Unit parameter int unsigned EVENT_UNIT_IRQ_WIDTH = 5; // Width of Event Unit IRQ ID signals (supports up to 32 different event types) - // Parameters used by RedMulE - parameter int unsigned REDMULE_DW = DWH-32; // RedMulE Data Width - parameter int unsigned REDMULE_ID_W = magia_pkg::ID_W + - magia_pkg::ID_W_OFFSET; // RedMulE ID Width - parameter int unsigned REDMULE_UW = UWH; // RedMulE User Width - - // Parameters used by OBI - parameter int unsigned AUSER_WIDTH = 1; // Width of the auser signal (see OBI documentation): not used by the CV32E40X - parameter int unsigned WUSER_WIDTH = 1; // Width of the wuser signal (see OBI documentation): not used by the CV32E40X - parameter int unsigned ACHK_WIDTH = 1; // Width of the achk signal (see OBI documentation): not used by the CV32E40X - parameter int unsigned RUSER_WIDTH = 1; // Width of the ruser signal (see OBI documentation): not used by the CV32E40X - parameter int unsigned RCHK_WIDTH = 1; // Width of the rchk signal (see OBI documentation): not used by the CV32E40X - parameter int unsigned AID_WIDTH = 1; // Width of the aid signal (address channel identifier, see OBI documentation) - parameter int unsigned RID_WIDTH = 1; // Width of the rid signal (response channel identifier, see OBI documentation) - parameter int unsigned MID_WIDTH = 1; // Width of the mid signal (manager identifier, see OBI documentation) - parameter int unsigned OBI_ID_WIDTH = 1; // Width of the id - configuration -`ifdef CV32E40X - parameter int unsigned N_SBR = 2; // Number of slaves (HCI, AXI XBAR) -`else - parameter int unsigned N_SBR = 5; // Number of slaves (HCI, AXI XBAR, RedMulE_Ctrl, iDMA_Ctrl, FSync_Ctrl) - Event_Unit now via eu_direct_link -`endif - parameter int unsigned N_MGR = 2; // Number of masters (Core, AXI XBAR) - parameter int unsigned N_MAX_TRAN = 1; // Number of maximum outstanding transactions -`ifdef CV32E40X - parameter int unsigned N_ADDR_RULE = 4; // Number of address rules (L2, L1, Stack, Reserved) -`else - parameter int unsigned N_ADDR_RULE = 7; // Number of address rules (L2, L1, Stack, Reserved, RedMulE_Ctrl, iDMA_Ctrl, FSync_Ctrl) - Event_Unit now via eu_direct_link -`endif - localparam int unsigned N_BIT_SBR = $clog2(N_SBR); // Number of bits required to identify each slave - - // Parameters used by AXI - parameter int unsigned AXI_DATA_ID_W = 2; // Width of the AXI Data ID (2 bits: Core, iDMA, I$, ext) - parameter int unsigned AXI_INSTR_ID_W = 1; // Width of the AXI Instruction ID (0 bits: direct Core - I$ connection) - parameter int unsigned AXI_ID_W = 2; // Width of the AXI Unified Communication Channel ID - parameter int unsigned AXI_DATA_U_W = magia_pkg::USR_W; // Width of the AXI Data User - parameter int unsigned AXI_INSTR_U_W = magia_pkg::USR_W; // Width of the AXI Instruction User - parameter int unsigned AXI_U_W = magia_pkg::USR_W; // Width of the AXI Unified Communication Channel User - // Parameters used by the iDMA localparam int unsigned iDMA_NumDims = 3; // iDMA Number of dimensions localparam int unsigned NumDim = iDMA_NumDims; // Needed by the iDMA typedef (wtf?) - parameter int unsigned iDMA_DataWidth = magia_pkg::DATA_W; // iDMA Data Width + parameter int unsigned iDMA_DataWidth = magia_pkg::WIDE_DATA_W; // iDMA Data Width parameter int unsigned iDMA_AddrWidth = magia_pkg::ADDR_W; // iDMA Address Width parameter int unsigned iDMA_UserWidth = AXI_DATA_U_W; // iDMA AXI User Width - parameter int unsigned iDMA_StrbWidth = magia_pkg::STRB_W; // iDMA AXI Strobe Width + parameter int unsigned iDMA_StrbWidth = magia_pkg::WIDE_STRB_W; // iDMA AXI Strobe Width parameter int unsigned iDMA_AxiIdWidth = AXI_DATA_ID_W; // iDMA AXI ID Width - parameter int unsigned iDMA_NumAxInFlight = 2; // iDMA Number of transaction that can be in-flight concurrently + parameter int unsigned iDMA_NumAxInFlight = 16; // iDMA Number of transaction that can be in-flight concurrently parameter int unsigned iDMA_BufferDepth = 3; // iDMA depth of the internal reorder buffer: '2' - minimal possible configuration; '3' - efficiently handle misaligned transfers (recommended) parameter int unsigned iDMA_TFLenWidth = 32; // iDMA With of a transfer: max transfer size is `2**TFLenWidth` bytes parameter int unsigned iDMA_MemSysDepth = 0; // iDMA depth of the memory system the backend is attached to @@ -208,7 +186,7 @@ package magia_tile_pkg; parameter int unsigned iDMA_PrintFifoInfo = 0; // iDMA Print the info of the FIFO configuration parameter int unsigned iDMA_NumRegs = 1; // iDMA Number of configuration register ports parameter int unsigned iDMA_NumStreams = 1; // iDMA Number of streams (max 16) - parameter int unsigned iDMA_JobFifoDepth = 2; // iDMA Stream FIFO depth + parameter int unsigned iDMA_JobFifoDepth = 16; // iDMA Stream FIFO depth parameter int unsigned iDMA_IdCounterWidth = 32; // iDMA Width of the transfer id (max 32-bit) parameter int unsigned iDMA_RepWidth = 32; // iDMA Width of the reps field localparam logic[iDMA_NumDims-1:0][31:0] @@ -218,6 +196,30 @@ package magia_tile_pkg; AXI2OBI = 1'b0, OBI2AXI = 1'b1 } idma_transfer_ch_e; // iDMA type of transfer channel + + // Parameters used by OBI + parameter int unsigned AUSER_WIDTH = 1; // Width of the auser signal (see OBI documentation): not used by the CV32E40X + parameter int unsigned WUSER_WIDTH = 1; // Width of the wuser signal (see OBI documentation): not used by the CV32E40X + parameter int unsigned ACHK_WIDTH = 1; // Width of the achk signal (see OBI documentation): not used by the CV32E40X + parameter int unsigned RUSER_WIDTH = 1; // Width of the ruser signal (see OBI documentation): not used by the CV32E40X + parameter int unsigned RCHK_WIDTH = 1; // Width of the rchk signal (see OBI documentation): not used by the CV32E40X + parameter int unsigned AID_WIDTH = 1; // Width of the aid signal (address channel identifier, see OBI documentation) + parameter int unsigned RID_WIDTH = 1; // Width of the rid signal (response channel identifier, see OBI documentation) + parameter int unsigned MID_WIDTH = 1; // Width of the mid signal (manager identifier, see OBI documentation) + parameter int unsigned OBI_ID_WIDTH = 1; // Width of the id - configuration +`ifdef CV32E40X + parameter int unsigned N_SBR = 2; // Number of slaves (HCI, AXI XBAR) +`else + parameter int unsigned N_SBR = 5; // Number of slaves (HCI, AXI XBAR, RedMulE_Ctrl, iDMA_Ctrl, FSync_Ctrl) - Event_Unit now via eu_direct_link +`endif + parameter int unsigned N_MGR = 2; // Number of masters (Core, AXI XBAR) + parameter int unsigned N_MAX_TRAN = 1; // Number of maximum outstanding transactions +`ifdef CV32E40X + parameter int unsigned N_ADDR_RULE = 4; // Number of address rules (L2, L1, Stack, Reserved) +`else + parameter int unsigned N_ADDR_RULE = 7; // Number of address rules (L2, L1, Stack, Reserved, RedMulE_Ctrl, iDMA_Ctrl, FSync_Ctrl) - Event_Unit now via eu_direct_link +`endif + localparam int unsigned N_BIT_SBR = $clog2(N_SBR); // Number of bits required to identify each slave // Parameters used by the Xif Instruction Dispatcher parameter int unsigned N_COPROC = 4; // RedMulE, iDMA, Fractal Sync and FPU @@ -307,8 +309,8 @@ package magia_tile_pkg; parameter bit FSYNC_STALL = 1; // Fractal Sync Stall during synchronization // Parameters of the AXI XBAR - parameter int unsigned AxiXbarNoSlvPorts = 4; // Number of Slave Ports (iDMA, Core Data, Core I$ and ext) - parameter int unsigned AxiXbarNoMstPorts = 2; // Number of Master Ports (to ext and to internal L1 from ext) + parameter int unsigned AxiXbarNoSlvPorts = 3; // Number of Slave Ports (Core Data, Core I$ and ext) + parameter int unsigned AxiXbarNoMstPorts = 2; // Number of Master Ports (OBI XBAR and ext) localparam int unsigned AxiXbarSlvAxiIDWidth = AXI_DATA_ID_W; // Number of bits to indentify each Slave Port parameter int unsigned AxiXbarMaxWTrans = 16; // Maximum number of outstanding transactions per write parameter int unsigned AxiXbarMaxMstTrans = AxiXbarMaxWTrans; // Maximum number of outstanding transactions per master @@ -476,11 +478,15 @@ package magia_tile_pkg; } axi_mem_array_idx_e; typedef enum logic[1:0]{ - AXI_EXT_IDX = 3, - AXI_IDMA_IDX = 2, - AXI_CORE_DATA_IDX = 1, - AXI_CORE_INSTR_IDX = 0 - } axi_xbar_idx_e; + AXI_SLV_CORE_INSTR_IDX = 2, + AXI_SLV_CORE_DATA_IDX = 1, + AXI_SLV_EXT_IDX = 0 + } axi_xbar_slv_idx_e; + + typedef enum logic{ + AXI_MST_OBI_IDX = 1, + AXI_MST_EXT_IDX = 0 + } axi_xbar_mst_idx_e; typedef struct packed { logic[N_SIGN-1:0][SIGN_W-1:0] sign_list; @@ -490,9 +496,9 @@ package magia_tile_pkg; `HWPE_CTRL_TYPEDEF_REQ_T(redmule_ctrl_req_t, logic[AWC-1:0], logic[DWH-1:0], logic[SWH-1:0], logic[IW-1:0]) `HWPE_CTRL_TYPEDEF_RSP_T(redmule_ctrl_rsp_t, logic[DWH-1:0], logic[IW-1:0]) - - `HCI_TYPEDEF_REQ_T(redmule_data_req_t, logic[AWC-1:0], logic[DWH-1:0], logic[SWH-1:0], logic[UWH-1:0], logic[0:0], logic[0:0], logic[0:0]) - `HCI_TYPEDEF_RSP_T(redmule_data_rsp_t, logic[DWH-1:0], logic[UWH-1:0], logic[0:0], logic[0:0], logic[0:0]) + + `HCI_TYPEDEF_REQ_T(redmule_data_req_t, logic[AWC-1:0], logic[DWH-1:0], logic[SWH-1:0], logic[UWH-1:0], logic[IW-1:0], logic[0:0], logic[0:0]) + `HCI_TYPEDEF_RSP_T(redmule_data_rsp_t, logic[DWH-1:0], logic[UWH-1:0], logic[IW-1:0], logic[0:0], logic[0:0]) localparam obi_pkg::obi_optional_cfg_t obi_amo_optional_cfg = obi_pkg::obi_all_optional_config(AUSER_WIDTH, WUSER_WIDTH, RUSER_WIDTH, MID_WIDTH, ACHK_WIDTH, RCHK_WIDTH); localparam obi_pkg::obi_cfg_t obi_amo_cfg = obi_pkg::obi_default_cfg(magia_pkg::ADDR_W, magia_pkg::DATA_W, OBI_ID_WIDTH, obi_amo_optional_cfg); @@ -512,8 +518,8 @@ package magia_tile_pkg; `OBI_TYPEDEF_DEFAULT_REQ_T(core_obi_instr_req_t, core_instr_obi_a_chan_t) `OBI_TYPEDEF_RSP_T(core_obi_instr_rsp_t, core_instr_obi_r_chan_t) - `HCI_TYPEDEF_REQ_T(core_hci_data_req_t, logic[AWC-1:0], logic[DW_LIC-1:0], logic[SW_LIC-1:0], logic[UWH-1:0], logic[0:0], logic[0:0], logic[0:0]) - `HCI_TYPEDEF_RSP_T(core_hci_data_rsp_t, logic[DW_LIC-1:0], logic[UWH-1:0], logic[0:0], logic[0:0], logic[0:0]) + `HCI_TYPEDEF_REQ_T(core_hci_data_req_t, logic[AWC-1:0], logic[DW_LIC-1:0], logic[SW_LIC-1:0], logic[UWH-1:0], logic[IW-1:0], logic[0:0], logic[0:0]) + `HCI_TYPEDEF_RSP_T(core_hci_data_rsp_t, logic[DW_LIC-1:0], logic[UWH-1:0], logic[IW-1:0], logic[0:0], logic[0:0]) `AXI_TYPEDEF_ALL_CT(core_axi_data, core_axi_data_req_t, core_axi_data_rsp_t, logic[magia_pkg::ADDR_W-1:0], logic[AXI_ID_W-1:0], logic[magia_pkg::DATA_W-1:0], logic[magia_pkg::STRB_W-1:0], logic[AXI_U_W-1:0]) `AXI_TYPEDEF_ALL_CT(core_axi_instr, core_axi_instr_req_t, core_axi_instr_rsp_t, logic[magia_pkg::ADDR_W-1:0], logic[AXI_ID_W-1:0], logic[magia_pkg::DATA_W-1:0], logic[magia_pkg::STRB_W-1:0], logic[AXI_U_W-1:0]) @@ -525,20 +531,11 @@ package magia_tile_pkg; `IDMA_TYPEDEF_FULL_ND_REQ_T(idma_nd_req_t, idma_be_req_t, logic[iDMA_RepWidth-1:0], logic[iDMA_StrideWidth-1:0]) `AXI_TYPEDEF_ALL_CT(idma_axi, idma_axi_req_t, idma_axi_rsp_t, logic[iDMA_AddrWidth-1:0], logic[iDMA_AxiIdWidth-1:0], logic[iDMA_DataWidth-1:0], logic[iDMA_StrbWidth-1:0], logic[iDMA_UserWidth-1:0]) - - parameter obi_pkg::obi_optional_cfg_t OptionalCfg = obi_pkg::ObiMinimalOptionalConfig; - parameter obi_pkg::obi_cfg_t obi_cfg = '{ - OptionalCfg : OptionalCfg, - AddrWidth : iDMA_AddrWidth, - DataWidth : iDMA_DataWidth, - IdWidth : iDMA_AxiIdWidth, - UseRReady : 1'b0, - CombGnt : 1'b0, - Integrity : 1'b0, - BeFull : 1'b1 - }; - `OBI_TYPEDEF_ALL(idma_obi, obi_cfg) + localparam obi_pkg::obi_optional_cfg_t obi_idma_optional_cfg = obi_pkg::obi_all_optional_config(AUSER_WIDTH, WUSER_WIDTH, RUSER_WIDTH, MID_WIDTH, ACHK_WIDTH, RCHK_WIDTH); + localparam obi_pkg::obi_cfg_t obi_idma_cfg = obi_pkg::obi_default_cfg(iDMA_AddrWidth, iDMA_DataWidth, iDMA_AxiIdWidth, obi_idma_optional_cfg); + + `OBI_TYPEDEF_ALL(idma_obi, obi_idma_cfg) typedef struct packed { struct packed { @@ -561,8 +558,8 @@ package magia_tile_pkg; `AXI_ALIAS(core_axi_data, axi_xbar_slv, core_axi_data_req_t, axi_xbar_slv_req_t, core_axi_data_rsp_t, axi_xbar_slv_rsp_t) `AXI_ALIAS(core_axi_data, axi_xbar_mst, core_axi_data_req_t, axi_xbar_mst_req_t, core_axi_data_rsp_t, axi_xbar_mst_rsp_t) - `HCI_TYPEDEF_REQ_T(idma_hci_req_t, logic[AWC-1:0], logic[DW_LIC-1:0], logic[SW_LIC-1:0], logic[UWH-1:0], logic[0:0], logic[0:0], logic[0:0]) - `HCI_TYPEDEF_RSP_T(idma_hci_rsp_t, logic[DW_LIC-1:0], logic[UWH-1:0], logic[0:0], logic[0:0], logic[0:0]) + `HCI_TYPEDEF_REQ_T(idma_hci_req_t, logic[iDMA_AddrWidth-1:0], logic[iDMA_DataWidth-1:0], logic[iDMA_StrbWidth-1:0], logic[iDMA_UserWidth-1:0], logic[IW-1:0], logic[0:0], logic[0:0]) + `HCI_TYPEDEF_RSP_T(idma_hci_rsp_t, logic[iDMA_DataWidth-1:0], logic[iDMA_UserWidth-1:0], logic[IW-1:0], logic[0:0], logic[0:0]) localparam axi_pkg::xbar_cfg_t axi_xbar_cfg = '{ NoSlvPorts : AxiXbarNoSlvPorts, diff --git a/target/sim/src/mesh/magia_fixture.sv b/target/sim/src/mesh/magia_fixture.sv index bf55ead..d87e3fe 100644 --- a/target/sim/src/mesh/magia_fixture.sv +++ b/target/sim/src/mesh/magia_fixture.sv @@ -61,10 +61,13 @@ module magia_fixture; logic wu_wfe; - floo_req_t [magia_pkg::N_TILES_Y-1:0] l2_noc_req_o; - floo_rsp_t [magia_pkg::N_TILES_Y-1:0] l2_noc_rsp_i; - floo_req_t [magia_pkg::N_TILES_Y-1:0] l2_noc_req_i; - floo_rsp_t [magia_pkg::N_TILES_Y-1:0] l2_noc_rsp_o; + floo_req_t [magia_pkg::N_TILES_Y-1:0] l2_noc_req_o; + floo_rsp_t [magia_pkg::N_TILES_Y-1:0] l2_noc_rsp_i; + floo_req_t [magia_pkg::N_TILES_Y-1:0] l2_noc_req_i; + floo_rsp_t [magia_pkg::N_TILES_Y-1:0] l2_noc_rsp_o; + + floo_wide_t [magia_pkg::N_TILES_Y-1:0] l2_noc_wide_o; + floo_wide_t [magia_pkg::N_TILES_Y-1:0] l2_noc_wide_i; /*******************************************************/ /** Internal Signal Definitions End **/ @@ -115,7 +118,9 @@ module magia_fixture; .l2_noc_req_i ( l2_noc_req_o ), .l2_noc_rsp_o ( l2_noc_rsp_i ), .l2_noc_req_o ( l2_noc_req_i ), - .l2_noc_rsp_i ( l2_noc_rsp_o ) + .l2_noc_rsp_i ( l2_noc_rsp_o ), + .l2_noc_wide_i ( l2_noc_wide_o ), + .l2_noc_wide_o ( l2_noc_wide_i ) ); /*******************************************************/ diff --git a/target/sim/src/mesh/magia_l2_mem_wrapper.sv b/target/sim/src/mesh/magia_l2_mem_wrapper.sv index 5790af3..05ffe6e 100644 --- a/target/sim/src/mesh/magia_l2_mem_wrapper.sv +++ b/target/sim/src/mesh/magia_l2_mem_wrapper.sv @@ -15,82 +15,144 @@ * SPDX-License-Identifier: SHL-0.51 * * Authors: Alessandro Nadalini + * Victor Isachi * * MAGIA L2 memory wrapper */ +`include "axi/assign.svh" + module magia_l2_mem_wrapper - `ifndef TARGET_STANDALONE_TILE - import magia_noc_pkg::*; - `else - import floo_axi_mesh_1x2_noc_pkg::*; - `endif - import floo_pkg::*; + `ifndef TARGET_STANDALONE_TILE + import magia_noc_pkg::*; + `else + import floo_axi_mesh_1x2_noc_pkg::*; + `endif + import floo_pkg::*; #( parameter int unsigned NumPorts = 32, parameter time ApplDelay = 0ps, parameter time AcqDelay = 0ps ) ( - input logic clk_i, - input logic rst_ni, - input floo_req_t [NumPorts-1:0] noc_req_i, - output floo_rsp_t [NumPorts-1:0] noc_rsp_o, - output floo_req_t [NumPorts-1:0] noc_req_o, - input floo_rsp_t [NumPorts-1:0] noc_rsp_i + input logic clk_i, + input logic rst_ni, + input floo_req_t [NumPorts-1:0] noc_req_i, + output floo_rsp_t [NumPorts-1:0] noc_rsp_o, + output floo_req_t [NumPorts-1:0] noc_req_o, + input floo_rsp_t [NumPorts-1:0] noc_rsp_i, + input floo_wide_t [NumPorts-1:0] noc_wide_i, + output floo_wide_t [NumPorts-1:0] noc_wide_o ); - // AXI bus for L2 memory - magia_pkg::axi_l2_req_t [NumPorts-1:0] l2_data_req; - magia_pkg::axi_l2_rsp_t [NumPorts-1:0] l2_data_rsp; + localparam int unsigned TotalNumPorts = NumPorts*2; // One set of ports for the narrow channels and one for the wide channel + localparam int unsigned AxiMaxReads = 8; // Number of outstanding reads + + // AXI bus for L2 memory + magia_pkg::axi_narrow_l2_req_t [NumPorts-1:0] l2_narrow_data_req; + magia_pkg::axi_narrow_l2_rsp_t [NumPorts-1:0] l2_narrow_data_rsp; + magia_pkg::axi_wide_l2_req_t [NumPorts-1:0] l2_wide_data_req; + magia_pkg::axi_wide_l2_rsp_t [NumPorts-1:0] l2_wide_data_rsp; + + // AXI bus narrow channel upsized + magia_pkg::axi_wide_l2_req_t [NumPorts-1:0] l2_upsize_data_req; + magia_pkg::axi_wide_l2_rsp_t [NumPorts-1:0] l2_upsize_data_rsp; + + // AXI bus total memory port transactions + magia_pkg::axi_wide_l2_req_t [TotalNumPorts-1:0] l2_data_req; + magia_pkg::axi_wide_l2_rsp_t [TotalNumPorts-1:0] l2_data_rsp; + + for (genvar i = 0; i < NumPorts; i++) begin: gen_data_converters + axi_dw_upsizer #( + .AxiMaxReads ( AxiMaxReads ), + .AxiSlvPortDataWidth ( magia_pkg::DATA_W ), + .AxiMstPortDataWidth ( magia_pkg::WIDE_DATA_W ), + .AxiAddrWidth ( magia_pkg::ADDR_W ), + .AxiIdWidth ( magia_tb_pkg::L2_ID_W ), + .aw_chan_t ( magia_pkg::axi_wide_l2_aw_chan_t ), + .mst_w_chan_t ( magia_pkg::axi_wide_l2_w_chan_t ), + .slv_w_chan_t ( magia_pkg::axi_narrow_l2_w_chan_t ), + .b_chan_t ( magia_pkg::axi_wide_l2_b_chan_t ), + .ar_chan_t ( magia_pkg::axi_wide_l2_ar_chan_t ), + .mst_r_chan_t ( magia_pkg::axi_wide_l2_r_chan_t ), + .slv_r_chan_t ( magia_pkg::axi_narrow_l2_r_chan_t ), + .axi_mst_req_t ( magia_pkg::axi_wide_l2_req_t ), + .axi_mst_resp_t ( magia_pkg::axi_wide_l2_rsp_t ), + .axi_slv_req_t ( magia_pkg::axi_narrow_l2_req_t ), + .axi_slv_resp_t ( magia_pkg::axi_narrow_l2_rsp_t ) + ) i_axi_narrow2wide ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( l2_narrow_data_req[i] ), + .slv_resp_o ( l2_narrow_data_rsp[i] ), + .mst_req_o ( l2_upsize_data_req[i] ), + .mst_resp_i ( l2_upsize_data_rsp[i] ) + ); + + `AXI_ASSIGN_REQ_STRUCT(l2_data_req[i], l2_upsize_data_req[i]) + `AXI_ASSIGN_REQ_STRUCT(l2_data_req[NumPorts+i], l2_wide_data_req[i]) + `AXI_ASSIGN_RESP_STRUCT(l2_upsize_data_rsp[i], l2_data_rsp[i]) + `AXI_ASSIGN_RESP_STRUCT(l2_wide_data_rsp[i], l2_data_rsp[NumPorts+i]) + end - generate - for(genvar i=0; i Date: Wed, 4 Mar 2026 10:35:52 +0100 Subject: [PATCH 2/6] Move the printf after the eu_clear_events in case the idma transaction completes before the printf finishes. --- sw/tests/eu_tests/idma_test_event_unit.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sw/tests/eu_tests/idma_test_event_unit.c b/sw/tests/eu_tests/idma_test_event_unit.c index 988d8d9..e53768b 100644 --- a/sw/tests/eu_tests/idma_test_event_unit.c +++ b/sw/tests/eu_tests/idma_test_event_unit.c @@ -166,12 +166,12 @@ int main(void) { uint32_t transfer_id_o2a = transfer_id_2; // OBI2AXI (L1->L2) already started uint32_t transfer_id_a2o = idma_L2ToL1(src_addr, dst_addr, len); // Start AXI2OBI (L2->L1) - printf("iDMA moving concurrently data from L1 to L2 and from L2 to L1...\n"); - // Clear Event Unit and ensure both masks are enabled eu_clear_events(0xFFFFFFFF); eu_enable_events(EU_IDMA_ALL_DONE_MASK); + printf("iDMA moving concurrently data from L1 to L2 and from L2 to L1...\n"); + if (USE_WFE) { eu_idma_wait_completion(EU_WAIT_MODE_WFE); printf("Detected WFE...\n"); @@ -201,4 +201,4 @@ int main(void) { printf("Finished test with %0d errors\n", num_errors); return num_errors; -} \ No newline at end of file +} From 1decfdee95feadc018356c422be6715b751c11ea Mon Sep 17 00:00:00 2001 From: Carlotta Chiarini Date: Mon, 9 Mar 2026 15:24:00 +0100 Subject: [PATCH 3/6] Updated default parameters of local_interconnect --- hw/tile/local_interconnect.sv | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/tile/local_interconnect.sv b/hw/tile/local_interconnect.sv index 84e94bd..e033396 100644 --- a/hw/tile/local_interconnect.sv +++ b/hw/tile/local_interconnect.sv @@ -32,15 +32,15 @@ module local_interconnect parameter int unsigned N_MEM = magia_pkg::N_MEM_BANKS, parameter int unsigned EXPFIFO = magia_tile_pkg::EXPFIFO, parameter int unsigned FILTER_WRITE_R_VALID[0:N_HWPE-1] = '{default: 0}, - parameter int unsigned MEM_DATA_W = magia_tile_pkg::MEM_DATA_W, - parameter int unsigned MEM_ADDR_W = magia_tile_pkg::MEM_ADDR_W, - parameter int unsigned MEM_BYTE_W = magia_tile_pkg::MEM_BYTE_W, - parameter int unsigned MEM_USER_W = magia_tile_pkg::MEM_USER_W, - parameter int unsigned MEM_ID_W = magia_tile_pkg::MEM_ID_W, - parameter hci_size_parameter_t `HCI_SIZE_PARAM(hwpe) = magia_tile_pkg::HCI_SIZE_HWPE, - parameter hci_size_parameter_t `HCI_SIZE_PARAM(dma) = magia_tile_pkg::HCI_SIZE_DMA, - parameter hci_size_parameter_t `HCI_SIZE_PARAM(core) = magia_tile_pkg::HCI_SIZE_CORE, - parameter hci_size_parameter_t `HCI_SIZE_PARAM(mem) = magia_tile_pkg::HCI_SIZE_MEM + parameter int unsigned MEM_DATA_W = 0, + parameter int unsigned MEM_ADDR_W = 0, + parameter int unsigned MEM_BYTE_W = 0, + parameter int unsigned MEM_USER_W = 0, + parameter int unsigned MEM_ID_W = 0, + parameter hci_size_parameter_t `HCI_SIZE_PARAM(hwpe) = '0, + parameter hci_size_parameter_t `HCI_SIZE_PARAM(dma) = '0, + parameter hci_size_parameter_t `HCI_SIZE_PARAM(core) = '0, + parameter hci_size_parameter_t `HCI_SIZE_PARAM(mem) = '0 ) ( input logic clk_i, input logic rst_ni, From 84959db76a3686aba6c59c5373fdb318e2c3ba38 Mon Sep 17 00:00:00 2001 From: Carlotta Chiarini Date: Tue, 10 Mar 2026 17:13:50 +0100 Subject: [PATCH 4/6] Fixed noc package in tile standalone configuration and added the corresponding yml file. --- .../floonoc_axi_nw_mesh_1x2_config.yml | 75 +++++++++++++++++++ target/sim/src/mesh/magia_l2_mem_wrapper.sv | 2 +- .../sim/src/tile/floo_axi_nw_mesh_1x2_pkg.sv | 30 ++++---- target/sim/src/tile/magia_tile_fixture.sv | 2 +- target/sim/src/tile/magia_tile_vip.sv | 18 ++--- 5 files changed, 103 insertions(+), 24 deletions(-) create mode 100644 hw/mesh/noc_configs/floonoc_axi_nw_mesh_1x2_config.yml diff --git a/hw/mesh/noc_configs/floonoc_axi_nw_mesh_1x2_config.yml b/hw/mesh/noc_configs/floonoc_axi_nw_mesh_1x2_config.yml new file mode 100644 index 0000000..191740d --- /dev/null +++ b/hw/mesh/noc_configs/floonoc_axi_nw_mesh_1x2_config.yml @@ -0,0 +1,75 @@ +name: axi_nw_mesh_1x2 +description: "Configuration file for a 1x2 MAGIA Mesh NoC" +network_type: "narrow-wide" + +routing: + route_algo: "XY" + use_id_table: true + +protocols: + - name: "narrow_data_mst" + type: "narrow" + protocol: "AXI4" + data_width: 32 + addr_width: 32 + id_width: 2 + user_width: 1 + - name: "narrow_data_slv" + type: "narrow" + protocol: "AXI4" + data_width: 32 + addr_width: 32 + id_width: 4 + user_width: 1 + - name: "wide_data_mst" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 + - name: "wide_data_slv" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 + +endpoints: + - name: "magia_tile" + addr_range: + base: 0x0000_0000 + size: 0x0010_0000 + mgr_port_protocol: + - "narrow_data_slv" + - "wide_data_slv" + sbr_port_protocol: + - "narrow_data_mst" + - "wide_data_mst" + array: [1] + - name: "L2" + array: [1] + addr_range: + base: 0xC000_0000 + size: 0x2000_0000 + sbr_port_protocol: + - "narrow_data_mst" + - "wide_data_mst" + +routers: + - name: "router" + array: [1,1] + degree: 5 + +connections: + - src: "magia_tile" + dst: "router" + src_idx: 0 + dst_idx: [0,0] + dst_dir: "Eject" + - src: "L2" + dst: "router" + src_idx: 0 + dst_idx: [0,0] + dst_dir: "West" diff --git a/target/sim/src/mesh/magia_l2_mem_wrapper.sv b/target/sim/src/mesh/magia_l2_mem_wrapper.sv index 05ffe6e..15ea475 100644 --- a/target/sim/src/mesh/magia_l2_mem_wrapper.sv +++ b/target/sim/src/mesh/magia_l2_mem_wrapper.sv @@ -26,7 +26,7 @@ module magia_l2_mem_wrapper `ifndef TARGET_STANDALONE_TILE import magia_noc_pkg::*; `else - import floo_axi_mesh_1x2_noc_pkg::*; + import floo_axi_nw_mesh_1x2_noc_pkg::*; `endif import floo_pkg::*; #( diff --git a/target/sim/src/tile/floo_axi_nw_mesh_1x2_pkg.sv b/target/sim/src/tile/floo_axi_nw_mesh_1x2_pkg.sv index 69206be..edeb578 100644 --- a/target/sim/src/tile/floo_axi_nw_mesh_1x2_pkg.sv +++ b/target/sim/src/tile/floo_axi_nw_mesh_1x2_pkg.sv @@ -1,4 +1,4 @@ -// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright 2026 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 @@ -50,8 +50,12 @@ typedef struct packed { } sam_rule_t; localparam sam_rule_t[SamNumRules-1:0] Sam = '{ -'{idx: '{x: 0, y: 0, port_id: 0}, start_addr: 32'hc0000000, end_addr: 32'he0000000},// L2_0_sam_idx -'{idx: '{x: 1, y: 0, port_id: 0}, start_addr: 32'h00000000, end_addr: 32'h00100000} // magia_tile_0_sam_idx +'{ idx: '{x: 0, y: 0, port_id: 0}, + start_addr: 32'hc0000000, + end_addr: 32'he0000000},// L20 +'{ idx: '{x: 1, y: 0, port_id: 0}, + start_addr: 32'h00000000, + end_addr: 32'h00100000} // MagiaTile0 }; @@ -66,7 +70,7 @@ localparam sam_rule_t[SamNumRules-1:0] Sam = '{ NumRoutes: 0}; - typedef logic[31:0] axi_narrow_data_mst_addr_t; + typedef logic[31:0] axi_narrow_data_mst_addr_t; typedef logic[31:0] axi_narrow_data_mst_data_t; typedef logic[3:0] axi_narrow_data_mst_strb_t; typedef logic[1:0] axi_narrow_data_mst_id_t; @@ -74,7 +78,7 @@ typedef logic[0:0] axi_narrow_data_mst_user_t; `AXI_TYPEDEF_ALL_CT(axi_narrow_data_mst, axi_narrow_data_mst_req_t, axi_narrow_data_mst_rsp_t, axi_narrow_data_mst_addr_t, axi_narrow_data_mst_id_t, axi_narrow_data_mst_data_t, axi_narrow_data_mst_strb_t, axi_narrow_data_mst_user_t) - typedef logic[31:0] axi_narrow_data_slv_addr_t; + typedef logic[31:0] axi_narrow_data_slv_addr_t; typedef logic[31:0] axi_narrow_data_slv_data_t; typedef logic[3:0] axi_narrow_data_slv_strb_t; typedef logic[3:0] axi_narrow_data_slv_id_t; @@ -82,7 +86,7 @@ typedef logic[0:0] axi_narrow_data_slv_user_t; `AXI_TYPEDEF_ALL_CT(axi_narrow_data_slv, axi_narrow_data_slv_req_t, axi_narrow_data_slv_rsp_t, axi_narrow_data_slv_addr_t, axi_narrow_data_slv_id_t, axi_narrow_data_slv_data_t, axi_narrow_data_slv_strb_t, axi_narrow_data_slv_user_t) - typedef logic[31:0] axi_wide_data_mst_addr_t; + typedef logic[31:0] axi_wide_data_mst_addr_t; typedef logic[255:0] axi_wide_data_mst_data_t; typedef logic[31:0] axi_wide_data_mst_strb_t; typedef logic[1:0] axi_wide_data_mst_id_t; @@ -90,10 +94,10 @@ typedef logic[0:0] axi_wide_data_mst_user_t; `AXI_TYPEDEF_ALL_CT(axi_wide_data_mst, axi_wide_data_mst_req_t, axi_wide_data_mst_rsp_t, axi_wide_data_mst_addr_t, axi_wide_data_mst_id_t, axi_wide_data_mst_data_t, axi_wide_data_mst_strb_t, axi_wide_data_mst_user_t) - typedef logic[31:0] axi_wide_data_slv_addr_t; + typedef logic[31:0] axi_wide_data_slv_addr_t; typedef logic[255:0] axi_wide_data_slv_data_t; typedef logic[31:0] axi_wide_data_slv_strb_t; -typedef logic[3:0] axi_wide_data_slv_id_t; +typedef logic[1:0] axi_wide_data_slv_id_t; typedef logic[0:0] axi_wide_data_slv_user_t; `AXI_TYPEDEF_ALL_CT(axi_wide_data_slv, axi_wide_data_slv_req_t, axi_wide_data_slv_rsp_t, axi_wide_data_slv_addr_t, axi_wide_data_slv_id_t, axi_wide_data_slv_data_t, axi_wide_data_slv_strb_t, axi_wide_data_slv_user_t) @@ -102,14 +106,14 @@ typedef logic[0:0] axi_wide_data_slv_user_t; `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, nw_ch_e, rob_idx_t) localparam axi_cfg_t AxiCfgN = '{ AddrWidth: 32, DataWidth: 32, - UserWidth: 1, InIdWidth: 4, - OutIdWidth: 2}; + OutIdWidth: 2, + UserWidth: 1}; localparam axi_cfg_t AxiCfgW = '{ AddrWidth: 32, DataWidth: 256, - UserWidth: 1, - InIdWidth: 4, - OutIdWidth: 2}; + InIdWidth: 2, + OutIdWidth: 2, + UserWidth: 1}; `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_data_slv, axi_wide_data_slv, AxiCfgN, AxiCfgW, hdr_t) `FLOO_TYPEDEF_NW_LINK_ALL(req, rsp, wide, req, rsp, wide) diff --git a/target/sim/src/tile/magia_tile_fixture.sv b/target/sim/src/tile/magia_tile_fixture.sv index a00718c..041ccf5 100644 --- a/target/sim/src/tile/magia_tile_fixture.sv +++ b/target/sim/src/tile/magia_tile_fixture.sv @@ -24,7 +24,7 @@ module magia_tile_fixture; import magia_tile_pkg::*; import magia_pkg::*; import magia_tile_tb_pkg::*; - import floo_axi_mesh_1x2_noc_pkg::*; + import floo_axi_nw_mesh_1x2_noc_pkg::*; /*******************************************************/ /** Internal Signal Definitions Beginning **/ diff --git a/target/sim/src/tile/magia_tile_vip.sv b/target/sim/src/tile/magia_tile_vip.sv index 4cb9e8c..801e4a8 100644 --- a/target/sim/src/tile/magia_tile_vip.sv +++ b/target/sim/src/tile/magia_tile_vip.sv @@ -23,7 +23,7 @@ module magia_tile_vip import magia_tile_pkg::*; import magia_pkg::*; import magia_tile_tb_pkg::*; - import floo_axi_mesh_1x2_noc_pkg::*; + import floo_axi_nw_mesh_1x2_noc_pkg::*; #( // Timing parameter time CLK_PERIOD = 5ns, @@ -218,21 +218,21 @@ int errors = -1; bit stdio_ready = 0; bit stderr_ready = 0; always @(posedge clk) begin: print_monitor - if ((i_magia_tile.axi_xbar_data_out_req.aw.addr == 32'hFFFF0000) && (i_magia_tile.axi_xbar_data_out_req.aw_valid)) stderr_ready = 1'b1; - if ((i_magia_tile.axi_xbar_data_out_req.aw.addr == 32'hFFFF0004) && (i_magia_tile.axi_xbar_data_out_req.aw_valid)) stdio_ready = 1'b1; - if ((i_magia_tile.axi_xbar_data_out_req.w_valid) && stderr_ready) begin + if ((i_magia_tile.i_axi_xbar.mst_ports_req_o[0].aw.addr == 32'hFFFF0000) && (i_magia_tile.i_axi_xbar.mst_ports_req_o[0].aw_valid)) stderr_ready = 1'b1; + if ((i_magia_tile.i_axi_xbar.mst_ports_req_o[0].aw.addr == 32'hFFFF0004) && (i_magia_tile.i_axi_xbar.mst_ports_req_o[0].aw_valid)) stdio_ready = 1'b1; + if ((i_magia_tile.i_axi_xbar.mst_ports_req_o[0].w_valid) && stderr_ready) begin // NOTE: This is stupid! But unless we keep track of the outstanding AXI writes (which would require some logic) this should work, // unless other modules (not related to the print function) transfer bytes (instead of words) to the L2 - if (i_magia_tile.axi_xbar_data_out_req.w.data < 256 && i_magia_tile.axi_xbar_data_out_req.w.data > 0) begin - errors = i_magia_tile.axi_xbar_data_out_req.w.data; + if (i_magia_tile.i_axi_xbar.mst_ports_req_o[0].w.data < 256 && i_magia_tile.i_axi_xbar.mst_ports_req_o[0].w.data > 0) begin + errors = i_magia_tile.i_axi_xbar.mst_ports_req_o[0].w.data; stderr_ready = 1'b0; end end - if ((i_magia_tile.axi_xbar_data_out_req.w_valid) && stdio_ready) begin + if ((i_magia_tile.i_axi_xbar.mst_ports_req_o[0].w_valid) && stdio_ready) begin // NOTE: This is stupid! But unless we keep track of the outstanding AXI writes (which would require some logic) this should work, // unless other modules (not related to the print function) transfer bytes (instead of words) to the L2 - if (i_magia_tile.axi_xbar_data_out_req.w.data < 256 && i_magia_tile.axi_xbar_data_out_req.w.data > 0) begin - $write("%c", i_magia_tile.axi_xbar_data_out_req.w.data); + if (i_magia_tile.i_axi_xbar.mst_ports_req_o[0].w.data < 256 && i_magia_tile.i_axi_xbar.mst_ports_req_o[0].w.data > 0) begin + $write("%c", i_magia_tile.i_axi_xbar.mst_ports_req_o[0].w.data); stdio_ready = 1'b0; end end From a842f6a26cae78a9f0ed47752ef13f3d3b0cbb64 Mon Sep 17 00:00:00 2001 From: Carlotta Chiarini Date: Tue, 10 Mar 2026 17:22:56 +0100 Subject: [PATCH 5/6] Minor fix --- ...axi_nw_mesh_1x2_config.yml => floonoc_axi_mesh_1x2_config.yml} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename hw/mesh/noc_configs/{floonoc_axi_nw_mesh_1x2_config.yml => floonoc_axi_mesh_1x2_config.yml} (100%) diff --git a/hw/mesh/noc_configs/floonoc_axi_nw_mesh_1x2_config.yml b/hw/mesh/noc_configs/floonoc_axi_mesh_1x2_config.yml similarity index 100% rename from hw/mesh/noc_configs/floonoc_axi_nw_mesh_1x2_config.yml rename to hw/mesh/noc_configs/floonoc_axi_mesh_1x2_config.yml From 73006c9598654db93ac8ab1de026a2c8b0b4a027 Mon Sep 17 00:00:00 2001 From: Carlotta Chiarini Date: Wed, 11 Mar 2026 12:03:36 +0100 Subject: [PATCH 6/6] Cleanup of the magia_tile_pkg --- hw/tile/magia_tile_pkg.sv | 76 +++++++++++++++++++-------------------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/hw/tile/magia_tile_pkg.sv b/hw/tile/magia_tile_pkg.sv index aee6c3c..02cbc98 100644 --- a/hw/tile/magia_tile_pkg.sv +++ b/hw/tile/magia_tile_pkg.sv @@ -75,14 +75,6 @@ package magia_tile_pkg; localparam logic [magia_pkg::ADDR_W-1:0] L2_SIZE = 32'h4000_0000; localparam logic [magia_pkg::ADDR_W-1:0] L2_ADDR_END = L2_ADDR_START + L2_SIZE; - // Parameters used by AXI - parameter int unsigned AXI_DATA_ID_W = 2; // Width of the AXI Data ID (2 bits: Core, iDMA, I$, ext) - parameter int unsigned AXI_INSTR_ID_W = 1; // Width of the AXI Instruction ID (0 bits: direct Core - I$ connection) - parameter int unsigned AXI_ID_W = 2; // Width of the AXI Unified Communication Channel ID - parameter int unsigned AXI_DATA_U_W = magia_pkg::USR_W; // Width of the AXI Data User - parameter int unsigned AXI_INSTR_U_W = magia_pkg::USR_W; // Width of the AXI Instruction User - parameter int unsigned AXI_U_W = magia_pkg::USR_W; // Width of the AXI Unified Communication Channel User - // Parameters used by the HCI parameter int unsigned N_HWPE = 1; // Number of HWPEs attached to the port parameter int unsigned N_CORE = 1; // Number of Core ports @@ -115,12 +107,6 @@ package magia_tile_pkg; localparam int unsigned SWH = DWH/BWH; // Strobe Width for HWPE Interconnect localparam int unsigned WDH = DWH/WWH; // Number of words per data for HWPE Interconnect - // Parameters used by RedMulE - parameter int unsigned REDMULE_DW = DWH - 32; // RedMulE Data Width: Hx(P+1)xBits + Bank width = 8x(1+1)x16+32 - parameter int unsigned REDMULE_UW = UWH; // RedMulE User Width - parameter int unsigned REDMULE_ID_W = magia_pkg::ID_W + - magia_pkg::ID_W_OFFSET; // RedMulE ID Width - // Parameters used by the cv32e40x core parameter bit X_EXT_EN = 1; // Enable eXtension Interface (X) support, see eXtension Interface parameter int unsigned X_ID_W = 4; // Identification width for the eXtension interface @@ -166,6 +152,44 @@ package magia_tile_pkg; // Parameters used by Event Unit parameter int unsigned EVENT_UNIT_IRQ_WIDTH = 5; // Width of Event Unit IRQ ID signals (supports up to 32 different event types) + // Parameters used by RedMulE + parameter int unsigned REDMULE_DW = DWH-32; // RedMulE Data Width + parameter int unsigned REDMULE_ID_W = magia_pkg::ID_W + + magia_pkg::ID_W_OFFSET; // RedMulE ID Width + parameter int unsigned REDMULE_UW = UWH; // RedMulE User Width + + // Parameters used by OBI + parameter int unsigned AUSER_WIDTH = 1; // Width of the auser signal (see OBI documentation): not used by the CV32E40X + parameter int unsigned WUSER_WIDTH = 1; // Width of the wuser signal (see OBI documentation): not used by the CV32E40X + parameter int unsigned ACHK_WIDTH = 1; // Width of the achk signal (see OBI documentation): not used by the CV32E40X + parameter int unsigned RUSER_WIDTH = 1; // Width of the ruser signal (see OBI documentation): not used by the CV32E40X + parameter int unsigned RCHK_WIDTH = 1; // Width of the rchk signal (see OBI documentation): not used by the CV32E40X + parameter int unsigned AID_WIDTH = 1; // Width of the aid signal (address channel identifier, see OBI documentation) + parameter int unsigned RID_WIDTH = 1; // Width of the rid signal (response channel identifier, see OBI documentation) + parameter int unsigned MID_WIDTH = 1; // Width of the mid signal (manager identifier, see OBI documentation) + parameter int unsigned OBI_ID_WIDTH = 1; // Width of the id - configuration +`ifdef CV32E40X + parameter int unsigned N_SBR = 2; // Number of slaves (HCI, AXI XBAR) +`else + parameter int unsigned N_SBR = 5; // Number of slaves (HCI, AXI XBAR, RedMulE_Ctrl, iDMA_Ctrl, FSync_Ctrl) - Event_Unit now via eu_direct_link +`endif + parameter int unsigned N_MGR = 2; // Number of masters (Core, AXI XBAR) + parameter int unsigned N_MAX_TRAN = 1; // Number of maximum outstanding transactions +`ifdef CV32E40X + parameter int unsigned N_ADDR_RULE = 4; // Number of address rules (L2, L1, Stack, Reserved) +`else + parameter int unsigned N_ADDR_RULE = 7; // Number of address rules (L2, L1, Stack, Reserved, RedMulE_Ctrl, iDMA_Ctrl, FSync_Ctrl) - Event_Unit now via eu_direct_link +`endif + localparam int unsigned N_BIT_SBR = $clog2(N_SBR); // Number of bits required to identify each slave + + // Parameters used by AXI + parameter int unsigned AXI_DATA_ID_W = 2; // Width of the AXI Data ID (2 bits: Core, iDMA, I$, ext) + parameter int unsigned AXI_INSTR_ID_W = 1; // Width of the AXI Instruction ID (0 bits: direct Core - I$ connection) + parameter int unsigned AXI_ID_W = 2; // Width of the AXI Unified Communication Channel ID + parameter int unsigned AXI_DATA_U_W = magia_pkg::USR_W; // Width of the AXI Data User + parameter int unsigned AXI_INSTR_U_W = magia_pkg::USR_W; // Width of the AXI Instruction User + parameter int unsigned AXI_U_W = magia_pkg::USR_W; // Width of the AXI Unified Communication Channel User + // Parameters used by the iDMA localparam int unsigned iDMA_NumDims = 3; // iDMA Number of dimensions localparam int unsigned NumDim = iDMA_NumDims; // Needed by the iDMA typedef (wtf?) @@ -196,30 +220,6 @@ package magia_tile_pkg; AXI2OBI = 1'b0, OBI2AXI = 1'b1 } idma_transfer_ch_e; // iDMA type of transfer channel - - // Parameters used by OBI - parameter int unsigned AUSER_WIDTH = 1; // Width of the auser signal (see OBI documentation): not used by the CV32E40X - parameter int unsigned WUSER_WIDTH = 1; // Width of the wuser signal (see OBI documentation): not used by the CV32E40X - parameter int unsigned ACHK_WIDTH = 1; // Width of the achk signal (see OBI documentation): not used by the CV32E40X - parameter int unsigned RUSER_WIDTH = 1; // Width of the ruser signal (see OBI documentation): not used by the CV32E40X - parameter int unsigned RCHK_WIDTH = 1; // Width of the rchk signal (see OBI documentation): not used by the CV32E40X - parameter int unsigned AID_WIDTH = 1; // Width of the aid signal (address channel identifier, see OBI documentation) - parameter int unsigned RID_WIDTH = 1; // Width of the rid signal (response channel identifier, see OBI documentation) - parameter int unsigned MID_WIDTH = 1; // Width of the mid signal (manager identifier, see OBI documentation) - parameter int unsigned OBI_ID_WIDTH = 1; // Width of the id - configuration -`ifdef CV32E40X - parameter int unsigned N_SBR = 2; // Number of slaves (HCI, AXI XBAR) -`else - parameter int unsigned N_SBR = 5; // Number of slaves (HCI, AXI XBAR, RedMulE_Ctrl, iDMA_Ctrl, FSync_Ctrl) - Event_Unit now via eu_direct_link -`endif - parameter int unsigned N_MGR = 2; // Number of masters (Core, AXI XBAR) - parameter int unsigned N_MAX_TRAN = 1; // Number of maximum outstanding transactions -`ifdef CV32E40X - parameter int unsigned N_ADDR_RULE = 4; // Number of address rules (L2, L1, Stack, Reserved) -`else - parameter int unsigned N_ADDR_RULE = 7; // Number of address rules (L2, L1, Stack, Reserved, RedMulE_Ctrl, iDMA_Ctrl, FSync_Ctrl) - Event_Unit now via eu_direct_link -`endif - localparam int unsigned N_BIT_SBR = $clog2(N_SBR); // Number of bits required to identify each slave // Parameters used by the Xif Instruction Dispatcher parameter int unsigned N_COPROC = 4; // RedMulE, iDMA, Fractal Sync and FPU