diff --git a/src/axi_burst_splitter_gran.sv b/src/axi_burst_splitter_gran.sv index 4a634ef8e..37833aa10 100644 --- a/src/axi_burst_splitter_gran.sv +++ b/src/axi_burst_splitter_gran.sv @@ -396,6 +396,7 @@ module axi_burst_splitter_gran #( // -------------------------------------------------- `ifndef VERILATOR `ifndef XSIM + `ifndef XILINX_SIMULATOR // pragma translate_off default disable iff (!rst_ni); // Inputs @@ -414,6 +415,7 @@ module axi_burst_splitter_gran #( // pragma translate_on `endif `endif + `endif endmodule diff --git a/src/axi_burst_unwrap.sv b/src/axi_burst_unwrap.sv index 59850e2a7..9d3596c54 100644 --- a/src/axi_burst_unwrap.sv +++ b/src/axi_burst_unwrap.sv @@ -365,6 +365,7 @@ module axi_burst_unwrap #( // -------------------------------------------------- `ifndef VERILATOR `ifndef XSIM + `ifndef XILINX_SIMULATOR // pragma translate_off default disable iff (!rst_ni); // Inputs @@ -381,6 +382,7 @@ module axi_burst_unwrap #( // pragma translate_on `endif `endif + `endif endmodule diff --git a/src/axi_demux_id_counters.sv b/src/axi_demux_id_counters.sv index 7e8c88da5..2cb038d80 100644 --- a/src/axi_demux_id_counters.sv +++ b/src/axi_demux_id_counters.sv @@ -133,6 +133,7 @@ module axi_demux_id_counters #( // pragma translate_off `ifndef VERILATOR `ifndef XSIM +`ifndef XILINX_SIMULATOR // Validate parameters. cnt_underflow: assert property( @(posedge clk_i) disable iff (~rst_ni) (pop_en[i] |=> !overflow)) else @@ -140,6 +141,7 @@ module axi_demux_id_counters #( The reason is probably a faulty AXI response.", i); `endif `endif +`endif // pragma translate_on end endmodule diff --git a/src/axi_demux_simple.sv b/src/axi_demux_simple.sv index 3f854c14f..230f8d9b1 100644 --- a/src/axi_demux_simple.sv +++ b/src/axi_demux_simple.sv @@ -469,6 +469,7 @@ module axi_demux_simple #( $fatal(1, "AxiIdBits has to be equal or smaller than AxiIdWidth."); end `ifndef XSIM +`ifndef XILINX_SIMULATOR default disable iff (!rst_ni); aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> (slv_aw_select_i < NoMstPorts))) else @@ -507,6 +508,7 @@ module axi_demux_simple #( `ASSUME(NoAtopAllowed, !AtopSupport && slv_req_i.aw_valid |-> slv_req_i.aw.atop == '0) `endif `endif +`endif // pragma translate_on end endmodule diff --git a/src/axi_err_slv.sv b/src/axi_err_slv.sv index 9035d9a80..6d5f77a12 100644 --- a/src/axi_err_slv.sv +++ b/src/axi_err_slv.sv @@ -249,6 +249,7 @@ module axi_err_slv #( $fatal(1, "This module may only generate RESP_DECERR or RESP_SLVERR responses!"); end `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); if (!ATOPs) begin : gen_assert_atops_unsupported assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> slv_req_i.aw.atop == '0)) else @@ -256,6 +257,7 @@ module axi_err_slv #( end `endif `endif + `endif // pragma translate_on endmodule diff --git a/src/axi_id_remap.sv b/src/axi_id_remap.sv index 86eaa79c2..a2f52f9e8 100644 --- a/src/axi_id_remap.sv +++ b/src/axi_id_remap.sv @@ -383,6 +383,7 @@ module axi_id_remap #( assert ($bits(mst_resp_i.r.id) == AxiMstPortIdWidth); end `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); assert property (@(posedge clk_i) slv_req_i.aw_valid && slv_resp_o.aw_ready |-> mst_req_o.aw_valid && mst_resp_i.aw_ready); @@ -400,6 +401,7 @@ module axi_id_remap #( |=> mst_req_o.aw_valid && $stable(mst_req_o.aw.id)); `endif `endif + `endif // pragma translate_on endmodule @@ -555,6 +557,7 @@ module axi_id_remap_table #( // pragma translate_off `ifndef VERILATOR `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); assume property (@(posedge clk_i) push_i |-> table_q[push_oup_id_i].cnt == '0 || table_q[push_oup_id_i].inp_id == push_inp_id_i) @@ -574,6 +577,7 @@ module axi_id_remap_table #( end `endif `endif + `endif // pragma translate_on endmodule diff --git a/src/axi_interleaved_xbar.sv b/src/axi_interleaved_xbar.sv index 83d215df7..772e74158 100644 --- a/src/axi_interleaved_xbar.sv +++ b/src/axi_interleaved_xbar.sv @@ -164,6 +164,7 @@ import cf_math_pkg::idx_width; // pragma translate_off `ifndef VERILATOR `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); default_aw_mst_port_en: assert property( @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) @@ -187,6 +188,7 @@ import cf_math_pkg::idx_width; "when there is an unserved Ar beat. Slave Port: %0d"}, i)); `endif `endif + `endif // pragma translate_on axi_demux #( .AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), // ID Width @@ -303,6 +305,7 @@ import cf_math_pkg::idx_width; // pragma translate_off `ifndef VERILATOR `ifndef XSIM + `ifndef XILINX_SIMULATOR initial begin : check_params id_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.id ) == Cfg.AxiIdWidthSlvPorts) else $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); @@ -311,6 +314,7 @@ import cf_math_pkg::idx_width; end `endif `endif + `endif // pragma translate_on endmodule : axi_interleaved_xbar diff --git a/src/axi_isolate.sv b/src/axi_isolate.sv index cb9a14852..f3088c3b6 100644 --- a/src/axi_isolate.sv +++ b/src/axi_isolate.sv @@ -393,6 +393,7 @@ module axi_isolate_inner #( assume (NumPending > 0) else $fatal(1, "At least one pending transaction required."); end `ifndef XSIM +`ifndef XILINX_SIMULATOR default disable iff (!rst_ni); aw_overflow: assert property (@(posedge clk_i) (pending_aw_q == '1) |=> (pending_aw_q != '0)) else @@ -408,6 +409,7 @@ module axi_isolate_inner #( $fatal(1, "pending_ar_q underflowed"); `endif `endif +`endif // pragma translate_on endmodule diff --git a/src/axi_lite_demux.sv b/src/axi_lite_demux.sv index 2c025e233..afd041d11 100644 --- a/src/axi_lite_demux.sv +++ b/src/axi_lite_demux.sv @@ -443,6 +443,7 @@ module axi_lite_demux #( // pragma translate_off `ifndef VERILATOR `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); aw_select: assume property( @(posedge clk_i) (slv_req_i.aw_valid |-> (slv_aw_select_i < NoMstPorts))) else @@ -466,6 +467,7 @@ module axi_lite_demux #( $fatal(1, "slv_aw_chan_select unstable with valid set."); `endif `endif + `endif // pragma translate_on end diff --git a/src/axi_lite_dw_converter.sv b/src/axi_lite_dw_converter.sv index 139c2d313..d85f9641a 100644 --- a/src/axi_lite_dw_converter.sv +++ b/src/axi_lite_dw_converter.sv @@ -465,6 +465,7 @@ module axi_lite_dw_converter #( assume ($onehot(AxiMstPortDataWidth)) else $fatal(1, "AxiMstPortDataWidth must be power of 2"); end `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); stable_aw: assert property (@(posedge clk_i) (mst_req_o.aw_valid && !mst_res_i.aw_ready) |=> $stable(mst_req_o.aw)) else @@ -483,6 +484,7 @@ module axi_lite_dw_converter #( $fatal(1, "R must remain stable until handshake happened."); `endif `endif + `endif // pragma translate_on endmodule diff --git a/src/axi_lite_from_mem.sv b/src/axi_lite_from_mem.sv index 2b7e9e38c..9e33b25d7 100644 --- a/src/axi_lite_from_mem.sv +++ b/src/axi_lite_from_mem.sv @@ -236,6 +236,7 @@ module axi_lite_from_mem #( $fatal(1, "DataWidth has to match axi_rsp_i.r.data!"); end `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); assert property (@(posedge clk_i) (mem_req_i && !mem_gnt_o) |=> mem_req_i) else $fatal(1, "It is not allowed to deassert the request if it was not granted!"); @@ -250,5 +251,6 @@ module axi_lite_from_mem #( `endif `endif `endif + `endif // pragma translate_on endmodule diff --git a/src/axi_lite_regs.sv b/src/axi_lite_regs.sv index 392bd17f1..f5828dcc8 100644 --- a/src/axi_lite_regs.sv +++ b/src/axi_lite_regs.sv @@ -381,6 +381,7 @@ module axi_lite_regs #( // pragma translate_off `ifndef VERILATOR `ifndef XSIM + `ifndef XILINX_SIMULATOR initial begin: p_assertions assert (RegNumBytes > 32'd0) else $fatal(1, "The number of bytes must be at least 1!"); @@ -404,6 +405,7 @@ module axi_lite_regs #( end `endif `endif + `endif // pragma translate_on endmodule diff --git a/src/axi_lite_xbar.sv b/src/axi_lite_xbar.sv index 72d1e0356..a8c1e7f3b 100644 --- a/src/axi_lite_xbar.sv +++ b/src/axi_lite_xbar.sv @@ -115,6 +115,7 @@ module axi_lite_xbar #( // pragma translate_off `ifndef VERILATOR `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); default_aw_mst_port_en: assert property( @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) @@ -138,6 +139,7 @@ module axi_lite_xbar #( when there is an unserved Ar beat. Slave Port: %0d", i)); `endif `endif + `endif // pragma translate_on axi_lite_demux #( .aw_chan_t ( aw_chan_t ), // AW Channel Type diff --git a/src/axi_serializer.sv b/src/axi_serializer.sv index 317faa062..9d262e292 100644 --- a/src/axi_serializer.sv +++ b/src/axi_serializer.sv @@ -198,6 +198,7 @@ module axi_serializer #( else $fatal(1, "Maximum number of write transactions must be >= 1!"); end `ifndef XSIM +`ifndef XILINX_SIMULATOR default disable iff (~rst_ni); aw_lost : assert property( @(posedge clk_i) (slv_req_i.aw_valid & slv_resp_o.aw_ready |-> mst_req_o.aw_valid & mst_resp_i.aw_ready)) @@ -216,6 +217,7 @@ module axi_serializer #( else $error("R beat lost."); `endif `endif +`endif // pragma translate_on endmodule diff --git a/src/axi_to_detailed_mem.sv b/src/axi_to_detailed_mem.sv index 8b26e169f..a1059b1b1 100644 --- a/src/axi_to_detailed_mem.sv +++ b/src/axi_to_detailed_mem.sv @@ -568,6 +568,7 @@ module axi_to_detailed_mem #( // pragma translate_off `ifndef VERILATOR `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (!rst_ni); assume property (@(posedge clk_i) axi_req_i.ar_valid && !axi_resp_o.ar_ready |=> $stable(axi_req_i.ar)) @@ -594,6 +595,7 @@ module axi_to_detailed_mem #( else $warning("Unexpected atomic operation on read."); `endif `endif + `endif // pragma translate_on endmodule diff --git a/src/axi_xbar_unmuxed.sv b/src/axi_xbar_unmuxed.sv index 73e50975c..dcdb57fe8 100644 --- a/src/axi_xbar_unmuxed.sv +++ b/src/axi_xbar_unmuxed.sv @@ -137,6 +137,7 @@ import cf_math_pkg::idx_width; // pragma translate_off `ifndef VERILATOR `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); default_aw_mst_port_en: assert property( @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) @@ -160,6 +161,7 @@ import cf_math_pkg::idx_width; when there is an unserved Ar beat. Slave Port: %0d", i)); `endif `endif + `endif // pragma translate_on axi_demux #( .AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), // ID Width @@ -256,6 +258,7 @@ import cf_math_pkg::idx_width; // pragma translate_off `ifndef VERILATOR `ifndef XSIM + `ifndef XILINX_SIMULATOR initial begin : check_params id_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.id ) == Cfg.AxiIdWidthSlvPorts) else $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); @@ -264,6 +267,7 @@ import cf_math_pkg::idx_width; end `endif `endif + `endif // pragma translate_on endmodule