From c47f91daaacf2a71eb22fbd0d9ed9dcf86100749 Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Mon, 17 Nov 2025 22:59:03 +0100
Subject: [PATCH 01/13] git: ignore simulation trace files

---
 verilator/.gitignore | 1 +
 vsim/.gitignore      | 1 +
 2 files changed, 2 insertions(+)

diff --git a/verilator/.gitignore b/verilator/.gitignore
index f3fb27dc..31607b29 100644
--- a/verilator/.gitignore
+++ b/verilator/.gitignore
@@ -2,4 +2,5 @@ obj_dir
 croc*.f
 *.vcd
 *.fst
+*.fst.hier
 *.log
diff --git a/vsim/.gitignore b/vsim/.gitignore
index dbab4cc4..1b34d86c 100644
--- a/vsim/.gitignore
+++ b/vsim/.gitignore
@@ -5,3 +5,4 @@ transcript
 vsim.wlf
 modelsim.ini
 *.vcd
+*.fst

From 43e0525b408ef072bc5193462b63d21e580a2401 Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Mon, 17 Nov 2025 23:15:46 +0100
Subject: [PATCH 02/13] sim: track simulators file lists and compile files

---
 verilator/.gitignore     |   1 -
 verilator/croc.f         | 166 +++++++++++++++++++++++++++++++++++++
 vsim/.gitignore          |   4 +-
 vsim/compile_netlist.tcl | 136 ++++++++++++++++++++++++++++++
 vsim/compile_rtl.tcl     | 175 +++++++++++++++++++++++++++++++++++++++
 vsim/compile_tech.tcl    |  25 +++---
 6 files changed, 491 insertions(+), 16 deletions(-)
 create mode 100644 verilator/croc.f
 create mode 100644 vsim/compile_netlist.tcl
 create mode 100644 vsim/compile_rtl.tcl

diff --git a/verilator/.gitignore b/verilator/.gitignore
index 31607b29..a239acf5 100644
--- a/verilator/.gitignore
+++ b/verilator/.gitignore
@@ -1,5 +1,4 @@
 obj_dir
-croc*.f
 *.vcd
 *.fst
 *.fst.hier
diff --git a/verilator/croc.f b/verilator/croc.f
new file mode 100644
index 00000000..f1938a76
--- /dev/null
+++ b/verilator/croc.f
@@ -0,0 +1,166 @@
+
++define+VERILATOR
++define+COMMON_CELLS_ASSERTS_OFF
+
++incdir+../rtl/apb/include
++incdir+../rtl/common_cells/include
++incdir+../rtl/cve2/include
++incdir+../rtl/obi/include
+
+../rtl/common_verification/clk_rst_gen.sv
+../rtl/tech_cells_generic/tc_sram.sv
+../rtl/tech_cells_generic/tc_sram_impl.sv
+../rtl/tech_cells_generic/tc_clk.sv
+../rtl/common_cells/binary_to_gray.sv
+../rtl/common_cells/cb_filter_pkg.sv
+../rtl/common_cells/cc_onehot.sv
+../rtl/common_cells/cdc_reset_ctrlr_pkg.sv
+../rtl/common_cells/cf_math_pkg.sv
+../rtl/common_cells/clk_int_div.sv
+../rtl/common_cells/credit_counter.sv
+../rtl/common_cells/delta_counter.sv
+../rtl/common_cells/ecc_pkg.sv
+../rtl/common_cells/edge_propagator_tx.sv
+../rtl/common_cells/exp_backoff.sv
+../rtl/common_cells/fifo_v3.sv
+../rtl/common_cells/gray_to_binary.sv
+../rtl/common_cells/heaviside.sv
+../rtl/common_cells/isochronous_4phase_handshake.sv
+../rtl/common_cells/isochronous_spill_register.sv
+../rtl/common_cells/lfsr.sv
+../rtl/common_cells/lfsr_16bit.sv
+../rtl/common_cells/lfsr_8bit.sv
+../rtl/common_cells/lossy_valid_to_stream.sv
+../rtl/common_cells/mv_filter.sv
+../rtl/common_cells/onehot_to_bin.sv
+../rtl/common_cells/plru_tree.sv
+../rtl/common_cells/passthrough_stream_fifo.sv
+../rtl/common_cells/popcount.sv
+../rtl/common_cells/ring_buffer.sv
+../rtl/common_cells/rr_arb_tree.sv
+../rtl/common_cells/rstgen_bypass.sv
+../rtl/common_cells/serial_deglitch.sv
+../rtl/common_cells/shift_reg.sv
+../rtl/common_cells/shift_reg_gated.sv
+../rtl/common_cells/spill_register_flushable.sv
+../rtl/common_cells/stream_demux.sv
+../rtl/common_cells/stream_filter.sv
+../rtl/common_cells/stream_fork.sv
+../rtl/common_cells/stream_intf.sv
+../rtl/common_cells/stream_join_dynamic.sv
+../rtl/common_cells/stream_mux.sv
+../rtl/common_cells/stream_throttle.sv
+../rtl/common_cells/sub_per_hash.sv
+../rtl/common_cells/sync.sv
+../rtl/common_cells/sync_wedge.sv
+../rtl/common_cells/unread.sv
+../rtl/common_cells/read.sv
+../rtl/common_cells/addr_decode_dync.sv
+../rtl/common_cells/boxcar.sv
+../rtl/common_cells/cdc_2phase.sv
+../rtl/common_cells/cdc_4phase.sv
+../rtl/common_cells/clk_int_div_static.sv
+../rtl/common_cells/trip_counter.sv
+../rtl/common_cells/addr_decode.sv
+../rtl/common_cells/addr_decode_napot.sv
+../rtl/common_cells/multiaddr_decode.sv
+../rtl/common_cells/cb_filter.sv
+../rtl/common_cells/cdc_fifo_2phase.sv
+../rtl/common_cells/clk_mux_glitch_free.sv
+../rtl/common_cells/counter.sv
+../rtl/common_cells/ecc_decode.sv
+../rtl/common_cells/ecc_encode.sv
+../rtl/common_cells/edge_detect.sv
+../rtl/common_cells/lzc.sv
+../rtl/common_cells/max_counter.sv
+../rtl/common_cells/rstgen.sv
+../rtl/common_cells/spill_register.sv
+../rtl/common_cells/stream_delay.sv
+../rtl/common_cells/stream_fifo.sv
+../rtl/common_cells/stream_fork_dynamic.sv
+../rtl/common_cells/stream_join.sv
+../rtl/common_cells/cdc_reset_ctrlr.sv
+../rtl/common_cells/cdc_fifo_gray.sv
+../rtl/common_cells/fall_through_register.sv
+../rtl/common_cells/id_queue.sv
+../rtl/common_cells/stream_to_mem.sv
+../rtl/common_cells/stream_arbiter_flushable.sv
+../rtl/common_cells/stream_fifo_optimal_wrap.sv
+../rtl/common_cells/stream_register.sv
+../rtl/common_cells/stream_xbar.sv
+../rtl/common_cells/cdc_fifo_gray_clearable.sv
+../rtl/common_cells/cdc_2phase_clearable.sv
+../rtl/common_cells/mem_to_banks_detailed.sv
+../rtl/common_cells/stream_arbiter.sv
+../rtl/common_cells/stream_omega_net.sv
+../rtl/common_cells/mem_to_banks.sv
+../rtl/obi/obi_pkg.sv
+../rtl/obi/obi_intf.sv
+../rtl/obi/obi_rready_converter.sv
+../rtl/obi/apb_to_obi.sv
+../rtl/obi/obi_to_apb.sv
+../rtl/obi/obi_atop_resolver.sv
+../rtl/obi/obi_cut.sv
+../rtl/obi/obi_demux.sv
+../rtl/obi/obi_err_sbr.sv
+../rtl/obi/obi_mux.sv
+../rtl/obi/obi_sram_shim.sv
+../rtl/obi/obi_xbar.sv
+../rtl/apb/apb_pkg.sv
+../rtl/cve2/cve2_pkg.sv
+../rtl/cve2/cve2_alu.sv
+../rtl/cve2/cve2_branch_predict.sv
+../rtl/cve2/cve2_compressed_decoder.sv
+../rtl/cve2/cve2_controller.sv
+../rtl/cve2/cve2_counter.sv
+../rtl/cve2/cve2_csr.sv
+../rtl/cve2/cve2_decoder.sv
+../rtl/cve2/cve2_fetch_fifo.sv
+../rtl/cve2/cve2_load_store_unit.sv
+../rtl/cve2/cve2_multdiv_fast.sv
+../rtl/cve2/cve2_multdiv_slow.sv
+../rtl/cve2/cve2_pmp.sv
+../rtl/cve2/cve2_register_file_ff.sv
+../rtl/cve2/cve2_wb.sv
+../rtl/cve2/cve2_cs_registers.sv
+../rtl/cve2/cve2_ex_block.sv
+../rtl/cve2/cve2_id_stage.sv
+../rtl/cve2/cve2_prefetch_buffer.sv
+../rtl/cve2/cve2_if_stage.sv
+../rtl/cve2/cve2_core.sv
+../rtl/obi_uart/obi_uart_pkg.sv
+../rtl/obi_uart/obi_uart_baudgen.sv
+../rtl/obi_uart/obi_uart_interrupts.sv
+../rtl/obi_uart/obi_uart_modem.sv
+../rtl/obi_uart/obi_uart_rx.sv
+../rtl/obi_uart/obi_uart_tx.sv
+../rtl/obi_uart/obi_uart_register.sv
+../rtl/obi_uart/obi_uart.sv
+../rtl/riscv-dbg/dm_pkg.sv
+../rtl/riscv-dbg/debug_rom/debug_rom.sv
+../rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv
+../rtl/riscv-dbg/dm_csrs.sv
+../rtl/riscv-dbg/dm_mem.sv
+../rtl/riscv-dbg/dmi_cdc.sv
+../rtl/riscv-dbg/dmi_jtag_tap.sv
+../rtl/riscv-dbg/dm_sba.sv
+../rtl/riscv-dbg/dm_top.sv
+../rtl/riscv-dbg/dmi_jtag.sv
+../rtl/riscv-dbg/dm_obi_top.sv
+../rtl/riscv-dbg/tb/jtag_test_simple.sv
+../rtl/croc_pkg.sv
+../rtl/user_pkg.sv
+../rtl/soc_ctrl/soc_ctrl_regs_pkg.sv
+../rtl/gpio/gpio_reg_pkg.sv
+../rtl/clint/clint_reg_pkg.sv
+../rtl/obi_timer/obi_timer_reg_pkg.sv
+../rtl/core_wrap.sv
+../rtl/soc_ctrl/soc_ctrl_regs.sv
+../rtl/gpio/gpio_reg_top.sv
+../rtl/gpio/gpio.sv
+../rtl/clint/clint.sv
+../rtl/obi_timer/obi_timer.sv
+../rtl/croc_domain.sv
+../rtl/user_domain.sv
+../rtl/croc_soc.sv
+../rtl/tb_croc_soc.sv
diff --git a/vsim/.gitignore b/vsim/.gitignore
index 1b34d86c..863483f2 100644
--- a/vsim/.gitignore
+++ b/vsim/.gitignore
@@ -1,8 +1,8 @@
 work
-compile_rtl.tcl
-compile_netlist.tcl
 transcript
 vsim.wlf
 modelsim.ini
 *.vcd
 *.fst
+*.log
+reports/
diff --git a/vsim/compile_netlist.tcl b/vsim/compile_netlist.tcl
new file mode 100644
index 00000000..1cf044d1
--- /dev/null
+++ b/vsim/compile_netlist.tcl
@@ -0,0 +1,136 @@
+set ROOT ".."
+
+# Compile testbench's dependencies RTL files
+vlog -incr -sv -svinputport=compat \
+    +define+SIMULATION \
+    +incdir+$ROOT/rtl/common_cells/include \
+    +incdir+$ROOT/rtl/apb/include \
+    +incdir+$ROOT/rtl/obi/include \
+    +incdir+$ROOT/rtl/cve2/include \
+    $ROOT/rtl/common_verification/clk_rst_gen.sv \
+    $ROOT/rtl/tech_cells_generic/tc_sram.sv \
+    $ROOT/rtl/tech_cells_generic/tc_sram_impl.sv \
+    $ROOT/rtl/tech_cells_generic/tc_clk.sv \
+    $ROOT/rtl/common_cells/binary_to_gray.sv \
+    $ROOT/rtl/common_cells/cb_filter_pkg.sv \
+    $ROOT/rtl/common_cells/cc_onehot.sv \
+    $ROOT/rtl/common_cells/cdc_reset_ctrlr_pkg.sv \
+    $ROOT/rtl/common_cells/cf_math_pkg.sv \
+    $ROOT/rtl/common_cells/clk_int_div.sv \
+    $ROOT/rtl/common_cells/credit_counter.sv \
+    $ROOT/rtl/common_cells/delta_counter.sv \
+    $ROOT/rtl/common_cells/ecc_pkg.sv \
+    $ROOT/rtl/common_cells/edge_propagator_tx.sv \
+    $ROOT/rtl/common_cells/exp_backoff.sv \
+    $ROOT/rtl/common_cells/fifo_v3.sv \
+    $ROOT/rtl/common_cells/gray_to_binary.sv \
+    $ROOT/rtl/common_cells/heaviside.sv \
+    $ROOT/rtl/common_cells/isochronous_4phase_handshake.sv \
+    $ROOT/rtl/common_cells/isochronous_spill_register.sv \
+    $ROOT/rtl/common_cells/lfsr.sv \
+    $ROOT/rtl/common_cells/lfsr_16bit.sv \
+    $ROOT/rtl/common_cells/lfsr_8bit.sv \
+    $ROOT/rtl/common_cells/lossy_valid_to_stream.sv \
+    $ROOT/rtl/common_cells/mv_filter.sv \
+    $ROOT/rtl/common_cells/onehot_to_bin.sv \
+    $ROOT/rtl/common_cells/plru_tree.sv \
+    $ROOT/rtl/common_cells/passthrough_stream_fifo.sv \
+    $ROOT/rtl/common_cells/popcount.sv \
+    $ROOT/rtl/common_cells/ring_buffer.sv \
+    $ROOT/rtl/common_cells/rr_arb_tree.sv \
+    $ROOT/rtl/common_cells/rstgen_bypass.sv \
+    $ROOT/rtl/common_cells/serial_deglitch.sv \
+    $ROOT/rtl/common_cells/shift_reg.sv \
+    $ROOT/rtl/common_cells/shift_reg_gated.sv \
+    $ROOT/rtl/common_cells/spill_register_flushable.sv \
+    $ROOT/rtl/common_cells/stream_demux.sv \
+    $ROOT/rtl/common_cells/stream_filter.sv \
+    $ROOT/rtl/common_cells/stream_fork.sv \
+    $ROOT/rtl/common_cells/stream_intf.sv \
+    $ROOT/rtl/common_cells/stream_join_dynamic.sv \
+    $ROOT/rtl/common_cells/stream_mux.sv \
+    $ROOT/rtl/common_cells/stream_throttle.sv \
+    $ROOT/rtl/common_cells/sub_per_hash.sv \
+    $ROOT/rtl/common_cells/sync.sv \
+    $ROOT/rtl/common_cells/sync_wedge.sv \
+    $ROOT/rtl/common_cells/unread.sv \
+    $ROOT/rtl/common_cells/read.sv \
+    $ROOT/rtl/common_cells/addr_decode_dync.sv \
+    $ROOT/rtl/common_cells/boxcar.sv \
+    $ROOT/rtl/common_cells/cdc_2phase.sv \
+    $ROOT/rtl/common_cells/cdc_4phase.sv \
+    $ROOT/rtl/common_cells/clk_int_div_static.sv \
+    $ROOT/rtl/common_cells/trip_counter.sv \
+    $ROOT/rtl/common_cells/addr_decode.sv \
+    $ROOT/rtl/common_cells/addr_decode_napot.sv \
+    $ROOT/rtl/common_cells/multiaddr_decode.sv \
+    $ROOT/rtl/common_cells/cb_filter.sv \
+    $ROOT/rtl/common_cells/cdc_fifo_2phase.sv \
+    $ROOT/rtl/common_cells/clk_mux_glitch_free.sv \
+    $ROOT/rtl/common_cells/counter.sv \
+    $ROOT/rtl/common_cells/ecc_decode.sv \
+    $ROOT/rtl/common_cells/ecc_encode.sv \
+    $ROOT/rtl/common_cells/edge_detect.sv \
+    $ROOT/rtl/common_cells/lzc.sv \
+    $ROOT/rtl/common_cells/max_counter.sv \
+    $ROOT/rtl/common_cells/rstgen.sv \
+    $ROOT/rtl/common_cells/spill_register.sv \
+    $ROOT/rtl/common_cells/stream_delay.sv \
+    $ROOT/rtl/common_cells/stream_fifo.sv \
+    $ROOT/rtl/common_cells/stream_fork_dynamic.sv \
+    $ROOT/rtl/common_cells/stream_join.sv \
+    $ROOT/rtl/common_cells/cdc_reset_ctrlr.sv \
+    $ROOT/rtl/common_cells/cdc_fifo_gray.sv \
+    $ROOT/rtl/common_cells/fall_through_register.sv \
+    $ROOT/rtl/common_cells/id_queue.sv \
+    $ROOT/rtl/common_cells/stream_to_mem.sv \
+    $ROOT/rtl/common_cells/stream_arbiter_flushable.sv \
+    $ROOT/rtl/common_cells/stream_fifo_optimal_wrap.sv \
+    $ROOT/rtl/common_cells/stream_register.sv \
+    $ROOT/rtl/common_cells/stream_xbar.sv \
+    $ROOT/rtl/common_cells/cdc_fifo_gray_clearable.sv \
+    $ROOT/rtl/common_cells/cdc_2phase_clearable.sv \
+    $ROOT/rtl/common_cells/mem_to_banks_detailed.sv \
+    $ROOT/rtl/common_cells/stream_arbiter.sv \
+    $ROOT/rtl/common_cells/stream_omega_net.sv \
+    $ROOT/rtl/common_cells/mem_to_banks.sv \
+    $ROOT/rtl/obi/obi_pkg.sv \
+    $ROOT/rtl/obi/obi_intf.sv \
+    $ROOT/rtl/obi/obi_rready_converter.sv \
+    $ROOT/rtl/obi/apb_to_obi.sv \
+    $ROOT/rtl/obi/obi_to_apb.sv \
+    $ROOT/rtl/obi/obi_atop_resolver.sv \
+    $ROOT/rtl/obi/obi_cut.sv \
+    $ROOT/rtl/obi/obi_demux.sv \
+    $ROOT/rtl/obi/obi_err_sbr.sv \
+    $ROOT/rtl/obi/obi_mux.sv \
+    $ROOT/rtl/obi/obi_sram_shim.sv \
+    $ROOT/rtl/obi/obi_xbar.sv \
+    $ROOT/rtl/apb/apb_pkg.sv \
+    $ROOT/rtl/cve2/cve2_pkg.sv \
+    $ROOT/rtl/obi_uart/obi_uart_pkg.sv \
+    $ROOT/rtl/riscv-dbg/dm_pkg.sv \
+    $ROOT/rtl/riscv-dbg/debug_rom/debug_rom.sv \
+    $ROOT/rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv \
+    $ROOT/rtl/riscv-dbg/dm_csrs.sv \
+    $ROOT/rtl/riscv-dbg/dm_mem.sv \
+    $ROOT/rtl/riscv-dbg/dmi_cdc.sv \
+    $ROOT/rtl/riscv-dbg/dmi_jtag_tap.sv \
+    $ROOT/rtl/riscv-dbg/dm_sba.sv \
+    $ROOT/rtl/riscv-dbg/dm_top.sv \
+    $ROOT/rtl/riscv-dbg/dmi_jtag.sv \
+    $ROOT/rtl/riscv-dbg/dm_obi_top.sv \
+    $ROOT/rtl/riscv-dbg/dmi_test.sv \
+    $ROOT/rtl/riscv-dbg/tb/jtag_test_simple.sv \
+    $ROOT/rtl/croc_pkg.sv \
+    $ROOT/rtl/user_pkg.sv \
+    $ROOT/rtl/soc_ctrl/soc_ctrl_regs_pkg.sv \
+    $ROOT/rtl/gpio/gpio_reg_pkg.sv \
+    $ROOT/rtl/clint/clint_reg_pkg.sv \
+    $ROOT/rtl/obi_timer/obi_timer_reg_pkg.sv
+
+# Compile Croc netlist
+vlog -incr $ROOT/yosys/out/croc_chip_yosys_debug.v
+
+# Compile Croc's testbench
+vlog -incr -sv -svinputport=compat +define+TARGET_NETLIST_YOSYS $ROOT/rtl/tb_croc_soc.sv
diff --git a/vsim/compile_rtl.tcl b/vsim/compile_rtl.tcl
new file mode 100644
index 00000000..cc7312cb
--- /dev/null
+++ b/vsim/compile_rtl.tcl
@@ -0,0 +1,175 @@
+set ROOT ".."
+
+# Compile Croc RTL files
+vlog -incr -sv -svinputport=compat \
+    +define+SIMULATION \
+    +incdir+$ROOT/rtl/common_cells/include \
+    +incdir+$ROOT/rtl/apb/include \
+    +incdir+$ROOT/rtl/obi/include \
+    +incdir+$ROOT/rtl/cve2/include \
+    $ROOT/rtl/common_verification/clk_rst_gen.sv \
+    $ROOT/rtl/tech_cells_generic/tc_sram.sv \
+    $ROOT/rtl/tech_cells_generic/tc_sram_impl.sv \
+    $ROOT/rtl/tech_cells_generic/tc_clk.sv \
+    $ROOT/rtl/common_cells/binary_to_gray.sv \
+    $ROOT/rtl/common_cells/cb_filter_pkg.sv \
+    $ROOT/rtl/common_cells/cc_onehot.sv \
+    $ROOT/rtl/common_cells/cdc_reset_ctrlr_pkg.sv \
+    $ROOT/rtl/common_cells/cf_math_pkg.sv \
+    $ROOT/rtl/common_cells/clk_int_div.sv \
+    $ROOT/rtl/common_cells/credit_counter.sv \
+    $ROOT/rtl/common_cells/delta_counter.sv \
+    $ROOT/rtl/common_cells/ecc_pkg.sv \
+    $ROOT/rtl/common_cells/edge_propagator_tx.sv \
+    $ROOT/rtl/common_cells/exp_backoff.sv \
+    $ROOT/rtl/common_cells/fifo_v3.sv \
+    $ROOT/rtl/common_cells/gray_to_binary.sv \
+    $ROOT/rtl/common_cells/heaviside.sv \
+    $ROOT/rtl/common_cells/isochronous_4phase_handshake.sv \
+    $ROOT/rtl/common_cells/isochronous_spill_register.sv \
+    $ROOT/rtl/common_cells/lfsr.sv \
+    $ROOT/rtl/common_cells/lfsr_16bit.sv \
+    $ROOT/rtl/common_cells/lfsr_8bit.sv \
+    $ROOT/rtl/common_cells/lossy_valid_to_stream.sv \
+    $ROOT/rtl/common_cells/mv_filter.sv \
+    $ROOT/rtl/common_cells/onehot_to_bin.sv \
+    $ROOT/rtl/common_cells/plru_tree.sv \
+    $ROOT/rtl/common_cells/passthrough_stream_fifo.sv \
+    $ROOT/rtl/common_cells/popcount.sv \
+    $ROOT/rtl/common_cells/ring_buffer.sv \
+    $ROOT/rtl/common_cells/rr_arb_tree.sv \
+    $ROOT/rtl/common_cells/rstgen_bypass.sv \
+    $ROOT/rtl/common_cells/serial_deglitch.sv \
+    $ROOT/rtl/common_cells/shift_reg.sv \
+    $ROOT/rtl/common_cells/shift_reg_gated.sv \
+    $ROOT/rtl/common_cells/spill_register_flushable.sv \
+    $ROOT/rtl/common_cells/stream_demux.sv \
+    $ROOT/rtl/common_cells/stream_filter.sv \
+    $ROOT/rtl/common_cells/stream_fork.sv \
+    $ROOT/rtl/common_cells/stream_intf.sv \
+    $ROOT/rtl/common_cells/stream_join_dynamic.sv \
+    $ROOT/rtl/common_cells/stream_mux.sv \
+    $ROOT/rtl/common_cells/stream_throttle.sv \
+    $ROOT/rtl/common_cells/sub_per_hash.sv \
+    $ROOT/rtl/common_cells/sync.sv \
+    $ROOT/rtl/common_cells/sync_wedge.sv \
+    $ROOT/rtl/common_cells/unread.sv \
+    $ROOT/rtl/common_cells/read.sv \
+    $ROOT/rtl/common_cells/addr_decode_dync.sv \
+    $ROOT/rtl/common_cells/boxcar.sv \
+    $ROOT/rtl/common_cells/cdc_2phase.sv \
+    $ROOT/rtl/common_cells/cdc_4phase.sv \
+    $ROOT/rtl/common_cells/clk_int_div_static.sv \
+    $ROOT/rtl/common_cells/trip_counter.sv \
+    $ROOT/rtl/common_cells/addr_decode.sv \
+    $ROOT/rtl/common_cells/addr_decode_napot.sv \
+    $ROOT/rtl/common_cells/multiaddr_decode.sv \
+    $ROOT/rtl/common_cells/cb_filter.sv \
+    $ROOT/rtl/common_cells/cdc_fifo_2phase.sv \
+    $ROOT/rtl/common_cells/clk_mux_glitch_free.sv \
+    $ROOT/rtl/common_cells/counter.sv \
+    $ROOT/rtl/common_cells/ecc_decode.sv \
+    $ROOT/rtl/common_cells/ecc_encode.sv \
+    $ROOT/rtl/common_cells/edge_detect.sv \
+    $ROOT/rtl/common_cells/lzc.sv \
+    $ROOT/rtl/common_cells/max_counter.sv \
+    $ROOT/rtl/common_cells/rstgen.sv \
+    $ROOT/rtl/common_cells/spill_register.sv \
+    $ROOT/rtl/common_cells/stream_delay.sv \
+    $ROOT/rtl/common_cells/stream_fifo.sv \
+    $ROOT/rtl/common_cells/stream_fork_dynamic.sv \
+    $ROOT/rtl/common_cells/stream_join.sv \
+    $ROOT/rtl/common_cells/cdc_reset_ctrlr.sv \
+    $ROOT/rtl/common_cells/cdc_fifo_gray.sv \
+    $ROOT/rtl/common_cells/fall_through_register.sv \
+    $ROOT/rtl/common_cells/id_queue.sv \
+    $ROOT/rtl/common_cells/stream_to_mem.sv \
+    $ROOT/rtl/common_cells/stream_arbiter_flushable.sv \
+    $ROOT/rtl/common_cells/stream_fifo_optimal_wrap.sv \
+    $ROOT/rtl/common_cells/stream_register.sv \
+    $ROOT/rtl/common_cells/stream_xbar.sv \
+    $ROOT/rtl/common_cells/cdc_fifo_gray_clearable.sv \
+    $ROOT/rtl/common_cells/cdc_2phase_clearable.sv \
+    $ROOT/rtl/common_cells/mem_to_banks_detailed.sv \
+    $ROOT/rtl/common_cells/stream_arbiter.sv \
+    $ROOT/rtl/common_cells/stream_omega_net.sv \
+    $ROOT/rtl/common_cells/mem_to_banks.sv \
+    $ROOT/rtl/obi/obi_pkg.sv \
+    $ROOT/rtl/obi/obi_intf.sv \
+    $ROOT/rtl/obi/obi_rready_converter.sv \
+    $ROOT/rtl/obi/apb_to_obi.sv \
+    $ROOT/rtl/obi/obi_to_apb.sv \
+    $ROOT/rtl/obi/obi_atop_resolver.sv \
+    $ROOT/rtl/obi/obi_cut.sv \
+    $ROOT/rtl/obi/obi_demux.sv \
+    $ROOT/rtl/obi/obi_err_sbr.sv \
+    $ROOT/rtl/obi/obi_mux.sv \
+    $ROOT/rtl/obi/obi_sram_shim.sv \
+    $ROOT/rtl/obi/obi_xbar.sv \
+    $ROOT/rtl/apb/apb_pkg.sv \
+    $ROOT/rtl/cve2/cve2_pkg.sv \
+    $ROOT/rtl/cve2/cve2_alu.sv \
+    $ROOT/rtl/cve2/cve2_branch_predict.sv \
+    $ROOT/rtl/cve2/cve2_compressed_decoder.sv \
+    $ROOT/rtl/cve2/cve2_controller.sv \
+    $ROOT/rtl/cve2/cve2_counter.sv \
+    $ROOT/rtl/cve2/cve2_csr.sv \
+    $ROOT/rtl/cve2/cve2_decoder.sv \
+    $ROOT/rtl/cve2/cve2_fetch_fifo.sv \
+    $ROOT/rtl/cve2/cve2_load_store_unit.sv \
+    $ROOT/rtl/cve2/cve2_multdiv_fast.sv \
+    $ROOT/rtl/cve2/cve2_multdiv_slow.sv \
+    $ROOT/rtl/cve2/cve2_pmp.sv \
+    $ROOT/rtl/cve2/cve2_register_file_ff.sv \
+    $ROOT/rtl/cve2/cve2_wb.sv \
+    $ROOT/rtl/cve2/cve2_cs_registers.sv \
+    $ROOT/rtl/cve2/cve2_ex_block.sv \
+    $ROOT/rtl/cve2/cve2_id_stage.sv \
+    $ROOT/rtl/cve2/cve2_prefetch_buffer.sv \
+    $ROOT/rtl/cve2/cve2_if_stage.sv \
+    $ROOT/rtl/cve2/cve2_core.sv \
+    $ROOT/rtl/obi_uart/obi_uart_pkg.sv \
+    $ROOT/rtl/obi_uart/obi_uart_baudgen.sv \
+    $ROOT/rtl/obi_uart/obi_uart_interrupts.sv \
+    $ROOT/rtl/obi_uart/obi_uart_modem.sv \
+    $ROOT/rtl/obi_uart/obi_uart_rx.sv \
+    $ROOT/rtl/obi_uart/obi_uart_tx.sv \
+    $ROOT/rtl/obi_uart/obi_uart_register.sv \
+    $ROOT/rtl/obi_uart/obi_uart.sv \
+    $ROOT/rtl/riscv-dbg/dm_pkg.sv \
+    $ROOT/rtl/riscv-dbg/debug_rom/debug_rom.sv \
+    $ROOT/rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv \
+    $ROOT/rtl/riscv-dbg/dm_csrs.sv \
+    $ROOT/rtl/riscv-dbg/dm_mem.sv \
+    $ROOT/rtl/riscv-dbg/dmi_cdc.sv \
+    $ROOT/rtl/riscv-dbg/dmi_jtag_tap.sv \
+    $ROOT/rtl/riscv-dbg/dm_sba.sv \
+    $ROOT/rtl/riscv-dbg/dm_top.sv \
+    $ROOT/rtl/riscv-dbg/dmi_jtag.sv \
+    $ROOT/rtl/riscv-dbg/dm_obi_top.sv \
+    $ROOT/rtl/riscv-dbg/dmi_test.sv \
+    $ROOT/rtl/riscv-dbg/tb/jtag_test_simple.sv \
+    $ROOT/rtl/croc_pkg.sv \
+    $ROOT/rtl/user_pkg.sv \
+    $ROOT/rtl/soc_ctrl/soc_ctrl_regs_pkg.sv \
+    $ROOT/rtl/gpio/gpio_reg_pkg.sv \
+    $ROOT/rtl/clint/clint_reg_pkg.sv \
+    $ROOT/rtl/obi_timer/obi_timer_reg_pkg.sv \
+    $ROOT/rtl/core_wrap.sv \
+    $ROOT/rtl/soc_ctrl/soc_ctrl_regs.sv \
+    $ROOT/rtl/gpio/gpio_reg_top.sv \
+    $ROOT/rtl/gpio/gpio.sv \
+    $ROOT/rtl/clint/clint.sv \
+    $ROOT/rtl/obi_timer/obi_timer.sv \
+    $ROOT/rtl/croc_domain.sv \
+    $ROOT/rtl/user_domain.sv \
+    $ROOT/rtl/croc_soc.sv
+
+# Compile Croc's testbench
+vlog -incr -sv -svinputport=compat \
+    +define+SIMULATION \
+    +incdir+$ROOT/rtl/common_cells/include \
+    +incdir+$ROOT/rtl/apb/include \
+    +incdir+$ROOT/rtl/obi/include \
+    +incdir+$ROOT/rtl/cve2/include \
+    $ROOT/rtl/tb_croc_soc.sv
diff --git a/vsim/compile_tech.tcl b/vsim/compile_tech.tcl
index d9eab05b..8e0f8046 100644
--- a/vsim/compile_tech.tcl
+++ b/vsim/compile_tech.tcl
@@ -9,17 +9,16 @@
 # Authors:
 # - Philippe Sauter <phsauter@iis.ee.ethz.ch>
 
-if {[catch { vlog -incr -sv \
+vlog -incr -sv \
     +define+FUNCTIONAL \
-    "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v" \
-    "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v" \
-    "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v" \
-    "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x64_c2_bm_bist.v" \
-    "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_512x64_c2_bm_bist.v" \
-    "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v" \
-    "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v" \
-    "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \
-    "$ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v" \
-    "$ROOT/ihp13/tc_sram.sv" \
-    "$ROOT/ihp13/tc_clk.s_implv" \
-}]} {return 1}
+    $ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v \
+    $ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v \
+    $ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_64x64_c2_bm_bist.v \
+    $ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x64_c2_bm_bist.v \
+    $ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_512x64_c2_bm_bist.v \
+    $ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x64_c2_bm_bist.v \
+    $ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_2048x64_c2_bm_bist.v \
+    $ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v \
+    $ROOT/ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_256x48_c2_bm_bist.v \
+    $ROOT/ihp13/tc_clk.sv \
+    $ROOT/ihp13/tc_sram_impl.sv

From 9dafe39d3b33bd612bc54e48eb34ebda18003daa Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Thu, 27 Nov 2025 17:22:20 +0100
Subject: [PATCH 03/13] verilator: add run.sh bash script

---
 verilator/run.sh | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100755 verilator/run.sh

diff --git a/verilator/run.sh b/verilator/run.sh
new file mode 100755
index 00000000..83ebb6d9
--- /dev/null
+++ b/verilator/run.sh
@@ -0,0 +1,28 @@
+#!/bin/bash
+
+# Set variables
+VERILATOR=${VERILATOR:-verilator}
+BINARY=${BINARY:-"../sw/bin/helloworld.hex"}
+
+# Clean up generated files
+[ -d ./obj_dir     ] && rm -r ./obj_dir
+[ -f croc.fst      ] && rm croc.fst
+[ -f croc.fst.hier ] && rm croc.fst.hier
+
+# Verilate design
+${VERILATOR} -Wno-fatal -Wno-style \
+    -Wno-BLKANDNBLK -Wno-WIDTHEXPAND \
+    -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT \
+    -Wno-ASCRANGE --binary -j 0 --timing \
+    --autoflush --trace-fst --trace-threads 2 \
+    --trace-structs --unroll-count 1 \
+    --unroll-stmts 1 --x-assign fast \
+    --x-initial fast -O3 --top tb_croc_soc \
+    -f croc.f
+
+# Run simulation
+if [ ! -f "${BINARY}" ]; then
+    echo "Cannot open binary file '${BINARY}'"
+else
+    obj_dir/Vtb_croc_soc +binary="${BINARY}" | tee croc.log
+fi

From 287f42c067f76b0f10143c9c31a645154737074c Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Thu, 27 Nov 2025 17:42:07 +0100
Subject: [PATCH 04/13] vsim: add run.sh and run_netlist.sh bash scripts

---
 vsim/compile_rtl.tcl |  5 +++++
 vsim/run.sh          | 45 ++++++++++++++++++++++++++++++++++++++++++++
 vsim/run_netlist.sh  | 45 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 95 insertions(+)
 create mode 100755 vsim/run.sh
 create mode 100755 vsim/run_netlist.sh

diff --git a/vsim/compile_rtl.tcl b/vsim/compile_rtl.tcl
index cc7312cb..3fd632bf 100644
--- a/vsim/compile_rtl.tcl
+++ b/vsim/compile_rtl.tcl
@@ -3,6 +3,8 @@ set ROOT ".."
 # Compile Croc RTL files
 vlog -incr -sv -svinputport=compat \
     +define+SIMULATION \
+    +define+RVFI \
+    +define+TRACE_EXECUTION \
     +incdir+$ROOT/rtl/common_cells/include \
     +incdir+$ROOT/rtl/apb/include \
     +incdir+$ROOT/rtl/obi/include \
@@ -128,6 +130,9 @@ vlog -incr -sv -svinputport=compat \
     $ROOT/rtl/cve2/cve2_prefetch_buffer.sv \
     $ROOT/rtl/cve2/cve2_if_stage.sv \
     $ROOT/rtl/cve2/cve2_core.sv \
+    $ROOT/rtl/cve2/cve2_tracer_pkg.sv \
+    $ROOT/rtl/cve2/cve2_tracer.sv \
+    $ROOT/rtl/cve2/cve2_core_tracing.sv \
     $ROOT/rtl/obi_uart/obi_uart_pkg.sv \
     $ROOT/rtl/obi_uart/obi_uart_baudgen.sv \
     $ROOT/rtl/obi_uart/obi_uart_interrupts.sv \
diff --git a/vsim/run.sh b/vsim/run.sh
new file mode 100755
index 00000000..64e28ab1
--- /dev/null
+++ b/vsim/run.sh
@@ -0,0 +1,45 @@
+#!/bin/bash
+
+# Set variables
+VSIM=${VSIM:-vsim}
+BINARY=${BINARY:-"../sw/bin/helloworld.hex"}
+USE_GUI=${USE_GUI:-0}
+
+# Clean up generated files
+[ -d work          ] && rm -r ./work
+[ -d reports       ] && rm reports/* || mkdir reports
+[ -f croc.fst      ] && rm croc.fst
+[ -f croc.fst.hier ] && rm croc.fst.hier
+[ -f vsim.wlf      ] && rm vsim.wlf
+
+# Compile design
+${VSIM} -c -do "source compile_rtl.tcl; exit" | tee reports/compile_rtl.log
+
+# Collect errors and warnings from compilation log and print summary
+echo "--- QuestaSim compilation report ---"  > reports/compile_rtl.rpt
+echo "Errors:"                              >> reports/compile_rtl.rpt
+grep "Error:" reports/compile_rtl.log       >> reports/compile_rtl.rpt
+echo ""                                     >> reports/compile_rtl.rpt
+echo "Warnings:"                            >> reports/compile_rtl.rpt
+grep "Warning:" reports/compile_rtl.log     >> reports/compile_rtl.rpt
+
+NUM_ERRORS=$(cat reports/compile_rtl.rpt | grep Error: | wc -l)
+NUM_WARNINGS=$(cat reports/compile_rtl.rpt | grep Warning: | wc -l)
+echo "#######################################################"
+echo "############### Compilation report ####################"
+echo "#######################################################"
+echo " Errors   : ${NUM_ERRORS}"
+echo " Warnings : ${NUM_WARNINGS}"
+echo "See 'reports/compile_rtl.rpt' for more info"
+echo "#######################################################"
+
+# Run simulation
+if [ ! -f "${BINARY}" ]; then
+    echo "Cannot open binary file '${BINARY}'"
+else
+    if [ "${USE_GUI}" = "1" ]; then
+        ${VSIM} +binary="${BINARY}" -gui tb_croc_soc -t 1ns -voptargs=+acc -suppress vsim-3009 -suppress vsim-8683 -suppress vsim-8386
+    else
+        ${VSIM} +binary="${BINARY}" -c tb_croc_soc -t 1ns -voptargs=+acc -suppress vsim-3009 -suppress vsim-8683 -suppress vsim-8386 -do "run -a; quit"
+    fi
+fi
diff --git a/vsim/run_netlist.sh b/vsim/run_netlist.sh
new file mode 100755
index 00000000..1cd1f292
--- /dev/null
+++ b/vsim/run_netlist.sh
@@ -0,0 +1,45 @@
+#!/bin/bash
+
+# Set variables
+VSIM=${VSIM:-vsim}
+BINARY=${BINARY:-"../sw/bin/helloworld.hex"}
+USE_GUI=${USE_GUI:-0}
+
+# Clean up generated files
+[ -d work          ] && rm -r ./work
+[ -d reports       ] && rm reports/* || mkdir reports
+[ -f croc.fst      ] && rm croc.fst
+[ -f croc.fst.hier ] && rm croc.fst.hier
+[ -f vsim.wlf      ] && rm vsim.wlf
+
+# Compile design
+${VSIM} -c -do "source compile_netlist.tcl; source compile_tech.tcl; exit" | tee reports/compile_netlist.log
+
+# Collect errors and warnings from compilation log and print summary
+echo "--- QuestaSim compilation report ---"  > reports/compile_netlist.rpt
+echo "Errors:"                              >> reports/compile_netlist.rpt
+grep "Error:" reports/compile_netlist.log   >> reports/compile_netlist.rpt
+echo ""                                     >> reports/compile_netlist.rpt
+echo "Warnings:"                            >> reports/compile_netlist.rpt
+grep "Warning:" reports/compile_netlist.log >> reports/compile_netlist.rpt
+
+NUM_ERRORS=$(cat reports/compile_netlist.rpt | grep Error: | wc -l)
+NUM_WARNINGS=$(cat reports/compile_compile_netlistrtl.rpt | grep Warning: | wc -l)
+echo "#######################################################"
+echo "############### Compilation report ####################"
+echo "#######################################################"
+echo " Errors   : ${NUM_ERRORS}"
+echo " Warnings : ${NUM_WARNINGS}"
+echo "See 'reports/compile_netlist.rpt' for more info"
+echo "#######################################################"
+
+# Run simulation
+if [ ! -f "${BINARY}" ]; then
+    echo "Cannot open binary file '${BINARY}'"
+else
+    if [ "${USE_GUI}" = "1" ]; then
+        ${VSIM} +binary="${BINARY}" -gui tb_croc_soc -t 1ns -voptargs=+acc -suppress vsim-3009 -suppress vsim-8683 -suppress vsim-8386
+    else
+        ${VSIM} +binary="${BINARY}" -c tb_croc_soc -t 1ns -voptargs=+acc -suppress vsim-3009 -suppress vsim-8683 -suppress vsim-8386 -do "run -a; quit"
+    fi
+fi

From 7e64aa17dd63871ec15f6c79a4b7067389e98182 Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Thu, 27 Nov 2025 23:54:45 +0100
Subject: [PATCH 05/13] yosys: add run.sh bash script

---
 yosys/croc.flist                  | 161 ++++++++++++++++++++++++++++++
 yosys/run.sh                      |  20 ++++
 yosys/scripts/yosys_common.tcl    |  46 +++------
 yosys/scripts/yosys_synthesis.tcl |   5 +-
 4 files changed, 196 insertions(+), 36 deletions(-)
 create mode 100644 yosys/croc.flist
 create mode 100755 yosys/run.sh

diff --git a/yosys/croc.flist b/yosys/croc.flist
new file mode 100644
index 00000000..2f68f54c
--- /dev/null
+++ b/yosys/croc.flist
@@ -0,0 +1,161 @@
++incdir+../rtl/apb/include
++incdir+../rtl/common_cells/include
++incdir+../rtl/cve2/include
++incdir+../rtl/obi/include
++define+TARGET_SYNTHESIS
++define+SYNTHESIS
++define+COMMON_CELLS_ASSERTS_OFF=1
+../rtl/common_cells/binary_to_gray.sv
+../rtl/common_cells/cb_filter_pkg.sv
+../rtl/common_cells/cc_onehot.sv
+../rtl/common_cells/cdc_reset_ctrlr_pkg.sv
+../rtl/common_cells/cf_math_pkg.sv
+../rtl/common_cells/clk_int_div.sv
+../rtl/common_cells/credit_counter.sv
+../rtl/common_cells/delta_counter.sv
+../rtl/common_cells/ecc_pkg.sv
+../rtl/common_cells/edge_propagator_tx.sv
+../rtl/common_cells/exp_backoff.sv
+../rtl/common_cells/fifo_v3.sv
+../rtl/common_cells/gray_to_binary.sv
+../rtl/common_cells/heaviside.sv
+../rtl/common_cells/isochronous_4phase_handshake.sv
+../rtl/common_cells/isochronous_spill_register.sv
+../rtl/common_cells/lfsr.sv
+../rtl/common_cells/lfsr_16bit.sv
+../rtl/common_cells/lfsr_8bit.sv
+../rtl/common_cells/lossy_valid_to_stream.sv
+../rtl/common_cells/mv_filter.sv
+../rtl/common_cells/onehot_to_bin.sv
+../rtl/common_cells/plru_tree.sv
+../rtl/common_cells/passthrough_stream_fifo.sv
+../rtl/common_cells/popcount.sv
+../rtl/common_cells/ring_buffer.sv
+../rtl/common_cells/rr_arb_tree.sv
+../rtl/common_cells/rstgen_bypass.sv
+../rtl/common_cells/serial_deglitch.sv
+../rtl/common_cells/shift_reg.sv
+../rtl/common_cells/shift_reg_gated.sv
+../rtl/common_cells/spill_register_flushable.sv
+../rtl/common_cells/stream_demux.sv
+../rtl/common_cells/stream_filter.sv
+../rtl/common_cells/stream_fork.sv
+../rtl/common_cells/stream_intf.sv
+../rtl/common_cells/stream_join_dynamic.sv
+../rtl/common_cells/stream_mux.sv
+../rtl/common_cells/stream_throttle.sv
+../rtl/common_cells/sub_per_hash.sv
+../rtl/common_cells/sync.sv
+../rtl/common_cells/sync_wedge.sv
+../rtl/common_cells/unread.sv
+../rtl/common_cells/read.sv
+../rtl/common_cells/addr_decode_dync.sv
+../rtl/common_cells/boxcar.sv
+../rtl/common_cells/cdc_2phase.sv
+../rtl/common_cells/cdc_4phase.sv
+../rtl/common_cells/clk_int_div_static.sv
+../rtl/common_cells/trip_counter.sv
+../rtl/common_cells/addr_decode.sv
+../rtl/common_cells/addr_decode_napot.sv
+../rtl/common_cells/multiaddr_decode.sv
+../rtl/common_cells/cb_filter.sv
+../rtl/common_cells/cdc_fifo_2phase.sv
+../rtl/common_cells/clk_mux_glitch_free.sv
+../rtl/common_cells/counter.sv
+../rtl/common_cells/ecc_decode.sv
+../rtl/common_cells/ecc_encode.sv
+../rtl/common_cells/edge_detect.sv
+../rtl/common_cells/lzc.sv
+../rtl/common_cells/max_counter.sv
+../rtl/common_cells/rstgen.sv
+../rtl/common_cells/spill_register.sv
+../rtl/common_cells/stream_delay.sv
+../rtl/common_cells/stream_fifo.sv
+../rtl/common_cells/stream_fork_dynamic.sv
+../rtl/common_cells/stream_join.sv
+../rtl/common_cells/cdc_reset_ctrlr.sv
+../rtl/common_cells/cdc_fifo_gray.sv
+../rtl/common_cells/fall_through_register.sv
+../rtl/common_cells/id_queue.sv
+../rtl/common_cells/stream_to_mem.sv
+../rtl/common_cells/stream_arbiter_flushable.sv
+../rtl/common_cells/stream_fifo_optimal_wrap.sv
+../rtl/common_cells/stream_register.sv
+../rtl/common_cells/stream_xbar.sv
+../rtl/common_cells/cdc_fifo_gray_clearable.sv
+../rtl/common_cells/cdc_2phase_clearable.sv
+../rtl/common_cells/mem_to_banks_detailed.sv
+../rtl/common_cells/stream_arbiter.sv
+../rtl/common_cells/stream_omega_net.sv
+../rtl/common_cells/mem_to_banks.sv
+../rtl/obi/obi_pkg.sv
+../rtl/obi/obi_intf.sv
+../rtl/obi/obi_rready_converter.sv
+../rtl/obi/apb_to_obi.sv
+../rtl/obi/obi_to_apb.sv
+../rtl/obi/obi_atop_resolver.sv
+../rtl/obi/obi_cut.sv
+../rtl/obi/obi_demux.sv
+../rtl/obi/obi_err_sbr.sv
+../rtl/obi/obi_mux.sv
+../rtl/obi/obi_sram_shim.sv
+../rtl/obi/obi_xbar.sv
+../rtl/apb/apb_pkg.sv
+../rtl/cve2/cve2_pkg.sv
+../rtl/cve2/cve2_alu.sv
+../rtl/cve2/cve2_branch_predict.sv
+../rtl/cve2/cve2_compressed_decoder.sv
+../rtl/cve2/cve2_controller.sv
+../rtl/cve2/cve2_counter.sv
+../rtl/cve2/cve2_csr.sv
+../rtl/cve2/cve2_decoder.sv
+../rtl/cve2/cve2_fetch_fifo.sv
+../rtl/cve2/cve2_load_store_unit.sv
+../rtl/cve2/cve2_multdiv_fast.sv
+../rtl/cve2/cve2_multdiv_slow.sv
+../rtl/cve2/cve2_pmp.sv
+../rtl/cve2/cve2_register_file_ff.sv
+../rtl/cve2/cve2_wb.sv
+../rtl/cve2/cve2_cs_registers.sv
+../rtl/cve2/cve2_ex_block.sv
+../rtl/cve2/cve2_id_stage.sv
+../rtl/cve2/cve2_prefetch_buffer.sv
+../rtl/cve2/cve2_if_stage.sv
+../rtl/cve2/cve2_core.sv
+../rtl/obi_uart/obi_uart_pkg.sv
+../rtl/obi_uart/obi_uart_baudgen.sv
+../rtl/obi_uart/obi_uart_interrupts.sv
+../rtl/obi_uart/obi_uart_modem.sv
+../rtl/obi_uart/obi_uart_rx.sv
+../rtl/obi_uart/obi_uart_tx.sv
+../rtl/obi_uart/obi_uart_register.sv
+../rtl/obi_uart/obi_uart.sv
+../rtl/riscv-dbg/dm_pkg.sv
+../rtl/riscv-dbg/debug_rom/debug_rom.sv
+../rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv
+../rtl/riscv-dbg/dm_csrs.sv
+../rtl/riscv-dbg/dm_mem.sv
+../rtl/riscv-dbg/dmi_cdc.sv
+../rtl/riscv-dbg/dmi_jtag_tap.sv
+../rtl/riscv-dbg/dm_sba.sv
+../rtl/riscv-dbg/dm_top.sv
+../rtl/riscv-dbg/dmi_jtag.sv
+../rtl/riscv-dbg/dm_obi_top.sv
+../ihp13/tc_clk.sv
+../ihp13/tc_sram_impl.sv
+../rtl/croc_pkg.sv
+../rtl/user_pkg.sv
+../rtl/soc_ctrl/soc_ctrl_regs_pkg.sv
+../rtl/gpio/gpio_reg_pkg.sv
+../rtl/clint/clint_reg_pkg.sv
+../rtl/obi_timer/obi_timer_reg_pkg.sv
+../rtl/core_wrap.sv
+../rtl/soc_ctrl/soc_ctrl_regs.sv
+../rtl/gpio/gpio_reg_top.sv
+../rtl/gpio/gpio.sv
+../rtl/clint/clint.sv
+../rtl/obi_timer/obi_timer.sv
+../rtl/croc_domain.sv
+../rtl/user_domain.sv
+../rtl/croc_soc.sv
+../rtl/croc_chip.sv
diff --git a/yosys/run.sh b/yosys/run.sh
new file mode 100755
index 00000000..5a48fab1
--- /dev/null
+++ b/yosys/run.sh
@@ -0,0 +1,20 @@
+#!/bin/bash
+
+# Set variables
+YOSYS=${YOSYS:-yosys}
+
+# Clean up generated files
+[ -f synthesis.log ] && rm synthesis.log
+rm -rf reports/
+rm -rf out/
+rm -rf tmp/
+mkdir reports
+mkdir out
+mkdir tmp
+
+# Run Yosys
+${YOSYS} -c scripts/yosys_synthesis.tcl 2>&1 \
+  | TZ=UTC gawk '{ print strftime("[%Y-%m-%d %H:%M %Z]"), $0 }' \
+  | tee synthesis.log \
+  | gawk -f scripts/filter_output.awk
+
diff --git a/yosys/scripts/yosys_common.tcl b/yosys/scripts/yosys_common.tcl
index 408c0f85..362536cc 100644
--- a/yosys/scripts/yosys_common.tcl
+++ b/yosys/scripts/yosys_common.tcl
@@ -8,38 +8,18 @@
 # Preparation for the synthesis flow
 # A common setup to provide some functionality and define variables
 
-# list of global variables that may be used
-# define with scheme: <local-var> { <ENVVAR>  <fallback> }
-set variables {
-    sv_flist    { SV_FLIST    "../croc.flist" }
-    top_design  { TOP_DESIGN  "croc_chip"     }
-    out_dir     { OUT         out             }
-    tmp_dir     { TMP         tmp             }
-    rep_dir     { REPORTS     reports         }
-}
-
-
-# check if an env-var exists and is non-empty
-proc envVarValid {var_name} {
-    if { [info exists ::env($var_name)]} {
-	    if {$::env($var_name) != "0" && $::env($var_name) ne ""} {
-            return 1
-        }
-    }
-    return 0
-}
-
-# If the ENVVAR is valid use it, otherwise use fallback
-foreach var [dict keys $variables] {  
-    set values [dict get $variables $var]
-    set env_var [lindex $values 0]
-    set fallback [lindex $values 1]
-
-    if {[envVarValid $env_var]} {
-        puts "using: $var= '$::env($env_var)'"
-        set $var $::env($env_var)
-    }
-}
+# set global variables
+set sv_flist   "./croc.flist"
+set top_design "croc_chip"
+set out_dir    out
+set tmp_dir    tmp
+set rep_dir    reports
+
+puts "using: sv_flist   = '$sv_flist'"
+puts "using: top_design = '$top_design'"
+puts "using: out_dir    = '$out_dir'"
+puts "using: tmp_dir    = '$tmp_dir'"
+puts "using: rep_dir    = '$rep_dir'"
 
 # process ABC script and write to temporary directory
 proc processAbcScript {abc_script} {
@@ -56,4 +36,4 @@ proc processAbcScript {abc_script} {
     flush $abc_out
     close $abc_out
     return $abc_out_path
-}
\ No newline at end of file
+}
diff --git a/yosys/scripts/yosys_synthesis.tcl b/yosys/scripts/yosys_synthesis.tcl
index 8167c40f..5c5ded8f 100644
--- a/yosys/scripts/yosys_synthesis.tcl
+++ b/yosys/scripts/yosys_synthesis.tcl
@@ -11,8 +11,7 @@ if {[info script] ne ""} {
     cd "[file dirname [info script]]/../"
 }
 
-# Configuration variables are in yosys_commono
-# get environment variables
+# Configuration variables are in yosys_common
 source scripts/yosys_common.tcl
 
 # ABC logic optimization script
@@ -22,7 +21,7 @@ set abc_script [processAbcScript scripts/abc-opt.script]
 source scripts/init_tech.tcl
 
 yosys plugin -i slang.so
-# default from yosys_common.tcl: top_design=croc_chip; sv_flist=../croc.flist
+# default from yosys_common.tcl: top_design=croc_chip; sv_flist=./croc.flist
 yosys read_slang --top $top_design -F $sv_flist \
         --compat-mode --keep-hierarchy \
         --allow-use-before-declare --ignore-unknown-modules

From 5ce7f3073e72217a70ed1300a0c5b0a0c60f6b6d Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Fri, 28 Nov 2025 09:22:03 +0100
Subject: [PATCH 06/13] openroad: hardcode path and design variables

---
 openroad/scripts/chip.tcl    | 19 +++++--------------
 openroad/scripts/startup.tcl | 27 +++++----------------------
 2 files changed, 10 insertions(+), 36 deletions(-)

diff --git a/openroad/scripts/chip.tcl b/openroad/scripts/chip.tcl
index f3f3ec83..b6fc3e94 100644
--- a/openroad/scripts/chip.tcl
+++ b/openroad/scripts/chip.tcl
@@ -8,23 +8,14 @@
 # - Philippe Sauter   <phsauter@iis.ee.ethz.ch>
 
 # The main OpenRoad chip flow
-set proj_name $::env(PROJ_NAME)
-set netlist $::env(NETLIST)
-set top_design $::env(TOP_DESIGN)
-set report_dir $::env(REPORTS)
-set save_dir $::env(SAVE)
-set time [elapsed_run_time]
-set step_by_step_debug 0
-
-# helper scripts
-source scripts/reports.tcl
-source scripts/checkpoint.tcl
-
-# initialize technology data
-source scripts/init_tech.tcl
 
+# Helper variables
 set log_id 0
+set step_by_step_debug 0
+set time [elapsed_run_time]
 
+# Define variables, helper functions and initialize technology data
+source scripts/startup.tcl
 
 ###############################################################################
 # Initialization                                                              #
diff --git a/openroad/scripts/startup.tcl b/openroad/scripts/startup.tcl
index 57ccf37d..2a526286 100644
--- a/openroad/scripts/startup.tcl
+++ b/openroad/scripts/startup.tcl
@@ -5,28 +5,11 @@
 # Authors:
 # - Tim Fischer <fischeti@iis.ee.ethz.ch>
 
-
-# Check whether PROJ_NAME is part of the environment variables
-
-
-
-if { [info exists ::env(PROJ_NAME)] } {
-    set proj_name $::env(PROJ_NAME)
-} else {
-    set proj_name "untitled"
-}
-
-if { [info exists ::env(REPORTS)] } {
-    set report_dir $::env(REPORTS)
-} else {
-    set report_dir "reports"
-}
-
-if { [info exists ::env(SAVE)] } {
-    set save_dir $::env(SAVE)
-} else {
-    set save_dir "save"
-}
+set proj_name  "croc"
+set netlist    "../yosys/out/croc_chip_yosys.v"
+set top_design "croc_chip"
+set report_dir "reports"
+set save_dir   "save"
 
 utl::report "Setting up project $proj_name"
 utl::report " - Report directory: $report_dir"

From 860b80426291a6c9090c4e747447bf9bedffeeae Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Fri, 28 Nov 2025 09:22:28 +0100
Subject: [PATCH 07/13] openroad: add run.sh bash script

---
 openroad/run.sh | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100755 openroad/run.sh

diff --git a/openroad/run.sh b/openroad/run.sh
new file mode 100755
index 00000000..416dd835
--- /dev/null
+++ b/openroad/run.sh
@@ -0,0 +1,18 @@
+#!/bin/bash
+
+# Set variables
+OPENROAD=${OPENROAD:-openroad}
+QT_QPA_PLATFORM=${QT_QPA_PLATFORM:-"offscreen"}
+
+# Clean up generated files
+[ -f croc.log ] && rm croc.log
+rm -rf reports/
+rm -rf out/
+rm -rf save/
+mkdir reports
+mkdir out
+mkdir save
+
+# Run OpenRoad
+QT_QPA_PLATFORM="offscreen" ${OPENROAD} scripts/chip.tcl -log croc.log 2>&1 | TZ=UTC gawk '{ print strftime("[%Y-%m-%d %H:%M %Z]"), $0 }'
+

From 4d93f23db5d94e2502136cce340f7cb363a0dab9 Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Fri, 28 Nov 2025 09:43:23 +0100
Subject: [PATCH 08/13] xilinx: track file list

---
 xilinx/.gitignore                       |   2 -
 xilinx/scripts/add_sources.genesys2.tcl | 189 ++++++++++++++++++++++++
 2 files changed, 189 insertions(+), 2 deletions(-)
 create mode 100644 xilinx/scripts/add_sources.genesys2.tcl

diff --git a/xilinx/.gitignore b/xilinx/.gitignore
index 8e0fd605..9bcdd5ab 100644
--- a/xilinx/.gitignore
+++ b/xilinx/.gitignore
@@ -1,4 +1,2 @@
 build
 out
-scripts/add_sources.genesys2.tcl
-
diff --git a/xilinx/scripts/add_sources.genesys2.tcl b/xilinx/scripts/add_sources.genesys2.tcl
new file mode 100644
index 00000000..cbcd2be4
--- /dev/null
+++ b/xilinx/scripts/add_sources.genesys2.tcl
@@ -0,0 +1,189 @@
+set ROOT "../../.."
+
+set_property verilog_define [list \
+    TARGET_GENESYS2 \
+    TARGET_SYNTHESIS \
+    TARGET_VIVADO \
+    COMMON_CELLS_ASSERTS_OFF \
+] [current_fileset]
+
+set_property verilog_define [list \
+    TARGET_GENESYS2 \
+    TARGET_SYNTHESIS \
+    TARGET_VIVADO \
+    COMMON_CELLS_ASSERTS_OFF \
+] [current_fileset -simset]
+
+set_property include_dirs [list \
+    $ROOT/rtl/apb/include \
+    $ROOT/rtl/common_cells/include \
+    $ROOT/rtl/cve2/include \
+    $ROOT/rtl/obi/include \
+] [current_fileset]
+
+set_property include_dirs [list \
+    $ROOT/rtl/apb/include \
+    $ROOT/rtl/common_cells/include \
+    $ROOT/rtl/cve2/include \
+    $ROOT/rtl/obi/include \
+] [current_fileset -simset]
+
+add_files -norecurse -fileset [current_fileset] [list \
+    $ROOT/rtl/tech_cells_generic/fpga/pad_functional_xilinx.sv \
+    $ROOT/rtl/tech_cells_generic/fpga/tc_clk_xilinx.sv \
+    $ROOT/rtl/tech_cells_generic/fpga/tc_sram_xilinx.sv \
+    $ROOT/rtl/tech_cells_generic/tc_sram_impl.sv \
+    $ROOT/rtl/common_cells/binary_to_gray.sv \
+    $ROOT/rtl/common_cells/cb_filter_pkg.sv \
+    $ROOT/rtl/common_cells/cc_onehot.sv \
+    $ROOT/rtl/common_cells/cdc_reset_ctrlr_pkg.sv \
+    $ROOT/rtl/common_cells/cf_math_pkg.sv \
+    $ROOT/rtl/common_cells/clk_int_div.sv \
+    $ROOT/rtl/common_cells/credit_counter.sv \
+    $ROOT/rtl/common_cells/delta_counter.sv \
+    $ROOT/rtl/common_cells/ecc_pkg.sv \
+    $ROOT/rtl/common_cells/edge_propagator_tx.sv \
+    $ROOT/rtl/common_cells/exp_backoff.sv \
+    $ROOT/rtl/common_cells/fifo_v3.sv \
+    $ROOT/rtl/common_cells/gray_to_binary.sv \
+    $ROOT/rtl/common_cells/heaviside.sv \
+    $ROOT/rtl/common_cells/isochronous_4phase_handshake.sv \
+    $ROOT/rtl/common_cells/isochronous_spill_register.sv \
+    $ROOT/rtl/common_cells/lfsr.sv \
+    $ROOT/rtl/common_cells/lfsr_16bit.sv \
+    $ROOT/rtl/common_cells/lfsr_8bit.sv \
+    $ROOT/rtl/common_cells/lossy_valid_to_stream.sv \
+    $ROOT/rtl/common_cells/mv_filter.sv \
+    $ROOT/rtl/common_cells/onehot_to_bin.sv \
+    $ROOT/rtl/common_cells/plru_tree.sv \
+    $ROOT/rtl/common_cells/passthrough_stream_fifo.sv \
+    $ROOT/rtl/common_cells/popcount.sv \
+    $ROOT/rtl/common_cells/ring_buffer.sv \
+    $ROOT/rtl/common_cells/rr_arb_tree.sv \
+    $ROOT/rtl/common_cells/rstgen_bypass.sv \
+    $ROOT/rtl/common_cells/serial_deglitch.sv \
+    $ROOT/rtl/common_cells/shift_reg.sv \
+    $ROOT/rtl/common_cells/shift_reg_gated.sv \
+    $ROOT/rtl/common_cells/spill_register_flushable.sv \
+    $ROOT/rtl/common_cells/stream_demux.sv \
+    $ROOT/rtl/common_cells/stream_filter.sv \
+    $ROOT/rtl/common_cells/stream_fork.sv \
+    $ROOT/rtl/common_cells/stream_intf.sv \
+    $ROOT/rtl/common_cells/stream_join_dynamic.sv \
+    $ROOT/rtl/common_cells/stream_mux.sv \
+    $ROOT/rtl/common_cells/stream_throttle.sv \
+    $ROOT/rtl/common_cells/sub_per_hash.sv \
+    $ROOT/rtl/common_cells/sync.sv \
+    $ROOT/rtl/common_cells/sync_wedge.sv \
+    $ROOT/rtl/common_cells/unread.sv \
+    $ROOT/rtl/common_cells/read.sv \
+    $ROOT/rtl/common_cells/addr_decode_dync.sv \
+    $ROOT/rtl/common_cells/boxcar.sv \
+    $ROOT/rtl/common_cells/cdc_2phase.sv \
+    $ROOT/rtl/common_cells/cdc_4phase.sv \
+    $ROOT/rtl/common_cells/clk_int_div_static.sv \
+    $ROOT/rtl/common_cells/trip_counter.sv \
+    $ROOT/rtl/common_cells/addr_decode.sv \
+    $ROOT/rtl/common_cells/addr_decode_napot.sv \
+    $ROOT/rtl/common_cells/multiaddr_decode.sv \
+    $ROOT/rtl/common_cells/cb_filter.sv \
+    $ROOT/rtl/common_cells/cdc_fifo_2phase.sv \
+    $ROOT/rtl/common_cells/clk_mux_glitch_free.sv \
+    $ROOT/rtl/common_cells/counter.sv \
+    $ROOT/rtl/common_cells/ecc_decode.sv \
+    $ROOT/rtl/common_cells/ecc_encode.sv \
+    $ROOT/rtl/common_cells/edge_detect.sv \
+    $ROOT/rtl/common_cells/lzc.sv \
+    $ROOT/rtl/common_cells/max_counter.sv \
+    $ROOT/rtl/common_cells/rstgen.sv \
+    $ROOT/rtl/common_cells/spill_register.sv \
+    $ROOT/rtl/common_cells/stream_delay.sv \
+    $ROOT/rtl/common_cells/stream_fifo.sv \
+    $ROOT/rtl/common_cells/stream_fork_dynamic.sv \
+    $ROOT/rtl/common_cells/stream_join.sv \
+    $ROOT/rtl/common_cells/cdc_reset_ctrlr.sv \
+    $ROOT/rtl/common_cells/cdc_fifo_gray.sv \
+    $ROOT/rtl/common_cells/fall_through_register.sv \
+    $ROOT/rtl/common_cells/id_queue.sv \
+    $ROOT/rtl/common_cells/stream_to_mem.sv \
+    $ROOT/rtl/common_cells/stream_arbiter_flushable.sv \
+    $ROOT/rtl/common_cells/stream_fifo_optimal_wrap.sv \
+    $ROOT/rtl/common_cells/stream_register.sv \
+    $ROOT/rtl/common_cells/stream_xbar.sv \
+    $ROOT/rtl/common_cells/cdc_fifo_gray_clearable.sv \
+    $ROOT/rtl/common_cells/cdc_2phase_clearable.sv \
+    $ROOT/rtl/common_cells/mem_to_banks_detailed.sv \
+    $ROOT/rtl/common_cells/stream_arbiter.sv \
+    $ROOT/rtl/common_cells/stream_omega_net.sv \
+    $ROOT/rtl/common_cells/mem_to_banks.sv \
+    $ROOT/rtl/obi/obi_pkg.sv \
+    $ROOT/rtl/obi/obi_intf.sv \
+    $ROOT/rtl/obi/obi_rready_converter.sv \
+    $ROOT/rtl/obi/apb_to_obi.sv \
+    $ROOT/rtl/obi/obi_to_apb.sv \
+    $ROOT/rtl/obi/obi_atop_resolver.sv \
+    $ROOT/rtl/obi/obi_cut.sv \
+    $ROOT/rtl/obi/obi_demux.sv \
+    $ROOT/rtl/obi/obi_err_sbr.sv \
+    $ROOT/rtl/obi/obi_mux.sv \
+    $ROOT/rtl/obi/obi_sram_shim.sv \
+    $ROOT/rtl/obi/obi_xbar.sv \
+    $ROOT/rtl/apb/apb_pkg.sv \
+    $ROOT/rtl/cve2/cve2_pkg.sv \
+    $ROOT/rtl/cve2/cve2_alu.sv \
+    $ROOT/rtl/cve2/cve2_branch_predict.sv \
+    $ROOT/rtl/cve2/cve2_compressed_decoder.sv \
+    $ROOT/rtl/cve2/cve2_controller.sv \
+    $ROOT/rtl/cve2/cve2_counter.sv \
+    $ROOT/rtl/cve2/cve2_csr.sv \
+    $ROOT/rtl/cve2/cve2_decoder.sv \
+    $ROOT/rtl/cve2/cve2_fetch_fifo.sv \
+    $ROOT/rtl/cve2/cve2_load_store_unit.sv \
+    $ROOT/rtl/cve2/cve2_multdiv_fast.sv \
+    $ROOT/rtl/cve2/cve2_multdiv_slow.sv \
+    $ROOT/rtl/cve2/cve2_pmp.sv \
+    $ROOT/rtl/cve2/cve2_register_file_ff.sv \
+    $ROOT/rtl/cve2/cve2_wb.sv \
+    $ROOT/rtl/cve2/cve2_cs_registers.sv \
+    $ROOT/rtl/cve2/cve2_ex_block.sv \
+    $ROOT/rtl/cve2/cve2_id_stage.sv \
+    $ROOT/rtl/cve2/cve2_prefetch_buffer.sv \
+    $ROOT/rtl/cve2/cve2_if_stage.sv \
+    $ROOT/rtl/cve2/cve2_core.sv \
+    $ROOT/rtl/obi_uart/obi_uart_pkg.sv \
+    $ROOT/rtl/obi_uart/obi_uart_baudgen.sv \
+    $ROOT/rtl/obi_uart/obi_uart_interrupts.sv \
+    $ROOT/rtl/obi_uart/obi_uart_modem.sv \
+    $ROOT/rtl/obi_uart/obi_uart_rx.sv \
+    $ROOT/rtl/obi_uart/obi_uart_tx.sv \
+    $ROOT/rtl/obi_uart/obi_uart_register.sv \
+    $ROOT/rtl/obi_uart/obi_uart.sv \
+    $ROOT/rtl/riscv-dbg/dm_pkg.sv \
+    $ROOT/rtl/riscv-dbg/debug_rom/debug_rom.sv \
+    $ROOT/rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv \
+    $ROOT/rtl/riscv-dbg/dm_csrs.sv \
+    $ROOT/rtl/riscv-dbg/dm_mem.sv \
+    $ROOT/rtl/riscv-dbg/dmi_cdc.sv \
+    $ROOT/rtl/riscv-dbg/dmi_jtag_tap.sv \
+    $ROOT/rtl/riscv-dbg/dm_sba.sv \
+    $ROOT/rtl/riscv-dbg/dm_top.sv \
+    $ROOT/rtl/riscv-dbg/dmi_jtag.sv \
+    $ROOT/rtl/riscv-dbg/dm_obi_top.sv \
+    $ROOT/rtl/croc_pkg.sv \
+    $ROOT/rtl/user_pkg.sv \
+    $ROOT/rtl/soc_ctrl/soc_ctrl_regs_pkg.sv \
+    $ROOT/rtl/gpio/gpio_reg_pkg.sv \
+    $ROOT/rtl/clint/clint_reg_pkg.sv \
+    $ROOT/rtl/obi_timer/obi_timer_reg_pkg.sv \
+    $ROOT/rtl/core_wrap.sv \
+    $ROOT/rtl/soc_ctrl/soc_ctrl_regs.sv \
+    $ROOT/rtl/gpio/gpio_reg_top.sv \
+    $ROOT/rtl/gpio/gpio.sv \
+    $ROOT/rtl/clint/clint.sv \
+    $ROOT/rtl/obi_timer/obi_timer.sv \
+    $ROOT/rtl/croc_domain.sv \
+    $ROOT/rtl/user_domain.sv \
+    $ROOT/rtl/croc_soc.sv \
+    $ROOT/xilinx/hw/croc_xilinx.sv \
+    $ROOT/xilinx/hw/fan_ctrl.sv \
+]

From 09c1bdcb530fb4d7143dcc4e830ea21c79ddce7e Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Fri, 28 Nov 2025 09:43:38 +0100
Subject: [PATCH 09/13] xilinx: rework implement.sh script

---
 xilinx/implement.sh | 50 +++++++++++++++++++++++++++------------------
 1 file changed, 30 insertions(+), 20 deletions(-)

diff --git a/xilinx/implement.sh b/xilinx/implement.sh
index 4ca25157..6ba3cd2c 100755
--- a/xilinx/implement.sh
+++ b/xilinx/implement.sh
@@ -1,20 +1,30 @@
-bender script vivado -t fpga -t rtl -t genesys2 > scripts/add_sources.genesys2.tcl
-mkdir -p build/genesys2.clkwiz
-cd build/genesys2.clkwiz && \
-    vitis-2022.1 vivado -mode batch -log ../genesys2.clkwiz.log -jou ../genesys2.clkwiz.jou \
-    -source ../../scripts/impl_ip.tcl \
-    -tclargs genesys2 clkwiz \
-    && cd ../..
-mkdir -p build/genesys2.vio
-cd build/genesys2.vio &&
-    vitis-2022.1 vivado -mode batch -log ../genesys2.vio.log -jou ../genesys2.vio.jou \
-    -source ../../scripts/impl_ip.tcl \
-    -tclargs genesys2 vio\
-    && cd ../..
-mkdir -p build/genesys2.croc
-cd build/genesys2.croc && \
-    vitis-2022.1 vivado -mode batch -log ../croc.genesys2.log -jou ../croc.genesys2.jou \
-    -source ../../scripts/impl_sys.tcl \
-    -tclargs genesys2 croc \
-    ../genesys2.clkwiz/out.xci \
-    ../genesys2.vio/out.xci
+#!/bin/bash
+
+# Set variables
+VIVADO=${VIVADO:-"vitis-2022.1 vivado"}
+
+# Clean up generated files
+rm -rf build/
+rm -rf out/
+mkdir build
+mkdir out
+mkdir build/genesys2.clkwiz
+mkdir build/genesys2.vio
+mkdir build/genesys2.croc
+
+# Implement clock wizard IP
+cd build/genesys2.clkwiz
+${VIVADO} -mode batch -source ../../scripts/impl_ip.tcl \
+    -tclargs genesys2 clkwiz
+cd ../..
+
+# Implement VirtualIO IP
+cd build/genesys2.vio
+${VIVADO} -mode batch -source ../../scripts/impl_ip.tcl \
+    -tclargs genesys2 vio
+cd ../..
+
+# Implement Croc
+cd build/genesys2.croc
+${VIVADO} -mode batch -source ../../scripts/impl_sys.tcl \
+    -tclargs genesys2 croc ../genesys2.clkwiz/out.xci ../genesys2.vio/out.xci

From 78bb3a1ebdb4aef3ced03ccb53fced20af51da19 Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Fri, 28 Nov 2025 10:41:58 +0100
Subject: [PATCH 10/13] ci: switch to bash scripts

---
 .github/workflows/full-flow.yml  | 2 +-
 .github/workflows/short-flow.yml | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/full-flow.yml b/.github/workflows/full-flow.yml
index ed315337..7f14969b 100644
--- a/.github/workflows/full-flow.yml
+++ b/.github/workflows/full-flow.yml
@@ -31,7 +31,7 @@ jobs:
       - name: Run Yosys, OpenROAD and KLayout
         uses: ./.github/actions/oseda-cmd
         with:
-          cmd: "make yosys && make openroad && make klayout"
+          cmd: "cd yosys && ./run.sh && cd ../openroad && ./run.sh && cd ../klayout && ./def2gds.sh"
       - name: Upload openroad outputs
         uses: actions/upload-artifact@v4
         with:
diff --git a/.github/workflows/short-flow.yml b/.github/workflows/short-flow.yml
index 41e412b0..c02c8c73 100644
--- a/.github/workflows/short-flow.yml
+++ b/.github/workflows/short-flow.yml
@@ -25,7 +25,7 @@ jobs:
       - name: Run simulation commands in OSEDA
         uses: ./.github/actions/oseda-cmd
         with:
-          cmd: "make sw && make verilator"
+          cmd: "make sw && cd verilator && ./run.sh"
       - name: Upload built software
         uses: actions/upload-artifact@v4
         with:
@@ -57,7 +57,7 @@ jobs:
       - name: Setup OSEDA container
         uses: ./.github/actions/oseda-cmd
         with:
-          cmd: "make yosys && tail -n 40 yosys/reports/*area.rpt"
+          cmd: "cd yosys && ./run.sh && tail -n 40 reports/*area.rpt"
       - name: Upload synthesis outputs
         uses: actions/upload-artifact@v4
         with:

From 9ce7f5d15958cb2f27da326533d5eb89b8aa04bd Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Tue, 25 Nov 2025 21:48:39 +0100
Subject: [PATCH 11/13] treewide: remove unnecessary make fragments

---
 Makefile             | 91 +-------------------------------------------
 openroad/openroad.mk | 70 ----------------------------------
 yosys/yosys.mk       | 54 --------------------------
 3 files changed, 2 insertions(+), 213 deletions(-)
 delete mode 100644 openroad/openroad.mk
 delete mode 100644 yosys/yosys.mk

diff --git a/Makefile b/Makefile
index 212311f2..5b90533a 100644
--- a/Makefile
+++ b/Makefile
@@ -6,13 +6,7 @@
 # - Philippe Sauter <phsauter@iis.ee.ethz.ch>
 
 # Tools
-BENDER	  ?= bender
-PYTHON3   ?= python3
-VERILATOR ?= /foss/tools/bin/verilator
-YOSYS     ?= yosys
-OPENROAD  ?= openroad
-KLAYOUT   ?= klayout
-VSIM      ?= vsim
+BENDER ?= bender
 
 # Directories
 # directory of the path to the last called Makefile (this one)
@@ -59,81 +53,6 @@ sw: $(SW_HEX)
 
 .PHONY: software sw
 
-##################
-# RTL Simulation #
-##################
-# Questasim/Modelsim/vsim
-VLOG_ARGS  = -svinputport=compat
-VSIM_ARGS  = -t 1ns -voptargs=+acc
-VSIM_ARGS += -suppress vsim-3009 -suppress vsim-8683 -suppress vsim-8386
-
-vsim/compile_rtl.tcl: Bender.lock Bender.yml
-	$(BENDER) script vsim -t rtl -t vsim -t simulation -t verilator -DSYNTHESIS -DSIMULATION  --vlog-arg="$(VLOG_ARGS)" > $@
-
-vsim/compile_netlist.tcl: Bender.lock Bender.yml
-	$(BENDER) script vsim -t ihp13 -t vsim -t simulation -t verilator -t netlist_yosys -DSYNTHESIS -DSIMULATION > $@
-
-## Simulate RTL using Questasim/Modelsim/vsim
-vsim: vsim/compile_rtl.tcl $(SW_HEX)
-	rm -rf vsim/work
-	cd vsim; $(VSIM) -c -do "source compile_rtl.tcl; exit"
-	cd vsim; $(VSIM) +binary="$(realpath $(SW_HEX))" -gui tb_croc_soc $(VSIM_ARGS)
-
-## Simulate netlist using Questasim/Modelsim/vsim
-vsim-yosys: vsim/compile_netlist.tcl $(SW_HEX) yosys/out/croc_chip_yosys_debug.v
-	rm -rf vsim/work
-	cd vsim; $(VSIM) -c -do "source compile_netlist.tcl; source compile_tech.tcl; exit"
-	cd vsim; $(VSIM) -gui tb_croc_soc $(VSIM_ARGS)
-
-
-# Verilator
-# Turn off style warnings and well-defined SystemVerilog warnings that should be part of -Wno-style
-VERILATOR_ARGS = -Wno-fatal -Wno-style \
-	-Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE
-
-VERILATOR_ARGS += --binary -j 0
-VERILATOR_ARGS += --timing --autoflush --trace-fst --trace-threads 2 --trace-structs
-VERILATOR_ARGS +=  --unroll-count 1 --unroll-stmts 1
-VERILATOR_ARGS += --x-assign fast --x-initial fast
-VERILATOR_CFLAGS += -O3 -march=native -mtune=native
-
-verilator/croc.f: Bender.lock Bender.yml
-	$(BENDER) script verilator -t rtl -t verilator -t cve2_include_tracer -DSYNTHESIS -DVERILATOR -DTRACE_EXECUTION > $@
-
-verilator/obj_dir/Vtb_croc_soc: verilator/croc.f $(SW_HEX)
-	cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -O3 --top tb_croc_soc -f croc.f
-
-## Simulate RTL using Verilator
-verilator: verilator/obj_dir/Vtb_croc_soc
-	cd verilator; obj_dir/Vtb_croc_soc +binary="$(realpath $(SW_HEX))" | tee croc.log
-
-.PHONY: verilator vsim vsim-yosys
-
-
-####################
-# Open Source Flow #
-####################
-# Bender manages the different IPs and can be used to generate file-lists for synthesis
-TOP_DESIGN     ?= croc_chip
-DUT_DESIGN	   ?= croc_soc
-BENDER_TARGETS ?= asic ihp13 rtl synthesis
-SV_DEFINES     ?= VERILATOR SYNTHESIS COMMON_CELLS_ASSERTS_OFF
-
-## Generate croc.flist used to read design in yosys
-yosys-flist: Bender.lock Bender.yml rtl/*/Bender.yml
-	$(BENDER) script flist-plus $(foreach t,$(BENDER_TARGETS),-t $(t)) $(foreach d,$(SV_DEFINES),-D $(d)=1) > $(PROJ_DIR)/croc.flist
-
-include yosys/yosys.mk
-include openroad/openroad.mk
-
-klayout/croc_chip.gds: $(OR_OUT)/croc.def klayout/*.sh klayout/*.py
-	./klayout/def2gds.sh
-
-## Generate merged .gds from openroads .def output
-klayout: klayout/croc_chip.gds
-
-.PHONY: klayout yosys-flist
-
 
 #################
 # Documentation #
@@ -162,12 +81,6 @@ help: Makefile
 
 ## Delete generated files and directories
 clean: 
-	rm -f $(SV_FLIST)
-	rm -f klayout/croc_chip.gds
-	rm -rf verilator/obj_dir/
-	rm -f verilator/croc.f
-	rm -f verilator/croc.vcd
-	$(MAKE) ys_clean
-	$(MAKE) or_clean
+	$(MAKE) -C sw clean
 
 .PHONY: clean
diff --git a/openroad/openroad.mk b/openroad/openroad.mk
deleted file mode 100644
index 5dc17ed0..00000000
--- a/openroad/openroad.mk
+++ /dev/null
@@ -1,70 +0,0 @@
-# Copyright 2023 ETH Zurich and University of Bologna.
-# Solderpad Hardware License, Version 0.51, see LICENSE for details.
-# SPDX-License-Identifier: SHL-0.51
-#
-# Authors:
-# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
-
-# Tools
-OPENROAD 		?= openroad
-
-# Directories
-# directory of the path to the last called Makefile (this one)
-OR_DIR    := $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST)))))
-
-# Project variables
-# if you are running the entire flow these are set by the top level Makefile
-# in that case do not change them here
-TOP_DESIGN 	?= croc_chip
-PROJ_NAME	?= croc
-NETLIST		?= $(realpath $(OR_DIR)/../yosys/out/$(PROJ_NAME)_yosys.v)
-
-SAVE	 	 ?= $(OR_DIR)/save
-REPORTS	 	 ?= $(OR_DIR)/reports
-OR_OUT  	 ?= $(OR_DIR)/out
-OR_OUT_FILES  = $(OR_OUT)/$(PROJ_NAME).def $(OR_OUT)/$(PROJ_NAME).v $(OR_OUT)/$(PROJ_NAME).sdc $(OR_OUT)/$(PROJ_NAME).odb
-
-backend: $(OR_OUT)/$(PROJ_NAME).def
-
-openroad: $(OR_OUT)/$(PROJ_NAME).def
-
-## Place & Route flow using OpenROAD
-$(OR_OUT_FILES): $(NETLIST) $(OR_DIR)/scripts/*.tcl $(OR_DIR)/src/*.tcl $(OR_DIR)/src/*.sdc $(OR_DIR)/IHP_rcx_patterns.rules
-	mkdir -p $(SAVE)
-	mkdir -p $(REPORTS)
-	mkdir -p $(OR_OUT)
-	echo $(CROC_ROOT)
-	cd $(OR_DIR) && \
-	NETLIST="$(NETLIST)" \
-	TOP_DESIGN="$(TOP_DESIGN)" \
-	PROJ_NAME="$(PROJ_NAME)" \
-	SAVE="$(SAVE)" \
-	REPORTS="$(REPORTS)" \
-	PDK="$(CROC_ROOT)/ihp13/pdk" \
-	QT_QPA_PLATFORM=$$(if [ -z "$$DISPLAY" ]; then echo "offscreen"; else echo "$$QT_QPA_PLATFORM"; fi) \
-	$(OPENROAD) scripts/chip.tcl \
-		$$(if [ "$(gui)" = "1" ]; then echo "-gui"; fi) \
-		-log $(PROJ_NAME).log \
-		2>&1 | TZ=UTC gawk '{ print strftime("[%Y-%m-%d %H:%M %Z]"), $$0 }';
-
-or_clean:
-	rm -rf $(SAVE)
-	rm -rf $(REPORTS)
-	rm -rf $(OR_OUT)
-	rm -f $(PROJ_NAME).log
-
-start_openroad:
-	cd $(OR_DIR) && \
-	PROJ_NAME="$(PROJ_NAME)" \
-	SAVE="$(SAVE)" \
-	REPORTS="$(REPORTS)" \
-	$(OPENROAD) scripts/startup.tcl
-
-start_openroad_gui:
-	cd $(OR_DIR) && \
-	PROJ_NAME="$(PROJ_NAME)" \
-	SAVE="$(SAVE)" \
-	REPORTS="$(REPORTS)" \
-	$(OPENROAD) -gui scripts/startup.tcl
-
-.PHONY: backend openroad or_clean start_openroad start_openroad_gui
diff --git a/yosys/yosys.mk b/yosys/yosys.mk
deleted file mode 100644
index 68e3b2e2..00000000
--- a/yosys/yosys.mk
+++ /dev/null
@@ -1,54 +0,0 @@
-# Copyright (c) 2022 ETH Zurich and University of Bologna.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-#
-# Authors:
-# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
-
-# Tools
-YOSYS    ?= yosys
-
-# Directories
-# directory of the path to the last called Makefile (this one)
-YOSYS_DIR 		:= $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST)))))
-YOSYS_OUT		:= $(YOSYS_DIR)/out
-YOSYS_TMP		:= $(YOSYS_DIR)/tmp
-YOSYS_REPORTS	:= $(YOSYS_DIR)/reports
-
-# top level to be synthesized
-TOP_DESIGN		?= croc_chip
-
-# file containing include dirs, defines and paths to all source files
-SV_FLIST    	:= $(realpath $(YOSYS_DIR)/..)/croc.flist
-
-# path to the resulting netlists (debug preserves multibit signals)
-NETLIST			:= $(YOSYS_OUT)/$(TOP_DESIGN)_yosys.v
-NETLIST_DEBUG	:= $(YOSYS_OUT)/$(TOP_DESIGN)_debug_yosys.v
-
-
-## Synthesize netlist using Yosys
-yosys: $(NETLIST)
-
-$(NETLIST) $(NETLIST_DEBUG):  $(SV_FLIST)
-	@mkdir -p $(YOSYS_OUT)
-	@mkdir -p $(YOSYS_TMP)
-	@mkdir -p $(YOSYS_REPORTS)
-	cd $(YOSYS_DIR) && \
-	SV_FLIST="$(SV_FLIST)" \
-	TOP_DESIGN="$(TOP_DESIGN)" \
-	TMP="$(YOSYS_TMP)" \
-	OUT="$(YOSYS_OUT)" \
-	REPORTS="$(YOSYS_REPORTS)" \
-	$(YOSYS) -c $(YOSYS_DIR)/scripts/yosys_synthesis.tcl \
-		2>&1 | TZ=UTC gawk '{ print strftime("[%Y-%m-%d %H:%M %Z]"), $$0 }' \
-		     | tee "$(YOSYS_DIR)/$(TOP_DESIGN).log" \
-		     | gawk -f $(YOSYS_DIR)/scripts/filter_output.awk;
-		
-
-ys_clean:
-	rm -rf $(YOSYS_OUT)
-	rm -rf $(YOSYS_TMP)
-	rm -rf $(YOSYS_REPORTS) 
-	rm -f $(YOSYS_DIR)/$(TOP_DESIGN).log
-
-.PHONY: ys_clean yosys

From 5ae248c1dcc97930f8e9ee2517636416c55ec76b Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Wed, 24 Dec 2025 00:58:00 +0100
Subject: [PATCH 12/13] tb: extend binary preload by one word

---
 rtl/tb_croc_soc.sv | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/rtl/tb_croc_soc.sv b/rtl/tb_croc_soc.sv
index 071d5901..228ab6f6 100644
--- a/rtl/tb_croc_soc.sv
+++ b/rtl/tb_croc_soc.sv
@@ -281,6 +281,8 @@ module tb_croc_soc #(
                 end
             end
         end
+        // Write one extra word to prevent the core from fetching uninitialized instructions
+        jtag_write(dm::SBData0, 32'h0);
         jtag_dbg.write_dmi(dm::SBCS, JtagInitSbcs);
         $fclose(file);
     endtask

From 64edda116a766899a0cf60d4ebeadf005eb9f607 Mon Sep 17 00:00:00 2001
From: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Date: Sat, 27 Dec 2025 19:58:12 +0100
Subject: [PATCH 13/13] Makefile: integrate Makefiles and simplify

---
 Makefile    | 139 +++++++++++++++++++++++++---------------------------
 sw/Makefile |  79 -----------------------------
 2 files changed, 67 insertions(+), 151 deletions(-)
 delete mode 100644 sw/Makefile

diff --git a/Makefile b/Makefile
index 5b90533a..56cf91c7 100644
--- a/Makefile
+++ b/Makefile
@@ -4,83 +4,78 @@
 #
 # Authors:
 # - Philippe Sauter <phsauter@iis.ee.ethz.ch>
-
-# Tools
-BENDER ?= bender
+# - Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
 
 # Directories
 # directory of the path to the last called Makefile (this one)
-PROJ_DIR  := $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST)))))
-
-
-default: help
-
-################
-# Dependencies #
-################
-# Download RCX file used for parasitic extraction from ORFS (configuration got ok by IHP)
-IHP_RCX_URL  := "https://raw.githubusercontent.com/The-OpenROAD-Project/OpenROAD-flow-scripts/7747f88f70daaeb63f43ce36e71829707b7e3fa7/flow/platforms/ihp-sg13g2/IHP_rcx_patterns.rules"
-IHP_RCX_FILE := $(PROJ_DIR)/openroad/IHP_rcx_patterns.rules
-
-## Checkout/update dependencies using Bender
-checkout: $(IHP_RCX_FILE)
-	$(BENDER) checkout
-	git submodule update --init --recursive
-
-$(IHP_RCX_FILE): 
-	curl -L -o $@ $(IHP_RCX_URL)
-
-## Reset dependencies (without updating Bender.lock)
-clean-deps:
-	rm -rf .bender
-	git submodule deinit -f --all
-
-.PHONY: checkout clean-deps
-
-
-############
-# Software #
-############
-SW_HEX ?= sw/bin/helloworld.hex
-
-$(SW_HEX): sw/*.c sw/*.h sw/*.S sw/*.ld
-	$(MAKE) -C sw/ compile
+PROJ_DIR := $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST)))))
+SW_DIR   := $(PROJ_DIR)/sw
+SRC_DIR  := $(SW_DIR)/lib/src
+INC_DIR  := $(SW_DIR)/lib/inc
+BIN_DIR  := $(SW_DIR)/bin
+
+# Toolchain
+RISCV_PREFIX  ?= riscv64-unknown-elf-
+RISCV_CC      := $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP := $(RISCV_PREFIX)objdump
+RISCV_OBJCOPY := $(RISCV_PREFIX)objcopy
+RISCV_LD      := $(RISCV_PREFIX)ld
+
+# Compilation and linking flags
+RISCV_FLAGS   := -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding
+RISCV_CCFLAGS := $(RISCV_FLAGS) -I$(INC_DIR) -I$(SW_DIR)
+RISCV_LDFLAGS := $(RISCV_FLAGS) -static -nostartfiles -lm -lgcc
+
+# Build files
+CRT0        := $(SW_DIR)/crt0.S
+LINK        := $(SW_DIR)/link.ld
+LIB_SOURCES := $(wildcard $(SRC_DIR)/*.[cS])
+LIB_OBJS    := $(LIB_SOURCES:$(SRC_DIR)/%=$(SRC_DIR)/%.o)
+
+# Build all assembly and C files in the top level as seperate binaries
+TOP_SOURCES   := $(filter-out $(CRT0), $(wildcard $(SW_DIR)/*.[cS]))
+TOP_BASENAMES := $(basename $(notdir $(TOP_SOURCES)))
+ALL_TARGETS   := $(TOP_BASENAMES:%=$(BIN_DIR)/%.dump) $(TOP_BASENAMES:%=$(BIN_DIR)/%.hex)
+
+# Default make target
+.PHONY: default
+default: all
+
+# Create output bin directory
+$(BIN_DIR):
+	mkdir -p $(BIN_DIR)
+
+# Compile assembly file
+%.S.o: %.S
+	$(RISCV_CC) $(RISCV_CCFLAGS) -c $< -o $@
+
+# Compile C file
+%.c.o: %.c
+	$(RISCV_CC) $(RISCV_CCFLAGS) -c $< -o $@
+
+# Link assembly application
+$(BIN_DIR)/%.elf: $(SW_DIR)/%.S.o $(CRT0).o $(LIB_OBJS) | $(BIN_DIR)
+	$(RISCV_CC) -o $@ $^ $(RISCV_LDFLAGS) -T$(LINK)
+
+# Link C application
+$(BIN_DIR)/%.elf: $(SW_DIR)/%.c.o $(CRT0).o $(LIB_OBJS) | $(BIN_DIR)
+	$(RISCV_CC) -o $@ $^ $(RISCV_LDFLAGS) -T$(LINK)
+
+# Create dis-assembled version of ELF binary
+$(BIN_DIR)/%.dump: $(BIN_DIR)/%.elf
+	$(RISCV_OBJDUMP) -D -s $< >$@
+
+# Create hex version of ELF binary
+$(BIN_DIR)/%.hex: $(BIN_DIR)/%.elf
+	$(RISCV_OBJCOPY) -O verilog $< $@
 
 ## Build all top-level programs in sw/
-software: $(SW_HEX)
-
-sw: $(SW_HEX)
-
-.PHONY: software sw
-
-
-#################
-# Documentation #
-#################
-
-help: Makefile
-	@printf "Available targets:\n------------------\n"
-	@for mkfile in $(MAKEFILE_LIST); do \
-		awk '/^[a-zA-Z\-\_0-9]+:/ { \
-			helpMessage = match(lastLine, /^## (.*)/); \
-			if (helpMessage) { \
-				helpCommand = substr($$1, 0, index($$1, ":")-1); \
-				helpMessage = substr(lastLine, RSTART + 3, RLENGTH); \
-				printf "%-20s %s\n", helpCommand, helpMessage; \
-			} \
-		} \
-		{ lastLine = $$0 }' $$mkfile; \
-	done
-
-.PHONY: help
-
-
-###########
-# Cleanup #
-###########
+.PHONY: all
+all: $(ALL_TARGETS)
 
 ## Delete generated files and directories
-clean: 
-	$(MAKE) -C sw clean
-
 .PHONY: clean
+clean:
+	rm -rf $(BIN_DIR)
+	rm -f $(PROJ_DIR)/sw/*.o
+	rm -f $(PROJ_DIR)/sw/lib/src/*.o
diff --git a/sw/Makefile b/sw/Makefile
deleted file mode 100644
index b1770957..00000000
--- a/sw/Makefile
+++ /dev/null
@@ -1,79 +0,0 @@
-# Copyright (c) 2024 ETH Zurich and University of Bologna.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-#
-# Authors:
-# - Paul Scheffler <paulsc@iis.ee.ethz.ch>
-# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
-
-SRCDIR  ?= lib/src
-INCDIR  ?= lib/inc
-
-# Toolchain
-
-RISCV_XLEN    ?= 32
-RISCV_MARCH   ?= rv$(RISCV_XLEN)i_zicsr
-RISCV_MABI    ?= ilp32
-RISCV_PREFIX  ?= riscv64-unknown-elf-
-RISCV_CC      ?= $(RISCV_PREFIX)gcc
-RISCV_CXX     ?= $(RISCV_PREFIX)g++
-RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
-RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy
-RISCV_AS      ?= $(RISCV_PREFIX)as
-RISCV_AR      ?= $(RISCV_PREFIX)ar
-RISCV_LD      ?= $(RISCV_PREFIX)ld
-RISCV_STRIP   ?= $(RISCV_PREFIX)strip
-
-RISCV_FLAGS    ?= -march=$(RISCV_MARCH) -mabi=$(RISCV_MABI) -mcmodel=medany -static -std=gnu99 -Os -nostdlib -fno-builtin -ffreestanding
-RISCV_CCFLAGS  ?= $(RISCV_FLAGS) -Iinclude -I$(INCDIR) -I$(CURDIR)
-RISCV_LDFLAGS  ?= -static -nostartfiles -lm -lgcc $(RISCV_FLAGS)
-
-# all
-
-all: compile
-
-# Building defaults
-
-BINDIR 	?= bin
-CRT0 	?= crt0.S
-LINK 	?= link.ld
-
-LIB_SOURCES := $(wildcard $(SRCDIR)/*.[cS])
-LIB_OBJS    := $(LIB_SOURCES:$(SRCDIR)/%=$(SRCDIR)/%.o)
-
-# Build all assembly and C files in the top level as seperate binaries
-TOP_SOURCES ?= $(filter-out $(CRT0), $(wildcard *.[cS]))
-TOP_BASENAMES := $(basename $(TOP_SOURCES))
-TOP_OBJS    := $(TOP_BASENAMES:=.o)
-ALL_TARGETS := $(TOP_BASENAMES:%=$(BINDIR)/%.elf) $(TOP_BASENAMES:%=$(BINDIR)/%.dump) $(TOP_BASENAMES:%=$(BINDIR)/%.hex)
-
-
-$(BINDIR):
-	mkdir -p $(BINDIR)
-
-%.S.o: %.S
-	$(RISCV_CC) $(RISCV_CCFLAGS) -c $< -o $@
-
-%.c.o: %.c
-	$(RISCV_CC) $(RISCV_CCFLAGS) -c $< -o $@
-
-$(BINDIR)/%.elf: %.S.o $(CRT0).o $(LIB_OBJS) | $(BINDIR)
-	$(RISCV_CC) -o $@ $^ $(RISCV_LDFLAGS) -T$(LINK)
-
-$(BINDIR)/%.elf: %.c.o $(CRT0).o $(LIB_OBJS) | $(BINDIR)
-	$(RISCV_CC) -o $@ $^ $(RISCV_LDFLAGS) -T$(LINK)
-
-$(BINDIR)/%.dump: $(BINDIR)/%.elf
-	$(RISCV_OBJDUMP) -D -s $< >$@
-
-$(BINDIR)/%.hex: $(BINDIR)/%.elf
-	$(RISCV_OBJCOPY) -O verilog $< $@
-
-# Phonies
-.PHONY: all clean compile
-
-clean:
-	rm -rf $(BINDIR)
-	rm -f *.o
-
-compile: $(BINDIR) $(ALL_TARGETS)