diff --git a/docker-compose.yml b/docker-compose.yml index 948564f1..8962efee 100644 --- a/docker-compose.yml +++ b/docker-compose.yml @@ -7,7 +7,7 @@ services: pulp-docker: - image: hpretl/iic-osic-tools:2025.07.pre1 + image: hpretl/iic-osic-tools:2025.11 environment: - UID=${UID} - GID=${GID} diff --git a/ihp13/pdk b/ihp13/pdk index 035037f6..62c1d640 160000 --- a/ihp13/pdk +++ b/ihp13/pdk @@ -1 +1 @@ -Subproject commit 035037f6312851414e4bb5daa5a9d18975c768b3 +Subproject commit 62c1d640dc1c91f57bc1a8e4e08e537a7a105ae8 diff --git a/openroad/scripts/chip.tcl b/openroad/scripts/chip.tcl index 06b6183e..73bf7fed 100644 --- a/openroad/scripts/chip.tcl +++ b/openroad/scripts/chip.tcl @@ -25,6 +25,8 @@ source scripts/init_tech.tcl set log_id 0 +# Set number of threads for multithreaded operations +set_thread_count 8 ############################################################################### # Initialization # @@ -48,20 +50,6 @@ report_checks -unconstrained -format end -no_line_splits >> ${report_dir}/${log_ report_checks -format end -no_line_splits >> ${report_dir}/${log_id_str}_${proj_name}_checks.rpt report_checks -format end -no_line_splits >> ${report_dir}/${log_id_str}_${proj_name}_checks.rpt -# Size of the chip -set chipW 1760.0 -set chipH 1760.0 - -# thickness of annular ring for pads (length of a pad) -set padRing 180.0 -set coreMargin [expr $padRing + 35]; # space for power ring - -utl::report "Initialize Chip" -initialize_floorplan -die_area "0 0 $chipW $chipH" \ - -core_area "$coreMargin $coreMargin [expr $chipW-$coreMargin] [expr $chipH-$coreMargin]" \ - -site "CoreSite" - - utl::report "Connect global nets (power)" source scripts/power_connect.tcl @@ -115,13 +103,11 @@ utl::report "################################################################### utl::report "# Step ${log_id_str}: GLOBAL PLACEMENT" utl::report "###############################################################################" -set_thread_count 8 - -set GPL_ARGS { -density 0.60 } +set GPL_ARGS { -density 0.75 } -set GPL2_ARGS { -density 0.60 +set GPL2_ARGS { -density 0.75 -routability_driven - -routability_check_overflow 0.30 + -routability_check_overflow 0.35 -timing_driven } # density: In every part of the chip, about N% of the area is occupied by standard cells # routability_driven: Reduce density target when there are a lot of wires in an area @@ -302,27 +288,26 @@ utl::report "################################################################### utl::report "# Step ${log_id_str}: DETAILED ROUTE" utl::report "###############################################################################" +utl::report "Detailed route" + # Requires LEF cell with class 'CORE ANTENNACELL', otherwise you need to give a cell repair_antennas -ratio_margin 30 -iterations 5 -# check_antennas -utl::report "Detailed route" -set_thread_count 8 detailed_route -output_drc ${report_dir}/${log_id_str}_${proj_name}_route_drc.rpt \ - -bottom_routing_layer Metal2 \ - -top_routing_layer TopMetal1 \ - -droute_end_iter 30 \ - -drc_report_iter_step 5 \ - -save_guide_updates \ - -clean_patches \ - -verbose 1 + -droute_end_iter 30 \ + -drc_report_iter_step 5 \ + -save_guide_updates \ + -clean_patches \ + -verbose 1 + +# Post-route antenna fixing +source scripts/post_route_antenna_fix.tcl utl::report "Saving detailed route" save_checkpoint ${log_id_str}_${proj_name}.drt report_metrics "${log_id_str}_${proj_name}.drt" report_image "${log_id_str}_${proj_name}.drt" true false false true - ############################################################################### # FINISHING # ############################################################################### diff --git a/openroad/scripts/floorplan.tcl b/openroad/scripts/floorplan.tcl index 0466d62a..6bdb5cf6 100644 --- a/openroad/scripts/floorplan.tcl +++ b/openroad/scripts/floorplan.tcl @@ -26,6 +26,35 @@ foreach inst $insts { } } +########################################################################## +# Die and Core Area +########################################################################## +# Dimensions: [um] +# final chip size (4sqmm) 2000.0 x 2000.0 +# io cell depth 180.0 , 180.0 +# bonding pad 70.0 , 70.0 +# seal ring thickness 35.0 , 35.0 +# --------------------------------------- +# -> OR core area 1715.0 x 1715.0 + +set chipH 2000; # final chip height (top to bottom) +set chipW 2000; # final chip width (left to right) +set padD 180; # pad depth (edge to core) +set padW 80; # pad width (beachfront) +set padBond 70; # bonding pad size +set sealRing 35; # seal ring thickness +set powerRing 50; # power ring thickness + +# starting from the outside and working towards the core area +set coreMargin [expr {$sealRing + $padD + $padBond + $powerRing}]; + +utl::report "Initialize Chip" +# coordinates are lower-left x and y, upper-right x and y +initialize_floorplan -die_area "0 0 $chipW $chipH" \ + -core_area "$coreMargin $coreMargin [expr $chipW-$coreMargin] [expr $chipH-$coreMargin]" \ + -site "CoreSite" + + ########################################################################## # Pads/IOs ########################################################################## @@ -92,7 +121,7 @@ placeInstance $bank0_sram0 $X $Y R0 # Bank1 set X [expr $X] -set Y [expr $Y - $RamSize256x64_H - 15] +set Y [expr $Y - $RamSize256x64_H - 20] placeInstance $bank1_sram0 $X $Y R0 diff --git a/openroad/scripts/init_tech.tcl b/openroad/scripts/init_tech.tcl index 625e4f8c..a07c80b3 100644 --- a/openroad/scripts/init_tech.tcl +++ b/openroad/scripts/init_tech.tcl @@ -79,11 +79,11 @@ set dont_use_cells sg13g2_IOPad* proc makeTracks {} { utl::report "Metal Tracks" - make_tracks Metal1 -x_offset 0 -x_pitch 0.48 -y_offset 0 -y_pitch 0.48 - make_tracks Metal2 -x_offset 0 -x_pitch 0.42 -y_offset 0 -y_pitch 0.42 - make_tracks Metal3 -x_offset 0 -x_pitch 0.48 -y_offset 0 -y_pitch 0.48 - make_tracks Metal4 -x_offset 0 -x_pitch 0.42 -y_offset 0 -y_pitch 0.42 - make_tracks Metal5 -x_offset 0 -x_pitch 0.48 -y_offset 0 -y_pitch 0.48 - make_tracks TopMetal1 -x_offset 1.46 -x_pitch 2.28 -y_offset 1.46 -y_pitch 2.28 + make_tracks Metal1 -x_offset 0 -x_pitch 0.42 -y_offset 0 -y_pitch 0.42 + make_tracks Metal2 -x_offset 0 -x_pitch 0.48 -y_offset 0 -y_pitch 0.48 + make_tracks Metal3 -x_offset 0 -x_pitch 0.42 -y_offset 0 -y_pitch 0.42 + make_tracks Metal4 -x_offset 0 -x_pitch 0.48 -y_offset 0 -y_pitch 0.48 + make_tracks Metal5 -x_offset 0 -x_pitch 0.42 -y_offset 0 -y_pitch 0.42 + make_tracks TopMetal1 -x_offset 1.64 -x_pitch 2.28 -y_offset 1.64 -y_pitch 2.28 make_tracks TopMetal2 -x_offset 2.00 -x_pitch 4.00 -y_offset 2.00 -y_pitch 4.00 } diff --git a/openroad/scripts/post_route_antenna_fix.tcl b/openroad/scripts/post_route_antenna_fix.tcl new file mode 100644 index 00000000..a51c6ef1 --- /dev/null +++ b/openroad/scripts/post_route_antenna_fix.tcl @@ -0,0 +1,153 @@ +# Copyright 2025 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Tobias Senti + +## Post-Route Antenna Fix Script +# This script checks for antenna violations after detailed routing +# and attempts to fix them by adding antenna diodes to the affected pins. +# Runs up to $max_iterations or until no violations are found anymore. + +# Maximum number of iterations until giving up +set max_iterations 3 + +# Counter for unique diode names +if {![info exists ::antennacounter]} { + set ::antennacounter 0 +} + +set early_exit 0 +for {set iteration 1} {$iteration <= $max_iterations} {incr iteration} { + puts "\n\n=== Antenna Fix Iteration $iteration ===" + set report_file_name "post_route_antenna_$iteration.rpt" + + puts "Check for antenna violations" + check_antennas -report_file $report_dir/$report_file_name + + puts "Parsing antenna report" + + # Read in report + set fp [open $report_dir/$report_file_name] + set lines [split [read $fp] "\n"] + close $fp + + # Parse report + set net_name "" + set pin_name "" + set has_violation 0 + set pin_with_violations {} + foreach line $lines { + # Trim and split line + set line [string trim $line] + set split_parts [split $line] + set parts {} + foreach part $split_parts { + if { $part ne "" } { + lappend parts $part + } + } + + # Check if it is a net or pin + set first_word [lindex $parts 0] + if { $first_word eq "Net:" } { + set net_name [lindex $parts 1] + puts "Processing net: $net_name" + } + if { $first_word eq "Pin:" } { + set pin_name [lindex $parts 1] + set has_violation 0 + puts " Pin: $pin_name" + } + + # Prevent multiple additions of the same pin + if { $has_violation eq 0 } { + # Check if it is a violation line + set last_word [lindex $parts end] + if { $last_word eq "(VIOLATED)" } { + lappend pin_with_violations $pin_name + set has_violation 1 + puts " Adding pin $pin_name to violation list" + } + } + } + + puts "\n\n" + + # If no violations, exit loop + if { [llength $pin_with_violations] eq 0 } { + puts "No antenna violations detected, exiting." + set early_exit 1 + break + } + + # Add one antenna diode per pin with violation + puts "Add antenna diodes" + set block [ord::get_db_block] + set ant_master [odb::dbDatabase_findMaster [ord::get_db] "sg13g2_antennanp"] + set violation_nets {} + foreach pin $pin_with_violations { + puts "Pin with antenna violation: $pin" + set parts [split $pin "/"] + set pin_name [lindex $parts end] + set cell_name [join [lrange $parts 0 end-1] "/"] + + # Get instance + set inst [odb::dbBlock_findInst $block $cell_name] + puts [odb::dbInst_getName $inst] + + # Get iterm (db representation of pin) + set iterm [odb::dbInst_findITerm $inst $pin_name] + + # Get net connected to iterm + set net [odb::dbITerm_getNet $iterm] + set net_name [odb::dbNet_getName $net] + # remove backslashes from net name + set net_name [string map {"\\" ""} $net_name] + lappend violation_nets $net_name + + # Remove routing of the net if it has any + set wire [odb::dbNet_getWire $net] + if { $wire ne "NULL"} { + odb::dbWire_destroy $wire + } + + # Create antenna diode instance + set ant_name "post_route_ant_diode_[incr ::antennacounter]" + set inst [odb::dbInst_create $block $ant_master $ant_name] + + # Connect antenna diode to the net + set inst_iterm [odb::dbInst_findITerm $inst "A"] + odb::dbITerm_connect $inst_iterm $net + + # Place antenna diode near the pin (gate to protect) + set xy [odb::dbITerm_getAvgXY $iterm] + puts "Placing antenna diode at $xy" + odb::dbInst_setLocation $inst [lindex $xy 1] [lindex $xy 2] + odb::dbInst_setPlacementStatus $inst "PLACED" + } + + # Refine placement of diodes + puts "Detailed placement" + detailed_placement + + # Ensure diodes are connected to power + puts "Connect power" + global_connect + + # Reroute affected nets + puts "Detailed route" + detailed_route -output_drc ${report_dir}/${log_id_str}_${proj_name}_post_route_antenna_fix_drc.rpt \ + -droute_end_iter 30 \ + -drc_report_iter_step 5 \ + -save_guide_updates \ + -clean_patches \ + -verbose 1 +} + +# Final antenna check if we have not exited early i.e. fixed all violations +if {$early_exit eq 0} { + puts "Final antenna check" + check_antennas -report_file $report_dir/$report_file_name +} diff --git a/openroad/scripts/power_grid.tcl b/openroad/scripts/power_grid.tcl index 1d5a2be9..3c4f774f 100644 --- a/openroad/scripts/power_grid.tcl +++ b/openroad/scripts/power_grid.tcl @@ -29,14 +29,12 @@ if {[info exists power_grid_defined]} { ## Power settings ########################################################################## # Core Power Ring -## Space between pads and core -> used for power ring -set PowRingSpace 35 +## Offset from core to power ring +set pgcrOffset 0 ## Spacing must meet TM2 rules set pgcrSpacing 6 ## Width must meet TM2 rules set pgcrWidth 10 -## Offset from core to power ring -set pgcrOffset [expr ($PowRingSpace - $pgcrSpacing - 2 * $pgcrWidth) / 2] # TopMetal2 Core Power Grid set tpg2Width 6; # arbitrary number @@ -54,7 +52,7 @@ set mprOffsetX 2.4 set mprOffsetY 0.6 # macro power grid (stripes on TopMetal1/TopMetal2 depending on orientation) -set mpgWidth 6 +set mpgWidth 4 set mpgSpacing 4 set mpgOffset 20; # arbitrary @@ -85,18 +83,18 @@ proc sram_power { name macro } { set stripe_dist [expr $stripe_dist/2] } - add_pdn_stripe -grid ${name}_grid -layer {TopMetal1} -width $mpgWidth -spacing $mpgSpacing \ + add_pdn_stripe -grid ${name}_grid -layer {Metal5} -width $mpgWidth -spacing $mpgSpacing \ -pitch $stripe_dist -offset $mpgOffset -extend_to_core_ring -starts_with POWER -snap_to_grid # Connection of Macro Power Ring to standard-cell rails - add_pdn_connect -grid ${name}_grid -layers {Metal3 Metal1} + add_pdn_connect -grid ${name}_grid -layers {Metal4 Metal2} + add_pdn_connect -grid ${name}_grid -layers {Metal4 Metal1} # Connection of Stripes on Macro to Macro Power Ring - add_pdn_connect -grid ${name}_grid -layers {TopMetal1 Metal3} - add_pdn_connect -grid ${name}_grid -layers {TopMetal1 Metal4} + add_pdn_connect -grid ${name}_grid -layers {Metal5 Metal4} # Connection of Stripes on Macro to Macro Power Pins - # add_pdn_connect -grid ${name}_grid -layers {TopMetal1 Metal4} + #add_pdn_connect -grid ${name}_grid -layers {TopMetal1 Metal4} # Connection of Stripes on Macro to Core Power Stripes - add_pdn_connect -grid ${name}_grid -layers {TopMetal2 TopMetal1} + add_pdn_connect -grid ${name}_grid -layers {TopMetal1 Metal5} } @@ -114,7 +112,7 @@ add_pdn_ring -grid {core_grid} \ -connect_to_pad_layers TopMetal2 # M1 Standardcell Rows (tracks) -add_pdn_stripe -grid {core_grid} -layer {Metal1} -width {0.44} -offset {0} \ +add_pdn_stripe -grid {core_grid} -layer {Metal1} -width {0.32} -offset {0} \ -followpins -extend_to_core_ring @@ -122,7 +120,7 @@ sram_power "sram_256x64" "RM_IHPSG13_1P_256x64_c2_bm_bist" # Top power grid # Top 2 Stripe -add_pdn_stripe -grid {core_grid} -layer {TopMetal2} -width $tpg2Width \ +add_pdn_stripe -grid {core_grid} -layer {TopMetal1} -width $tpg2Width \ -pitch $tpg2Pitch -spacing $tpg2Spacing -offset $tpg2Offset \ -extend_to_core_ring -snap_to_grid -number_of_straps 7 @@ -130,13 +128,12 @@ add_pdn_stripe -grid {core_grid} -layer {TopMetal2} -width $tpg2Width \ # During power grid generation, vias will be added for overlapping power nets and overlapping ground nets." # M1 is declared vertical but tracks still horizontal # vertical TopMetal2 to below horizonals (M1 has horizontal power tracks) -add_pdn_connect -grid {core_grid} -layers {TopMetal2 Metal1} -add_pdn_connect -grid {core_grid} -layers {TopMetal2 Metal2} -add_pdn_connect -grid {core_grid} -layers {TopMetal2 Metal4} -# add_pdn_connect -grid {core_grid} -layers {TopMetal2 TopMetal1} +add_pdn_connect -grid {core_grid} -layers {TopMetal1 Metal1} +add_pdn_connect -grid {core_grid} -layers {TopMetal1 Metal3} +add_pdn_connect -grid {core_grid} -layers {TopMetal1 Metal5} # power ring to standard cell rails -add_pdn_connect -grid {core_grid} -layers {Metal3 Metal1} add_pdn_connect -grid {core_grid} -layers {Metal3 Metal2} +add_pdn_connect -grid {core_grid} -layers {Metal2 Metal1} ########################################################################## diff --git a/openroad/src/padring.tcl b/openroad/src/padring.tcl index 287b24b0..493811fe 100644 --- a/openroad/src/padring.tcl +++ b/openroad/src/padring.tcl @@ -9,138 +9,137 @@ # - The "#pin no.: nn" comment shows the corresponding pin number for the package. # [QFN48] -# package die -# pins 48 56 -# I/O 40 40 -# Core power 4 4 -# Core ground - 4 -# Pad power 4 4 -# Pad ground - 4 +# package die +# pins 48 56 +# I/O 40 40 +# Core power 4 4 +# Core ground - 4 +# Pad power 4 4 +# Pad ground - 4 # +# pad pitch (min) 90.0 90.0 # -# final dimensions: [um] -# die area (4sqmm) 2000.0 x 2000.0 -# io cell dimensions 180.0 x 80.0 -# bonding pad area (est) 70.0 x 70.0 -# seal ring width (est) 50.0 x - -# -# OpenROAD: -# OR die area 1760.0 x 1760.0 -# core area 1400.0 x 1400.0 -# total silicon area -# -# pad pitch (min) 90.0 90.0 +# Chip geometry comes from floorplan.tcl +# Keep only the pad positioning/spacing here + +# Positioning for every edge works like this: +# - the IO site spans the entire edge +# - pads start padKeepout microns away from the corner (pad -> bond -> gap) +# - the remaining usable edge length is split into (numPads-1) equal gaps +set numPadsPerEdge 16 +set padGap 20; # walk-off between IO pads and corners +set padKeepout [expr {$padD + $padBond + $padGap}] make_io_sites -horizontal_site sg13g2_ioSite \ -vertical_site sg13g2_ioSite \ -corner_site sg13g2_ioSite \ - -offset 0 \ + -offset $padBond \ -rotation_horizontal R0 \ -rotation_vertical R0 \ -rotation_corner R0 -set padD 180; # pad depth (edge to core) -set padW 80; # pad width (beachfront) - -set chipH 1760; # left/right (height) -set chipW 1760; # top/bottom (width) - -#Edge: LEFT (top to bottom) -set numPads 16 -set offset 20 -set pitch [expr {floor( ($chipH - 2*$padD -2*$offset - $padW)/($numPads-1) )}] -puts "IO_WEST_pitch: $pitch " -set start [expr $chipH - $padD - $offset - $padW] -place_pad -row IO_WEST -location [expr $start - 0*$pitch] "pad_vssio0" ; # pin no: 1 -place_pad -row IO_WEST -location [expr $start - 1*$pitch] "pad_vddio0" ; # pin no: 2 -place_pad -row IO_WEST -location [expr $start - 2*$pitch] "pad_uart_rx_i" ; # pin no: 3 -place_pad -row IO_WEST -location [expr $start - 3*$pitch] "pad_uart_tx_o" ; # pin no: 4 -place_pad -row IO_WEST -location [expr $start - 4*$pitch] "pad_fetch_en_i" ; # pin no: 5 -place_pad -row IO_WEST -location [expr $start - 5*$pitch] "pad_status_o" ; # pin no: 6 -place_pad -row IO_WEST -location [expr $start - 6*$pitch] "pad_clk_i" ; # pin no: 7 -place_pad -row IO_WEST -location [expr $start - 7*$pitch] "pad_ref_clk_i" ; # pin no: 8 -place_pad -row IO_WEST -location [expr $start - 8*$pitch] "pad_rst_ni" ; # pin no: 9 -place_pad -row IO_WEST -location [expr $start - 9*$pitch] "pad_jtag_tck_i" ; # pin no: 10 -place_pad -row IO_WEST -location [expr $start - 10*$pitch] "pad_jtag_trst_ni" ; # pin no: 11 -place_pad -row IO_WEST -location [expr $start - 11*$pitch] "pad_jtag_tms_i" ; # pin no: 12 -place_pad -row IO_WEST -location [expr $start - 12*$pitch] "pad_jtag_tdi_i" ; # pin no: 13 -place_pad -row IO_WEST -location [expr $start - 13*$pitch] "pad_jtag_tdo_o" ; # pin no: 14 -place_pad -row IO_WEST -location [expr $start - 14*$pitch] "pad_vss0" ; # pin no: 15 -place_pad -row IO_WEST -location [expr $start - 15*$pitch] "pad_vdd0" ; # pin no: 16 - - -#Edge: BOTTOM (left to right) -set numPads 16 -set offset 20 -set pitch [expr {floor( ($chipW - 2*$padD -2*$offset - $padW)/($numPads-1) )}] -puts "IO_SOUTH_pitch: $pitch " -set start [expr $padD + $offset] -place_pad -row IO_SOUTH -location [expr $start + 0*$pitch] "pad_vssio1" ; # pin no: 1 -place_pad -row IO_SOUTH -location [expr $start + 1*$pitch] "pad_vddio1" ; # pin no: 2 -place_pad -row IO_SOUTH -location [expr $start + 2*$pitch] "pad_gpio0_io" ; # pin no: 3 -place_pad -row IO_SOUTH -location [expr $start + 3*$pitch] "pad_gpio1_io" ; # pin no: 4 -place_pad -row IO_SOUTH -location [expr $start + 4*$pitch] "pad_gpio2_io" ; # pin no: 5 -place_pad -row IO_SOUTH -location [expr $start + 5*$pitch] "pad_gpio3_io" ; # pin no: 6 -place_pad -row IO_SOUTH -location [expr $start + 6*$pitch] "pad_gpio4_io" ; # pin no: 7 -place_pad -row IO_SOUTH -location [expr $start + 7*$pitch] "pad_gpio5_io" ; # pin no: 8 -place_pad -row IO_SOUTH -location [expr $start + 8*$pitch] "pad_gpio6_io" ; # pin no: 9 -place_pad -row IO_SOUTH -location [expr $start + 9*$pitch] "pad_gpio7_io" ; # pin no: 10 -place_pad -row IO_SOUTH -location [expr $start + 10*$pitch] "pad_gpio8_io" ; # pin no: 11 -place_pad -row IO_SOUTH -location [expr $start + 11*$pitch] "pad_gpio9_io" ; # pin no: 12 -place_pad -row IO_SOUTH -location [expr $start + 12*$pitch] "pad_gpio10_io" ; # pin no: 13 -place_pad -row IO_SOUTH -location [expr $start + 13*$pitch] "pad_gpio11_io" ; # pin no: 14 -place_pad -row IO_SOUTH -location [expr $start + 14*$pitch] "pad_vss1" ; # pin no: 15 -place_pad -row IO_SOUTH -location [expr $start + 15*$pitch] "pad_vdd1" ; # pin no: 16 - - -#Edge: RIGHT (bottom to top) -set numPads 16 -set offset 20 -set pitch [expr {floor( ($chipH - 2*$padD -2*$offset - $padW)/($numPads-1) )}] -puts "IO_EAST_pitch: $pitch " -set start [expr $padD + $offset] -place_pad -row IO_EAST -location [expr $start + 0*$pitch] "pad_vssio2" ; # pin no: 1 -place_pad -row IO_EAST -location [expr $start + 1*$pitch] "pad_vddio2" ; # pin no: 2 -place_pad -row IO_EAST -location [expr $start + 2*$pitch] "pad_gpio12_io" ; # pin no: 3 -place_pad -row IO_EAST -location [expr $start + 3*$pitch] "pad_gpio13_io" ; # pin no: 4 -place_pad -row IO_EAST -location [expr $start + 4*$pitch] "pad_gpio14_io" ; # pin no: 5 -place_pad -row IO_EAST -location [expr $start + 5*$pitch] "pad_gpio15_io" ; # pin no: 6 -place_pad -row IO_EAST -location [expr $start + 6*$pitch] "pad_gpio16_io" ; # pin no: 7 -place_pad -row IO_EAST -location [expr $start + 7*$pitch] "pad_gpio17_io" ; # pin no: 8 -place_pad -row IO_EAST -location [expr $start + 8*$pitch] "pad_gpio18_io" ; # pin no: 9 -place_pad -row IO_EAST -location [expr $start + 9*$pitch] "pad_gpio19_io" ; # pin no: 10 -place_pad -row IO_EAST -location [expr $start + 10*$pitch] "pad_gpio20_io" ; # pin no: 11 -place_pad -row IO_EAST -location [expr $start + 11*$pitch] "pad_gpio21_io" ; # pin no: 12 -place_pad -row IO_EAST -location [expr $start + 12*$pitch] "pad_gpio22_io" ; # pin no: 13 -place_pad -row IO_EAST -location [expr $start + 13*$pitch] "pad_gpio23_io" ; # pin no: 14 -place_pad -row IO_EAST -location [expr $start + 14*$pitch] "pad_vss2" ; # pin no: 15 -place_pad -row IO_EAST -location [expr $start + 15*$pitch] "pad_vdd2" ; # pin no: 16 - - -#Edge: TOP (right to left) -set numPads 16 -set offset 20 -set pitch [expr {floor( ($chipW - 2*$padD -2*$offset - $padW)/($numPads-1) )}] -puts "IO_NORTH_pitch: $pitch " -set start [expr $chipW - $padD - $padW -$offset] -place_pad -row IO_NORTH -location [expr $start - 0*$pitch] "pad_vssio3" ; # pin no: 1 -place_pad -row IO_NORTH -location [expr $start - 1*$pitch] "pad_vddio3" ; # pin no: 2 -place_pad -row IO_NORTH -location [expr $start - 2*$pitch] "pad_gpio24_io" ; # pin no: 3 -place_pad -row IO_NORTH -location [expr $start - 3*$pitch] "pad_gpio25_io" ; # pin no: 4 -place_pad -row IO_NORTH -location [expr $start - 4*$pitch] "pad_gpio26_io" ; # pin no: 5 -place_pad -row IO_NORTH -location [expr $start - 5*$pitch] "pad_gpio27_io" ; # pin no: 6 -place_pad -row IO_NORTH -location [expr $start - 6*$pitch] "pad_gpio28_io" ; # pin no: 7 -place_pad -row IO_NORTH -location [expr $start - 7*$pitch] "pad_gpio29_io" ; # pin no: 8 -place_pad -row IO_NORTH -location [expr $start - 8*$pitch] "pad_gpio30_io" ; # pin no: 9 -place_pad -row IO_NORTH -location [expr $start - 9*$pitch] "pad_gpio31_io" ; # pin no: 10 -place_pad -row IO_NORTH -location [expr $start - 10*$pitch] "pad_unused0_o" ; # pin no: 11 -place_pad -row IO_NORTH -location [expr $start - 11*$pitch] "pad_unused1_o" ; # pin no: 12 -place_pad -row IO_NORTH -location [expr $start - 12*$pitch] "pad_unused2_o" ; # pin no: 13 -place_pad -row IO_NORTH -location [expr $start - 13*$pitch] "pad_unused3_o" ; # pin no: 14 -place_pad -row IO_NORTH -location [expr $start - 14*$pitch] "pad_vss3" ; # pin no: 15 -place_pad -row IO_NORTH -location [expr $start - 15*$pitch] "pad_vdd3" ; # pin no: 16 - +########################################################################## +# Edge: LEFT (top to bottom) # +########################################################################## +set westSpan $chipH +set westUsable [expr {$westSpan - 2*$padKeepout - $padW}] +set westPitch [expr {floor($westUsable / double($numPadsPerEdge - 1))}] +set westStart [expr {$westSpan - $padKeepout - $padW}] + +place_pad -row IO_WEST -location [expr {$westStart - 0*$westPitch}] "pad_vssio0" ; # pin no: 1 +place_pad -row IO_WEST -location [expr {$westStart - 1*$westPitch}] "pad_vddio0" ; # pin no: 2 +place_pad -row IO_WEST -location [expr {$westStart - 2*$westPitch}] "pad_uart_rx_i" ; # pin no: 3 +place_pad -row IO_WEST -location [expr {$westStart - 3*$westPitch}] "pad_uart_tx_o" ; # pin no: 4 +place_pad -row IO_WEST -location [expr {$westStart - 4*$westPitch}] "pad_fetch_en_i" ; # pin no: 5 +place_pad -row IO_WEST -location [expr {$westStart - 5*$westPitch}] "pad_status_o" ; # pin no: 6 +place_pad -row IO_WEST -location [expr {$westStart - 6*$westPitch}] "pad_clk_i" ; # pin no: 7 +place_pad -row IO_WEST -location [expr {$westStart - 7*$westPitch}] "pad_ref_clk_i" ; # pin no: 8 +place_pad -row IO_WEST -location [expr {$westStart - 8*$westPitch}] "pad_rst_ni" ; # pin no: 9 +place_pad -row IO_WEST -location [expr {$westStart - 9*$westPitch}] "pad_jtag_tck_i" ; # pin no: 10 +place_pad -row IO_WEST -location [expr {$westStart - 10*$westPitch}] "pad_jtag_trst_ni" ; # pin no: 11 +place_pad -row IO_WEST -location [expr {$westStart - 11*$westPitch}] "pad_jtag_tms_i" ; # pin no: 12 +place_pad -row IO_WEST -location [expr {$westStart - 12*$westPitch}] "pad_jtag_tdi_i" ; # pin no: 13 +place_pad -row IO_WEST -location [expr {$westStart - 13*$westPitch}] "pad_jtag_tdo_o" ; # pin no: 14 +place_pad -row IO_WEST -location [expr {$westStart - 14*$westPitch}] "pad_vss0" ; # pin no: 15 +place_pad -row IO_WEST -location [expr {$westStart - 15*$westPitch}] "pad_vdd0" ; # pin no: 16 + +########################################################################## +# Edge: BOTTOM (left to right) # +########################################################################## +set southSpan $chipW +set southUsable [expr {$southSpan - 2*$padKeepout - $padW}] +set southPitch [expr {floor($southUsable / double($numPadsPerEdge - 1))}] +set southStart $padKeepout + +place_pad -row IO_SOUTH -location [expr {$southStart + 0*$southPitch}] "pad_vssio1" ; # pin no: 1 +place_pad -row IO_SOUTH -location [expr {$southStart + 1*$southPitch}] "pad_vddio1" ; # pin no: 2 +place_pad -row IO_SOUTH -location [expr {$southStart + 2*$southPitch}] "pad_gpio0_io" ; # pin no: 3 +place_pad -row IO_SOUTH -location [expr {$southStart + 3*$southPitch}] "pad_gpio1_io" ; # pin no: 4 +place_pad -row IO_SOUTH -location [expr {$southStart + 4*$southPitch}] "pad_gpio2_io" ; # pin no: 5 +place_pad -row IO_SOUTH -location [expr {$southStart + 5*$southPitch}] "pad_gpio3_io" ; # pin no: 6 +place_pad -row IO_SOUTH -location [expr {$southStart + 6*$southPitch}] "pad_gpio4_io" ; # pin no: 7 +place_pad -row IO_SOUTH -location [expr {$southStart + 7*$southPitch}] "pad_gpio5_io" ; # pin no: 8 +place_pad -row IO_SOUTH -location [expr {$southStart + 8*$southPitch}] "pad_gpio6_io" ; # pin no: 9 +place_pad -row IO_SOUTH -location [expr {$southStart + 9*$southPitch}] "pad_gpio7_io" ; # pin no: 10 +place_pad -row IO_SOUTH -location [expr {$southStart + 10*$southPitch}] "pad_gpio8_io" ; # pin no: 11 +place_pad -row IO_SOUTH -location [expr {$southStart + 11*$southPitch}] "pad_gpio9_io" ; # pin no: 12 +place_pad -row IO_SOUTH -location [expr {$southStart + 12*$southPitch}] "pad_gpio10_io" ; # pin no: 13 +place_pad -row IO_SOUTH -location [expr {$southStart + 13*$southPitch}] "pad_gpio11_io" ; # pin no: 14 +place_pad -row IO_SOUTH -location [expr {$southStart + 14*$southPitch}] "pad_vss1" ; # pin no: 15 +place_pad -row IO_SOUTH -location [expr {$southStart + 15*$southPitch}] "pad_vdd1" ; # pin no: 16 + +########################################################################## +# Edge: RIGHT (bottom to top) # +########################################################################## +set eastSpan $chipH +set eastUsable [expr {$eastSpan - 2*$padKeepout - $padW}] +set eastPitch [expr {floor($eastUsable / double($numPadsPerEdge - 1))}] +set eastStart $padKeepout + +place_pad -row IO_EAST -location [expr {$eastStart + 0*$eastPitch}] "pad_vssio2" ; # pin no: 1 +place_pad -row IO_EAST -location [expr {$eastStart + 1*$eastPitch}] "pad_vddio2" ; # pin no: 2 +place_pad -row IO_EAST -location [expr {$eastStart + 2*$eastPitch}] "pad_gpio12_io" ; # pin no: 3 +place_pad -row IO_EAST -location [expr {$eastStart + 3*$eastPitch}] "pad_gpio13_io" ; # pin no: 4 +place_pad -row IO_EAST -location [expr {$eastStart + 4*$eastPitch}] "pad_gpio14_io" ; # pin no: 5 +place_pad -row IO_EAST -location [expr {$eastStart + 5*$eastPitch}] "pad_gpio15_io" ; # pin no: 6 +place_pad -row IO_EAST -location [expr {$eastStart + 6*$eastPitch}] "pad_gpio16_io" ; # pin no: 7 +place_pad -row IO_EAST -location [expr {$eastStart + 7*$eastPitch}] "pad_gpio17_io" ; # pin no: 8 +place_pad -row IO_EAST -location [expr {$eastStart + 8*$eastPitch}] "pad_gpio18_io" ; # pin no: 9 +place_pad -row IO_EAST -location [expr {$eastStart + 9*$eastPitch}] "pad_gpio19_io" ; # pin no: 10 +place_pad -row IO_EAST -location [expr {$eastStart + 10*$eastPitch}] "pad_gpio20_io" ; # pin no: 11 +place_pad -row IO_EAST -location [expr {$eastStart + 11*$eastPitch}] "pad_gpio21_io" ; # pin no: 12 +place_pad -row IO_EAST -location [expr {$eastStart + 12*$eastPitch}] "pad_gpio22_io" ; # pin no: 13 +place_pad -row IO_EAST -location [expr {$eastStart + 13*$eastPitch}] "pad_gpio23_io" ; # pin no: 14 +place_pad -row IO_EAST -location [expr {$eastStart + 14*$eastPitch}] "pad_vss2" ; # pin no: 15 +place_pad -row IO_EAST -location [expr {$eastStart + 15*$eastPitch}] "pad_vdd2" ; # pin no: 16 + +########################################################################## +# Edge: TOP (right to left) # +########################################################################## +set northSpan $chipW +set northUsable [expr {$northSpan - 2*$padKeepout - $padW}] +set northPitch [expr {floor($northUsable / double($numPadsPerEdge - 1))}] +set northStart [expr {$northSpan - $padKeepout - $padW}] + +place_pad -row IO_NORTH -location [expr {$northStart - 0*$northPitch}] "pad_vssio3" ; # pin no: 1 +place_pad -row IO_NORTH -location [expr {$northStart - 1*$northPitch}] "pad_vddio3" ; # pin no: 2 +place_pad -row IO_NORTH -location [expr {$northStart - 2*$northPitch}] "pad_gpio24_io" ; # pin no: 3 +place_pad -row IO_NORTH -location [expr {$northStart - 3*$northPitch}] "pad_gpio25_io" ; # pin no: 4 +place_pad -row IO_NORTH -location [expr {$northStart - 4*$northPitch}] "pad_gpio26_io" ; # pin no: 5 +place_pad -row IO_NORTH -location [expr {$northStart - 5*$northPitch}] "pad_gpio27_io" ; # pin no: 6 +place_pad -row IO_NORTH -location [expr {$northStart - 6*$northPitch}] "pad_gpio28_io" ; # pin no: 7 +place_pad -row IO_NORTH -location [expr {$northStart - 7*$northPitch}] "pad_gpio29_io" ; # pin no: 8 +place_pad -row IO_NORTH -location [expr {$northStart - 8*$northPitch}] "pad_gpio30_io" ; # pin no: 9 +place_pad -row IO_NORTH -location [expr {$northStart - 9*$northPitch}] "pad_gpio31_io" ; # pin no: 10 +place_pad -row IO_NORTH -location [expr {$northStart - 10*$northPitch}] "pad_unused0_o" ; # pin no: 11 +place_pad -row IO_NORTH -location [expr {$northStart - 11*$northPitch}] "pad_unused1_o" ; # pin no: 12 +place_pad -row IO_NORTH -location [expr {$northStart - 12*$northPitch}] "pad_unused2_o" ; # pin no: 13 +place_pad -row IO_NORTH -location [expr {$northStart - 13*$northPitch}] "pad_unused3_o" ; # pin no: 14 +place_pad -row IO_NORTH -location [expr {$northStart - 14*$northPitch}] "pad_vss3" ; # pin no: 15 +place_pad -row IO_NORTH -location [expr {$northStart - 15*$northPitch}] "pad_vdd3" ; # pin no: 16 + +# Fill in the rest of the padring place_corners $iocorner place_io_fill -row IO_NORTH {*}$iofill @@ -148,8 +147,7 @@ place_io_fill -row IO_SOUTH {*}$iofill place_io_fill -row IO_WEST {*}$iofill place_io_fill -row IO_EAST {*}$iofill - -# Connect built-in rings +# Connect built-in power rings connect_by_abutment # Bondpad integrated into IO cell (or bondpad after OpenROAD): @@ -162,4 +160,4 @@ connect_by_abutment place_bondpad -bond bondpad_70x70 -offset {5.0 -70.0} pad_* # remove rows created by via make_io_sites as they are no longer needed -remove_io_rows \ No newline at end of file +remove_io_rows diff --git a/start_vnc.bat b/start_vnc.bat index 3e2b908a..2250f9eb 100644 --- a/start_vnc.bat +++ b/start_vnc.bat @@ -46,7 +46,7 @@ if not exist "%DESIGNS%" %ECHO_IF_DRY_RUN% mkdir "%DESIGNS%" IF "%DOCKER_USER%"=="" SET DOCKER_USER=hpretl IF "%DOCKER_IMAGE%"=="" SET DOCKER_IMAGE=iic-osic-tools -IF "%DOCKER_TAG%"=="" SET DOCKER_TAG=2025.07.pre1 +IF "%DOCKER_TAG%"=="" SET DOCKER_TAG=2025.11 IF "%CONTAINER_USER%"=="" SET CONTAINER_USER=1000 IF "%CONTAINER_GROUP%"=="" SET CONTAINER_GROUP=1000 diff --git a/start_vnc.sh b/start_vnc.sh index 1f2e138c..9e8948cd 100755 --- a/start_vnc.sh +++ b/start_vnc.sh @@ -52,7 +52,7 @@ if [ -z ${DOCKER_IMAGE+z} ]; then fi if [ -z ${DOCKER_TAG+z} ]; then - DOCKER_TAG="2025.07.pre1" + DOCKER_TAG="2025.11" fi if [ -z ${CONTAINER_NAME+z} ]; then