Some files are missing

[dassheladiya]

I have cloned the repository as instructed in the README using the following command:

git clone https://github.com/planvtech/culsans.git --recursive

However, when I attempt to synthesize using make fpga, the process fails, indicating that the SyncThreePortRam.sv file is missing. This file is available in the master branch but not in commit 338d4c1. I would greatly appreciate your guidance on how to proceed with generating the bit stream.

Below is the log:

Synthesis finished with 0 errors, 0 critical warnings and 12 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:02:04 ; elapsed = 00:02:34 . Memory (MB): peak = 2708.340 ; gain = 712.434 ; free physical = 117952 ; free virtual = 121874
Synthesis Optimization Complete : Time (s): cpu = 00:02:13 ; elapsed = 00:02:40 . Memory (MB): peak = 2708.340 ; gain = 911.027 ; free physical = 117951 ; free virtual = 121872
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2708.340 ; gain = 0.000 ; free physical = 117939 ; free virtual = 121861
INFO: [Netlist 29-17] Analyzing 868 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 4 inverter(s) to 32 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2744.449 ; gain = 0.000 ; free physical = 117835 ; free virtual = 121756
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 338 instances were transformed.
(MUXCY,XORCY) => CARRY4: 45 instances
IBUFGDS => IBUFDS: 1 instance
IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances
IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances
LUT6_2 => LUT6_2 (LUT5, LUT6): 26 instances
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 229 instances

INFO: [Common 17-83] Releasing license: Synthesis
674 Infos, 333 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:02:19 ; elapsed = 00:02:50 . Memory (MB): peak = 2744.449 ; gain = 1229.000 ; free physical = 117938 ; free virtual = 121859
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2744.449 ; gain = 0.000 ; free physical = 117938 ; free virtual = 121859
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint '/root/isolde/culsans/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3.dcp' has been generated.
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_mig_7_ddr3, cache-ID = c3aee5655a48f094
INFO: [Coretcl 2-1174] Renamed 216 cell refs.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.461 ; gain = 0.000 ; free physical = 117936 ; free virtual = 121886
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint '/root/isolde/culsans/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file xlnx_mig_7_ddr3_utilization_synth.rpt -pb xlnx_mig_7_ddr3_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Thu Mar 27 13:37:16 2025...
[Thu Mar 27 13:37:16 2025] xlnx_mig_7_ddr3_synth_1 finished
wait_on_run: Time (s): cpu = 00:02:35 ; elapsed = 00:03:08 . Memory (MB): peak = 2049.082 ; gain = 0.000 ; free physical = 119129 ; free virtual = 123052
INFO: [Common 17-206] Exiting Vivado at Thu Mar 27 13:37:16 2025...
make[2]: Leaving directory '/root/isolde/culsans/fpga/xilinx/xlnx_mig_7_ddr3'
make[1]: *** No rule to make target '/root/isolde/culsans/modules/cva6/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv', needed by 'scripts/add_sources.tcl'. Stop.
make[1]: Leaving directory '/root/isolde/culsans/fpga'
make: *** [Makefile:19: fpga] Error 2