diff --git a/.github/authors-cfg.yaml b/.github/authors-cfg.yaml
index 3d0098d5..b06b0822 100644
--- a/.github/authors-cfg.yaml
+++ b/.github/authors-cfg.yaml
@@ -27,6 +27,7 @@ exclude-ext:
- svg
- txt
- json
+ - toml
- md
- lock
- local
diff --git a/.github/workflows/analyze.yml b/.github/workflows/analyze.yml
index 9b2db9a4..b022d43c 100644
--- a/.github/workflows/analyze.yml
+++ b/.github/workflows/analyze.yml
@@ -21,14 +21,13 @@ jobs:
name: Checkout
uses: actions/checkout@v4
-
- name: Install Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.9'
- cache: 'pip'
+ name: Install uv
+ uses: astral-sh/setup-uv@v5
-
- name: Python Requirements
- run: pip install -r requirements.txt
+ name: Install Python dependencies
+ run: |
+ uv sync --locked
+ echo "$PWD/.venv/bin" >> $GITHUB_PATH
-
name: List contributors
run: scripts/list-contributors | tee contributions.txt
@@ -48,14 +47,13 @@ jobs:
name: Checkout
uses: actions/checkout@v4
-
- name: Install Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.9'
- cache: 'pip'
+ name: Install uv
+ uses: astral-sh/setup-uv@v5
-
- name: Python Requirements
- run: pip install -r requirements.txt
+ name: Install Python dependencies
+ run: |
+ uv sync --locked
+ echo "$PWD/.venv/bin" >> $GITHUB_PATH
-
name: List todos
run: scripts/list-todos | tee open_todos.txt
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 6068359c..e473ec90 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -25,14 +25,8 @@ jobs:
name: Checkout
uses: actions/checkout@v4
-
- name: Install Python
- uses: actions/setup-python@v5
- with:
- python-version: 3.9
- cache: pip
- -
- name: Install Python requirements
- run: pip install -r requirements.txt
+ name: Install uv
+ uses: astral-sh/setup-uv@v5
-
name: Setup Graphviz
uses: ts-graphviz/setup-graphviz@v2
@@ -58,13 +52,13 @@ jobs:
echo "PATH=.:$PATH" >> ${GITHUB_ENV}
-
name: Check clean
- run: make idma_clean_all
+ run: uv run --locked make idma_clean_all
-
name: Check whether clean
run: git status && test -z "$(git status --porcelain --ignore-submodules)"
-
name: Build target
- run: make -j9 idma_${{ matrix.target }}_all
+ run: uv run --locked make -j9 idma_${{ matrix.target }}_all
-
name: Check whether stale
run: git status && test -z "$(git status --porcelain --ignore-submodules)"
diff --git a/.github/workflows/deploy.yml b/.github/workflows/deploy.yml
index 935d4e9c..51b1ca95 100644
--- a/.github/workflows/deploy.yml
+++ b/.github/workflows/deploy.yml
@@ -22,14 +22,8 @@ jobs:
with:
fetch-depth: 0
-
- name: Install Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.9'
- cache: 'pip'
- -
- name: Python Requirements
- run: pip install -r requirements.txt
+ name: Install uv
+ uses: astral-sh/setup-uv@v5
-
name: Install Bender
uses: pulp-platform/pulp-actions/bender-install@v2
@@ -45,11 +39,11 @@ jobs:
echo "PATH=.:$PATH" >> ${GITHUB_ENV}
-
name: Build hardware
- run: make -B idma_hw_all
+ run: uv run --locked make -B idma_hw_all
-
name: Deploy generated files
run: |
git config user.email "github-ci@iis.ee.ethz.ch"
git config user.name "github-ci"
git fetch --all
- python3 util/deploy.py
+ uv run --locked util/deploy.py
diff --git a/.github/workflows/docs.yml b/.github/workflows/docs.yml
index aa626bc8..db83ffa1 100644
--- a/.github/workflows/docs.yml
+++ b/.github/workflows/docs.yml
@@ -24,14 +24,10 @@ jobs:
name: Checkout
uses: actions/checkout@v4
-
- name: Install Python
- uses: actions/setup-python@v5
+ name: Install uv
+ uses: astral-sh/setup-uv@v6
with:
- python-version: 3.9
- cache: pip
- -
- name: Install Python requirements
- run: pip install -r requirements.txt
+ python-version: "3.11"
-
name: Setup Graphviz
uses: ts-graphviz/setup-graphviz@v2
@@ -57,7 +53,7 @@ jobs:
echo "PATH=.:$PATH" >> ${GITHUB_ENV}
-
name: Build Doc
- run: make idma_doc_all
+ run: uv run --locked make idma_doc_all
-
name: Create publish docs
uses: actions/upload-pages-artifact@v3
diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml
index 7d6c570d..f8085471 100644
--- a/.github/workflows/lint.yml
+++ b/.github/workflows/lint.yml
@@ -81,7 +81,7 @@ jobs:
name: Install Python
uses: actions/setup-python@v5
with:
- python-version: 3.9
+ python-version: 3.11
-
name: Lint Python
uses: py-actions/flake8@v2
@@ -99,7 +99,7 @@ jobs:
name: Install Python
uses: actions/setup-python@v5
with:
- python-version: 3.9
+ python-version: 3.11
-
name: Lint Yaml
uses: ibiqlik/action-yamllint@v3
@@ -119,16 +119,10 @@ jobs:
with:
ref: ${{ github.event.pull_request.head.sha }}
-
- uses: actions/setup-python@v5
- with:
- python-version: '3.9'
- cache: 'pip'
- -
- name: Python Requirements
- run: python3 -m pip install -r requirements.txt
+ uses: astral-sh/setup-uv@v5
-
name: Lint commits
- run: python3 util/lint-commits.py HEAD
+ run: uv run --locked util/lint-commits.py HEAD
lint-author:
runs-on: ubuntu-latest
@@ -137,14 +131,8 @@ jobs:
name: Checkout
uses: actions/checkout@v4
-
- name: Install Python
- uses: actions/setup-python@v5
- with:
- python-version: '3.9'
- cache: 'pip'
- -
- name: Python Requirements
- run: pip install -r requirements.txt
+ name: Install uv
+ uses: astral-sh/setup-uv@v5
-
name: Lint authors
- run: python3 util/lint-authors.py .github/authors-cfg.yaml
+ run: uv run --locked util/lint-authors.py .github/authors-cfg.yaml
diff --git a/Bender.lock b/Bender.lock
index 9f1098b1..e7177edc 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -7,8 +7,8 @@ packages:
dependencies:
- common_cells
axi:
- revision: fccffb5953ec8564218ba05e20adbedec845e014
- version: 0.39.1
+ revision: 39f5f2d51c5e524f6fc5cf8b6e901f7dcc5622d7
+ version: 0.39.6
source:
Git: https://github.com/pulp-platform/axi.git
dependencies:
@@ -23,30 +23,30 @@ packages:
dependencies:
- common_cells
common_cells:
- revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239
- version: 1.33.0
+ revision: 9afda9abb565971649c2aa0985639c096f351171
+ version: 1.38.0
source:
Git: https://github.com/pulp-platform/common_cells.git
dependencies:
- common_verification
- tech_cells_generic
common_verification:
- revision: 9c07fa860593b2caabd9b5681740c25fac04b878
- version: 0.2.3
+ revision: fb1885f48ea46164a10568aeff51884389f67ae3
+ version: 0.2.5
source:
Git: https://github.com/pulp-platform/common_verification.git
dependencies: []
obi:
- revision: 1aa411df145c4ebdd61f8fed4d003c33f7b20636
- version: 0.1.2
+ revision: 8097928cf1b43712f93d5356f336397879b4ad2c
+ version: 0.1.6
source:
Git: https://github.com/pulp-platform/obi.git
dependencies:
- common_cells
- common_verification
register_interface:
- revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19
- version: 0.4.3
+ revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467
+ version: 0.4.5
source:
Git: https://github.com/pulp-platform/register_interface.git
dependencies:
diff --git a/Bender.yml b/Bender.yml
index 9a0972b2..a6e10a67 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -19,6 +19,7 @@ dependencies:
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.33.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 }
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3 }
+ apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.3 }
obi: { git: "https://github.com/pulp-platform/obi.git", version: 0.1.2 }
export_include_dirs:
diff --git a/doc/src/frontends/descriptor_fe.rst b/doc/src/frontends/descriptor_fe.rst
index 09bdae0b..2d977d35 100644
--- a/doc/src/frontends/descriptor_fe.rst
+++ b/doc/src/frontends/descriptor_fe.rst
@@ -5,7 +5,7 @@ Frontend for Ariane (CVA6) ready for Linux use.
.. only:: html
-- `descriptor-based frontend <../regs/idma_desc64.html>`_
+- `descriptor-based frontend <../regs/idma_desc64_reg/index.html>`_
Morty docs:
diff --git a/doc/src/frontends/register_fe.rst b/doc/src/frontends/register_fe.rst
index 2d9a2d27..d0e55846 100644
--- a/doc/src/frontends/register_fe.rst
+++ b/doc/src/frontends/register_fe.rst
@@ -11,5 +11,6 @@ Currently supported are:
.. only:: html
-- `32bit 3D register frontend <../regs/idma_reg32_3d.html>`_
-- `64bit 2D register frontend <../regs/idma_reg64_2d.html>`_
+- `32bit 3D register frontend <../regs/idma_reg32_3d_reg/index.html>`_
+- `64bit 1D register frontend <../regs/idma_reg64_1d_reg/index.html>`_
+- `64bit 2D register frontend <../regs/idma_reg64_2d_reg/index.html>`_
diff --git a/idma.mk b/idma.mk
index 06d6c4b8..db2c73b3 100644
--- a/idma.mk
+++ b/idma.mk
@@ -10,12 +10,14 @@ CAT ?= cat
DOT ?= dot
GIT ?= git
MORTY ?= morty
+PEAKRDL ?= peakrdl
PRINTF ?= printf
PYTHON ?= python3
SPHINXBUILD ?= sphinx-build
VCS ?= vcs
VERILATOR ?= verilator
VLOGAN ?= vlogan
+SED ?= sed
# Shell
SHELL := /bin/bash
@@ -163,52 +165,65 @@ IDMA_FE_DIR := $(IDMA_ROOT)/src/frontend
IDMA_FE_REGS := desc64
IDMA_FE_REGS += $(IDMA_FE_IDS)
-# customize the HJSON
-$(IDMA_RTL_DIR)/idma_%.hjson: $(IDMA_GEN) $(IDMA_FE_DIR)/reg/tpl/idma_reg.hjson.tpl
- $(call idma_gen,reg_hjson,$(IDMA_FE_DIR)/reg/tpl/idma_reg.hjson.tpl,,,$*,$@)
-
-IDMA_REG_CUST_ALL += $(foreach Y,$(IDMA_FE_IDS),$(IDMA_RTL_DIR)/idma_$Y.hjson)
-
# ----
-$(IDMA_HTML_DIR)/regs/reg_html.css:
- mkdir -p $(IDMA_HTML_DIR)/regs
- cp $(IDMA_REG_DIR)/vendor/lowrisc_opentitan/util/reggen/reg_html.css $@
-
-$(IDMA_RTL_DIR)/idma_%_reg_pkg.sv $(IDMA_RTL_DIR)/idma_%_reg_top.sv: $(IDMA_REG_CUST_ALL)
- if [ -a "$(IDMA_FE_DIR)/$*/idma_$*.hjson" ]; then \
- $(PYTHON) $(IDMA_REGTOOL) $(IDMA_FE_DIR)/$*/idma_$*.hjson -t $(IDMA_RTL_DIR) -r; \
- else \
- $(PYTHON) $(IDMA_REGTOOL) $(IDMA_RTL_DIR)/idma_$*.hjson -t $(IDMA_RTL_DIR) -r; \
- fi
+regwidth = $(word 1,$(subst _, ,$1))
+dimension = $(word 2,$(subst _, ,$1))
+log2dimension = $(shell echo $$(( $$( echo "obase=2;$$(($(1)-1))" | bc | wc -c ) - 1 )) )
+
+$(IDMA_RTL_DIR)/idma_reg%d_reg_pkg.sv $(IDMA_RTL_DIR)/idma_reg%d_reg_top.sv $(IDMA_RTL_DIR)/idma_reg%d_addrmap_pkg.sv:
+ $(PEAKRDL) regblock $(IDMA_FE_DIR)/reg/idma_reg.rdl -o $(IDMA_RTL_DIR) \
+ --default-reset arst_n --cpuif apb4-flat \
+ --module-name idma_reg$*d_reg_top \
+ --package idma_reg$*d_reg_pkg \
+ -P SysAddrWidth=$(call regwidth,$*) \
+ -P NumDims=$(call dimension,$*) \
+ -P Log2NumDims=$(call log2dimension,$(call dimension,$*))
+ $(PEAKRDL) raw-header $(IDMA_FE_DIR)/reg/idma_reg.rdl \
+ --format svpkg \
+ -o $(IDMA_RTL_DIR)/idma_reg$*d_addrmap_pkg.sv \
+ --base_name idma_reg$*d \
+ --license_str="Copyright 2025 ETH Zurich and University of Bologna.\nSolderpad Hardware License, Version 0.51, see LICENSE for details.\nSPDX-License-Identifier: SHL-0.51" \
+ -P SysAddrWidth=$(call regwidth,$*) \
+ -P NumDims=$(call dimension,$*) \
+ -P Log2NumDims=$(call log2dimension,$(call dimension,$*))
+
+$(IDMA_RTL_DIR)/idma_desc64_reg_pkg.sv $(IDMA_RTL_DIR)/idma_desc64_reg_top.sv $(IDMA_RTL_DIR)/idma_desc64_addrmap_pkg.sv:
+ $(PEAKRDL) regblock $(IDMA_FE_DIR)/desc64/idma_desc64_reg.rdl -o $(IDMA_RTL_DIR) \
+ --default-reset arst_n --cpuif apb4-flat \
+ --module-name idma_desc64_reg_top \
+ --package idma_desc64_reg_pkg
+ $(PEAKRDL) raw-header $(IDMA_FE_DIR)/desc64/idma_desc64_reg.rdl \
+ --format svpkg \
+ -o $(IDMA_RTL_DIR)/idma_desc64_addrmap_pkg.sv \
+ --base_name idma_desc64 \
+ --license_str="Copyright 2025 ETH Zurich and University of Bologna.\nSolderpad Hardware License, Version 0.51, see LICENSE for details.\nSPDX-License-Identifier: SHL-0.51"
$(IDMA_RTL_DIR)/idma_%_top.sv: $(IDMA_GEN) $(IDMA_FE_DIR)/reg/tpl/idma_reg.sv.tpl
$(call idma_gen,reg_top,$(IDMA_FE_DIR)/reg/tpl/idma_reg.sv.tpl,,,$*,$@)
-$(IDMA_HTML_DIR)/regs/idma_%.html: $(IDMA_HTML_DIR)/regs/reg_html.css $(IDMA_REG_CUST_ALL)
- if [ -a "$(IDMA_FE_DIR)/$*/idma_$*.hjson" ]; then \
- $(PRINTF) "\n\n\n\n\n" > $@; \
- $(PYTHON) $(IDMA_REGTOOL) $(IDMA_FE_DIR)/$*/idma_$*.hjson -d >> $@; \
- $(PRINTF) "\n" >> $@; \
- else \
- $(PRINTF) "\n\n\n\n\n" > $@; \
- $(PYTHON) $(IDMA_REGTOOL) $(IDMA_RTL_DIR)/idma_$*.hjson -d >> $@; \
- $(PRINTF) "\n" >> $@; \
- fi
+$(IDMA_HTML_DIR)/regs/idma_reg%d_reg/index.html:
+ $(PEAKRDL) html $(IDMA_FE_DIR)/reg/idma_reg.rdl -o $(IDMA_HTML_DIR)/regs/idma_reg$*d_reg \
+ -P SysAddrWidth=$(call regwidth,$*) \
+ -P NumDims=$(call dimension,$*) \
+ -P Log2NumDims=$(call log2dimension,$(call dimension,$*))
+
+$(IDMA_HTML_DIR)/regs/idma_desc64_reg/index.html:
+ $(PEAKRDL) html $(IDMA_FE_DIR)/desc64/idma_desc64_reg.rdl -o $(IDMA_HTML_DIR)/regs/idma_desc64_reg
idma_reg_clean:
rm -rf $(IDMA_HTML_DIR)/regs
rm -f $(IDMA_RTL_DIR)/*_reg_top.sv
rm -f $(IDMA_RTL_DIR)/*_reg_pkg.sv
rm -f $(IDMA_RTL_DIR)/Bender.yml
- rm -f $(IDMA_RTL_DIR)/*.hjson
rm -f $(IDMA_REG_CUST_ALL)
# assemble the required files
IDMA_RTL_ALL += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_RTL_DIR)/idma_$Y_reg_pkg.sv)
IDMA_RTL_ALL += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_RTL_DIR)/idma_$Y_reg_top.sv)
+IDMA_RTL_ALL += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_RTL_DIR)/idma_$Y_addrmap_pkg.sv)
IDMA_RTL_ALL += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_RTL_DIR)/idma_$Y_top.sv)
-IDMA_RTL_DOC_ALL += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_HTML_DIR)/regs/idma_$Y.html)
+IDMA_RTL_DOC_ALL += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_HTML_DIR)/regs/idma_$Y_reg/index.html)
IDMA_HJSON_ALL += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_RTL_DIR)/idma_$Y.hjson)
@@ -244,6 +259,8 @@ $(IDMA_PICKLE_DIR)/%.sv: $(IDMA_PICKLE_DIR)/sources.json
else \
$(CAT) $(IDMA_CF_PKG) $@.pre > $@; \
fi
+ # Hack apb_pkg::prot_t to logic [2:0]
+ $(SED) -i 's/apb_pkg::prot_t/logic [2:0]/g' $@
rm -f $@.pre
$(IDMA_HTML_DIR)/%/index.html: $(IDMA_PICKLE_DIR)/%.sv
@@ -390,13 +407,15 @@ IDMA_VLT_PARAMS ?=
$(IDMA_VLT_DIR)/%_elab.log: $(IDMA_PICKLE_DIR)/sources.json
mkdir -p $(IDMA_VLT_DIR)
# We need a dedicated pickle here to set the defines
- $(MORTY) -f $< -i --top $(IDMA_VLT_TOP) -DVERILATOR --propagate_defines -o $(IDMA_VLT_DIR)/$(IDMA_VLT_TOP).sv.pre
+ $(MORTY) -f $< -i --top $(IDMA_VLT_TOP) -DVERILATOR -D ASSERTS_OFF --propagate_defines -o $(IDMA_VLT_DIR)/$(IDMA_VLT_TOP).sv.pre
# Hack cf_math_pkg in
if grep -q "package cf_math_pkg;" "$(IDMA_VLT_DIR)/$(IDMA_VLT_TOP).sv.pre"; then \
$(CAT) $(IDMA_VLT_DIR)/$(IDMA_VLT_TOP).sv.pre > $(IDMA_VLT_DIR)/$(IDMA_VLT_TOP).sv; \
else \
$(CAT) $(IDMA_CF_PKG) $(IDMA_VLT_DIR)/$(IDMA_VLT_TOP).sv.pre > $(IDMA_VLT_DIR)/$(IDMA_VLT_TOP).sv; \
fi
+ # Hack apb_pkg::prot_t to logic [2:0]
+ $(SED) -i 's/apb_pkg::prot_t/logic [2:0]/g' $(IDMA_VLT_DIR)/$(IDMA_VLT_TOP).sv
rm -f $(IDMA_VLT_DIR)/$(IDMA_VLT_TOP).sv.pre
cd $(IDMA_VLT_DIR); $(VERILATOR) $(IDMA_VLT_ARGS) $(IDMA_VLT_PARAMS) -Mdir obj_$* $(IDMA_VLT_TOP).sv --top-module $(IDMA_VLT_TOP) 2> $*_elab.log
@@ -441,7 +460,7 @@ idma_spinx_doc_clean:
IDMA_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:bslk/idma/idma-non-free.git
IDMA_NONFREE_DIR ?= $(IDMA_ROOT)/nonfree
-IDMA_NONFREE_COMMIT ?= deploy
+IDMA_NONFREE_COMMIT ?= fischeti/uv # TODO(fischeti): Revert back when merged
idma_nonfree_init:
git clone $(IDMA_NONFREE_REMOTE) $(IDMA_NONFREE_DIR)
@@ -481,7 +500,7 @@ idma_doc_all: idma_spinx_doc
idma_pickle_all: $(IDMA_PICKLE_ALL)
-idma_hw_all: $(IDMA_FULL_RTL) $(IDMA_INCLUDE_ALL) $(IDMA_FULL_TB) $(IDMA_HJSON_ALL) $(IDMA_WAVE_ALL)
+idma_hw_all: $(IDMA_FULL_RTL) $(IDMA_INCLUDE_ALL) $(IDMA_FULL_TB) $(IDMA_WAVE_ALL)
idma_sim_all: $(IDMA_VCS_DIR)/compile.sh $(IDMA_VSIM_DIR)/compile.tcl
diff --git a/pyproject.toml b/pyproject.toml
new file mode 100644
index 00000000..2744662f
--- /dev/null
+++ b/pyproject.toml
@@ -0,0 +1,26 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Authors:
+# - Tim Fischer
+
+[project]
+name = "idma"
+version = "0.1.0"
+requires-python = ">=3.11"
+dependencies = [
+ "GitPython",
+ "pre-commit",
+ "hjson",
+ "tabulate",
+ "pyyaml",
+ "mako",
+ "sphinx",
+ "sphinx-rtd-theme",
+ "recommonmark",
+ "sphinxcontrib-svg2pdfconverter",
+ "pylint",
+ "peakrdl>=1.5.0",
+ "peakrdl-rawheader>=0.2.2",
+]
diff --git a/requirements.txt b/requirements.txt
deleted file mode 100644
index 55c3f8e8..00000000
--- a/requirements.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-GitPython
-pre-commit
-hjson
-tabulate
-pyyaml
-mako
-sphinx
-sphinx-rtd-theme
-recommonmark
-sphinxcontrib-svg2pdfconverter
-pylint
diff --git a/src/frontend/desc64/idma_desc64.hjson b/src/frontend/desc64/idma_desc64.hjson
deleted file mode 100644
index 5f2a8cdc..00000000
--- a/src/frontend/desc64/idma_desc64.hjson
+++ /dev/null
@@ -1,66 +0,0 @@
-// Copyright 2023 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
-
-// Authors:
-// - Axel Vanoni
-
-{
- name: idma_desc64
- regwidth: 64
- clock_primary: clk_i
- bus_interfaces: [
- {
- protocol: reg_iface
- direction: device
- }
- ]
- registers: [
- {
- name: desc_addr
- desc:
- '''
- This register specifies the bus address at which the first transfer
- descriptor can be found. A write to this register starts the transfer.
- '''
- swaccess: wo
- hwaccess: hro
- hwqe: true
- resval: 0xFFFFFFFFFFFFFFFF
- fields: [
- {
- bits: "63:0"
- }
- ]
- }
- {
- name: status
- desc:
- '''
- This register contains status information for the DMA.
- '''
- swaccess: ro
- hwaccess: hwo
- resval: 0
- fields: [
- {
- name: "busy"
- desc:
- '''
- The DMA is busy
- '''
- bits: "0"
- }
- {
- name: "fifo_full"
- desc:
- '''
- If this bit is set, the buffers of the DMA are full. Any further submissions via the
- desc_addr register may overwrite previously submitted jobs or get lost.
- '''
- bits: "1"
- }
- ]
- }
- ]
-}
diff --git a/src/frontend/desc64/idma_desc64_reg.rdl b/src/frontend/desc64/idma_desc64_reg.rdl
new file mode 100644
index 00000000..219a94ff
--- /dev/null
+++ b/src/frontend/desc64/idma_desc64_reg.rdl
@@ -0,0 +1,45 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+// Authors:
+// - Axel Vanoni
+// - Michael Rogenmoser
+
+`ifndef IDMA_DESC64_REG_RDL
+`define IDMA_DESC64_REG_RDL
+
+addrmap idma_desc64_reg {
+ default regwidth = 64;
+
+ reg desc_addr {
+ name = "desc_addr";
+ desc = "This register specifies the bus address at which the first transfer
+ descriptor can be found. A write to this register starts the transfer.";
+ default sw = w;
+ default hw = r;
+ field {
+ swmod;
+ } desc_addr [63:0] = 0xFFFFFFFFFFFFFFFF;
+ };
+
+ reg status {
+ name = "status";
+ desc = "This register contains status information for the DMA.";
+ default sw = r;
+ default hw = w;
+ field {
+ desc = "The DMA is busy";
+ } busy [0:0] = 0;
+ field {
+ desc = "If this bit is set, the buffers of the DMA are full. Any further submissions via the
+ desc_addr register may overwrite previously submitted jobs or get lost.";
+ } fifo_full [1:1] = 0;
+
+ };
+
+ desc_addr desc_addr;
+ status status;
+};
+
+`endif // IDMA_DESC64_REG_RDL
diff --git a/src/frontend/desc64/idma_desc64_reg_wrapper.sv b/src/frontend/desc64/idma_desc64_reg_wrapper.sv
index 6bc59009..41a78ce4 100644
--- a/src/frontend/desc64/idma_desc64_reg_wrapper.sv
+++ b/src/frontend/desc64/idma_desc64_reg_wrapper.sv
@@ -10,75 +10,80 @@
/// This module implements backpressure via ready/valid handshakes
/// for the regbus registers and exposes it to the descriptor fifo
module idma_desc64_reg_wrapper
-import idma_desc64_reg_pkg::idma_desc64_reg2hw_t;
-import idma_desc64_reg_pkg::idma_desc64_hw2reg_t; #(
- parameter type reg_req_t = logic,
- parameter type reg_rsp_t = logic
+import idma_desc64_reg_pkg::idma_desc64_reg__out_t;
+import idma_desc64_reg_pkg::idma_desc64_reg__in_t; #(
+ parameter type apb_req_t = logic,
+ parameter type apb_rsp_t = logic
) (
- input logic clk_i ,
- input logic rst_ni ,
- input reg_req_t reg_req_i ,
- output reg_rsp_t reg_rsp_o ,
- output idma_desc64_reg2hw_t reg2hw_o ,
- input idma_desc64_hw2reg_t hw2reg_i ,
- input logic devmode_i ,
- output logic input_addr_valid_o,
- input logic input_addr_ready_i
+ input logic clk_i ,
+ input logic rst_ni ,
+ input apb_req_t apb_req_i ,
+ output apb_rsp_t apb_rsp_o ,
+ output idma_desc64_reg__out_t reg2hw_o ,
+ input idma_desc64_reg__in_t hw2reg_i ,
+ input logic devmode_i ,
+ output logic input_addr_valid_o,
+ input logic input_addr_ready_i
);
- import idma_desc64_reg_pkg::IDMA_DESC64_DESC_ADDR_OFFSET;
+ import idma_desc64_addrmap_pkg::IDMA_DESC64_REG_DESC_ADDR_BASE_ADDR;
+ import idma_desc64_addrmap_pkg::IDMA_DESC64_REG_STATUS_BASE_ADDR;
- reg_req_t request;
- reg_rsp_t response;
+ logic apb_psel, apb_psel_q, apb_penable, apb_pready;
logic input_addr_valid_q, input_addr_valid_d;
- idma_desc64_reg_top #(
- .reg_req_t (reg_req_t),
- .reg_rsp_t (reg_rsp_t)
- ) i_register_file_controller (
- .clk_i (clk_i) ,
- .rst_ni (rst_ni) ,
- .reg_req_i (request),
- .reg_rsp_o (response) ,
- .reg2hw (reg2hw_o) ,
- .hw2reg (hw2reg_i) ,
- .devmode_i (devmode_i)
+ idma_desc64_reg_top i_register_file_controller (
+ .clk (clk_i) ,
+ .arst_n (rst_ni) ,
+
+ .s_apb_psel (apb_psel) ,
+ .s_apb_penable (apb_penable) ,
+ .s_apb_pwrite (apb_req_i.pwrite) ,
+ .s_apb_pprot (apb_req_i.pprot) ,
+ .s_apb_paddr (
+ apb_req_i.paddr[idma_desc64_reg_pkg::IDMA_DESC64_REG_TOP_MIN_ADDR_WIDTH-1:0]) ,
+ .s_apb_pwdata (apb_req_i.pwdata) ,
+ .s_apb_pstrb (apb_req_i.pstrb) ,
+ .s_apb_pready (apb_pready) ,
+ .s_apb_prdata (apb_rsp_o.prdata) ,
+ .s_apb_pslverr (apb_rsp_o.pslverr) ,
+
+ .hwif_out (reg2hw_o) ,
+ .hwif_in (hw2reg_i)
);
- assign request.addr = reg_req_i.addr;
- assign request.write = reg_req_i.write;
- assign request.wdata = reg_req_i.wdata;
- assign request.wstrb = reg_req_i.wstrb;
- assign reg_rsp_o.rdata = response.rdata;
- assign reg_rsp_o.error = response.error;
+ assign apb_penable = apb_psel_q & apb_req_i.penable;
always_comb begin
- if (reg_req_i.addr == IDMA_DESC64_DESC_ADDR_OFFSET) begin
- request.valid = reg_req_i.valid && input_addr_ready_i;
+ if (apb_req_i.paddr == IDMA_DESC64_REG_DESC_ADDR_BASE_ADDR) begin
+ apb_psel = apb_req_i.psel & input_addr_ready_i;
end else begin
- request.valid = reg_req_i.valid;
+ apb_psel = apb_req_i.psel;
end
end
+ assign input_addr_valid_o = input_addr_valid_q;
+
always_comb begin
// only take into account the fifo if a write is going to it
- if (reg_req_i.addr == IDMA_DESC64_DESC_ADDR_OFFSET) begin
- reg_rsp_o.ready = response.ready && input_addr_ready_i;
- input_addr_valid_o = reg2hw_o.desc_addr.qe || input_addr_valid_q;
+ if (apb_req_i.paddr == IDMA_DESC64_REG_DESC_ADDR_BASE_ADDR) begin
+ apb_rsp_o.pready = apb_pready & (input_addr_ready_i | ~input_addr_valid_q);
end else begin
- reg_rsp_o.ready = response.ready;
- input_addr_valid_o = '0;
+ apb_rsp_o.pready = apb_pready;
end
end
always_comb begin
input_addr_valid_d = input_addr_valid_q;
- if (reg2hw_o.desc_addr.qe && !input_addr_ready_i) begin
- input_addr_valid_d = 1'b1;
- end else if (input_addr_ready_i) begin
+ if (input_addr_ready_i) begin
input_addr_valid_d = '0;
end
+ if (reg2hw_o.desc_addr.desc_addr.swmod) begin
+ input_addr_valid_d = 1'b1;
+ end
end
- `FF(input_addr_valid_q, input_addr_valid_d, '0)
+
+ `FF(input_addr_valid_q, input_addr_valid_d, '0);
+ `FF(apb_psel_q, apb_psel, '0);
endmodule
diff --git a/src/frontend/desc64/idma_desc64_synth.sv b/src/frontend/desc64/idma_desc64_synth.sv
index 842aff06..957f7a5e 100644
--- a/src/frontend/desc64/idma_desc64_synth.sv
+++ b/src/frontend/desc64/idma_desc64_synth.sv
@@ -16,8 +16,8 @@ module idma_desc64_synth #(
parameter type axi_req_t = idma_desc64_synth_pkg::axi_req_t,
parameter type axi_ar_chan_t = idma_desc64_synth_pkg::axi_ar_chan_t,
parameter type axi_r_chan_t = idma_desc64_synth_pkg::axi_r_chan_t,
- parameter type reg_rsp_t = idma_desc64_synth_pkg::reg_rsp_t,
- parameter type reg_req_t = idma_desc64_synth_pkg::reg_req_t,
+ parameter type apb_rsp_t = idma_desc64_synth_pkg::apb_resp_t,
+ parameter type apb_req_t = idma_desc64_synth_pkg::apb_req_t,
parameter int unsigned InputFifoDepth = idma_desc64_synth_pkg::InputFifoDepth,
parameter int unsigned PendingFifoDepth = idma_desc64_synth_pkg::PendingFifoDepth
)(
@@ -27,8 +27,8 @@ module idma_desc64_synth #(
input axi_rsp_t master_rsp_i ,
input logic [AxiIdWidth-1:0] axi_ar_id_i ,
input logic [AxiIdWidth-1:0] axi_aw_id_i ,
- input reg_req_t slave_req_i ,
- output reg_rsp_t slave_rsp_o ,
+ input apb_req_t slave_req_i ,
+ output apb_rsp_t slave_rsp_o ,
output idma_req_t idma_req_o ,
output logic idma_req_valid_o,
input logic idma_req_ready_i,
@@ -49,8 +49,8 @@ module idma_desc64_synth #(
.axi_rsp_t ( axi_rsp_t ),
.axi_ar_chan_t ( axi_ar_chan_t ),
.axi_r_chan_t ( axi_r_chan_t ),
- .reg_req_t ( reg_req_t ),
- .reg_rsp_t ( reg_rsp_t ),
+ .apb_req_t ( apb_req_t ),
+ .apb_rsp_t ( apb_rsp_t ),
.InputFifoDepth ( InputFifoDepth ),
.PendingFifoDepth ( PendingFifoDepth )
) i_dma_desc64 (
diff --git a/src/frontend/desc64/idma_desc64_synth_pkg.sv b/src/frontend/desc64/idma_desc64_synth_pkg.sv
index 0ec1cf6b..aeff7bd3 100644
--- a/src/frontend/desc64/idma_desc64_synth_pkg.sv
+++ b/src/frontend/desc64/idma_desc64_synth_pkg.sv
@@ -8,7 +8,7 @@
/// synth package
package idma_desc64_synth_pkg;
- `include "register_interface/typedef.svh"
+ `include "apb/typedef.svh"
`include "axi/typedef.svh"
`include "idma/typedef.svh"
@@ -30,7 +30,7 @@ package idma_desc64_synth_pkg;
typedef logic [UserWidth-1:0] user_t;
typedef logic [TFLenWidth-1:0] tf_len_t;
- `REG_BUS_TYPEDEF_ALL(reg, addr_t, data_t, strb_t)
+ `APB_TYPEDEF_ALL(apb, addr_t, data_t, strb_t)
`AXI_TYPEDEF_ALL_CT(axi, axi_req_t, axi_rsp_t, addr_t, id_t, data_t, strb_t, user_t)
`IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, id_t, addr_t, tf_len_t)
`IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, addr_t)
diff --git a/src/frontend/desc64/idma_desc64_top.sv b/src/frontend/desc64/idma_desc64_top.sv
index b9fcea0b..995b1382 100644
--- a/src/frontend/desc64/idma_desc64_top.sv
+++ b/src/frontend/desc64/idma_desc64_top.sv
@@ -20,10 +20,10 @@ module idma_desc64_top #(
parameter type idma_req_t = logic,
/// burst response type. See the documentation of the idma backend for details
parameter type idma_rsp_t = logic,
- /// regbus interface types. Use the REG_BUS_TYPEDEF macros to define the types
+ /// regbus interface types. Use the APB_TYPEDEF macros to define the types
/// or see the idma backend documentation for more details
- parameter type reg_rsp_t = logic,
- parameter type reg_req_t = logic,
+ parameter type apb_rsp_t = logic,
+ parameter type apb_req_t = logic,
/// AXI interface types used for fetching descriptors.
/// Use the AXI_TYPEDEF_ALL macros to define the types
parameter type axi_rsp_t = logic,
@@ -62,9 +62,9 @@ module idma_desc64_top #(
/// exposes whether the DMA is busy on bit 0 and whether FIFOs are full
/// on bit 1.
/// master request
- input reg_req_t slave_req_i ,
+ input apb_req_t slave_req_i ,
/// master response
- output reg_rsp_t slave_rsp_o ,
+ output apb_rsp_t slave_rsp_o ,
/// backend interface
/// burst request submission
@@ -164,8 +164,8 @@ logic input_addr_valid, input_addr_ready;
logic do_irq_out;
-idma_desc64_reg_pkg::idma_desc64_reg2hw_t reg2hw;
-idma_desc64_reg_pkg::idma_desc64_hw2reg_t hw2reg;
+idma_desc64_reg_pkg::idma_desc64_reg__out_t reg2hw;
+idma_desc64_reg_pkg::idma_desc64_reg__in_t hw2reg;
addr_t aw_addr;
@@ -234,29 +234,27 @@ end else begin : gen_aw_w_chan
end
end
-assign hw2reg.status.busy.d = queued_addr_valid ||
- next_wb_addr_valid ||
- idma_req_valid_o ||
- master_req_o.b_ready ||
- master_req_o.aw_valid ||
- w_counter_q > 0 ||
- idma_busy_i ||
- ar_busy;
+assign hw2reg.status.busy.next = queued_addr_valid ||
+ next_wb_addr_valid ||
+ idma_req_valid_o ||
+ master_req_o.b_ready ||
+ master_req_o.aw_valid ||
+ w_counter_q > 0 ||
+ idma_busy_i ||
+ ar_busy;
-assign hw2reg.status.busy.de = 1'b1;
-assign hw2reg.status.fifo_full.d = !input_addr_ready;
-assign hw2reg.status.fifo_full.de = 1'b1;
+assign hw2reg.status.fifo_full.next = !input_addr_ready;
-assign input_addr = reg2hw.desc_addr.q;
+assign input_addr = reg2hw.desc_addr.desc_addr.value;
idma_desc64_reg_wrapper #(
- .reg_req_t(reg_req_t),
- .reg_rsp_t(reg_rsp_t)
+ .apb_req_t(apb_req_t),
+ .apb_rsp_t(apb_rsp_t)
) i_reg_wrapper (
.clk_i,
.rst_ni,
- .reg_req_i (slave_req_i),
- .reg_rsp_o (slave_rsp_o),
+ .apb_req_i (slave_req_i),
+ .apb_rsp_o (slave_rsp_o),
.reg2hw_o (reg2hw),
.hw2reg_i (hw2reg),
.devmode_i (1'b0),
diff --git a/src/frontend/reg/idma_reg.rdl b/src/frontend/reg/idma_reg.rdl
new file mode 100644
index 00000000..a46b73c1
--- /dev/null
+++ b/src/frontend/reg/idma_reg.rdl
@@ -0,0 +1,165 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+// Authors:
+// - Michael Rogenmoser
+// - Thomas Benz
+
+`ifndef IDMA_REG_REG_RDL
+`define IDMA_REG_REG_RDL
+
+addrmap idma_reg #(
+ longint unsigned SysAddrWidth = 32, // Address width
+ longint unsigned NumDims = 2, // Number of dimensions available
+ longint unsigned Log2NumDims = 0, // Log2 of NumDims
+ longint unsigned NumProtBits = 3 // Number of protocol bits
+) {
+ default regwidth = 32;
+
+ reg conf {
+ regwidth = 32;
+ name = "conf";
+ desc = "Configuration Register for DMA settings";
+ default sw = rw;
+ default hw = r;
+ field {
+ desc = "Decouple R-AW";
+ } decouple_aw [0:0] = 0;
+ field {
+ desc = "Decouple R-W";
+ } decouple_rw [1:1] = 0;
+ field {
+ desc = "Reduce maximal source burst length";
+ } src_reduce_len [2:2] = 0;
+ field {
+ desc = "Reduce maximal destination burst length";
+ } dst_reduce_len [3:3] = 0;
+ field {
+ desc = "Maximal logarithmic source burst length";
+ } src_max_llen [6:4] = 0;
+ field {
+ desc = "Maximal logarithmic destination burst length";
+ } dst_max_llen [9:7] = 0;
+ field {
+ desc = "ND-extension enabled";
+ } enable_nd [10+Log2NumDims:10] = 0;
+ field {
+ desc = "Selection of the source protocol";
+ } src_protocol [NumProtBits+11+Log2NumDims-1:11+Log2NumDims] = 0;
+ field {
+ desc = "Selection of the destination protocol";
+ } dst_protocol [2*NumProtBits+11+Log2NumDims-1:11+Log2NumDims+NumProtBits] = 0;
+ };
+
+ reg status {
+ regwidth = 32;
+ name = "status";
+ desc = "DMA Status";
+ default sw = r;
+ default hw = w;
+ field {
+ desc = "DMA busy";
+ } busy [9:0] = 0;
+ };
+
+ reg next_id {
+ regwidth = 32;
+ name = "next_id";
+ desc = "Next ID, launches transfer, returns 0 if transfer not set up properly.";
+ default sw = r;
+ default hw = rw;
+ field {
+ desc = "Next ID, launches transfer, returns 0 if transfer not set up properly.";
+ } next_id [31:0] = 0;
+ };
+
+ reg done_id {
+ regwidth = 32;
+ name = "done_id";
+ desc = "Get ID of finished transactions.";
+ default sw = r;
+ default hw = w;
+ field {
+ desc = "Get ID of finished transactions.";
+ } done_id [31:0] = 0;
+ };
+
+ reg dst_addr {
+ name = "dst_addr";
+ desc = "Destination address";
+ default sw = rw;
+ default hw = r;
+ field {
+ desc = "Destination address";
+ } dst_addr [31:0] = 0;
+ };
+
+ reg src_addr {
+ name = "src_addr";
+ desc = "Source address";
+ default sw = rw;
+ default hw = r;
+ field {
+ desc = "Source address";
+ } src_addr [31:0] = 0;
+ };
+
+ reg length {
+ name = "length";
+ desc = "Transfer length in bytes";
+ default sw = rw;
+ default hw = r;
+ field {
+ desc = "Transfer length in bytes";
+ } length [31:0] = 0;
+ };
+
+ reg dst_stride {
+ name = "dst_stride";
+ desc = "Destination stride";
+ default sw = rw;
+ default hw = r;
+ field {
+ desc = "Destination stride";
+ } dst_stride [31:0] = 0;
+ };
+
+ reg src_stride {
+ name = "src_stride";
+ desc = "Source stride";
+ default sw = rw;
+ default hw = r;
+ field {
+ desc = "Source stride";
+ } src_stride [31:0] = 0;
+ };
+
+ reg reps {
+ name = "reps";
+ desc = "Number of repetitions";
+ default sw = rw;
+ default hw = r;
+ field {
+ desc = "Number of repetitions";
+ } reps [31:0] = 0;
+ };
+
+ regfile dim {
+ dst_stride dst_stride[SysAddrWidth/32];
+ src_stride src_stride[SysAddrWidth/32];
+ reps reps[SysAddrWidth/32];
+ ispresent = NumDims > 1;
+ };
+
+ conf conf;
+ external status status[16];
+ external next_id next_id[16];
+ external done_id done_id[16];
+ dst_addr dst_addr[SysAddrWidth/32] @ 0xD0;
+ src_addr src_addr[SysAddrWidth/32];
+ length length[SysAddrWidth/32];
+ dim dim[NumDims-1 | NumDims == 1];
+};
+
+`endif // IDMA_REG_RDL
diff --git a/src/frontend/reg/tpl/idma_reg.hjson.tpl b/src/frontend/reg/tpl/idma_reg.hjson.tpl
deleted file mode 100644
index 5a5a4c33..00000000
--- a/src/frontend/reg/tpl/idma_reg.hjson.tpl
+++ /dev/null
@@ -1,120 +0,0 @@
-// Copyright 2023 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
-
-// Authors:
-// - Michael Rogenmoser
-// - Thomas Benz
-
-{
- name: "idma_${identifier}",
- clock_primary: "clk_i",
- reset_primary: "rst_ni",
- bus_interfaces: [
- { protocol: "reg_iface",
- direction: "device"
- }
- ],
- regwidth: "32",
- param_list: [
-${params}
- ],
- registers: [
- { name: "conf",
- desc: "Configuration Register for DMA settings",
- swaccess: "rw",
- hwaccess: "hro",
- fields: [
- { bits: "0",
- name: "decouple_aw",
- desc: "Decouple R-AW"
- },
- { bits: "1",
- name: "decouple_rw",
- desc: "Decouple R-W"
- },
- { bits: "2",
- name: "src_reduce_len",
- desc: "Reduce maximal source burst length"
- },
- { bits: "3",
- name: "dst_reduce_len",
- desc: "Reduce maximal destination burst length"
- }
- { bits: "6:4",
- name: "src_max_llen",
- desc: "Maximal logarithmic source burst length"
- }
- { bits: "9:7",
- name: "dst_max_llen",
- desc: "Maximal logarithmic destination burst length"
- }
- { bits: "${dim_range}",
- name: "enable_nd",
- desc: "ND-extension enabled"
- }
- { bits: "${src_prot_range}",
- name: "src_protocol",
- desc: "Selection of the source protocol"
- }
- { bits: "${dst_prot_range}",
- name: "dst_protocol",
- desc: "Selection of the destination protocol"
- }
- ]
- },
- { multireg:
- { name: "status",
- desc: "DMA Status",
- swaccess: "ro",
- hwaccess: "hwo",
- count: "16",
- cname: "status",
- hwext: "true",
- compact: "false",
- fields: [
- { bits: "9:0",
- name: "busy",
- desc: "DMA busy"
- }
- ]
- }
- },
- { multireg:
- { name: "next_id",
- desc: "Next ID, launches transfer, returns 0 if transfer not set up properly.",
- swaccess: "ro",
- hwaccess: "hrw",
- hwre: "true",
- count: "16",
- cname: "next_id",
- hwext: "true",
- compact: "false",
- fields: [
- { bits: "31:0",
- name: "next_id",
- desc: "Next ID, launches transfer, returns 0 if transfer not set up properly."
- }
- ]
- }
- },
- { multireg:
- { name: "done_id",
- desc: "Get ID of finished transactions.",
- swaccess: "ro",
- hwaccess: "hwo",
- count: "16",
- cname: "done_id",
- hwext: "true",
- compact: "false",
- fields: [
- { bits: "31:0",
- name: "done_id",
- desc: "Get ID of finished transactions."
- }
- ]
- }
- },
-${registers}
- ]
-}
diff --git a/src/frontend/reg/tpl/idma_reg.sv.tpl b/src/frontend/reg/tpl/idma_reg.sv.tpl
index 27de593f..3055b59d 100644
--- a/src/frontend/reg/tpl/idma_reg.sv.tpl
+++ b/src/frontend/reg/tpl/idma_reg.sv.tpl
@@ -6,6 +6,8 @@
// - Michael Rogenmoser
// - Thomas Benz
+`include "apb/typedef.svh"
+
/// Description: Register-based front-end for iDMA
module idma_${identifier} #(
/// Number of configuration register ports
@@ -48,9 +50,14 @@ module idma_${identifier} #(
/// needs to be adapted too.
localparam int unsigned MaxNumStreams = 32'd16;
+ `APB_TYPEDEF_ALL(apb, logic[31:0], logic[31:0], logic[3:0])
+ apb_req_t [NumRegs-1:0] apb_req;
+ apb_resp_t [NumRegs-1:0] apb_rsp;
+
+
// register connections
- idma_${identifier}_reg_pkg::idma_${identifier}_reg2hw_t [NumRegs-1:0] dma_reg2hw;
- idma_${identifier}_reg_pkg::idma_${identifier}_hw2reg_t [NumRegs-1:0] dma_hw2reg;
+ idma_${identifier}_reg_pkg::idma_reg__out_t dma_reg2hw [NumRegs-1:0];
+ idma_${identifier}_reg_pkg::idma_reg__in_t dma_hw2reg [NumRegs-1:0];
// arbitration output
dma_req_t [NumRegs-1:0] arb_dma_req;
@@ -64,7 +71,7 @@ module idma_${identifier} #(
stream_idx_o = '0;
for (int r = 0; r < NumRegs; r++) begin
for (int c = 0; c < NumStreams; c++) begin
- if (dma_reg2hw[r].next_id[c].re) begin
+ if (dma_reg2hw[r].next_id[c].req && !dma_reg2hw[r].next_id[c].req_is_wr) begin
stream_idx_o = c;
end
end
@@ -74,17 +81,38 @@ module idma_${identifier} #(
// generate the registers
for (genvar i = 0; i < NumRegs; i++) begin : gen_core_regs
- idma_${identifier}_reg_top #(
- .reg_req_t ( reg_req_t ),
- .reg_rsp_t ( reg_rsp_t )
- ) i_idma_${identifier}_reg_top (
+
+ reg_to_apb #(
+ .reg_req_t ( reg_req_t ),
+ .reg_rsp_t ( reg_rsp_t ),
+ .apb_req_t ( apb_req_t ),
+ .apb_rsp_t ( apb_resp_t )
+ ) chs_regs_reg_to_apb (
.clk_i,
.rst_ni,
.reg_req_i ( dma_ctrl_req_i [i] ),
.reg_rsp_o ( dma_ctrl_rsp [i] ),
- .reg2hw ( dma_reg2hw [i] ),
- .hw2reg ( dma_hw2reg [i] ),
- .devmode_i ( 1'b1 )
+ .apb_req_o ( apb_req [i] ),
+ .apb_rsp_i ( apb_rsp [i] )
+ );
+
+ idma_${identifier}_reg_top i_idma_${identifier}_reg_top (
+ .clk ( clk_i ),
+ .arst_n ( rst_ni ),
+
+ .s_apb_psel (apb_req[i].psel),
+ .s_apb_penable (apb_req[i].penable),
+ .s_apb_pwrite (apb_req[i].pwrite),
+ .s_apb_pprot (apb_req[i].pprot),
+ .s_apb_paddr (apb_req[i].paddr),
+ .s_apb_pwdata (apb_req[i].pwdata),
+ .s_apb_pstrb (apb_req[i].pstrb),
+ .s_apb_pready (apb_rsp[i].pready),
+ .s_apb_prdata (apb_rsp[i].prdata),
+ .s_apb_pslverr (apb_rsp[i].pslverr),
+
+ .hwif_out ( dma_reg2hw [i] ),
+ .hwif_in ( dma_hw2reg [i] )
);
logic read_happens;
@@ -100,7 +128,7 @@ module idma_${identifier} #(
always_comb begin : proc_launch
read_happens = 1'b0;
for (int c = 0; c < NumStreams; c++) begin
- read_happens |= dma_reg2hw[i].next_id[c].re;
+ read_happens |= dma_reg2hw[i].next_id[c].req & ~dma_reg2hw[i].next_id[c].req_is_wr;
end
arb_valid[i] = read_happens;
end
@@ -112,18 +140,18 @@ module idma_${identifier} #(
// address and length
% if bit_width == '32':
- arb_dma_req[i]${sep}length = dma_reg2hw[i].length_low.q;
- arb_dma_req[i]${sep}src_addr = dma_reg2hw[i].src_addr_low.q;
- arb_dma_req[i]${sep}dst_addr = dma_reg2hw[i].dst_addr_low.q;
+ arb_dma_req[i]${sep}length = dma_reg2hw[i].length[0].length.value;
+ arb_dma_req[i]${sep}src_addr = dma_reg2hw[i].src_addr[0].src_addr.value;
+ arb_dma_req[i]${sep}dst_addr = dma_reg2hw[i].dst_addr[0].dst_addr.value;
% else:
- arb_dma_req[i]${sep}length = {dma_reg2hw[i].length_high.q, dma_reg2hw[i].length_low.q};
- arb_dma_req[i]${sep}src_addr = {dma_reg2hw[i].src_addr_high.q, dma_reg2hw[i].src_addr_low.q};
- arb_dma_req[i]${sep}dst_addr = {dma_reg2hw[i].dst_addr_high.q, dma_reg2hw[i].dst_addr_low.q};
+ arb_dma_req[i]${sep}length = {dma_reg2hw[i].length[1].length.value, dma_reg2hw[i].length[0].length.value};
+ arb_dma_req[i]${sep}src_addr = {dma_reg2hw[i].src_addr[1].src_addr.value, dma_reg2hw[i].src_addr[0].src_addr.value};
+ arb_dma_req[i]${sep}dst_addr = {dma_reg2hw[i].dst_addr[1].dst_addr.value, dma_reg2hw[i].dst_addr[0].dst_addr.value};
% endif
// Protocols
- arb_dma_req[i]${sep}opt.src_protocol = idma_pkg::protocol_e'(dma_reg2hw[i].conf.src_protocol);
- arb_dma_req[i]${sep}opt.dst_protocol = idma_pkg::protocol_e'(dma_reg2hw[i].conf.dst_protocol);
+ arb_dma_req[i]${sep}opt.src_protocol = idma_pkg::protocol_e'(dma_reg2hw[i].conf.src_protocol.value);
+ arb_dma_req[i]${sep}opt.dst_protocol = idma_pkg::protocol_e'(dma_reg2hw[i].conf.dst_protocol.value);
// Current backend only supports incremental burst
arb_dma_req[i]${sep}opt.src.burst = axi_pkg::BURST_INCR;
@@ -133,38 +161,38 @@ module idma_${identifier} #(
arb_dma_req[i]${sep}opt.dst.cache = axi_pkg::CACHE_MODIFIABLE;
// Backend options
- arb_dma_req[i]${sep}opt.beo.decouple_aw = dma_reg2hw[i].conf.decouple_aw.q;
- arb_dma_req[i]${sep}opt.beo.decouple_rw = dma_reg2hw[i].conf.decouple_rw.q;
- arb_dma_req[i]${sep}opt.beo.src_max_llen = dma_reg2hw[i].conf.src_max_llen.q;
- arb_dma_req[i]${sep}opt.beo.dst_max_llen = dma_reg2hw[i].conf.dst_max_llen.q;
- arb_dma_req[i]${sep}opt.beo.src_reduce_len = dma_reg2hw[i].conf.src_reduce_len.q;
- arb_dma_req[i]${sep}opt.beo.dst_reduce_len = dma_reg2hw[i].conf.dst_reduce_len.q;
+ arb_dma_req[i]${sep}opt.beo.decouple_aw = dma_reg2hw[i].conf.decouple_aw.value;
+ arb_dma_req[i]${sep}opt.beo.decouple_rw = dma_reg2hw[i].conf.decouple_rw.value;
+ arb_dma_req[i]${sep}opt.beo.src_max_llen = dma_reg2hw[i].conf.src_max_llen.value;
+ arb_dma_req[i]${sep}opt.beo.dst_max_llen = dma_reg2hw[i].conf.dst_max_llen.value;
+ arb_dma_req[i]${sep}opt.beo.src_reduce_len = dma_reg2hw[i].conf.src_reduce_len.value;
+ arb_dma_req[i]${sep}opt.beo.dst_reduce_len = dma_reg2hw[i].conf.dst_reduce_len.value;
% if num_dim != 1:
// ND connections
% for nd in range(0, num_dim-1):
% if bit_width == '32':
- arb_dma_req[i].d_req[${nd}].reps = dma_reg2hw[i].reps_${nd+2}_low.q;
- arb_dma_req[i].d_req[${nd}].src_strides = dma_reg2hw[i].src_stride_${nd+2}_low.q;
- arb_dma_req[i].d_req[${nd}].dst_strides = dma_reg2hw[i].dst_stride_${nd+2}_low.q;
+ arb_dma_req[i].d_req[${nd}].reps = dma_reg2hw[i].dim[${nd}].reps[0].reps.value;
+ arb_dma_req[i].d_req[${nd}].src_strides = dma_reg2hw[i].dim[${nd}].src_stride[0].src_stride.value;
+ arb_dma_req[i].d_req[${nd}].dst_strides = dma_reg2hw[i].dim[${nd}].dst_stride[0].dst_stride.value;
% else:
- arb_dma_req[i].d_req[${nd}].reps = {dma_reg2hw[i].reps_${nd+2}_high.q,
- dma_reg2hw[i].reps_${nd+2}_low.q };
- arb_dma_req[i].d_req[${nd}].src_strides = {dma_reg2hw[i].src_stride_${nd+2}_high.q,
- dma_reg2hw[i].src_stride_${nd+2}_low.q};
- arb_dma_req[i].d_req[${nd}].dst_strides = {dma_reg2hw[i].dst_stride_${nd+2}_high.q,
- dma_reg2hw[i].dst_stride_${nd+2}_low.q};
+ arb_dma_req[i].d_req[${nd}].reps = {dma_reg2hw[i].dim[${nd}].reps[1].reps.value,
+ dma_reg2hw[i].dim[${nd}].reps[0].reps.value };
+ arb_dma_req[i].d_req[${nd}].src_strides = {dma_reg2hw[i].dim[${nd}].src_stride[1].src_stride.value,
+ dma_reg2hw[i].dim[${nd}].src_stride[0].src_stride.value};
+ arb_dma_req[i].d_req[${nd}].dst_strides = {dma_reg2hw[i].dim[${nd}].dst_stride[1].dst_stride.value,
+ dma_reg2hw[i].dim[${nd}].dst_stride[0].dst_stride.value};
% endif
% endfor
// Disable higher dimensions
- if ( dma_reg2hw[i].conf.enable_nd.q == 0) begin
+ if ( dma_reg2hw[i].conf.enable_nd.value == 0) begin
% for nd in range(0, num_dim-1):
arb_dma_req[i].d_req[${nd}].reps = ${"'0" if nd != num_dim-2 else "'d1"};
% endfor
end
% for nd in range(1, num_dim-1):
- else if ( dma_reg2hw[i].conf.enable_nd.q == ${nd}) begin
+ else if ( dma_reg2hw[i].conf.enable_nd.value == ${nd}) begin
% for snd in range(nd, num_dim-1):
arb_dma_req[i].d_req[${snd}].reps = 'd1;
% endfor
@@ -175,16 +203,22 @@ module idma_${identifier} #(
// observational registers
for (genvar c = 0; c < NumStreams; c++) begin : gen_hw2reg_connections
- assign dma_hw2reg[i].status[c] = {midend_busy_i[c], busy_i[c]};
- assign dma_hw2reg[i].next_id[c] = next_id_i;
- assign dma_hw2reg[i].done_id[c] = done_id_i[c];
+ assign dma_hw2reg[i].status[c].rd_data.busy = {midend_busy_i[c], busy_i[c]};
+ assign dma_hw2reg[i].status[c].rd_ack = 1'b1;
+ assign dma_hw2reg[i].next_id[c].rd_data.next_id = next_id_i;
+ assign dma_hw2reg[i].next_id[c].rd_ack = 1'b1;
+ assign dma_hw2reg[i].done_id[c].rd_data.done_id = done_id_i[c];
+ assign dma_hw2reg[i].done_id[c].rd_ack = 1'b1;
end
// tie-off unused channels
for (genvar c = NumStreams; c < MaxNumStreams; c++) begin : gen_hw2reg_unused
- assign dma_hw2reg[i].status[c] = '0;
- assign dma_hw2reg[i].next_id[c] = '0;
- assign dma_hw2reg[i].done_id[c] = '0;
+ assign dma_hw2reg[i].status[c].rd_data = '0;
+ assign dma_hw2reg[i].status[c].rd_ack = '0;
+ assign dma_hw2reg[i].next_id[c].rd_data.next_id = '0;
+ assign dma_hw2reg[i].next_id[c].rd_ack = '0;
+ assign dma_hw2reg[i].done_id[c].rd_data.done_id = '0;
+ assign dma_hw2reg[i].done_id[c].rd_ack = '0;
end
end
diff --git a/test/frontend/tb_idma_desc64_bench.sv b/test/frontend/tb_idma_desc64_bench.sv
index 872a70ac..fbdc53cf 100644
--- a/test/frontend/tb_idma_desc64_bench.sv
+++ b/test/frontend/tb_idma_desc64_bench.sv
@@ -5,8 +5,8 @@
// Authors:
// - Axel Vanoni
-`include "register_interface/typedef.svh"
-`include "register_interface/assign.svh"
+`include "apb/typedef.svh"
+`include "apb/assign.svh"
`include "idma/tracer.svh"
`include "idma/typedef.svh"
`include "axi/typedef.svh"
@@ -16,11 +16,11 @@
/// Benchmarking TB for the descriptor-based frontend
module tb_idma_desc64_bench
- import idma_desc64_reg_pkg::IDMA_DESC64_DESC_ADDR_OFFSET;
- import idma_desc64_reg_pkg::IDMA_DESC64_STATUS_OFFSET;
+ import idma_desc64_addrmap_pkg::IDMA_DESC64_REG_DESC_ADDR_BASE_ADDR;
+ import idma_desc64_addrmap_pkg::IDMA_DESC64_REG_STATUS_BASE_ADDR;
import rand_verif_pkg::rand_wait;
import axi_pkg::*;
- import reg_test::reg_driver; #(
+ import apb_test::apb_driver; #(
parameter integer NumberOfTests = 100,
parameter integer SimulationTimeoutCycles = 1000000,
parameter integer ChainedDescriptors = 10,
@@ -70,7 +70,7 @@ module tb_idma_desc64_bench
typedef axi_test::axi_w_beat #(.DW(64), .UW(1)) w_beat_t;
typedef axi_test::axi_b_beat #(.IW(3), .UW(1)) b_beat_t;
- `REG_BUS_TYPEDEF_ALL(reg, /* addr */ addr_t, /* data */ logic [63:0], /* strobe */ logic [7:0])
+ `APB_TYPEDEF_ALL(apb, /* addr */ addr_t, /* data */ logic [63:0], /* strobe */ logic [7:0])
`AXI_TYPEDEF_ALL(axi, /* addr */ addr_t, /* id */ axi_id_t, /* data */ logic [63:0], /* strb */ logic [7:0], /* user */ logic [0:0])
`AXI_TYPEDEF_ALL(mem_axi, /* addr */ addr_t, /* id */ mem_axi_id_t, /* data */ logic [63:0], /* strb */ logic [7:0], /* user */ logic [0:0])
@@ -158,17 +158,17 @@ module tb_idma_desc64_bench
);
// dut signals and module
- REG_BUS #(
+ APB_DV #(
.ADDR_WIDTH(64),
.DATA_WIDTH(64)
- ) i_reg_iface_bus (clk);
+ ) i_apb_iface_bus (clk);
- reg_driver #(
- .AW(64),
- .DW(64),
+ apb_driver #(
+ .ADDR_WIDTH(64),
+ .DATA_WIDTH(64),
.TA(APPL_DELAY),
.TT(ACQ_DELAY)
- ) i_reg_iface_driver = new (i_reg_iface_bus);
+ ) i_apb_driver = new (i_apb_iface_bus);
axi_resp_t dma_fe_master_response;
axi_req_t dma_fe_master_request;
@@ -206,8 +206,8 @@ module tb_idma_desc64_bench
.TT(ACQ_DELAY)
) i_axi_iface_driver = new (i_axi_iface_bus);
- reg_rsp_t dma_slave_response;
- reg_req_t dma_slave_request;
+ apb_resp_t dma_slave_response;
+ apb_req_t dma_slave_request;
idma_pkg::idma_busy_t busy;
idma_req_t dma_be_req;
@@ -229,8 +229,8 @@ module tb_idma_desc64_bench
.axi_req_t (axi_req_t),
.axi_ar_chan_t (axi_ar_chan_t),
.axi_r_chan_t (axi_r_chan_t),
- .reg_rsp_t (reg_rsp_t),
- .reg_req_t (reg_req_t),
+ .apb_rsp_t (apb_resp_t),
+ .apb_req_t (apb_req_t),
.InputFifoDepth (InputFifoDepth),
.PendingFifoDepth(PendingFifoDepth),
.BackendDepth (NumAxInFlight + BufferDepth),
@@ -383,7 +383,21 @@ module tb_idma_desc64_bench
.clk_i ( clk ),
.rst_ni ( rst_n ),
.axi_req_i ( axi_mem_request ),
- .axi_rsp_o ( axi_mem_response )
+ .axi_rsp_o ( axi_mem_response ),
+ .mon_w_valid_o (),
+ .mon_w_addr_o (),
+ .mon_w_data_o (),
+ .mon_w_id_o (),
+ .mon_w_user_o (),
+ .mon_w_beat_count_o (),
+ .mon_w_last_o (),
+ .mon_r_valid_o (),
+ .mon_r_addr_o (),
+ .mon_r_data_o (),
+ .mon_r_id_o (),
+ .mon_r_user_o (),
+ .mon_r_beat_count_o (),
+ .mon_r_last_o ()
);
// allow 1 AR, 1 AW in-flight
@@ -422,8 +436,16 @@ module tb_idma_desc64_bench
.mst_resp_i ( axi_mem_response )
);
- `REG_BUS_ASSIGN_TO_REQ(dma_slave_request, i_reg_iface_bus);
- `REG_BUS_ASSIGN_FROM_RSP(i_reg_iface_bus, dma_slave_response);
+ assign dma_slave_request.paddr = i_apb_iface_bus.paddr;
+ assign dma_slave_request.pprot = i_apb_iface_bus.pprot;
+ assign dma_slave_request.psel = i_apb_iface_bus.psel;
+ assign dma_slave_request.penable = i_apb_iface_bus.penable;
+ assign dma_slave_request.pwrite = i_apb_iface_bus.pwrite;
+ assign dma_slave_request.pwdata = i_apb_iface_bus.pwdata;
+ assign dma_slave_request.pstrb = i_apb_iface_bus.pstrb;
+ assign i_apb_iface_bus.pready = dma_slave_response.pready;
+ assign i_apb_iface_bus.prdata = dma_slave_response.prdata;
+ assign i_apb_iface_bus.pslverr = dma_slave_response.pslverr;
`AXI_ASSIGN_FROM_REQ(i_axi_iface_bus, dma_fe_master_request);
`AXI_ASSIGN_FROM_RESP(i_axi_iface_bus, dma_fe_master_response);
@@ -598,7 +620,7 @@ module tb_idma_desc64_bench
// regbus slave interaction (we're acting as master)
task regbus_slave_interaction();
automatic stimulus_t current_stimulus_group[$];
- i_reg_iface_driver.reset_master();
+ i_apb_driver.reset_master();
@(posedge rst_n);
forever begin
@@ -609,11 +631,11 @@ module tb_idma_desc64_bench
wait (generated_stimuli.size() > '0);
current_stimulus_group = generated_stimuli.pop_front();
- i_reg_iface_driver.send_write(
- .addr (IDMA_DESC64_DESC_ADDR_OFFSET) ,
- .data (current_stimulus_group[0].base),
- .strb (8'hff) ,
- .error(error)
+ i_apb_driver.write(
+ .addr(IDMA_DESC64_REG_DESC_ADDR_BASE_ADDR) ,
+ .data(current_stimulus_group[0].base),
+ .strb(8'hff) ,
+ .err (error)
);
end
endtask
@@ -848,10 +870,10 @@ module tb_idma_desc64_bench
forever begin
automatic logic [63:0] status;
automatic logic error;
- i_reg_iface_driver.send_read(
- .addr(IDMA_DESC64_STATUS_OFFSET),
+ i_apb_driver.read(
+ .addr(IDMA_DESC64_REG_STATUS_BASE_ADDR),
.data(status),
- .error(error)
+ .err (error)
);
if (status[0] != 1'b1) break;
end
diff --git a/test/frontend/tb_idma_desc64_top.sv b/test/frontend/tb_idma_desc64_top.sv
index 6ad784bb..01055bd6 100644
--- a/test/frontend/tb_idma_desc64_top.sv
+++ b/test/frontend/tb_idma_desc64_top.sv
@@ -5,8 +5,8 @@
// Authors:
// - Axel Vanoni
-`include "register_interface/typedef.svh"
-`include "register_interface/assign.svh"
+`include "apb/typedef.svh"
+`include "apb/assign.svh"
`include "idma/typedef.svh"
`include "axi/typedef.svh"
`include "axi/assign.svh"
@@ -15,11 +15,11 @@
/// VIP for the descriptor-based frontend
module tb_idma_desc64_top
- import idma_desc64_reg_pkg::IDMA_DESC64_DESC_ADDR_OFFSET;
- import idma_desc64_reg_pkg::IDMA_DESC64_STATUS_OFFSET;
+ import idma_desc64_addrmap_pkg::IDMA_DESC64_REG_DESC_ADDR_BASE_ADDR;
+ import idma_desc64_addrmap_pkg::IDMA_DESC64_REG_STATUS_BASE_ADDR;
import rand_verif_pkg::rand_wait;
import axi_pkg::*;
- import reg_test::reg_driver; #(
+ import apb_test::apb_driver; #(
parameter integer NumberOfTests = 100,
parameter integer SimulationTimeoutCycles = 100000,
parameter integer ChainedDescriptors = -1,
@@ -52,7 +52,7 @@ module tb_idma_desc64_top
typedef axi_test::axi_w_beat #(.DW(64), .UW(1)) w_beat_t;
typedef axi_test::axi_b_beat #(.IW(3), .UW(1)) b_beat_t;
- `REG_BUS_TYPEDEF_ALL(reg, /* addr */ addr_t, /* data */ logic [63:0], /* strobe */ logic [7:0])
+ `APB_TYPEDEF_ALL(apb, /* addr */ addr_t, /* data */ logic [63:0], /* strobe */ logic [7:0])
`AXI_TYPEDEF_ALL(axi, /* addr */ addr_t, /* id */ axi_id_t, /* data */ logic [63:0], /* strb */ logic [7:0], /* user */ logic [0:0])
// iDMA struct definitions
@@ -123,17 +123,17 @@ module tb_idma_desc64_top
);
// dut signals and module
- REG_BUS #(
+ APB_DV #(
.ADDR_WIDTH(64),
.DATA_WIDTH(64)
- ) i_reg_iface_bus (clk);
+ ) i_apb_iface_bus (clk);
- reg_driver #(
- .AW(64),
- .DW(64),
+ apb_driver #(
+ .ADDR_WIDTH(64),
+ .DATA_WIDTH(64),
.TA(APPL_DELAY),
.TT(ACQ_DELAY)
- ) i_reg_iface_driver = new (i_reg_iface_bus);
+ ) i_apb_driver = new (i_apb_iface_bus);
axi_resp_t dma_master_response;
axi_req_t dma_master_request;
@@ -154,8 +154,8 @@ module tb_idma_desc64_top
.TT(ACQ_DELAY)
) i_axi_iface_driver = new (i_axi_iface_bus);
- reg_rsp_t dma_slave_response;
- reg_req_t dma_slave_request;
+ apb_resp_t dma_slave_response;
+ apb_req_t dma_slave_request;
idma_req_t dma_be_req;
@@ -176,8 +176,8 @@ module tb_idma_desc64_top
.axi_req_t (axi_req_t),
.axi_ar_chan_t (axi_ar_chan_t),
.axi_r_chan_t (axi_r_chan_t),
- .reg_rsp_t (reg_rsp_t),
- .reg_req_t (reg_req_t),
+ .apb_rsp_t (apb_resp_t),
+ .apb_req_t (apb_req_t),
.InputFifoDepth (InputFifoDepth),
.PendingFifoDepth(PendingFifoDepth),
.BackendDepth (BackendDepth),
@@ -217,17 +217,33 @@ module tb_idma_desc64_top
.clk_i ( clk ),
.rst_ni ( rst_n ),
.axi_req_i ( dma_master_request ),
- .axi_rsp_o ( dma_master_response )
+ .axi_rsp_o ( dma_master_response ),
+ .mon_w_valid_o (),
+ .mon_w_addr_o (),
+ .mon_w_data_o (),
+ .mon_w_id_o (),
+ .mon_w_user_o (),
+ .mon_w_beat_count_o (),
+ .mon_w_last_o (),
+ .mon_r_valid_o (),
+ .mon_r_addr_o (),
+ .mon_r_data_o (),
+ .mon_r_id_o (),
+ .mon_r_user_o (),
+ .mon_r_beat_count_o (),
+ .mon_r_last_o ()
);
- assign dma_slave_request.addr = i_reg_iface_bus.addr;
- assign dma_slave_request.write = i_reg_iface_bus.write;
- assign dma_slave_request.wdata = i_reg_iface_bus.wdata;
- assign dma_slave_request.wstrb = i_reg_iface_bus.wstrb;
- assign dma_slave_request.valid = i_reg_iface_bus.valid;
- assign i_reg_iface_bus.rdata = dma_slave_response.rdata;
- assign i_reg_iface_bus.ready = dma_slave_response.ready;
- assign i_reg_iface_bus.error = dma_slave_response.error;
+ assign dma_slave_request.paddr = i_apb_iface_bus.paddr;
+ assign dma_slave_request.pprot = i_apb_iface_bus.pprot;
+ assign dma_slave_request.psel = i_apb_iface_bus.psel;
+ assign dma_slave_request.penable = i_apb_iface_bus.penable;
+ assign dma_slave_request.pwrite = i_apb_iface_bus.pwrite;
+ assign dma_slave_request.pwdata = i_apb_iface_bus.pwdata;
+ assign dma_slave_request.pstrb = i_apb_iface_bus.pstrb;
+ assign i_apb_iface_bus.pready = dma_slave_response.pready;
+ assign i_apb_iface_bus.prdata = dma_slave_response.prdata;
+ assign i_apb_iface_bus.pslverr = dma_slave_response.pslverr;
`AXI_ASSIGN_FROM_REQ(i_axi_iface_bus, dma_master_request);
`AXI_ASSIGN_FROM_RESP(i_axi_iface_bus, dma_master_response);
@@ -368,7 +384,7 @@ module tb_idma_desc64_top
task apply_stimuli();
fork
- regbus_slave_interaction();
+ apb_slave_interaction();
backend_tx_done_notifier();
backend_acceptor();
join
@@ -383,10 +399,10 @@ module tb_idma_desc64_top
join
endtask
- // regbus slave interaction (we're acting as master)
- task regbus_slave_interaction();
+ // apb slave interaction (we're acting as master)
+ task apb_slave_interaction();
automatic stimulus_t current_stimulus_group[$];
- i_reg_iface_driver.reset_master();
+ i_apb_driver.reset_master();
@(posedge rst_n);
forever begin
@@ -397,11 +413,11 @@ module tb_idma_desc64_top
wait (generated_stimuli.size() > '0);
current_stimulus_group = generated_stimuli.pop_front();
- i_reg_iface_driver.send_write(
- .addr (IDMA_DESC64_DESC_ADDR_OFFSET) ,
+ i_apb_driver.write(
+ .addr (IDMA_DESC64_REG_DESC_ADDR_BASE_ADDR),
.data (current_stimulus_group[0].base),
.strb (8'hff) ,
- .error(error)
+ .err (error)
);
inflight_stimuli.push_back(current_stimulus_group);
end
@@ -691,10 +707,10 @@ module tb_idma_desc64_top
forever begin
automatic logic [63:0] status;
automatic logic error;
- i_reg_iface_driver.send_read(
- .addr(IDMA_DESC64_STATUS_OFFSET),
+ i_apb_driver.read(
+ .addr(idma_desc64_addrmap_pkg::IDMA_DESC64_REG_STATUS_BASE_ADDR),
.data(status),
- .error(error)
+ .err(error)
);
if (status[0] != 1'b1) break;
end
diff --git a/uv.lock b/uv.lock
new file mode 100644
index 00000000..9e043cde
--- /dev/null
+++ b/uv.lock
@@ -0,0 +1,984 @@
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