diff --git a/jobs/backend_rw_axi/simple.txt b/jobs/backend_rw_axi/simple.txt
index 2e0a0e88..097bae0a 100644
--- a/jobs/backend_rw_axi/simple.txt
+++ b/jobs/backend_rw_axi/simple.txt
@@ -1,4 +1,4 @@
-2
+100
 0x0
 0x3ff
 0
@@ -8,3 +8,13 @@
 0
 0
 0
+100
+0x4000
+0x43ff
+0
+0
+256
+4
+0
+1
+0
diff --git a/src/backend/idma_axi_write.sv b/src/backend/idma_axi_write.sv
index ee27349d..2123e2bb 100644
--- a/src/backend/idma_axi_write.sv
+++ b/src/backend/idma_axi_write.sv
@@ -68,6 +68,10 @@ module idma_axi_write #(
     /// AXI4+ATOP write manager port response
     input  write_rsp_t write_rsp_i,
 
+    output logic w_chan_valid_o,
+    output logic w_chan_ready_o,
+    output logic w_chan_first_o,
+
     /// Data from buffer
     input  byte_t [StrbWidth-1:0] buffer_out_i,
     /// Valid from buffer
@@ -256,6 +260,10 @@ module idma_axi_write #(
         end
     end
 
+    // Channel management signals
+    assign w_chan_valid_o = write_req_o.w_valid;
+    assign w_chan_ready_o = write_rsp_i.w_ready;
+    assign w_chan_first_o = first_w;
 
     //--------------------------------------
     // Write response
diff --git a/src/backend/idma_axil_write.sv b/src/backend/idma_axil_write.sv
index 0a47b41b..65ec6d86 100644
--- a/src/backend/idma_axil_write.sv
+++ b/src/backend/idma_axil_write.sv
@@ -61,6 +61,10 @@ module idma_axil_write #(
     /// AXI Lite write manager port response
     input  write_rsp_t write_rsp_i,
 
+    output logic w_chan_valid_o,
+    output logic w_chan_ready_o,
+    output logic w_chan_first_o,
+
     /// Data from buffer
     input  byte_t [StrbWidth-1:0] buffer_out_i,
     /// Valid from buffer
@@ -161,6 +165,11 @@ module idma_axil_write #(
     // we are ready for the next transfer internally, once the w last signal is applied
     assign w_dp_ready_o = write_happening;
 
+    // Channel management signals
+    assign w_chan_valid_o = write_req_o.w_valid;
+    assign w_chan_ready_o = write_rsp_i.w_ready;
+    assign w_chan_first_o = 1'b1; // always first, no bursting
+
     //--------------------------------------
     // Write response
     //--------------------------------------
diff --git a/src/backend/idma_axis_write.sv b/src/backend/idma_axis_write.sv
index ee5b0b17..b05fdac7 100644
--- a/src/backend/idma_axis_write.sv
+++ b/src/backend/idma_axis_write.sv
@@ -66,6 +66,10 @@ module idma_axis_write #(
     /// AXI Stream write manager port response
     input  write_rsp_t write_rsp_i,
 
+    output logic w_chan_valid_o,
+    output logic w_chan_ready_o,
+    output logic w_chan_first_o,
+
     /// Data from buffer
     input  byte_t [StrbWidth-1:0] buffer_out_i,
     /// Valid from buffer
@@ -152,6 +156,10 @@ module idma_axis_write #(
     assign w_dp_req_ready_o = write_happening;
     assign aw_ready_o       = write_happening;
 
+    assign w_chan_valid_o   = write_req_o.tvalid;
+    assign w_chan_ready_o   = write_rsp_i.tready;
+    assign w_chan_first_o   = 1'b1; // always first, no AW channel
+
     //--------------------------------------
     // Write response
     //--------------------------------------
diff --git a/src/backend/idma_channel_coupler.sv b/src/backend/idma_channel_coupler.sv
index 1491716a..64ce32b3 100644
--- a/src/backend/idma_channel_coupler.sv
+++ b/src/backend/idma_channel_coupler.sv
@@ -31,14 +31,12 @@ module idma_channel_coupler #(
     /// Testmode in
     input  logic testmode_i,
 
-    /// R response valid
-    input  logic r_rsp_valid_i,
-    /// R response ready
-    input  logic r_rsp_ready_i,
-    /// First R response
-    input  logic r_rsp_first_i,
-    /// Did the read originate from a decoupled request
-    input  logic r_decouple_aw_i,
+    /// W request valid
+    input  logic w_req_valid_i,
+    /// W request ready
+    input  logic w_req_ready_i,
+    /// First W request
+    input  logic w_req_first_i,
     /// Is the `AW` in the queue a decoupled request?
     input  logic aw_decouple_aw_i,
 
@@ -86,9 +84,13 @@ module idma_channel_coupler #(
 
     // counter to keep track of AR to send
     cnt_t aw_to_send_d, aw_to_send_q;
+    cnt_t aw_to_stall_d, aw_to_stall_q;
 
-    // first signal -> an R has arrived that needs to free an AW
-    assign first = r_rsp_valid_i & r_rsp_ready_i & r_rsp_first_i & !r_decouple_aw_i;
+    logic aw_stall_d, aw_stall_q;
+
+    // first signal -> a W has data that needs to free an AW
+    assign first = w_req_valid_i & w_req_first_i & ~aw_stall_q;
+    assign aw_stall_d = w_req_valid_i & ~w_req_ready_i;
 
     // stream fifo to hold AWs back
     stream_fifo_optimal_wrap #(
@@ -132,26 +134,40 @@ module idma_channel_coupler #(
 
         // defaults
         aw_to_send_d = aw_to_send_q;
+        aw_to_stall_d = aw_to_stall_q;
 
         // if we bypass the logic
         aw_sent = aw_decoupled_head & aw_valid;
-
-        // first is asserted and aw is ready -> just send AW out
-        // without changing the credit counter value
-        if (aw_ready_decoupled & first) begin
-            aw_sent = 1'b1;
-        end
-
-        // if first is asserted and aw is not ready -> increment
-        // credit counter
-        else if (!aw_ready_decoupled & first) begin
-            aw_to_send_d = aw_to_send_q + 1;
+        // if the AW is decoupled, we need to keep track of the sent AWs
+        if (aw_decoupled_head & aw_valid & aw_to_send_q == '0) begin
+            aw_to_stall_d = aw_to_stall_q + 1;
+            if (aw_ready_decoupled & first) begin
+                aw_to_stall_d = aw_to_stall_q;
+            end
         end
 
-        // if not first, aw is ready and we have credit -> count down
-        else if (aw_ready_decoupled & !first & aw_to_send_q != '0) begin
-            aw_sent = 1'b1;
-            aw_to_send_d = aw_to_send_q - 1;
+        if (aw_to_stall_q != '0) begin
+            if (first && !(aw_decoupled_head & aw_valid)) begin
+                aw_to_stall_d = aw_to_stall_q - 1;
+            end
+        end else begin
+            // first is asserted and aw is ready -> just send AW out
+            // without changing the credit counter value
+            if (aw_ready_decoupled & first) begin
+                aw_sent = 1'b1;
+            end
+
+            // if first is asserted and aw is not ready -> increment
+            // credit counter
+            else if (!aw_ready_decoupled & first) begin
+                aw_to_send_d = aw_to_send_q + 1;
+            end
+
+            // if not first, aw is ready and we have credit -> count down
+            else if (aw_ready_decoupled & !first & aw_to_send_q != '0) begin
+                aw_sent = 1'b1;
+                aw_to_send_d = aw_to_send_q - 1;
+            end
         end
     end
 
@@ -159,7 +175,7 @@ module idma_channel_coupler #(
     assign aw_ready = aw_valid_o & aw_ready_i;
 
     // fall through register to decouple the aw valid signal from the aw ready
-    // now payload is required; just the decoupling of the handshaking signals
+    // no payload is required; just the decoupling of the handshaking signals
     fall_through_register #(
         .T ( logic [0:0] )
     ) i_fall_through_register_decouple_aw_valid (
@@ -180,6 +196,8 @@ module idma_channel_coupler #(
 
     // state
     `FF(aw_to_send_q, aw_to_send_d, '0, clk_i, rst_ni)
+    `FF(aw_to_stall_q, aw_to_stall_d, '0, clk_i, rst_ni)
+    `FF(aw_stall_q, aw_stall_d, '0, clk_i, rst_ni)
 
 
 endmodule
diff --git a/src/backend/idma_init_write.sv b/src/backend/idma_init_write.sv
index 61e9b9bb..0eb573df 100644
--- a/src/backend/idma_init_write.sv
+++ b/src/backend/idma_init_write.sv
@@ -62,6 +62,10 @@ module idma_init_write #(
     /// INIT write manager port response
     input  write_rsp_t write_rsp_i,
 
+    output logic w_chan_valid_o,
+    output logic w_chan_ready_o,
+    output logic w_chan_first_o,
+
     /// Data from buffer
     input  byte_t [StrbWidth-1:0] buffer_out_i,
     /// Valid from buffer
@@ -151,6 +155,11 @@ module idma_init_write #(
     assign w_dp_ready_o       = write_happening;
     assign write_meta_ready_o = write_happening;
 
+    // Channel management signals
+    assign w_chan_valid_o = write_req_o.req_valid;
+    assign w_chan_ready_o = write_rsp_i.req_ready;
+    assign w_chan_first_o = 1'b1; // always first, no AW channel
+
     //--------------------------------------
     // Write response
     //--------------------------------------
diff --git a/src/backend/idma_obi_write.sv b/src/backend/idma_obi_write.sv
index d79163c1..5b9ef117 100644
--- a/src/backend/idma_obi_write.sv
+++ b/src/backend/idma_obi_write.sv
@@ -61,6 +61,10 @@ module idma_obi_write #(
     /// OBI write manager port response
     input  write_rsp_t write_rsp_i,
 
+    output logic w_chan_valid_o,
+    output logic w_chan_ready_o,
+    output logic w_chan_first_o,
+
     /// Data from buffer
     input  byte_t [StrbWidth-1:0] buffer_out_i,
     /// Valid from buffer
@@ -153,6 +157,11 @@ module idma_obi_write #(
     assign w_dp_ready_o = write_happening;
     assign aw_ready_o   = write_happening;
 
+    // Channel management signals
+    assign w_chan_valid_o = write_req_o.req;
+    assign w_chan_ready_o = write_rsp_i.gnt;
+    assign w_chan_first_o = 1'b1; // always first, no bursting
+
     //--------------------------------------
     // Write response
     //--------------------------------------
diff --git a/src/backend/idma_tilelink_write.sv b/src/backend/idma_tilelink_write.sv
index 50c94b5e..95865f31 100644
--- a/src/backend/idma_tilelink_write.sv
+++ b/src/backend/idma_tilelink_write.sv
@@ -70,6 +70,10 @@ module idma_tilelink_write #(
     /// TileLink write manager port response
     input  write_rsp_t write_rsp_i,
 
+    output logic w_chan_valid_o,
+    output logic w_chan_ready_o,
+    output logic w_chan_first_o,
+
     /// Data from buffer
     input  byte_t [StrbWidth-1:0] buffer_out_i,
     /// Valid from buffer
@@ -254,6 +258,10 @@ module idma_tilelink_write #(
         end
     end
 
+    // Channel management signals
+    assign w_chan_valid_o = write_req_o.a_valid;
+    assign w_chan_ready_o = write_rsp_i.a_ready;
+    assign w_chan_first_o = first_w;
 
     //--------------------------------------
     // Write response
diff --git a/src/backend/tpl/idma_backend.sv.tpl b/src/backend/tpl/idma_backend.sv.tpl
index c5a2e164..9672dd70 100644
--- a/src/backend/tpl/idma_backend.sv.tpl
+++ b/src/backend/tpl/idma_backend.sv.tpl
@@ -371,9 +371,13 @@ _rsp_t ${protocol}_write_rsp_i,
     logic      rsp_valid;
     logic      rsp_ready;
 
-    // Respone Channel valid and ready -> needed for bursting
-    logic r_chan_valid;
-    logic r_chan_ready;
+    // // Respone Channel valid and ready -> needed for bursting
+    // logic r_chan_valid;
+    // logic r_chan_ready;
+
+    logic w_chan_valid;
+    logic w_chan_ready;
+    logic w_chan_first;
 
     //--------------------------------------
     // Reject Zero Length Transfers
@@ -770,8 +774,11 @@ _rsp_t ${protocol}_write_rsp_i,
         .r_dp_busy_o     ( busy_o.r_dp_busy     ),
         .w_dp_busy_o     ( busy_o.w_dp_busy     ),
         .buffer_busy_o   ( busy_o.buffer_busy   ),
-        .r_chan_ready_o  ( r_chan_ready         ),
-        .r_chan_valid_o  ( r_chan_valid         )
+        .w_chan_valid_o  ( w_chan_valid         ),
+        .w_chan_ready_o  ( w_chan_ready         ),
+        .w_chan_first_o  ( w_chan_first         )
+        // .r_chan_ready_o  ( r_chan_ready         ),
+        // .r_chan_valid_o  ( r_chan_valid         )
     );
 
     //--------------------------------------
@@ -803,10 +810,13 @@ _rsp_t ${protocol}_write_rsp_i,
             .clk_i            ( clk_i                       ),
             .rst_ni           ( rst_ni                      ),
             .testmode_i       ( testmode_i                  ),
-            .r_rsp_valid_i    ( r_chan_valid                ),
-            .r_rsp_ready_i    ( r_chan_ready                ),
-            .r_rsp_first_i    ( r_dp_rsp.first              ),
-            .r_decouple_aw_i  ( r_dp_req_out.decouple_aw    ),
+            .w_req_valid_i    ( w_chan_valid                ),
+            .w_req_ready_i    ( w_chan_ready                ),
+            .w_req_first_i    ( w_chan_first                ),
+            // .r_rsp_valid_i    ( r_chan_valid                ),
+            // .r_rsp_ready_i    ( r_chan_ready                ),
+            // .r_rsp_first_i    ( r_dp_rsp.first              ),
+            // .r_decouple_aw_i  ( r_dp_req_out.decouple_aw    ),
             .aw_decouple_aw_i ( \
 % if one_write_port:
 w_req.decouple_aw\
diff --git a/src/backend/tpl/idma_transport_layer.sv.tpl b/src/backend/tpl/idma_transport_layer.sv.tpl
index 91d27131..82e647f8 100644
--- a/src/backend/tpl/idma_transport_layer.sv.tpl
+++ b/src/backend/tpl/idma_transport_layer.sv.tpl
@@ -172,9 +172,12 @@ _rsp_t ${protocol}_write_rsp_i,
     /// Datapath poison signal
     input  logic dp_poison_i,
 
-    /// Response channel valid and ready
-    output logic r_chan_ready_o,
-    output logic r_chan_valid_o,
+    // /// Response channel valid and ready
+    // output logic r_chan_ready_o,
+    // output logic r_chan_valid_o,
+    output logic w_chan_valid_o,
+    output logic w_chan_ready_o,
+    output logic w_chan_first_o,
 
     /// Read part of the datapath is busy
     output logic r_dp_busy_o,
@@ -231,7 +234,7 @@ _rsp_t ${protocol}_write_rsp_i,
 % if not one_read_port:
 
     // Read multiplexed signals
-    logic\
+    // logic\
     % for index, protocol in enumerate(used_read_protocols):
  ${protocol}_r_chan_valid\
         % if index == len(used_read_protocols)-1:
@@ -240,7 +243,7 @@ _rsp_t ${protocol}_write_rsp_i,
 ,\
         % endif
     %endfor
-    logic\
+    // logic\
     % for index, protocol in enumerate(used_read_protocols):
  ${protocol}_r_chan_ready\
         % if index == len(used_read_protocols)-1:
@@ -292,6 +295,33 @@ _rsp_t ${protocol}_write_rsp_i,
     // Write multiplexed signals
     logic\
     % for index, protocol in enumerate(used_write_protocols):
+ ${protocol}_w_chan_valid\
+        % if index == len(used_write_protocols)-1:
+;
+        % else:
+,\
+        % endif
+    %endfor
+    logic\
+    % for index, protocol in enumerate(used_write_protocols):
+ ${protocol}_w_chan_ready\
+        % if index == len(used_write_protocols)-1:
+;
+        % else:
+,\
+        % endif
+    %endfor
+    logic\
+    % for index, protocol in enumerate(used_write_protocols):
+ ${protocol}_w_chan_first\
+        % if index == len(used_write_protocols)-1:
+;
+        % else:
+,\
+        % endif
+    %endfor
+    logic\
+    % for index, protocol in enumerate(used_write_protocols):
  ${protocol}_w_dp_rsp_valid\
         % if index == len(used_write_protocols)-1:
 ;
@@ -376,8 +406,8 @@ ${rendered_read_ports[read_port]}
             case(r_dp_req_i.src_protocol)
 % for rp in used_read_protocols:
             idma_pkg::${database[rp]['protocol_enum']}: begin
-                r_chan_valid_o  = ${rp}_r_chan_valid;
-                r_chan_ready_o  = ${rp}_r_chan_ready;
+                //r_chan_valid_o  = ${rp}_r_chan_valid;
+                //r_chan_ready_o  = ${rp}_r_chan_ready;
 
                 r_dp_ready_o    = ${rp}_r_dp_ready;
                 r_dp_rsp_o      = ${rp}_r_dp_rsp;
@@ -388,8 +418,8 @@ ${rendered_read_ports[read_port]}
             end
 % endfor
             default: begin
-                r_chan_valid_o  = 1'b0;
-                r_chan_ready_o  = 1'b0;
+                //r_chan_valid_o  = 1'b0;
+                //r_chan_ready_o  = 1'b0;
 
                 r_dp_ready_o    = 1'b0;
                 r_dp_rsp_o      = '0;
@@ -400,8 +430,8 @@ ${rendered_read_ports[read_port]}
             end
             endcase
         end else begin
-            r_chan_valid_o  = 1'b0;
-            r_chan_ready_o  = 1'b0;
+            //r_chan_valid_o  = 1'b0;
+            //r_chan_ready_o  = 1'b0;
 
             r_dp_ready_o    = 1'b0;
             r_dp_rsp_o      = '0;
@@ -475,11 +505,17 @@ ${rendered_read_ports[read_port]}
         idma_pkg::${database[wp]['protocol_enum']}: begin
             w_dp_req_ready   = ${wp}_w_dp_ready;
             buffer_out_ready = ${wp}_buffer_out_ready;
+            w_chan_valid_o   = ${wp}_w_chan_valid;
+            w_chan_ready_o   = ${wp}_w_chan_ready;
+            w_chan_first_o   = ${wp}_w_chan_first;
         end
 % endfor
         default: begin
             w_dp_req_ready   = 1'b0;
             buffer_out_ready = '0;
+            w_chan_valid_o   = 1'b0;
+            w_chan_ready_o   = 1'b0;
+            w_chan_first_o   = 1'b0;
         end
         endcase
     end
diff --git a/src/db/idma_axi.yml b/src/db/idma_axi.yml
index 02c7f884..d2d2039e 100644
--- a/src/db/idma_axi.yml
+++ b/src/db/idma_axi.yml
@@ -92,8 +92,8 @@ read_template: |
         .ar_ready_o        ( ${read_meta_ready} ),
         .read_req_o        ( ${read_request} ),
         .read_rsp_i        ( ${read_response} ),
-        .r_chan_valid_o    ( ${r_chan_valid} ),
-        .r_chan_ready_o    ( ${r_chan_ready} ),
+        .r_chan_valid_o    ( /*${r_chan_valid}*/ ),
+        .r_chan_ready_o    ( /*${r_chan_ready}*/ ),
         .buffer_in_o       ( ${buffer_in} ),
         .buffer_in_valid_o ( ${buffer_in_valid} ),
         .buffer_in_ready_i ( buffer_in_ready )
@@ -125,6 +125,9 @@ write_template: |
         .aw_ready_o         ( ${write_meta_ready} ),
         .write_req_o        ( ${write_request} ),
         .write_rsp_i        ( ${write_response} ),
+        .w_chan_valid_o     ( ${w_chan_valid} ),
+        .w_chan_ready_o     ( ${w_chan_ready} ),
+        .w_chan_first_o     ( ${w_chan_first} ),
         .buffer_out_i       ( buffer_out_shifted ),
         .buffer_out_valid_i ( buffer_out_valid_shifted ),
         .buffer_out_ready_o ( ${buffer_out_ready} )
diff --git a/src/db/idma_axi_lite.yml b/src/db/idma_axi_lite.yml
index edb5637a..5e310a80 100644
--- a/src/db/idma_axi_lite.yml
+++ b/src/db/idma_axi_lite.yml
@@ -77,8 +77,8 @@ read_template: |
         .ar_ready_o        ( ${read_meta_ready}   ),
         .read_req_o        ( ${read_request}     ),
         .read_rsp_i        ( ${read_response}     ),
-        .r_chan_valid_o    ( ${r_chan_valid}     ),
-        .r_chan_ready_o    ( ${r_chan_ready}     ),
+        .r_chan_valid_o    ( /*${r_chan_valid}*/ ),
+        .r_chan_ready_o    ( /*${r_chan_ready}*/ ),
         .buffer_in_o       ( ${buffer_in}         ),
         .buffer_in_valid_o ( ${buffer_in_valid}   ),
         .buffer_in_ready_i ( buffer_in_ready      )
@@ -108,6 +108,9 @@ write_template: |
         .aw_ready_o         ( ${write_meta_ready} ),
         .write_req_o        ( ${write_request} ),
         .write_rsp_i        ( ${write_response} ),
+        .w_chan_valid_o     ( ${w_chan_valid} ),
+        .w_chan_ready_o     ( ${w_chan_ready} ),
+        .w_chan_first_o     ( ${w_chan_first} ),
         .buffer_out_i       ( buffer_out_shifted ),
         .buffer_out_valid_i ( buffer_out_valid_shifted ),
         .buffer_out_ready_o ( ${buffer_out_ready} )
diff --git a/src/db/idma_axi_stream.yml b/src/db/idma_axi_stream.yml
index ac639ff3..d52282d0 100644
--- a/src/db/idma_axi_stream.yml
+++ b/src/db/idma_axi_stream.yml
@@ -240,8 +240,8 @@ read_template: |
         .read_meta_ready_o ( ${read_meta_ready} ),
         .read_req_i        ( ${read_request} ),
         .read_rsp_o        ( ${read_response} ),
-        .r_chan_valid_o    ( ${r_chan_valid} ),
-        .r_chan_ready_o    ( ${r_chan_ready} ),
+        .r_chan_valid_o    ( /*${r_chan_valid}*/ ),
+        .r_chan_ready_o    ( /*${r_chan_ready}*/ ),
         .buffer_in_o       ( ${buffer_in} ),
         .buffer_in_valid_o ( ${buffer_in_valid} ),
         .buffer_in_ready_i ( buffer_in_ready )
@@ -273,6 +273,9 @@ write_template: |
         .aw_ready_o         ( ${write_meta_ready}  ),
         .write_req_o        ( ${write_request} ),
         .write_rsp_i        ( ${write_response} ),
+        .w_chan_valid_o     ( ${w_chan_valid} ),
+        .w_chan_ready_o     ( ${w_chan_ready} ),
+        .w_chan_first_o     ( ${w_chan_first} ),
         .buffer_out_i       ( buffer_out_shifted ),
         .buffer_out_valid_i ( buffer_out_valid_shifted ),
         .buffer_out_ready_o ( ${buffer_out_ready} )
diff --git a/src/db/idma_init.yml b/src/db/idma_init.yml
index 35e40911..a542fc68 100644
--- a/src/db/idma_init.yml
+++ b/src/db/idma_init.yml
@@ -98,8 +98,8 @@ read_template: |
         .read_meta_ready_o ( ${read_meta_ready} ),
         .read_req_o        ( ${read_request} ),
         .read_rsp_i        ( ${read_response} ),
-        .r_chan_valid_o    ( ${r_chan_valid} ),
-        .r_chan_ready_o    ( ${r_chan_ready} ),
+        .r_chan_valid_o    ( /*${r_chan_valid}*/ ),
+        .r_chan_ready_o    ( /*${r_chan_ready}*/ ),
         .buffer_in_o       ( ${buffer_in} ),
         .buffer_in_valid_o ( ${buffer_in_valid} ),
         .buffer_in_ready_i ( buffer_in_ready )
@@ -128,6 +128,9 @@ write_template: |
         .write_meta_ready_o ( ${write_meta_ready}  ),
         .write_req_o        ( ${write_request} ),
         .write_rsp_i        ( ${write_response} ),
+        .w_chan_valid_o     ( ${w_chan_valid} ),
+        .w_chan_ready_o     ( ${w_chan_ready} ),
+        .w_chan_first_o     ( ${w_chan_first} ),
         .buffer_out_i       ( buffer_out_shifted ),
         .buffer_out_valid_i ( buffer_out_valid_shifted ),
         .buffer_out_ready_o ( ${buffer_out_ready} )
diff --git a/src/db/idma_obi.yml b/src/db/idma_obi.yml
index e4664735..926cf48f 100644
--- a/src/db/idma_obi.yml
+++ b/src/db/idma_obi.yml
@@ -84,8 +84,8 @@ read_template: |
         .read_meta_ready_o ( ${read_meta_ready} ),
         .read_req_o        ( ${read_request} ),
         .read_rsp_i        ( ${read_response} ),
-        .r_chan_valid_o    ( ${r_chan_valid} ),
-        .r_chan_ready_o    ( ${r_chan_ready} ),
+        .r_chan_valid_o    ( /*${r_chan_valid}*/ ),
+        .r_chan_ready_o    ( /*${r_chan_ready}*/ ),
         .buffer_in_o       ( ${buffer_in} ),
         .buffer_in_valid_o ( ${buffer_in_valid} ),
         .buffer_in_ready_i ( buffer_in_ready )
@@ -115,6 +115,9 @@ write_template: |
         .aw_ready_o         ( ${write_meta_ready}  ),
         .write_req_o        ( ${write_request} ),
         .write_rsp_i        ( ${write_response} ),
+        .w_chan_valid_o     ( ${w_chan_valid} ),
+        .w_chan_ready_o     ( ${w_chan_ready} ),
+        .w_chan_first_o     ( ${w_chan_first} ),
         .buffer_out_i       ( buffer_out_shifted ),
         .buffer_out_valid_i ( buffer_out_valid_shifted ),
         .buffer_out_ready_o ( ${buffer_out_ready} )
diff --git a/src/db/idma_tilelink.yml b/src/db/idma_tilelink.yml
index 652a6caf..54bcf139 100644
--- a/src/db/idma_tilelink.yml
+++ b/src/db/idma_tilelink.yml
@@ -111,8 +111,8 @@ read_template: |
         .read_meta_ready_o ( ${read_meta_ready} ),
         .read_req_o        ( ${read_request} ),
         .read_rsp_i        ( ${read_response} ),
-        .r_chan_valid_o    ( ${r_chan_valid} ),
-        .r_chan_ready_o    ( ${r_chan_ready} ),
+        .r_chan_valid_o    ( /*${r_chan_valid}*/ ),
+        .r_chan_ready_o    ( /*${r_chan_ready}*/ ),
         .buffer_in_o       ( ${buffer_in} ),
         .buffer_in_valid_o ( ${buffer_in_valid} ),
         .buffer_in_ready_i ( buffer_in_ready )
@@ -150,6 +150,9 @@ write_template: |
         .write_meta_ready_o ( ${write_meta_ready} ),
         .write_req_o        ( ${write_request} ),
         .write_rsp_i        ( ${write_response} ),
+        .w_chan_valid_o     ( ${w_chan_valid} ),
+        .w_chan_ready_o     ( ${w_chan_ready} ),
+        .w_chan_first_o     ( ${w_chan_first} ),
         .buffer_out_i       ( buffer_out_shifted ),
         .buffer_out_valid_i ( buffer_out_valid_shifted ),
         .buffer_out_ready_o ( ${buffer_out_ready} )
diff --git a/util/mario/transport_layer.py b/util/mario/transport_layer.py
index 17a23a36..379046fe 100644
--- a/util/mario/transport_layer.py
+++ b/util/mario/transport_layer.py
@@ -130,6 +130,9 @@ def render_write_mgr_inst(prot_id: str, prot_ids: dict, db: dict) -> dict:
             write_meta_request = 'aw_req_i'
             write_meta_valid = 'aw_valid_i'
             write_meta_ready = 'aw_ready_o'
+            w_chan_valid = 'w_chan_valid_o'
+            w_chan_ready = 'w_chan_ready_o'
+            w_chan_first = 'w_chan_first_o'
             buffer_out_ready = 'buffer_out_ready'
         else:
             write_dp_valid_in = f'''\
@@ -144,6 +147,9 @@ def render_write_mgr_inst(prot_id: str, prot_ids: dict, db: dict) -> dict:
 (aw_req_i.dst_protocol == idma_pkg::{db[wp]["protocol_enum"]}) & aw_valid_i\
 '''
             write_meta_ready = f'{wp}_aw_ready'
+            w_chan_valid = f'{wp}_w_chan_valid'
+            w_chan_ready = f'{wp}_w_chan_ready'
+            w_chan_first = f'{wp}_w_chan_first'
             buffer_out_ready = f'{wp}_buffer_out_ready'
 
         write_port_context = {
@@ -160,6 +166,9 @@ def render_write_mgr_inst(prot_id: str, prot_ids: dict, db: dict) -> dict:
             'write_meta_ready': write_meta_ready,
             'write_request': f'{wp}_write_req_o',
             'write_response': f'{wp}_write_rsp_i',
+            'w_chan_valid': w_chan_valid,
+            'w_chan_ready': w_chan_ready,
+            'w_chan_first': w_chan_first,
             'buffer_out_ready': buffer_out_ready
         }