Underflow OBI Typedef macros

[LucaRufer]

Many OBI typedef macros have xxx_WIDTH parameters, which are used in vector declaration. The vectors are created as logic[xxx_WIDTH-1:0]. If the xxx feature is not used and a value of 0 is passed for xxx_WIDTH, two things can happen:

• If the 0 is a literal or a signed number, the vector is created as logic[-1:0], which is fine according to the System Verilog specification and widely supported.
• If the 0 is an unsigned number, an underflow occurs (0u - 1) and the behaviour is implementation defined: "Implementations may set a limit on the maximum length of a vector, but the limit shall be at least 65 536 (2^16) bits. Implementations are not required to detect overflow of integer operations." This can become a problem on some simulators like VCS and on some synthesis tools.

The problem especially occurs when using the macros OBI_TYPEDEF_ALL and OBI_TYPEDEF_DEFAULT_ALL that generate OBI structs based on the Config struct, in which the xxx_WIDTH are declared as int unsigned type.

I see multiple possible options for resolving this issue, all with their own drawbacks:

• Use a iomsb function like in AXI to catch this vector generation problem. The problem with this solution is that the function would have to be defined in the typedef.svh file, which can cause problems with re-definition or collission with other packages that provide this function.
• Change the xxx_WIDTH types in the Config structure from int unsigned to signed int. This only solves the problem when using the cfg-based typedef macros.
• Instead of having xxx_WIDTH parameters, use type parameters like AXI does. This would unfortunately not be backwards-compatible.
• Use logic[$signed(xxx_WIDTH)-1:0] in the typedefs to prevent underflow. This would not break anything and be backwards-compatible.

I would be willing to open a PR on this with your preffered solution.