vsim error about "helloworld" test

[JacoboJin]

Hello,

when I run make helloworld.vsim, I met this problem as below:

source tcl_files/run.tcl

vsim -quiet tb -L pulpino_lib -L unisim -L unisims_ver -L apb_gpio_lib -L axi_slice_dc_lib -L apb_event_unit_lib -L axi_node_lib -L riscv_lib -L apb_pulpino_lib -L axi_mem_if_DP_lib -L apb_fll_if_lib -L axi_slice_lib -L apb_uart_lib -L apb_spi_master_lib -L apb_timer_lib -L axi2apb_lib -L axi_spi_slave_lib -L apb_i2c_lib -L adv_dbg_if_lib -L axi_spi_master_lib -L core2axi_lib -L apb_node_lib -L apb2per_lib "+nowarnTRAN" "+nowarnTSCALE" "+nowarnTFMPC" "+MEMLOAD=PRELOAD" -t ps -voptargs="+acc -suppress 2103" -GTEST="" 

Start time: 21:18:42 on Dec 28,2023
** Note: (vsim-3812) Design is being optimized...
** Error (suppressible): /home/jin_eda/dift/pulpino/rtl/pulpino_top.sv(175): (vopt-2732) Module parameter 'USE_ZERO_RISCY' not found for override.
** Error (suppressible): /home/jin_eda/dift/pulpino/rtl/pulpino_top.sv(176): (vopt-2732) Module parameter 'RISCY_RV32F' not found for override.
** Error (suppressible): /home/jin_eda/dift/pulpino/rtl/pulpino_top.sv(177): (vopt-2732) Module parameter 'ZERO_RV32M' not found for override.
** Error (suppressible): /home/jin_eda/dift/pulpino/rtl/pulpino_top.sv(178): (vopt-2732) Module parameter 'ZERO_RV32E' not found for override.
** Warning: (vopt-13) Recompile unisim.vpkg because ieee.std_logic_1164 has changed.
** Warning: (vopt-13) Recompile unisim.vcomponents because ieee.std_logic_1164 has changed.
** Warning: (vopt-12) Recompile unisim.RAMB16_S2_S2 after unisim.vpkg, unisim.vcomponents are recompiled.
** Warning: (vopt-13) Recompile unisim.RAMB16_S2_S2 because ieee.std_logic_1164 has changed.
** Warning: (vopt-12) Recompile unisim.ramb16_s2_s2(ramb16_s2_s2_v) after unisim.RAMB16_S2_S2, unisim.vpkg, unisim.vcomponents are recompiled.
** Warning: (vopt-13) Recompile unisim.ramb16_s2_s2(ramb16_s2_s2_v) because ieee.std_logic_1164 has changed.
** Warning: (vopt-12) Recompile unisim.vpkg(body) after unisim.vpkg is recompiled.
** Warning: (vopt-13) Recompile unisim.vpkg(body) because ieee.std_logic_1164 has changed.

Optimization failed

** Note: (vsim-12126) Error and warning message counts have been restored: Errors=4, Warnings=8.
Error loading design

End time: 21:18:43 on Dec 28,2023, Elapsed time: 0:00:01
Errors: 4, Warnings: 8

Then I checked my pulpino_top.sv and tb.sv files, it has these parameter with default value. I have not never encountered this problem.

# pulpino_top.sv
module pulpino_top
  #(
    parameter USE_ZERO_RISCY       = 0,
    parameter RISCY_RV32F          = 0,
    parameter ZERO_RV32M           = 1,
    parameter ZERO_RV32E           = 0
  )
  (
   ......
);

# tb.sv
....

  pulpino_top
  #(
    .USE_ZERO_RISCY    ( USE_ZERO_RISCY ),
    .RISCY_RV32F       ( RISCY_RV32F    ),
    .ZERO_RV32M        ( ZERO_RV32M     ),
    .ZERO_RV32E        ( ZERO_RV32E     )
   )
  top_i
  (
    .clk               ( s_clk        ),
    .rst_n             ( s_rst_n      ),

    .clk_sel_i         ( 1'b0         ),
    .testmode_i        ( 1'b0         ),
    .fetch_enable_i    ( fetch_enable ),

....

So how to slove it?

Thanks for all contributors.