APB Protocol Handling Concern in PULPino UART Integration #412
Description
I am currently working on extending the PULPino platform and integrating it with additional IPs, including a UART module that adheres strictly to the AMBA APB protocol specification. During this process, I noticed a protocol compliance issue in the existing APB implementation within PULPino, specifically in the way the UART peripheral is accessed.
In the current PULPino design, the UART interface appears to operate using only the Access phase of the APB protocol (i.e., PSEL=1, PENABLE=1). The Setup phase (PSEL=1, PENABLE=0), which is an essential part of the APB specification, is not utilized or enforced.
Because of this, the peripheral logic directly reacts to PSEL and PENABLE both being high, without validating if the correct transition from the setup to access phase has occurred.
Read and write operations may not behave as expected, especially when used with verified third-party IPs.
A possible solution might be to Introduce a simple FSM or state-tracking logic at the peripheral interface level that distinguishes between setup and access phases.
Please let me know your thoughts on this, and whether such enhancements would be considered for future updates.
Thank you for listening.