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Goal: CoreMark, Embench benchmarks within 20% of M2 CPI. Validates overall timing model correctness.
No due dateGoal: SPEC CPU 2017 within 25% of M2. Requires full instruction coverage and memory hierarchy tuning.
No due dateGoal: Tune timing parameters until microbenchmarks have <30% average error. Focus: Branch prediction, forwarding, cache timing.
No due dateGoal: Run CoreMark and Embench benchmarks to completion without unknown instruction errors.
No due date•1/1 issues closedBasic ARM64 execution - decoder, ALU, registers, simple test programs
No due date•4/4 issues closed