From b37c78f8ad818e50823abc26a4964b39139dd4cc Mon Sep 17 00:00:00 2001
From: noloerino <jhshi07@gmail.com>
Date: Sun, 14 Mar 2021 19:03:49 -0700
Subject: [PATCH 1/3] Bump chisel/firrtl

---
 build.sbt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/build.sbt b/build.sbt
index 2b4333a..1371b1c 100644
--- a/build.sbt
+++ b/build.sbt
@@ -17,9 +17,9 @@ resolvers ++= Seq(
 
 // Managed dependency on latest FIRRTL + chisel3
 //libraryDependencies += "edu.berkeley.cs" %% "firrtl" % "1.2.0-RC1"
-libraryDependencies += "edu.berkeley.cs" %% "firrtl" % "1.3.2"
+libraryDependencies += "edu.berkeley.cs" %% "firrtl" % "1.4.2"
 //libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.2.0-RC1"
-libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.3.2"
+libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.2"
 
 libraryDependencies += "org.json4s" %% "json4s-native" % "3.6.9"
 

From 95d7d555674d1408aec37f3e40a2ce3cd294c61d Mon Sep 17 00:00:00 2001
From: noloerino <jhshi07@gmail.com>
Date: Tue, 16 Mar 2021 02:00:56 -0700
Subject: [PATCH 2/3] Implement translation for cvt/andr/orr/xorr unary ops

---
 .../chiselucl/backend/UclidEmitter.scala      | 21 ++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/chiselucl/backend/UclidEmitter.scala b/src/main/scala/chiselucl/backend/UclidEmitter.scala
index 967209f..8331725 100644
--- a/src/main/scala/chiselucl/backend/UclidEmitter.scala
+++ b/src/main/scala/chiselucl/backend/UclidEmitter.scala
@@ -94,11 +94,30 @@ class UclidEmitter extends Transform with DependencyAPIMigration {
 
   private def serialize_unop(p: DoPrim, arg0: String): String = p.op match {
     case Neg => s"-$arg0"
-    case Not => s"~${arg0}"
+    case Not => s"~$arg0"
     // TODO: Handle asUInt operator
     case AsUInt => arg0
     // TODO: Handle asSInt operator
     case AsSInt => arg0
+    case Cvt =>
+      // Converts unsigned to signed
+      val dstLen = get_width(p.tpe)
+      val srcLen = get_width(p.args.head.tpe)
+      val diff = dstLen - srcLen
+      if (diff == 0) {
+        arg0
+      } else {
+        s"bv_sign_extend($diff, $arg0)"
+      }
+    case Andr | Orr | Xorr =>
+      // Simulate bitwise reduction operators
+      (0 until get_width(p.args.head.tpe)).map(i => s"${arg0}[$i]").mkString(
+        p.op match {
+          case Andr => " & "
+          case Orr => " | "
+          case Xorr => " ^ "
+        }
+      )
     case _ => throwInternalError(s"Illegal unary operator: ${p.op}")
   }
 

From d9a344ceead8d23f9c423de6d7a929b077aee7c5 Mon Sep 17 00:00:00 2001
From: noloerino <jhshi07@gmail.com>
Date: Tue, 16 Mar 2021 02:12:37 -0700
Subject: [PATCH 3/3] Fix bv index in unops

---
 src/main/scala/chiselucl/backend/UclidEmitter.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/chiselucl/backend/UclidEmitter.scala b/src/main/scala/chiselucl/backend/UclidEmitter.scala
index 8331725..a4c1ab9 100644
--- a/src/main/scala/chiselucl/backend/UclidEmitter.scala
+++ b/src/main/scala/chiselucl/backend/UclidEmitter.scala
@@ -111,7 +111,7 @@ class UclidEmitter extends Transform with DependencyAPIMigration {
       }
     case Andr | Orr | Xorr =>
       // Simulate bitwise reduction operators
-      (0 until get_width(p.args.head.tpe)).map(i => s"${arg0}[$i]").mkString(
+      (0 until get_width(p.args.head.tpe)).map(i => s"$arg0[$i:$i]").mkString(
         p.op match {
           case Andr => " & "
           case Orr => " | "