Pipelined Processing Unit (PPU) for RISC-V Instructions

This repository contains the implementation and simulation in Verilog of a 5 stage pipeline CPU using RISCV Architecture.

Name		Name	Last commit message	Last commit date
Latest commit History 49 Commits
Adder_Plus4.v		Adder_Plus4.v
ConditionHandler.v		ConditionHandler.v
Control_Unit.v		Control_Unit.v
Hazard_Fowarding_Unit.v		Hazard_Fowarding_Unit.v
Hazard_Fowarding_Unit.v.out		Hazard_Fowarding_Unit.v.out
HelpersConcatenateOR.v		HelpersConcatenateOR.v
Instruction_memory.v		Instruction_memory.v
Muxes.v		Muxes.v
Muxes.v.out		Muxes.v.out
PC_Register.v		PC_Register.v
PF4_debbug_input.txt		PF4_debbug_input.txt
PF4_input.txt		PF4_input.txt
PPU.v		PPU.v
PPU.v.out		PPU.v.out
README.md		README.md
RegisterFileModule.v		RegisterFileModule.v
Stages.v		Stages.v
alu.v		alu.v
alu.v.out		alu.v.out
dataMemory.v		dataMemory.v
dataMemory.v.out		dataMemory.v.out
finaltest.txt		finaltest.txt
input_file.txt		input_file.txt
reset.v		reset.v
secondOperand.v		secondOperand.v
signalLogicBox.v		signalLogicBox.v
targetAddressAdder.v		targetAddressAdder.v
test3.txt		test3.txt

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