Verilog experiment #43
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Transforms the experimental _svtest.py into a complete VerilogWrapper system that creates Amaranth wiring.Component classes from TOML configuration files. Features: - Automatic Signature generation from TOML port/pin definitions - SpinalHDL code generation support - Clock and reset signal mapping - Port interface mapping (Wishbone, simple signals, etc.) - Verilog file loading for platform.add_file() Also adds: - Unit tests for the wrapper system - Package exports for VerilogWrapper and load_wrapper_from_toml - pydantic and tomli as new dependencies
Extends the Verilog wrapper system to support SystemVerilog files: - Add GenerateSV2V class for SystemVerilog to Verilog conversion via sv2v - Add SYSTEMVERILOG generator type for TOML configs - Support .sv file extensions in source collection - Add include_dirs, defines, and top_module options for sv2v Also includes a sample wb_timer IP: - Simple 32-bit Wishbone B4 timer/counter in SystemVerilog - Features: prescaler, compare match, interrupt generation - TOML config and C driver header included This enables wrapping external SystemVerilog IPs (like OpenTitan) in Amaranth designs by converting them to Verilog at build time.
Enhances the Verilog wrapper system with proper ChipFlow integration:
- Add DriverConfig for SoftwareDriverSignature support (regs_struct, c_files, h_files)
- Add explicit 'direction' field to Port config ('in' or 'out')
- Ports default to direction='in', pins default to direction='out'
- Use SoftwareDriverSignature when driver config is provided
This enables wrapped Verilog modules to work with ChipFlow's driver
generation system, matching the pattern used by native peripherals
like GPIOPeripheral and I2CPeripheral.
Also updates wb_timer example:
- Moves irq to pins section (as it goes to IO pads)
- Adds proper driver config with regs_struct
- Creates separate C header file in drivers/ directory
Adds automatic port mapping generation for known interface types, reducing TOML verbosity and ensuring consistent signal naming. - Add interface registry for Wishbone, CSR, GPIO, UART, I2C, SPI, QSPI - Port.map is now optional - uses auto-generation when not provided - Add Port.prefix field for customizing auto-generated signal names - Infer prefix from port name and interface type when not specified - Update wb_timer example to use auto-mapping instead of explicit map - Add comprehensive tests for auto-mapping functionality
Instead of generating expected signal names from a prefix, auto-mapping now parses the actual Verilog module ports and matches patterns to identify interface signals. This adapts to any naming convention. - Add _parse_verilog_ports() to extract port names from Verilog - Add _infer_auto_map() to match patterns against actual ports - Pattern-based matching for Wishbone, CSR, UART, I2C, SPI, GPIO - Falls back to prefix-based generation if Verilog not available - Update wb_timer to use inference (no prefix needed for bus) - Update tests with Verilog parsing and inference tests
Adds comprehensive tests for the wb_timer SystemVerilog IP: - Configuration tests verify TOML parsing works correctly - Wrapper tests check signature creation (requires sv2v) - Simulation tests verify timer functionality via Wishbone bus: - Timer enable and counting - Compare match and IRQ generation - Prescaler divides count rate Tests use @skipUnless decorator to gracefully skip when sv2v is not installed, allowing config tests to pass regardless.
Add GenerateYosysSlang as an alternative to sv2v for converting SystemVerilog to Verilog. This allows using yowasp-yosys (pure Python) for a portable solution without native tool dependencies. - Add GenerateYosysSlang class with yosys-slang plugin support - Add YOSYS_SLANG to Generators enum - Update wb_timer.toml to use yosys_slang generator - Update test_wb_timer.py with _has_yosys_slang() check
yowasp-yosys statically links yosys-slang, so read_slang is available without -m slang. Update GenerateYosysSlang._find_yosys() to return both the command and whether slang is built-in, then conditionally add -m slang only for native yosys.
yowasp-yosys includes yosys-slang built-in, enabling SystemVerilog parsing without native tool dependencies. This allows the YOSYS_SLANG generator to work in CI and any Python environment.
- Resolve source_path relative to TOML file directory, not CWD - Use local build/ directory for test output (yowasp-yosys WASM can't access /tmp) - Fix type hint: remove unsupported In | Out union - Fix submodule check: use hasattr() instead of dict() - Fix auto-map direction flipping: only flip for bus interfaces (Wishbone, CSR), not pin interfaces (UART, I2C, SPI, GPIO) - Update requires-python to >=3.12 (required by chipflow-lib)
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