feat: Add CXXRTL-based simulation infrastructure#159
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Add Python bindings and build tools for CXXRTL compiled simulation: - chipflow.sim.build: Compile HDL (Verilog/SystemVerilog) to CXXRTL shared libraries using yowasp-yosys or native yosys with slang - chipflow.sim.cxxrtl: Python ctypes bindings for CXXRTL C API supporting signal get/set, stepping, and enumeration This enables fast compiled simulation of mixed Amaranth/Verilog/SystemVerilog designs with Python testbenches, solving the limitation that Amaranth's built-in Python simulator cannot simulate Instance() black boxes. Validated with wb_timer SystemVerilog IP - all tests pass including register read/write, timer counting, compare match, and IRQ generation. Co-developed-by: Claude Code v2.1.7 (claude-opus-4-5-20251101)
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Co-developed-by: Claude Code v2.1.7 (claude-opus-4-5-20251101)
Co-developed-by: Claude Code v2.1.7 (claude-opus-4-5-20251101)
- Change _lib and _handle types to non-optional (always set after init) - Add type: ignore for amaranth.back.rtlil import (missing from stubs) - Fix sources list type annotation and extend call Co-developed-by: Claude Code v2.1.7 (claude-opus-4-5-20251101)
- Add :: for literal code blocks in Example sections - Update signal name examples to match CXXRTL conventions (no backslash) Co-developed-by: Claude Code v2.1.7 (claude-opus-4-5-20251101)
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Co-developed-by: Claude Code v2.1.7 (claude-opus-4-5-20251101)
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Summary
chipflow/sim/cxxrtl.py)chipflow/sim/build.py)Key Features
CxxrtlSimulator class: Python wrapper for CXXRTL compiled simulations
get(name)/set(name, value)for signal accessstep()for simulation advancementsignals()/inputs()/outputs()iterators for introspectionbuild_cxxrtl(): Compiles HDL sources to shared library
build_cxxrtl_from_amaranth(): Builds from Amaranth Elaboratable
Test plan
Technical Notes
cxxrtl_get_partsinstead ofcxxrtl_get(which is an inline function)p_prefix, underscores doubled (wb_timer→p_wb__timer)