feat: Add CXXRTL-based simulation infrastructure#161
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Add Python ctypes bindings for CXXRTL simulation engine and build tooling: - chipflow/sim/cxxrtl.py: CxxrtlSimulator class for signal access and stepping - chipflow/sim/build.py: build_cxxrtl() and build_cxxrtl_from_amaranth() - tests/test_cxxrtl_sim.py: Tests using wb_timer SystemVerilog IP Enables fast compiled simulation of mixed Amaranth/Verilog/SystemVerilog designs with Python testbenches. Co-developed-by: Claude Code v1.0.21 (claude-sonnet-4-20250514)
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v4 fixes branch name resolution by using commit hashes instead of branch names in override URLs, which resolves UnpackError failures during pdm lock. Co-developed-by: Claude Code v1.0.21 (claude-sonnet-4-20250514)
Co-developed-by: Claude Code v1.0.21 (claude-sonnet-4-20250514)
Use the ziglang package for consistent cross-platform C++ compilation when building CXXRTL shared libraries. Due to zig 0.11.0 having issues with -shared flag (missing std library files), we use a two-step approach: 1. Compile to object file with zig c++ 2. Link with system linker (c++/g++/clang++) Falls back to system compiler if zig is not available. Co-developed-by: Claude Code v2.1.9 (claude-opus-4-5-20250929)
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Summary
Add Python ctypes bindings for CXXRTL simulation engine and build tooling:
chipflow/sim/cxxrtl.py: CxxrtlSimulator class for signal access and steppingchipflow/sim/build.py:build_cxxrtl()andbuild_cxxrtl_from_amaranth()functionstests/test_cxxrtl_sim.py: Tests using wb_timer SystemVerilog IPEnables fast compiled simulation of mixed Amaranth/Verilog/SystemVerilog designs with Python testbenches.
Features
CxxrtlSimulator: Python wrapper for CXXRTL compiled simulations
cxxrtl_enumget()/set()step(),eval(),commit()build_cxxrtl(): Build CXXRTL shared library from Verilog/SystemVerilog sources
build_cxxrtl_from_amaranth(): Build from Amaranth Elaboratable with optional extra Verilog/SV sources
Test plan
🤖 Generated with Claude Code