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chipflow_lib/platforms/utils.py
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| @property | ||
| @abc.abstractmethod | ||
| def heartbeat(self) -> Dict(int, Pin): |
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The clock in some cases comes as two pins close to each other to be connected to XTAL.
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hmm, good point. Is that a config option to generate a oscillator?
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Currently we have nothing to specify use of XTAL, this needs to be added somehow.
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The clock in some cases comes as two pins close to each other to be connected to XTAL.
If you have external crystal you will need a crystal oscillator analog block on the chip. The actual clock will then be an output of this oscillator.
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What also can happen is that clock is delivered as differential signal; but this can also be for digital signals. Likely only to add when use case is there.
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I've updated this PR to implement a complete interface for package pins as discussed. Key enhancements:
All tests are passing. Ready for review! |
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gatecat
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Haven't looked through the tests yet, but these are my comments so far
chipflow_lib/platforms/utils.py
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| core_jtag: JTAGPins | ||
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| def to_set(self) -> Set[Pin]: | ||
| return {p for pp in self.core_power for p in asdict(pp).values()} | \ |
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what is the asdict doing here?
chipflow_lib/platforms/utils.py
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| ret = [] | ||
| for q in range(0,3): | ||
| ret.append(sorted(quadrants[q])) | ||
| return ret |
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it's worth noting that this won't give pins in bonding pad order which might be relevant in some cases - this can only be determined on a pattern-by-package (or by custom design in the case of a substrate or RDL for a WLCSP package).
An example for the PGA144 we used for the previous tapeout is the table on page 3 of https://europractice-ic.com/wp-content/uploads/2019/06/CD_PGA144.pdf but this is always going to differ
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…efinition Also enables grid array and quad format packages
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Has some WIP for better pin allocation. This should become shell and padring aware |
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This is massively outdated, but keeping it around as there were some good ideas that need extracting |
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Package Pin Interface
This PR implements a structured interface for determining package pins in ChipFlow.
Key Changes
Added abstract methods to define standard pin types in package definitions:
Implemented these methods in both package types:
Enhanced the Package class to:
Added comprehensive tests in test_package_pins.py
Created documentation in docs/package_pins.md
Backward Compatibility
The implementation maintains backward compatibility with the existing TOML configuration format while introducing a new, more flexible format.
Ready for Review
All tests are passing, and the implementation is ready for review.