Testing-for-mac

.gitignore

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+.DS_Store
+repo/.DS_Store

repo/rtl/alu.sv

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+    // 0000 = ADD
+    // 0001 = SUB
+    // 0010 = AND
+    // 0011 = OR
+    // 0100 = XOR
+    // 0101 = SLL
+    // 0110 = SRL
+    // 0111 = SRA
+    // 1000 = SLT (signed)
+    // 1001 = SLTU (unsigned)
+    // 1111 = LUI operation
+
+module alu (
+    input logic [31:0] SrcA,
+    input logic [31:0] SrcB,
+    input logic [3:0] ALUControl,
+    output logic [31:0] ALUResult,
+    output logic        Zero
+);
+
+    always_comb begin
+        case (ALUControl)
+            4'b0000: ALUResult = SrcA + SrcB; // add
+            4'b0001: ALUResult = SrcA - SrcB; // sub
+            4'b0010: ALUResult = SrcA & SrcB; // and
+            4'b0011: ALUResult = SrcA | SrcB; // or
+            4'b0100: ALUResult = SrcA ^ SrcB; // xor
+
+            4'b0101: ALUResult = SrcA << SrcB[4:0]; // sll
+            4'b0110: ALUResult = SrcA >> SrcB[4:0]; // srl
+            4'b0111: ALUResult = $signed(SrcA) >>> SrcB[4:0]; // sra
+            4'b1000: ALUResult = ($signed(SrcA) < $signed(SrcB)) ? 32'b1 : 32'b0; //slt
+            4'b1001: ALUResult = (SrcA < SrcB) ? 32'b1 : 32'b0; //sltu
+            4'b1111: ALUResult = SrcB; // LUI operation (Load Upper Immediate)
+
+            default: ALUResult = 32'b0;
+        endcase
+
+        Zero = (ALUResult == 32'd0);
+    end
+endmodule

repo/rtl/control.sv

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+module control(
+    input logic [6:0]  opcode,
+    input logic [2:0]  funct3,
+    input logic [6:0]  funct7,
+
+    output logic RegWrite,  // enable write to register
+    output logic [3:0] ALUControl, // control operation in ALU
+    output logic ALUSrcA, // choose PC (1) or register (0) for ALU operand A
+    output logic ALUSrcB, // choose immediate (1) or register (0) operand    
+    output logic MemWrite, // enable write into the data memory
+    // output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr))
+    output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4)
+    output logic Branch,
+    output logic [2:0] BranchType, 
+    output logic [1:0] Jump,       // indicates jump instruction (00 = no jump, 01 = JAL, 10 = JALR)
+    output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100)
+    output logic [2:0] AddressingControl // choose which type of load/store instruction to perform 
+);
+
+    // logic [6:0] opcode;
+    // logic [2:0] funct3;
+    // logic [6:0] funct7;
+
+    // assign opcode = Instr[6:0];
+    // assign funct3 = Instr[14:12];
+    // assign funct7 = Instr[31:25];
+    // assign AddressingControl = funct3; // store width
+
+    always_comb begin
+        // Default values to prevent latches
+        RegWrite = 1'b0;
+        ALUControl = 4'b0000;
+        ALUSrcA = 1'b0;
+        ALUSrcB = 1'b0;
+        MemWrite = 1'b0;
+        ResultSrc = 2'b00;
+        Branch = 1'b0;
+        BranchType = 3'b000;
+        Jump = 2'b00;
+        ImmSrc = 3'b000;
+        AddressingControl = 3'b000;
+
+
+        case(opcode)
+            // R-type instructions
+            7'b0110011: begin
+                RegWrite = 1'b1;
+                ALUSrcB = 1'b0;
+
+                case(funct3)
+                    3'b000: begin
+                        case(funct7)
+                            7'b0000000: ALUControl = 4'b0000; // add
+                            7'b0100000: ALUControl = 4'b0001; // sub
+                            default:    ALUControl = 4'b0000;
+                        endcase
+                    end
+                    3'b001: ALUControl = 4'b0101; // sll
+                    3'b010: ALUControl = 4'b1000; // slt
+                    3'b011: ALUControl = 4'b1001; // sltu
+                    3'b100: ALUControl = 4'b0100; // xor
+                    3'b101: begin
+                        case(funct7)
+                            7'b0000000: ALUControl = 4'b0110; // srl
+                            7'b0100000: ALUControl = 4'b0111; // sra 
+                            default:    ALUControl = 4'b0110;
+                        endcase
+                    end
+                    3'b110: ALUControl = 4'b0011; // or
+                    3'b111: ALUControl = 4'b0010; // and
+
+                    default: ALUControl = 4'b0000;
+                endcase
+            end
+
+            // I-type instructions (Arithmetic/Logic)
+            7'b0010011: begin
+                RegWrite = 1'b1;
+                ImmSrc = 3'b000; // I-type imm
+                ALUSrcB = 1'b1;
+
+                case(funct3)
+                    3'b000: ALUControl = 4'b0000; // addi
+                    3'b001: ALUControl = 4'b0101; // slli
+                    3'b010: ALUControl = 4'b1000; // slti (Added)
+                    3'b011: ALUControl = 4'b1001; // sltiu (Added)
+                    3'b100: ALUControl = 4'b0100; // xori
+                    3'b101: begin
+                        case(funct7)
+                            7'b0000000: ALUControl = 4'b0110; // srli
+                            7'b0100000: ALUControl = 4'b0111; // srai 
+                            default:    ALUControl = 4'b0110;
+                        endcase
+                    end
+                    3'b110: ALUControl = 4'b0011; // ori
+                    3'b111: ALUControl = 4'b0010; // andi
+                    default: ALUControl = 4'b0000;
+                endcase
+            end
+
+            // I-type Load instructions
+            7'b0000011: begin
+                RegWrite = 1'b1;
+                ALUSrcB = 1'b1; // SrcB = imm
+                ResultSrc = 2'b01; // From Memory
+                ImmSrc = 3'b000; // I-type imm
+                AddressingControl = funct3;
+                ALUControl = 4'b0000; // Add for address
+            end
+
+            // S-type Store instructions
+            7'b0100011: begin
+                MemWrite = 1'b1;
+                ALUSrcB   = 1'b1; // read from immediate
+                ImmSrc   = 3'b001; // S-type immediate
+                ALUControl = 4'b0000; // Add for address
+                AddressingControl = funct3;
+            end
+
+            // B-type Branch instructions
+            7'b1100011: begin
+                Branch = 1'b1;
+                ImmSrc = 3'b010; // B-type imm
+                BranchType = funct3;
+
+                case(funct3)
+                    // BEQ, BNE: ALU does SUB (0001)
+                    // If A == B, Result = 0, Zero = 1
+                    3'b000: ALUControl = 4'b0001; // beq
+                    3'b001: ALUControl = 4'b0001; // bne
+
+                    // BLT, BGE: ALU does SLT (1000)
+                    // If A < B: Result = 1, Zero = 0. If A >= B: Result = 0, Zero = 1.
+                    3'b100: ALUControl = 4'b1000; // blt
+                    3'b101: ALUControl = 4'b1000; // bge
+
+                    // BLTU, BGEU: ALU does SLTU (1001)
+                    3'b110: ALUControl = 4'b1001; // bltu
+                    3'b111: ALUControl = 4'b1001; // bgeu
+                    default: ALUControl = 4'b0000;
+
+                endcase
+            end
+
+            // J-type JAL
+            7'b1101111: begin
+                RegWrite = 1'b1;
+                ResultSrc = 2'b10; // PC+4
+                ImmSrc = 3'b011;   // J-type imm
+                Jump = 2'b01;
+            end
+
+            // I-type JALR
+            7'b1100111: begin
+                RegWrite = 1'b1;
+                ALUSrcB = 1'b1; // SrcB = imm
+                ResultSrc = 2'b10; // PC+4
+                ImmSrc = 3'b000; // I-type imm
+                Jump = 2'b10;
+                // ALUControl = 4'b0000; // Add for target address
+            end
+
+            // U-type LUI
+            7'b0110111: begin
+                RegWrite = 1'b1;
+                ALUSrcB = 1'b1;
+                ResultSrc = 2'b00;
+                ImmSrc = 3'b100; // U-type imm
+                ALUControl = 4'b1111; // LUI operation (0 + imm shifted)
+            end
+
+            // U-type AUIPC rd <- PC + imm << 12
+            7'b0010111: begin
+                RegWrite = 1'b1;
+                MemWrite = 1'b0;
+                ALUSrcA = 1'b1;     // Select PC
+                ALUSrcB = 1'b1;     // Select Imm
+                ImmSrc = 3'b100;   // U-type imm
+                ALUControl = 4'b000; // AUIPC operation (PC + imm shifted)
+            end
+
+            default: begin
+               // Already handled by defaults at top
+            end
+        endcase
+    end
+endmodule

repo/rtl/control_path.sv

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+module control_path(
+    /* verilator lint_off UNUSED */
+    input logic [31:0]  Instr,
+    /* verilator lint_on UNUSED */
+    input  logic         Zero,
+
+    output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr))
+    output logic RegWrite,  // enable write to register
+    output logic [3:0] ALUControl, // control operation in ALU
+    output logic ALUSrcA, // choose PC (1) or register (0) for ALU operand A
+    output logic ALUSrcB, // choose immediate (1) or register (0) operand    
+    output logic MemWrite, // enable write into the data memory
+    // output logic [1:0] PCSrc, // control the source for the next PC value (00 = PC+4, 01 = PC + imm(branch/jal), 10 = ALUResult (jalr))
+    output logic [1:0] ResultSrc, // control the source of data to write back to register file (00 = ALU, 01 = Memory, 10 = PC+4)
+    output logic [2:0] ImmSrc, // selects type of immediate (I = 000, S = 001, B = 010, J = 011, U = 100)
+    output logic [2:0] AddressingControl // choose which type of load/store instruction to perform 
+);
+
+    logic Branch;
+    logic [2:0] BranchType;
+    logic [1:0] Jump;
+
+    logic [6:0] opcode;
+    logic [2:0] funct3;
+    logic [6:0] funct7;
+
+    assign opcode = Instr[6:0];
+    assign funct3 = Instr[14:12];
+    assign funct7 = Instr[31:25];
+
+    control control_unit (
+        .opcode(opcode),
+        .funct3(funct3),
+        .funct7(funct7),
+        .RegWrite(RegWrite),
+        .ALUControl(ALUControl),
+        .ALUSrcA(ALUSrcA),
+        .ALUSrcB(ALUSrcB),
+        .MemWrite(MemWrite),
+        .ResultSrc(ResultSrc),
+        .Branch(Branch),
+        .BranchType(BranchType),
+        .Jump(Jump),
+        .ImmSrc(ImmSrc),
+        .AddressingControl(AddressingControl)
+    );
+
+    pcsrc_unit pcsrc_unit_inst (
+        .Jump(Jump),
+        .Branch(Branch),
+        .Zero(Zero),
+        .BranchType(BranchType),
+        .PCSrc(PCSrc)
+    );
+
+endmodule

repo/rtl/data_mem.sv

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+module data_mem #(
+    parameter XLEN = 32,
+    parameter ADDRESS_WIDTH = 16,
+    parameter DATA_WIDTH = 8
+) (
+    input  logic clk,
+    input  logic WE, // write enable
+    /* verilator lint_off UNUSED */
+    input  logic [XLEN-1:0] A, // memory address
+    /* verilator lint_on UNUSED */
+    input  logic [XLEN-1:0] WD, // data to write
+    input  logic [2:0] AddressingControl, // funct3 to determine load/store type
+    output logic [XLEN-1:0] RD // data read
+);
+    logic [DATA_WIDTH-1:0] ram_array [2**ADDRESS_WIDTH-1:0]; // 64KB data memory
+
+    logic [ADDRESS_WIDTH-1:0] addr;
+    assign addr = A[ADDRESS_WIDTH-1:0]; // use lower ADDRESS_WIDTH bits of address
+
+    always_ff @(posedge clk) begin
+        if (WE) begin
+            case (AddressingControl)
+                3'b000: ram_array[addr] <= WD[7:0]; // SB
+                3'b001: begin                      // SH
+                    ram_array[addr]   <= WD[7:0];
+                    ram_array[addr+1] <= WD[15:8];
+                end
+                3'b010: begin                      // SW
+                    ram_array[addr]   <= WD[7:0];
+                    ram_array[addr+1] <= WD[15:8];
+                    ram_array[addr+2] <= WD[23:16];
+                    ram_array[addr+3] <= WD[31:24];
+                end
+                default: ; // ignore other funct3
+            endcase
+        end
+    end
+
+    always_comb begin
+        case (AddressingControl)
+            3'b000: RD = {{24{ram_array[addr][7]}}, ram_array[addr]}; // LB (signed)
+            3'b001: RD = {{16{ram_array[addr+1][7]}}, ram_array[addr+1], ram_array[addr]}; // LH (signed)
+            3'b010: RD = {ram_array[addr+3], ram_array[addr+2], ram_array[addr+1], ram_array[addr]}; // LW
+            3'b100: RD = {24'b0, ram_array[addr]}; // LBU
+            3'b101: RD = {16'b0, ram_array[addr+1], ram_array[addr]}; // LHU
+            default: RD = 32'b0;
+        endcase
+    end
+
+
+endmodule