Enabling LogicalQ LogicalCircuit-pytket Circuit compatibility

[RasmitDevkota]

There are multiple steps in the process towards running a LogicalCircuit on Quantinuum hardware:

1. Transpile LogicalCircuit such that the pytket qiskit_to_tk function knows how to handle each step of the process
2. Convert LogicalCircuit to Circuit
3. Compile pytket Circuit down to lower level representations (notably QIR) based on backend
4. Submit compiled circuit to hardware

Throughout this process, multiple hiccups occur:

1. LogicalCircuit uses complex conditional operations (via IfElseOps) which pytket by itself supports in its library, but does not know how to convert from Qiskit to pytket
2. The pytket qiskit_to_tk function does not allow binary conditions
3. Pytket QIR does not know how to compile nested conditionals down to QIR (or, at least, raises an exception when attempted)
4. The pytket circuit constructor has a tight limit on the number of temporary "scratch bits" which can be stored at once in a circuit/operation

This pull request simultaneously resolves all known issues while satisfying the above known constraints via the following:

1. Replacing occurrences of expr.lift with simpler tuple conditions and splitting especially-heavy if_tests into multiple pieces, thereby getting around the limit on the number of scratch bits within LogicalCircuit.
2. Providing a FlattenIfElseOps TransformationPass, along with a DoWhileController-based FlattenIfElseOpsTask which terminates once there are no remaining IfElseOps.
3. Lastly, in order for the changes in this pull request to be effective, certain changes must be implemented in pytket (e.g. see Incorrect bits list referenced in _append_if_else_circuit Quantinuum/pytket-qiskit#514); I have implemented these locally and created a separate repository for storing them until the fixes are made upstream: https://github.com/RasmitDevkota/pytket. This is a temporary patch - users must modify their local installation of the pytket package until we can merge these changes upstream.

I have provided test case for these changes in the demo notebooks FlattenIfElseOps.ipynb and LogicalCircuitToTketCircuit.ipynb. The notebooks run in their entirety (though costing is currently slow, making full debugging difficult).

Currently, I am marking this as a draft pull request because I have not verified that these changes are effective once run on hardware or even emulator. I think a good verification step, at least, would be to run the circuit through both:

1. AerSimulator to verify that it replicates the results in LogicalCircuit_Demo.ipynb, and
2. Either a local or cloud Quantinuum emulator

Once the relevant metrics (e.g. SPAM fidelity, idle QEC fidelity, gate fidelities) are verified, this pull request can be merged.

[RasmitDevkota]

@benjaminhagan Could you take a look at my changes to Logical.py to verify that the restructuring is correct and not obviously problematic?