Support for Multiple Nodes

[dcmid]

This PR removes the assertion blocking the use of multiple memory nodes, allowing uses such as registers and memories in the same addrmap.

A change is also made in addrmap.h.j2, where memories were assigned the name of their parent class instead of their own names, allowing for the use of multiple mem types in one addrmap. Previously, this resulted in the classes in the generated header having identical names.

A test description regs_and_mem.rdl is added which places multiple registers and memories in the same addrmap. Its generated output is also committed, and a loop is added to export.py to support multiple .rdl examples.

[Risto97]

Hello @dcmid ,

Thank you for the pull request.
This pull request makes sense to merge for me.

To give you a bit of a history why it was done this way.
Another plugin is using SystemRDL to describe the whole SoC, including the HDL connections.

The reason for mem element to be inside the addrmap, is to be able to add interface, port information.
We would define a memory component with an APB interface in the following way.
https://github.com/HEP-SoC/PeakRDL-socgen/blob/7bfb9a653fc799c79d8c802b436dd62133044116/examples/apb_test/apb_slave.rdl#L7
And instantiate it in an SoC like this:
https://github.com/HEP-SoC/PeakRDL-socgen/blob/7bfb9a653fc799c79d8c802b436dd62133044116/examples/apb_test/apb_soc.rdl#L12

We should just verify with @benoitdenkinger if this change doesn't break the designs he is working with, I think it should not break anything.

[benoitdenkinger]

Hello @dcmid,

Thank you for your contribution. I'll check and test it.

The use of memory parent's name was a workaround fix for something I don't remember exactly. This will break our setup for sure, but I agree that your changes make more sense. I'll check again our exact problem, test with your PR and come back to you.

[dcmid]

Thank you!