- I like hardware design and CPU
- en.cs10@nycu.edu.tw
- BS @ NYCU CS / MS @ NTU GIEE
- Research Focus: Design and implementation of caches against side-channel attack
- Interest: Digital Design, Computer Architecture, Ray Tracing Hardware Architecture
- Verilog/SystemVerilog
- Python/C/C++
- UVM/Gem5
- ICLAB 2025 SPRING
- Computer Organization Course Material w/ Porting Lab CPU on FPGA
- Contains I2C, UART circuit intergration and DPI-C for verification


