GitHub: https://github.com/0xtaruhi/Beceros
A simple RISC-V soc written in Verilog.
| Name | Contents |
|---|---|
| doc | A report for our project |
| sim | Testbench and isa tests |
| src/core | Core rtl files |
| src/debug | JTAG debug module |
| src/constrs | Constrants of fpga boards |
| src/soc | top Module of the soc |
| src/headers | Header files |
| tools | Compile and Test tools |