Integration testing with Nexys 4 DDR (xilfpga)

[btgoodwin]

Pursuant with the license agreement on the MIPSfpga SoC Linux Project provided by Imagination Technologies, I'm making the result of my coursework available to the community with this pull request and the meta-img-manfiest (which I would like to transfer ownership of to the MIPS org, if there is interest).

The changes made to the layer were to support using the MIPSfpga 2.0 IP core (beta, released 3/2017 to our class at JHU) with the Nexys 4 DDR evaluation board. Changes include:

• Patches for incorporating the various labs (GPIO, ethernet, UIO, and I2C) into the 4.8.12 kernel recipe
• Example recipes for libfdc and the Simple GPIO application (which corresponds to the UIO interface, not the GPIO interface)
• Establishing a base image that results in a kernel plus RAM-based file system build similar to the SoC project's buildroot -based build that served as the example baseline.
• Sample configuration files (bblayers.conf and local.conf) to facilitate initial project configuration (via the TEMPLATECONF environment variable).

GPIO interfaces to the switches and LEDs has been tested as working as well as the I2C access of the temperature sensor. The ethernet driver loads, but ifconfig fails. Some forum posts suggest this may be power related. Attempting to use UIO results in a bus error (which also occurs if using devmem2 to debug that address).

[ZubairLK]

First of all. Apologies for the late response.
Thank-you for your work. Its a very interesting contribution to MIPSfpga.

I'd prefer to keep this work in a separate fork rather than merging it into meta-img.
I'll leave this pull-request open for a while.
And could you please keep your source repos and not delete them from your github account as well.
Those are directly linked in the MIPSfpga community forums.

Thanks.