Specializing in Heterogeneous Computing, Hardware-Software Co-Design, and Scientific AI.
I am an R&D Engineer bridging the gap between Scientific Computing and Embedded Hardware. My work focuses on running complex physical models (PDEs) and AI inference on specialized silicon with strict real-time constraints.
- Master's Thesis: Real-Time Determinism of Equivariant GNNs on RISC-V (Bare-metal/FreeRTOS).
- Key Interest: Eliminating the "Real-Time Gap" in AI for Scientific Computing using Vector Intrinsics (RVV/NEON) and Heterogeneous SoCs.
| Domain | Technologies & Tools |
|---|---|
| HPC & Acceleration | CUDA, OpenMP, MPI, SIMD (AVX/RVV), AHMED Library |
| Embedded Systems | FreeRTOS, Embedded Linux (Yocto), Bare-metal C, UART/I2C/SPI Drivers |
| Hardware Design | RISC-V (T-Head TH1520), ARM Cortex-A/M, SystemVerilog, SoC Partitioning |
| Algorithms | Numerical Methods (Elliptic PDEs), FFT/IFFT, Graph Neural Networks (GNN) |
| DevOps & Tools | CMake, Docker, Git, NVIDIA Nsight, Verilator |
Note: Some repositories are private for IP reasons. Detailed documentation available upon request.
| Project | Tech Stack | Impact / Metric |
|---|---|---|
| RISC-V GNN Accelerator(Ongoing) | C, RVV Intrinsics, FreeRTOS |
Aiming for 3.5x speedup on MACE kernels via vectorization; with <1ms deterministic latency. |
| Automotive Simulation Engine | CUDA, C++, NVIDIA Nsight |
Optimized GPU memory patterns for ZF Group, enabling real-time vehicle dynamics solving. |
| SoC Partitioning Framework | Python, SystemC, Graph Theory |
Reduced NoC traffic by 40% for Siemens multi-core architectures. |
| Radar/SAR Imaging Pipeline | CUDA, OpenMP, Jetson TX2 |
Accelerated FFT/IFFT kernels by 600% for high-fidelity radar imaging. |
When I am not optimizing kernels or debugging Verilog:
- Music: Classical Flute (Learning & Practice).
- Philosophy: Student of Tantra (Science of Inner Transformation) & Dvait-Advait Philosophy.
- Sport: Swimming & Endurance Training.
"Seeker of knowledge. Builder of ideas. Explorer of the inner and outer worlds."