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in verilog, the statement ``` reg my_reg = 0; ``` is the same as ``` reg my_reg; initial my_reg = 0; ``` whereas in the current HEAD, the statement above is translated to ``` reg my_reg; assign my_reg = 0; ``` This commit fixes this bug
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Problem:
In Verilog, the statement
is the same as
whereas in the current HEAD, the statement above
is translated to
Solution
This commit fixes this bug by converting the assignment ast node to a blocking assignment wrapped in an initial block.